aarch64 1.0.1 → 2.0.0

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (277) hide show
  1. checksums.yaml +4 -4
  2. data/README.md +1 -1
  3. data/Rakefile +37 -0
  4. data/aarch64.gemspec +1 -0
  5. data/lib/aarch64/instructions/adc.rb +10 -10
  6. data/lib/aarch64/instructions/adcs.rb +10 -10
  7. data/lib/aarch64/instructions/add_addsub_ext.rb +14 -14
  8. data/lib/aarch64/instructions/add_addsub_imm.rb +12 -12
  9. data/lib/aarch64/instructions/add_addsub_shift.rb +14 -14
  10. data/lib/aarch64/instructions/addg.rb +10 -10
  11. data/lib/aarch64/instructions/adds_addsub_ext.rb +14 -14
  12. data/lib/aarch64/instructions/adds_addsub_imm.rb +12 -12
  13. data/lib/aarch64/instructions/adds_addsub_shift.rb +14 -14
  14. data/lib/aarch64/instructions/adr.rb +7 -7
  15. data/lib/aarch64/instructions/adrp.rb +7 -7
  16. data/lib/aarch64/instructions/and_log_imm.rb +14 -14
  17. data/lib/aarch64/instructions/and_log_shift.rb +14 -14
  18. data/lib/aarch64/instructions/ands_log_imm.rb +14 -14
  19. data/lib/aarch64/instructions/ands_log_shift.rb +14 -14
  20. data/lib/aarch64/instructions/asrv.rb +10 -10
  21. data/lib/aarch64/instructions/autda.rb +9 -12
  22. data/lib/aarch64/instructions/autdb.rb +9 -12
  23. data/lib/aarch64/instructions/autia.rb +9 -12
  24. data/lib/aarch64/instructions/autib.rb +9 -12
  25. data/lib/aarch64/instructions/axflag.rb +1 -1
  26. data/lib/aarch64/instructions/b_cond.rb +5 -5
  27. data/lib/aarch64/instructions/b_uncond.rb +3 -3
  28. data/lib/aarch64/instructions/bc_cond.rb +5 -5
  29. data/lib/aarch64/instructions/bfm.rb +13 -13
  30. data/lib/aarch64/instructions/bic_log_shift.rb +14 -14
  31. data/lib/aarch64/instructions/bics.rb +14 -14
  32. data/lib/aarch64/instructions/bl.rb +3 -3
  33. data/lib/aarch64/instructions/blr.rb +4 -4
  34. data/lib/aarch64/instructions/blra.rb +10 -10
  35. data/lib/aarch64/instructions/br.rb +4 -4
  36. data/lib/aarch64/instructions/bra.rb +10 -10
  37. data/lib/aarch64/instructions/brk.rb +3 -3
  38. data/lib/aarch64/instructions/bti.rb +3 -3
  39. data/lib/aarch64/instructions/cas.rb +14 -14
  40. data/lib/aarch64/instructions/casb.rb +12 -12
  41. data/lib/aarch64/instructions/cash.rb +12 -12
  42. data/lib/aarch64/instructions/casp.rb +14 -14
  43. data/lib/aarch64/instructions/cbnz.rb +7 -7
  44. data/lib/aarch64/instructions/cbz.rb +7 -7
  45. data/lib/aarch64/instructions/ccmn_imm.rb +12 -12
  46. data/lib/aarch64/instructions/ccmn_reg.rb +12 -12
  47. data/lib/aarch64/instructions/ccmp_imm.rb +12 -12
  48. data/lib/aarch64/instructions/ccmp_reg.rb +12 -12
  49. data/lib/aarch64/instructions/cfinv.rb +2 -9
  50. data/lib/aarch64/instructions/clrex.rb +3 -3
  51. data/lib/aarch64/instructions/cls_int.rb +8 -8
  52. data/lib/aarch64/instructions/clz_int.rb +8 -8
  53. data/lib/aarch64/instructions/crc32.rb +12 -12
  54. data/lib/aarch64/instructions/crc32c.rb +12 -12
  55. data/lib/aarch64/instructions/csdb.rb +1 -1
  56. data/lib/aarch64/instructions/csel.rb +12 -12
  57. data/lib/aarch64/instructions/csinc.rb +12 -12
  58. data/lib/aarch64/instructions/csinv.rb +12 -12
  59. data/lib/aarch64/instructions/csneg.rb +12 -12
  60. data/lib/aarch64/instructions/dcps.rb +5 -5
  61. data/lib/aarch64/instructions/dgh.rb +1 -1
  62. data/lib/aarch64/instructions/dmb.rb +3 -3
  63. data/lib/aarch64/instructions/drps.rb +2 -9
  64. data/lib/aarch64/instructions/dsb.rb +3 -3
  65. data/lib/aarch64/instructions/eon.rb +14 -14
  66. data/lib/aarch64/instructions/eor_log_imm.rb +14 -14
  67. data/lib/aarch64/instructions/eor_log_shift.rb +14 -14
  68. data/lib/aarch64/instructions/eret.rb +2 -9
  69. data/lib/aarch64/instructions/ereta.rb +3 -3
  70. data/lib/aarch64/instructions/esb.rb +1 -1
  71. data/lib/aarch64/instructions/extr.rb +13 -13
  72. data/lib/aarch64/instructions/gmi.rb +8 -8
  73. data/lib/aarch64/instructions/hint.rb +5 -5
  74. data/lib/aarch64/instructions/hlt.rb +3 -3
  75. data/lib/aarch64/instructions/hvc.rb +3 -3
  76. data/lib/aarch64/instructions/irg.rb +8 -8
  77. data/lib/aarch64/instructions/isb.rb +3 -3
  78. data/lib/aarch64/instructions/ld64b.rb +6 -6
  79. data/lib/aarch64/instructions/ldadd.rb +14 -14
  80. data/lib/aarch64/instructions/ldaddb.rb +12 -12
  81. data/lib/aarch64/instructions/ldaddh.rb +12 -12
  82. data/lib/aarch64/instructions/ldapr.rb +8 -8
  83. data/lib/aarch64/instructions/ldaprb.rb +6 -6
  84. data/lib/aarch64/instructions/ldaprh.rb +6 -6
  85. data/lib/aarch64/instructions/ldapur_gen.rb +12 -12
  86. data/lib/aarch64/instructions/ldar.rb +8 -8
  87. data/lib/aarch64/instructions/ldaxp.rb +10 -10
  88. data/lib/aarch64/instructions/ldaxr.rb +8 -8
  89. data/lib/aarch64/instructions/ldclr.rb +14 -14
  90. data/lib/aarch64/instructions/ldclrb.rb +14 -14
  91. data/lib/aarch64/instructions/ldeor.rb +14 -14
  92. data/lib/aarch64/instructions/ldg.rb +8 -8
  93. data/lib/aarch64/instructions/ldgm.rb +6 -6
  94. data/lib/aarch64/instructions/ldlar.rb +8 -8
  95. data/lib/aarch64/instructions/ldnp_gen.rb +12 -12
  96. data/lib/aarch64/instructions/ldp_gen.rb +14 -14
  97. data/lib/aarch64/instructions/ldpsw.rb +12 -12
  98. data/lib/aarch64/instructions/ldr_imm_gen.rb +12 -12
  99. data/lib/aarch64/instructions/ldr_imm_unsigned.rb +10 -10
  100. data/lib/aarch64/instructions/ldr_lit_gen.rb +7 -7
  101. data/lib/aarch64/instructions/ldr_reg_gen.rb +14 -14
  102. data/lib/aarch64/instructions/ldra.rb +14 -14
  103. data/lib/aarch64/instructions/ldrb_imm.rb +10 -10
  104. data/lib/aarch64/instructions/ldrb_reg.rb +12 -12
  105. data/lib/aarch64/instructions/ldrb_unsigned.rb +8 -8
  106. data/lib/aarch64/instructions/ldrh_imm.rb +10 -10
  107. data/lib/aarch64/instructions/ldrh_reg.rb +12 -12
  108. data/lib/aarch64/instructions/ldrh_unsigned.rb +8 -8
  109. data/lib/aarch64/instructions/ldrsb_imm.rb +12 -12
  110. data/lib/aarch64/instructions/ldrsb_reg.rb +14 -14
  111. data/lib/aarch64/instructions/ldrsb_unsigned.rb +10 -10
  112. data/lib/aarch64/instructions/ldrsh_imm.rb +12 -12
  113. data/lib/aarch64/instructions/ldrsh_reg.rb +14 -14
  114. data/lib/aarch64/instructions/ldrsh_unsigned.rb +10 -10
  115. data/lib/aarch64/instructions/ldrsw_imm.rb +10 -10
  116. data/lib/aarch64/instructions/ldrsw_lit.rb +5 -5
  117. data/lib/aarch64/instructions/ldrsw_reg.rb +12 -12
  118. data/lib/aarch64/instructions/ldrsw_unsigned.rb +8 -8
  119. data/lib/aarch64/instructions/ldset.rb +14 -14
  120. data/lib/aarch64/instructions/ldsetb.rb +12 -12
  121. data/lib/aarch64/instructions/ldseth.rb +12 -12
  122. data/lib/aarch64/instructions/ldsmax.rb +14 -14
  123. data/lib/aarch64/instructions/ldsmaxb.rb +12 -12
  124. data/lib/aarch64/instructions/ldsmaxh.rb +12 -12
  125. data/lib/aarch64/instructions/ldsmin.rb +14 -14
  126. data/lib/aarch64/instructions/ldsminb.rb +12 -12
  127. data/lib/aarch64/instructions/ldsminh.rb +12 -12
  128. data/lib/aarch64/instructions/ldtr.rb +10 -10
  129. data/lib/aarch64/instructions/ldtrb.rb +8 -8
  130. data/lib/aarch64/instructions/ldtrh.rb +8 -8
  131. data/lib/aarch64/instructions/ldtrsb.rb +10 -10
  132. data/lib/aarch64/instructions/ldtrsh.rb +10 -10
  133. data/lib/aarch64/instructions/ldtrsw.rb +8 -8
  134. data/lib/aarch64/instructions/ldumax.rb +14 -14
  135. data/lib/aarch64/instructions/ldumaxb.rb +12 -12
  136. data/lib/aarch64/instructions/ldumaxh.rb +12 -12
  137. data/lib/aarch64/instructions/ldumin.rb +14 -14
  138. data/lib/aarch64/instructions/lduminb.rb +12 -12
  139. data/lib/aarch64/instructions/lduminh.rb +12 -12
  140. data/lib/aarch64/instructions/ldur_gen.rb +10 -10
  141. data/lib/aarch64/instructions/ldursb.rb +10 -10
  142. data/lib/aarch64/instructions/ldursh.rb +10 -10
  143. data/lib/aarch64/instructions/ldursw.rb +8 -8
  144. data/lib/aarch64/instructions/ldxp.rb +10 -10
  145. data/lib/aarch64/instructions/ldxr.rb +8 -8
  146. data/lib/aarch64/instructions/lslv.rb +10 -10
  147. data/lib/aarch64/instructions/lsrv.rb +10 -10
  148. data/lib/aarch64/instructions/madd.rb +12 -12
  149. data/lib/aarch64/instructions/movk.rb +10 -10
  150. data/lib/aarch64/instructions/movn.rb +10 -10
  151. data/lib/aarch64/instructions/movz.rb +10 -10
  152. data/lib/aarch64/instructions/mrs.rb +14 -14
  153. data/lib/aarch64/instructions/msr_imm.rb +7 -7
  154. data/lib/aarch64/instructions/msr_reg.rb +14 -14
  155. data/lib/aarch64/instructions/msub.rb +12 -12
  156. data/lib/aarch64/instructions/nop.rb +1 -1
  157. data/lib/aarch64/instructions/orn_log_shift.rb +14 -14
  158. data/lib/aarch64/instructions/orr_log_imm.rb +14 -14
  159. data/lib/aarch64/instructions/orr_log_shift.rb +14 -14
  160. data/lib/aarch64/instructions/pacda.rb +8 -8
  161. data/lib/aarch64/instructions/pacdb.rb +8 -8
  162. data/lib/aarch64/instructions/pacga.rb +8 -8
  163. data/lib/aarch64/instructions/pacia.rb +8 -8
  164. data/lib/aarch64/instructions/pacia2.rb +5 -5
  165. data/lib/aarch64/instructions/pacib.rb +8 -8
  166. data/lib/aarch64/instructions/prfm_imm.rb +8 -8
  167. data/lib/aarch64/instructions/prfm_lit.rb +8 -8
  168. data/lib/aarch64/instructions/prfm_reg.rb +12 -12
  169. data/lib/aarch64/instructions/prfum.rb +8 -8
  170. data/lib/aarch64/instructions/psb.rb +2 -9
  171. data/lib/aarch64/instructions/rbit_int.rb +8 -8
  172. data/lib/aarch64/instructions/ret.rb +4 -4
  173. data/lib/aarch64/instructions/reta.rb +3 -3
  174. data/lib/aarch64/instructions/rev.rb +10 -10
  175. data/lib/aarch64/instructions/rmif.rb +8 -8
  176. data/lib/aarch64/instructions/rorv.rb +10 -10
  177. data/lib/aarch64/instructions/sb.rb +1 -1
  178. data/lib/aarch64/instructions/sbc.rb +10 -10
  179. data/lib/aarch64/instructions/sbcs.rb +10 -10
  180. data/lib/aarch64/instructions/sbfm.rb +13 -13
  181. data/lib/aarch64/instructions/sdiv.rb +10 -10
  182. data/lib/aarch64/instructions/setf.rb +6 -6
  183. data/lib/aarch64/instructions/sev.rb +1 -7
  184. data/lib/aarch64/instructions/sevl.rb +1 -1
  185. data/lib/aarch64/instructions/smaddl.rb +10 -10
  186. data/lib/aarch64/instructions/smc.rb +3 -3
  187. data/lib/aarch64/instructions/smsubl.rb +10 -10
  188. data/lib/aarch64/instructions/smulh.rb +8 -8
  189. data/lib/aarch64/instructions/st2g.rb +10 -10
  190. data/lib/aarch64/instructions/st64b.rb +6 -6
  191. data/lib/aarch64/instructions/st64bv.rb +8 -8
  192. data/lib/aarch64/instructions/st64bv0.rb +8 -8
  193. data/lib/aarch64/instructions/stg.rb +10 -10
  194. data/lib/aarch64/instructions/stgm.rb +6 -6
  195. data/lib/aarch64/instructions/stgp.rb +12 -12
  196. data/lib/aarch64/instructions/stllr.rb +8 -8
  197. data/lib/aarch64/instructions/stllrb.rb +6 -6
  198. data/lib/aarch64/instructions/stllrh.rb +6 -6
  199. data/lib/aarch64/instructions/stlr.rb +8 -8
  200. data/lib/aarch64/instructions/stlrb.rb +6 -6
  201. data/lib/aarch64/instructions/stlrh.rb +6 -6
  202. data/lib/aarch64/instructions/stlur_gen.rb +10 -10
  203. data/lib/aarch64/instructions/stlxp.rb +12 -12
  204. data/lib/aarch64/instructions/stlxr.rb +10 -10
  205. data/lib/aarch64/instructions/stlxrb.rb +8 -8
  206. data/lib/aarch64/instructions/stlxrh.rb +8 -8
  207. data/lib/aarch64/instructions/stnp_gen.rb +12 -12
  208. data/lib/aarch64/instructions/stp_gen.rb +14 -14
  209. data/lib/aarch64/instructions/str_imm_gen.rb +12 -12
  210. data/lib/aarch64/instructions/str_imm_unsigned.rb +10 -10
  211. data/lib/aarch64/instructions/str_reg_gen.rb +14 -14
  212. data/lib/aarch64/instructions/strb_imm.rb +10 -10
  213. data/lib/aarch64/instructions/strb_imm_unsigned.rb +8 -8
  214. data/lib/aarch64/instructions/strb_reg.rb +12 -12
  215. data/lib/aarch64/instructions/strh_imm.rb +10 -10
  216. data/lib/aarch64/instructions/strh_imm_unsigned.rb +8 -8
  217. data/lib/aarch64/instructions/strh_reg.rb +12 -12
  218. data/lib/aarch64/instructions/sttr.rb +10 -10
  219. data/lib/aarch64/instructions/stur_gen.rb +10 -10
  220. data/lib/aarch64/instructions/stxp.rb +12 -12
  221. data/lib/aarch64/instructions/stxr.rb +10 -10
  222. data/lib/aarch64/instructions/stxrb.rb +8 -8
  223. data/lib/aarch64/instructions/stxrh.rb +8 -8
  224. data/lib/aarch64/instructions/stz2g.rb +10 -10
  225. data/lib/aarch64/instructions/stzg.rb +10 -10
  226. data/lib/aarch64/instructions/stzgm.rb +6 -6
  227. data/lib/aarch64/instructions/sub_addsub_ext.rb +14 -14
  228. data/lib/aarch64/instructions/sub_addsub_imm.rb +12 -12
  229. data/lib/aarch64/instructions/sub_addsub_shift.rb +14 -14
  230. data/lib/aarch64/instructions/subg.rb +10 -10
  231. data/lib/aarch64/instructions/subp.rb +8 -8
  232. data/lib/aarch64/instructions/subps.rb +8 -8
  233. data/lib/aarch64/instructions/subs_addsub_ext.rb +14 -14
  234. data/lib/aarch64/instructions/subs_addsub_imm.rb +12 -12
  235. data/lib/aarch64/instructions/subs_addsub_shift.rb +14 -14
  236. data/lib/aarch64/instructions/svc.rb +3 -3
  237. data/lib/aarch64/instructions/swp.rb +14 -14
  238. data/lib/aarch64/instructions/swpb.rb +12 -12
  239. data/lib/aarch64/instructions/swph.rb +12 -12
  240. data/lib/aarch64/instructions/sys.rb +12 -12
  241. data/lib/aarch64/instructions/sysl.rb +12 -12
  242. data/lib/aarch64/instructions/tbnz.rb +9 -9
  243. data/lib/aarch64/instructions/tbz.rb +9 -9
  244. data/lib/aarch64/instructions/tsb.rb +1 -7
  245. data/lib/aarch64/instructions/ubfm.rb +13 -13
  246. data/lib/aarch64/instructions/udf_perm_undef.rb +3 -3
  247. data/lib/aarch64/instructions/udiv.rb +10 -10
  248. data/lib/aarch64/instructions/umaddl.rb +10 -10
  249. data/lib/aarch64/instructions/umsubl.rb +10 -10
  250. data/lib/aarch64/instructions/umulh.rb +8 -8
  251. data/lib/aarch64/instructions/wfe.rb +2 -9
  252. data/lib/aarch64/instructions/wfet.rb +4 -4
  253. data/lib/aarch64/instructions/wfi.rb +1 -1
  254. data/lib/aarch64/instructions/wfit.rb +4 -4
  255. data/lib/aarch64/instructions/xaflag.rb +1 -1
  256. data/lib/aarch64/instructions/xpac.rb +6 -6
  257. data/lib/aarch64/instructions/xpaclri.rb +1 -1
  258. data/lib/aarch64/instructions/yield.rb +2 -9
  259. data/lib/aarch64/instructions.rb +26 -8
  260. data/lib/aarch64/parser.rb +227 -0
  261. data/lib/aarch64/parser.tab.rb +6534 -0
  262. data/lib/aarch64/parser.y +1394 -0
  263. data/lib/aarch64/utils.rb +34 -0
  264. data/lib/aarch64/version.rb +1 -1
  265. data/lib/aarch64.rb +128 -58
  266. data/test/base_instructions_test.rb +34 -4
  267. data/test/helper.rb +48 -8
  268. data/test/parser_test.rb +1820 -0
  269. metadata +25 -14
  270. data/lib/aarch64/instructions/setgp.rb +0 -25
  271. data/lib/aarch64/instructions/setgpn.rb +0 -25
  272. data/lib/aarch64/instructions/setgpt.rb +0 -25
  273. data/lib/aarch64/instructions/setgptn.rb +0 -25
  274. data/lib/aarch64/instructions/setp.rb +0 -25
  275. data/lib/aarch64/instructions/setpn.rb +0 -25
  276. data/lib/aarch64/instructions/setpt.rb +0 -25
  277. data/lib/aarch64/instructions/setptn.rb +0 -25
@@ -8,28 +8,28 @@ module AArch64
8
8
  # LDRSH <Xt>, [<Xn|SP>, #<simm>]!
9
9
  # LDRSH <Wt>, [<Xn|SP>{, #<pimm>}]
10
10
  # LDRSH <Xt>, [<Xn|SP>{, #<pimm>}]
11
- class LDRSH_imm
11
+ class LDRSH_imm < Instruction
12
12
  def initialize rt, rn, imm9, option, opc
13
- @rt = rt
14
- @rn = rn
15
- @imm9 = imm9
16
- @option = option
17
- @opc = opc
13
+ @rt = check_mask(rt, 0x1f)
14
+ @rn = check_mask(rn, 0x1f)
15
+ @imm9 = check_mask(imm9, 0x1ff)
16
+ @option = check_mask(option, 0x03)
17
+ @opc = check_mask(opc, 0x03)
18
18
  end
19
19
 
20
20
  def encode
21
- LDRSH_imm(@opc, @imm9, @option, @rn.to_i, @rt.to_i)
21
+ LDRSH_imm(@opc, @imm9, @option, @rn, @rt)
22
22
  end
23
23
 
24
24
  private
25
25
 
26
26
  def LDRSH_imm opc, imm9, option, rn, rt
27
27
  insn = 0b01_111_0_00_00_0_000000000_00_00000_00000
28
- insn |= ((opc & 0x3) << 22)
29
- insn |= ((imm9 & 0x1ff) << 12)
30
- insn |= ((option & 0x3) << 10)
31
- insn |= ((rn & 0x1f) << 5)
32
- insn |= (rt & 0x1f)
28
+ insn |= ((opc) << 22)
29
+ insn |= ((imm9) << 12)
30
+ insn |= ((option) << 10)
31
+ insn |= ((rn) << 5)
32
+ insn |= (rt)
33
33
  insn
34
34
  end
35
35
  end
@@ -4,30 +4,30 @@ module AArch64
4
4
  # Load Register Signed Halfword (register)
5
5
  # LDRSH <Wt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
6
6
  # LDRSH <Xt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
7
- class LDRSH_reg
7
+ class LDRSH_reg < Instruction
8
8
  def initialize rt, rn, rm, s, option, opc
9
- @rt = rt
10
- @rn = rn
11
- @rm = rm
12
- @s = s
13
- @option = option
14
- @opc = opc
9
+ @rt = check_mask(rt, 0x1f)
10
+ @rn = check_mask(rn, 0x1f)
11
+ @rm = check_mask(rm, 0x1f)
12
+ @s = check_mask(s, 0x01)
13
+ @option = check_mask(option, 0x07)
14
+ @opc = check_mask(opc, 0x03)
15
15
  end
16
16
 
17
17
  def encode
18
- LDRSH_reg(@opc, @rm.to_i, @option, @s, @rn.to_i, @rt.to_i)
18
+ LDRSH_reg(@opc, @rm, @option, @s, @rn, @rt)
19
19
  end
20
20
 
21
21
  private
22
22
 
23
23
  def LDRSH_reg opc, rm, option, s, rn, rt
24
24
  insn = 0b01_111_0_00_00_1_00000_000_0_10_00000_00000
25
- insn |= ((opc & 0x3) << 22)
26
- insn |= ((rm & 0x1f) << 16)
27
- insn |= ((option & 0x7) << 13)
28
- insn |= ((s & 0x1) << 12)
29
- insn |= ((rn & 0x1f) << 5)
30
- insn |= (rt & 0x1f)
25
+ insn |= ((opc) << 22)
26
+ insn |= ((rm) << 16)
27
+ insn |= ((option) << 13)
28
+ insn |= ((s) << 12)
29
+ insn |= ((rn) << 5)
30
+ insn |= (rt)
31
31
  insn
32
32
  end
33
33
  end
@@ -4,26 +4,26 @@ module AArch64
4
4
  # Load Register Signed Halfword (immediate)
5
5
  # LDRSH <Wt>, [<Xn|SP>{, #<pimm>}]
6
6
  # LDRSH <Xt>, [<Xn|SP>{, #<pimm>}]
7
- class LDRSH_unsigned
7
+ class LDRSH_unsigned < Instruction
8
8
  def initialize rt, rn, imm12, opc
9
- @rt = rt
10
- @rn = rn
11
- @imm12 = imm12
12
- @opc = opc
9
+ @rt = check_mask(rt, 0x1f)
10
+ @rn = check_mask(rn, 0x1f)
11
+ @imm12 = check_mask(imm12, 0xfff)
12
+ @opc = check_mask(opc, 0x03)
13
13
  end
14
14
 
15
15
  def encode
16
- LDRSH_unsigned(@opc, @imm12, @rn.to_i, @rt.to_i)
16
+ LDRSH_unsigned(@opc, @imm12, @rn, @rt)
17
17
  end
18
18
 
19
19
  private
20
20
 
21
21
  def LDRSH_unsigned opc, imm12, rn, rt
22
22
  insn = 0b01_111_0_01_00_0_00000000000_00000_00000
23
- insn |= ((opc & 0x3) << 22)
24
- insn |= ((imm12 & 0xfff) << 10)
25
- insn |= ((rn & 0x1f) << 5)
26
- insn |= (rt & 0x1f)
23
+ insn |= ((opc) << 22)
24
+ insn |= ((imm12) << 10)
25
+ insn |= ((rn) << 5)
26
+ insn |= (rt)
27
27
  insn
28
28
  end
29
29
  end
@@ -5,26 +5,26 @@ module AArch64
5
5
  # LDRSW <Xt>, [<Xn|SP>], #<simm>
6
6
  # LDRSW <Xt>, [<Xn|SP>, #<simm>]!
7
7
  # LDRSW <Xt>, [<Xn|SP>{, #<pimm>}]
8
- class LDRSW_imm
8
+ class LDRSW_imm < Instruction
9
9
  def initialize rt, rn, imm9, option
10
- @rt = rt
11
- @rn = rn
12
- @imm9 = imm9
13
- @option = option
10
+ @rt = check_mask(rt, 0x1f)
11
+ @rn = check_mask(rn, 0x1f)
12
+ @imm9 = check_mask(imm9, 0x1ff)
13
+ @option = check_mask(option, 0x03)
14
14
  end
15
15
 
16
16
  def encode
17
- LDRSW_imm(@imm9, @rn.to_i, @rt.to_i, @option)
17
+ LDRSW_imm(@imm9, @rn, @rt, @option)
18
18
  end
19
19
 
20
20
  private
21
21
 
22
22
  def LDRSW_imm imm9, rn, rt, option
23
23
  insn = 0b10_111_0_00_10_0_000000000_01_00000_00000
24
- insn |= ((imm9 & 0x1ff) << 12)
25
- insn |= ((option & 0x3) << 10)
26
- insn |= ((rn & 0x1f) << 5)
27
- insn |= (rt & 0x1f)
24
+ insn |= ((imm9) << 12)
25
+ insn |= ((option) << 10)
26
+ insn |= ((rn) << 5)
27
+ insn |= (rt)
28
28
  insn
29
29
  end
30
30
  end
@@ -3,22 +3,22 @@ module AArch64
3
3
  # LDRSW (literal) -- A64
4
4
  # Load Register Signed Word (literal)
5
5
  # LDRSW <Xt>, <label>
6
- class LDRSW_lit
6
+ class LDRSW_lit < Instruction
7
7
  def initialize rt, imm19
8
- @rt = rt
8
+ @rt = check_mask(rt, 0x1f)
9
9
  @imm19 = imm19
10
10
  end
11
11
 
12
12
  def encode
13
- LDRSW_lit(@imm19.to_i / 4, @rt.to_i)
13
+ LDRSW_lit(check_mask(unwrap_label(@imm19), 0x7ffff), @rt)
14
14
  end
15
15
 
16
16
  private
17
17
 
18
18
  def LDRSW_lit imm19, rt
19
19
  insn = 0b10_011_0_00_0000000000000000000_00000
20
- insn |= ((imm19 & 0x7ffff) << 5)
21
- insn |= (rt & 0x1f)
20
+ insn |= (imm19 << 5)
21
+ insn |= rt
22
22
  insn
23
23
  end
24
24
  end
@@ -3,28 +3,28 @@ module AArch64
3
3
  # LDRSW (register) -- A64
4
4
  # Load Register Signed Word (register)
5
5
  # LDRSW <Xt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
6
- class LDRSW_reg
6
+ class LDRSW_reg < Instruction
7
7
  def initialize rt, rn, rm, s, option
8
- @rt = rt
9
- @rn = rn
10
- @rm = rm
11
- @s = s
12
- @option = option
8
+ @rt = check_mask(rt, 0x1f)
9
+ @rn = check_mask(rn, 0x1f)
10
+ @rm = check_mask(rm, 0x1f)
11
+ @s = check_mask(s, 0x01)
12
+ @option = check_mask(option, 0x07)
13
13
  end
14
14
 
15
15
  def encode
16
- LDRSW_reg(@rm.to_i, @option, @s, @rn.to_i, @rt.to_i)
16
+ LDRSW_reg(@rm, @option, @s, @rn, @rt)
17
17
  end
18
18
 
19
19
  private
20
20
 
21
21
  def LDRSW_reg rm, option, s, rn, rt
22
22
  insn = 0b10_111_0_00_10_1_00000_000_0_10_00000_00000
23
- insn |= ((rm & 0x1f) << 16)
24
- insn |= ((option & 0x7) << 13)
25
- insn |= ((s & 0x1) << 12)
26
- insn |= ((rn & 0x1f) << 5)
27
- insn |= (rt & 0x1f)
23
+ insn |= ((rm) << 16)
24
+ insn |= ((option) << 13)
25
+ insn |= ((s) << 12)
26
+ insn |= ((rn) << 5)
27
+ insn |= (rt)
28
28
  insn
29
29
  end
30
30
  end
@@ -5,24 +5,24 @@ module AArch64
5
5
  # LDRSW <Xt>, [<Xn|SP>], #<simm>
6
6
  # LDRSW <Xt>, [<Xn|SP>, #<simm>]!
7
7
  # LDRSW <Xt>, [<Xn|SP>{, #<pimm>}]
8
- class LDRSW_unsigned
8
+ class LDRSW_unsigned < Instruction
9
9
  def initialize rt, rn, imm12
10
- @rt = rt
11
- @rn = rn
12
- @imm12 = imm12
10
+ @rt = check_mask(rt, 0x1f)
11
+ @rn = check_mask(rn, 0x1f)
12
+ @imm12 = check_mask(imm12, 0xfff)
13
13
  end
14
14
 
15
15
  def encode
16
- LDRSW_unsigned(@imm12, @rn.to_i, @rt.to_i)
16
+ LDRSW_unsigned(@imm12, @rn, @rt)
17
17
  end
18
18
 
19
19
  private
20
20
 
21
21
  def LDRSW_unsigned imm12, rn, rt
22
22
  insn = 0b10_111_0_01_10_0_00000000000_00000_00000
23
- insn |= ((imm12 & 0xfff) << 10)
24
- insn |= ((rn & 0x1f) << 5)
25
- insn |= (rt & 0x1f)
23
+ insn |= ((imm12) << 10)
24
+ insn |= ((rn) << 5)
25
+ insn |= (rt)
26
26
  insn
27
27
  end
28
28
  end
@@ -10,30 +10,30 @@ module AArch64
10
10
  # LDSETA <Xs>, <Xt>, [<Xn|SP>]
11
11
  # LDSETAL <Xs>, <Xt>, [<Xn|SP>]
12
12
  # LDSETL <Xs>, <Xt>, [<Xn|SP>]
13
- class LDSET
13
+ class LDSET < Instruction
14
14
  def initialize rs, rt, rn, size, a, r
15
- @rs = rs
16
- @rt = rt
17
- @rn = rn
18
- @size = size
19
- @a = a
20
- @r = r
15
+ @rs = check_mask(rs, 0x1f)
16
+ @rt = check_mask(rt, 0x1f)
17
+ @rn = check_mask(rn, 0x1f)
18
+ @size = check_mask(size, 0x03)
19
+ @a = check_mask(a, 0x01)
20
+ @r = check_mask(r, 0x01)
21
21
  end
22
22
 
23
23
  def encode
24
- LDSET(@size, @a, @r.to_i, @rs.to_i, @rn.to_i, @rt.to_i)
24
+ LDSET(@size, @a, @r, @rs, @rn, @rt)
25
25
  end
26
26
 
27
27
  private
28
28
 
29
29
  def LDSET size, a, r, rs, rn, rt
30
30
  insn = 0b00_111_0_00_0_0_1_00000_0_011_00_00000_00000
31
- insn |= ((size & 0x3) << 30)
32
- insn |= ((a & 0x1) << 23)
33
- insn |= ((r & 0x1) << 22)
34
- insn |= ((rs & 0x1f) << 16)
35
- insn |= ((rn & 0x1f) << 5)
36
- insn |= (rt & 0x1f)
31
+ insn |= ((size) << 30)
32
+ insn |= ((a) << 23)
33
+ insn |= ((r) << 22)
34
+ insn |= ((rs) << 16)
35
+ insn |= ((rn) << 5)
36
+ insn |= (rt)
37
37
  insn
38
38
  end
39
39
  end
@@ -6,28 +6,28 @@ module AArch64
6
6
  # LDSETALB <Ws>, <Wt>, [<Xn|SP>]
7
7
  # LDSETB <Ws>, <Wt>, [<Xn|SP>]
8
8
  # LDSETLB <Ws>, <Wt>, [<Xn|SP>]
9
- class LDSETB
9
+ class LDSETB < Instruction
10
10
  def initialize rs, rt, rn, a, r
11
- @rs = rs
12
- @rt = rt
13
- @rn = rn
14
- @a = a
15
- @r = r
11
+ @rs = check_mask(rs, 0x1f)
12
+ @rt = check_mask(rt, 0x1f)
13
+ @rn = check_mask(rn, 0x1f)
14
+ @a = check_mask(a, 0x01)
15
+ @r = check_mask(r, 0x01)
16
16
  end
17
17
 
18
18
  def encode
19
- LDSETB(@a, @r.to_i, @rs.to_i, @rn.to_i, @rt.to_i)
19
+ LDSETB(@a, @r, @rs, @rn, @rt)
20
20
  end
21
21
 
22
22
  private
23
23
 
24
24
  def LDSETB a, r, rs, rn, rt
25
25
  insn = 0b00_111_0_00_0_0_1_00000_0_011_00_00000_00000
26
- insn |= ((a & 0x1) << 23)
27
- insn |= ((r & 0x1) << 22)
28
- insn |= ((rs & 0x1f) << 16)
29
- insn |= ((rn & 0x1f) << 5)
30
- insn |= (rt & 0x1f)
26
+ insn |= ((a) << 23)
27
+ insn |= ((r) << 22)
28
+ insn |= ((rs) << 16)
29
+ insn |= ((rn) << 5)
30
+ insn |= (rt)
31
31
  insn
32
32
  end
33
33
  end
@@ -6,28 +6,28 @@ module AArch64
6
6
  # LDSETALH <Ws>, <Wt>, [<Xn|SP>]
7
7
  # LDSETH <Ws>, <Wt>, [<Xn|SP>]
8
8
  # LDSETLH <Ws>, <Wt>, [<Xn|SP>]
9
- class LDSETH
9
+ class LDSETH < Instruction
10
10
  def initialize rs, rt, rn, a, r
11
- @rs = rs
12
- @rt = rt
13
- @rn = rn
14
- @a = a
15
- @r = r
11
+ @rs = check_mask(rs, 0x1f)
12
+ @rt = check_mask(rt, 0x1f)
13
+ @rn = check_mask(rn, 0x1f)
14
+ @a = check_mask(a, 0x01)
15
+ @r = check_mask(r, 0x01)
16
16
  end
17
17
 
18
18
  def encode
19
- LDSETH(@a, @r.to_i, @rs.to_i, @rn.to_i, @rt.to_i)
19
+ LDSETH(@a, @r, @rs, @rn, @rt)
20
20
  end
21
21
 
22
22
  private
23
23
 
24
24
  def LDSETH a, r, rs, rn, rt
25
25
  insn = 0b01_111_0_00_0_0_1_00000_0_011_00_00000_00000
26
- insn |= ((a & 0x1) << 23)
27
- insn |= ((r & 0x1) << 22)
28
- insn |= ((rs & 0x1f) << 16)
29
- insn |= ((rn & 0x1f) << 5)
30
- insn |= (rt & 0x1f)
26
+ insn |= ((a) << 23)
27
+ insn |= ((r) << 22)
28
+ insn |= ((rs) << 16)
29
+ insn |= ((rn) << 5)
30
+ insn |= (rt)
31
31
  insn
32
32
  end
33
33
  end
@@ -10,30 +10,30 @@ module AArch64
10
10
  # LDSMAXA <Xs>, <Xt>, [<Xn|SP>]
11
11
  # LDSMAXAL <Xs>, <Xt>, [<Xn|SP>]
12
12
  # LDSMAXL <Xs>, <Xt>, [<Xn|SP>]
13
- class LDSMAX
13
+ class LDSMAX < Instruction
14
14
  def initialize rs, rt, rn, size, a, r
15
- @rs = rs
16
- @rt = rt
17
- @rn = rn
18
- @size = size
19
- @a = a
20
- @r = r
15
+ @rs = check_mask(rs, 0x1f)
16
+ @rt = check_mask(rt, 0x1f)
17
+ @rn = check_mask(rn, 0x1f)
18
+ @size = check_mask(size, 0x03)
19
+ @a = check_mask(a, 0x01)
20
+ @r = check_mask(r, 0x01)
21
21
  end
22
22
 
23
23
  def encode
24
- LDSMAX(@size, @a, @r.to_i, @rs.to_i, @rn.to_i, @rt.to_i)
24
+ LDSMAX(@size, @a, @r, @rs, @rn, @rt)
25
25
  end
26
26
 
27
27
  private
28
28
 
29
29
  def LDSMAX size, a, r, rs, rn, rt
30
30
  insn = 0b00_111_0_00_0_0_1_00000_0_100_00_00000_00000
31
- insn |= ((size & 0x3) << 30)
32
- insn |= ((a & 0x1) << 23)
33
- insn |= ((r & 0x1) << 22)
34
- insn |= ((rs & 0x1f) << 16)
35
- insn |= ((rn & 0x1f) << 5)
36
- insn |= (rt & 0x1f)
31
+ insn |= ((size) << 30)
32
+ insn |= ((a) << 23)
33
+ insn |= ((r) << 22)
34
+ insn |= ((rs) << 16)
35
+ insn |= ((rn) << 5)
36
+ insn |= (rt)
37
37
  insn
38
38
  end
39
39
  end
@@ -6,28 +6,28 @@ module AArch64
6
6
  # LDSMAXALB <Ws>, <Wt>, [<Xn|SP>]
7
7
  # LDSMAXB <Ws>, <Wt>, [<Xn|SP>]
8
8
  # LDSMAXLB <Ws>, <Wt>, [<Xn|SP>]
9
- class LDSMAXB
9
+ class LDSMAXB < Instruction
10
10
  def initialize rs, rt, rn, a, r
11
- @rs = rs
12
- @rt = rt
13
- @rn = rn
14
- @a = a
15
- @r = r
11
+ @rs = check_mask(rs, 0x1f)
12
+ @rt = check_mask(rt, 0x1f)
13
+ @rn = check_mask(rn, 0x1f)
14
+ @a = check_mask(a, 0x01)
15
+ @r = check_mask(r, 0x01)
16
16
  end
17
17
 
18
18
  def encode
19
- LDSMAXB(@a, @r.to_i, @rs.to_i, @rn.to_i, @rt.to_i)
19
+ LDSMAXB(@a, @r, @rs, @rn, @rt)
20
20
  end
21
21
 
22
22
  private
23
23
 
24
24
  def LDSMAXB a, r, rs, rn, rt
25
25
  insn = 0b00_111_0_00_0_0_1_00000_0_100_00_00000_00000
26
- insn |= ((a & 0x1) << 23)
27
- insn |= ((r & 0x1) << 22)
28
- insn |= ((rs & 0x1f) << 16)
29
- insn |= ((rn & 0x1f) << 5)
30
- insn |= (rt & 0x1f)
26
+ insn |= ((a) << 23)
27
+ insn |= ((r) << 22)
28
+ insn |= ((rs) << 16)
29
+ insn |= ((rn) << 5)
30
+ insn |= (rt)
31
31
  insn
32
32
  end
33
33
  end
@@ -6,28 +6,28 @@ module AArch64
6
6
  # LDSMAXALH <Ws>, <Wt>, [<Xn|SP>]
7
7
  # LDSMAXH <Ws>, <Wt>, [<Xn|SP>]
8
8
  # LDSMAXLH <Ws>, <Wt>, [<Xn|SP>]
9
- class LDSMAXH
9
+ class LDSMAXH < Instruction
10
10
  def initialize rs, rt, rn, a, r
11
- @rs = rs
12
- @rt = rt
13
- @rn = rn
14
- @a = a
15
- @r = r
11
+ @rs = check_mask(rs, 0x1f)
12
+ @rt = check_mask(rt, 0x1f)
13
+ @rn = check_mask(rn, 0x1f)
14
+ @a = check_mask(a, 0x01)
15
+ @r = check_mask(r, 0x01)
16
16
  end
17
17
 
18
18
  def encode
19
- LDSMAXH(@a, @r.to_i, @rs.to_i, @rn.to_i, @rt.to_i)
19
+ LDSMAXH(@a, @r, @rs, @rn, @rt)
20
20
  end
21
21
 
22
22
  private
23
23
 
24
24
  def LDSMAXH a, r, rs, rn, rt
25
25
  insn = 0b01_111_0_00_0_0_1_00000_0_100_00_00000_00000
26
- insn |= ((a & 0x1) << 23)
27
- insn |= ((r & 0x1) << 22)
28
- insn |= ((rs & 0x1f) << 16)
29
- insn |= ((rn & 0x1f) << 5)
30
- insn |= (rt & 0x1f)
26
+ insn |= ((a) << 23)
27
+ insn |= ((r) << 22)
28
+ insn |= ((rs) << 16)
29
+ insn |= ((rn) << 5)
30
+ insn |= (rt)
31
31
  insn
32
32
  end
33
33
  end
@@ -10,30 +10,30 @@ module AArch64
10
10
  # LDSMINA <Xs>, <Xt>, [<Xn|SP>]
11
11
  # LDSMINAL <Xs>, <Xt>, [<Xn|SP>]
12
12
  # LDSMINL <Xs>, <Xt>, [<Xn|SP>]
13
- class LDSMIN
13
+ class LDSMIN < Instruction
14
14
  def initialize rs, rt, rn, size, a, r
15
- @rs = rs
16
- @rt = rt
17
- @rn = rn
18
- @size = size
19
- @a = a
20
- @r = r
15
+ @rs = check_mask(rs, 0x1f)
16
+ @rt = check_mask(rt, 0x1f)
17
+ @rn = check_mask(rn, 0x1f)
18
+ @size = check_mask(size, 0x03)
19
+ @a = check_mask(a, 0x01)
20
+ @r = check_mask(r, 0x01)
21
21
  end
22
22
 
23
23
  def encode
24
- LDSMIN(@size, @a, @r.to_i, @rs.to_i, @rn.to_i, @rt.to_i)
24
+ LDSMIN(@size, @a, @r, @rs, @rn, @rt)
25
25
  end
26
26
 
27
27
  private
28
28
 
29
29
  def LDSMIN size, a, r, rs, rn, rt
30
30
  insn = 0b00_111_0_00_0_0_1_00000_0_101_00_00000_00000
31
- insn |= ((size & 0x3) << 30)
32
- insn |= ((a & 0x1) << 23)
33
- insn |= ((r & 0x1) << 22)
34
- insn |= ((rs & 0x1f) << 16)
35
- insn |= ((rn & 0x1f) << 5)
36
- insn |= (rt & 0x1f)
31
+ insn |= ((size) << 30)
32
+ insn |= ((a) << 23)
33
+ insn |= ((r) << 22)
34
+ insn |= ((rs) << 16)
35
+ insn |= ((rn) << 5)
36
+ insn |= (rt)
37
37
  insn
38
38
  end
39
39
  end
@@ -6,28 +6,28 @@ module AArch64
6
6
  # LDSMINALB <Ws>, <Wt>, [<Xn|SP>]
7
7
  # LDSMINB <Ws>, <Wt>, [<Xn|SP>]
8
8
  # LDSMINLB <Ws>, <Wt>, [<Xn|SP>]
9
- class LDSMINB
9
+ class LDSMINB < Instruction
10
10
  def initialize rs, rt, rn, a, r
11
- @rs = rs
12
- @rt = rt
13
- @rn = rn
14
- @a = a
15
- @r = r
11
+ @rs = check_mask(rs, 0x1f)
12
+ @rt = check_mask(rt, 0x1f)
13
+ @rn = check_mask(rn, 0x1f)
14
+ @a = check_mask(a, 0x01)
15
+ @r = check_mask(r, 0x01)
16
16
  end
17
17
 
18
18
  def encode
19
- LDSMINB(@a, @r.to_i, @rs.to_i, @rn.to_i, @rt.to_i)
19
+ LDSMINB(@a, @r, @rs, @rn, @rt)
20
20
  end
21
21
 
22
22
  private
23
23
 
24
24
  def LDSMINB a, r, rs, rn, rt
25
25
  insn = 0b00_111_0_00_0_0_1_00000_0_101_00_00000_00000
26
- insn |= ((a & 0x1) << 23)
27
- insn |= ((r & 0x1) << 22)
28
- insn |= ((rs & 0x1f) << 16)
29
- insn |= ((rn & 0x1f) << 5)
30
- insn |= (rt & 0x1f)
26
+ insn |= ((a) << 23)
27
+ insn |= ((r) << 22)
28
+ insn |= ((rs) << 16)
29
+ insn |= ((rn) << 5)
30
+ insn |= (rt)
31
31
  insn
32
32
  end
33
33
  end
@@ -6,28 +6,28 @@ module AArch64
6
6
  # LDSMINALH <Ws>, <Wt>, [<Xn|SP>]
7
7
  # LDSMINH <Ws>, <Wt>, [<Xn|SP>]
8
8
  # LDSMINLH <Ws>, <Wt>, [<Xn|SP>]
9
- class LDSMINH
9
+ class LDSMINH < Instruction
10
10
  def initialize rs, rt, rn, a, r
11
- @rs = rs
12
- @rt = rt
13
- @rn = rn
14
- @a = a
15
- @r = r
11
+ @rs = check_mask(rs, 0x1f)
12
+ @rt = check_mask(rt, 0x1f)
13
+ @rn = check_mask(rn, 0x1f)
14
+ @a = check_mask(a, 0x01)
15
+ @r = check_mask(r, 0x01)
16
16
  end
17
17
 
18
18
  def encode
19
- LDSMINH(@a, @r.to_i, @rs.to_i, @rn.to_i, @rt.to_i)
19
+ LDSMINH(@a, @r, @rs, @rn, @rt)
20
20
  end
21
21
 
22
22
  private
23
23
 
24
24
  def LDSMINH a, r, rs, rn, rt
25
25
  insn = 0b01_111_0_00_0_0_1_00000_0_101_00_00000_00000
26
- insn |= ((a & 0x1) << 23)
27
- insn |= ((r & 0x1) << 22)
28
- insn |= ((rs & 0x1f) << 16)
29
- insn |= ((rn & 0x1f) << 5)
30
- insn |= (rt & 0x1f)
26
+ insn |= ((a) << 23)
27
+ insn |= ((r) << 22)
28
+ insn |= ((rs) << 16)
29
+ insn |= ((rn) << 5)
30
+ insn |= (rt)
31
31
  insn
32
32
  end
33
33
  end