aarch64 1.0.1 → 2.0.0

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
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-  data.tar.gz: df47808a244cedf79c32481681dc7328324ce973afdab9c8227753940deddbb8
+  metadata.gz: e04700eac89cfbce749a76679b4e7d408bf59bc8eaec3e208b6ed5742dbad36a
+  data.tar.gz: 7cfd0854a30b04974127ab7f5ed53d36e1fd04742c4a36893195e00e3a973c9f
 SHA512:
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-  data.tar.gz: fb1ed26e0d5ada7e3a9454e633965fc0d4c2d1c60aa238cae45eb83143814f0654d87e64c9bf5fe6916d90bd47bb65e2851798de3da652f654ce261d84ab0084
+  metadata.gz: c3476189b664bdec820cf5c8fe5e1243c85aa5fd73f1e5994c71db193f32b00f24e32fb3892415a03c865fedc760f33a8e266681e688e4d4ff753a1c6ffab25e
+  data.tar.gz: 1d37e4223349cf1b6360f1704344dcde6812124684dbe23079d6c1d07d529707f4f89b281f5b724ae6ef65cdddd2ec111d984721033bf815dec61cdc92c60a62

data/README.md

@@ -25,7 +25,7 @@ asm.pretty do
 end
 
 # Write the instructions to a JIT buffer
-jit_buffer.writable!
+jit_buffer.writeable!
 asm.write_to jit_buffer
 jit_buffer.executable!
 

data/Rakefile

@@ -160,6 +160,12 @@ file SYSTEM_REGS_FILE do |t|
   download SYSTEM_REGS_URL, t.name
 end
 
+rule ".tab.rb" => [".y"] do |t|
+  puts "#" * 90
+  sh "gel exec racc -E -v #{t.source}"
+  puts "#" * 90
+end
+
 Rake::TestTask.new(:test) do |t|
   t.libs << "test/lib" << "test"
   t.test_files = FileList['test/**/*_test.rb']
@@ -167,4 +173,35 @@ Rake::TestTask.new(:test) do |t|
   t.warning = true
 end
 
+task :test => "lib/aarch64/parser.tab.rb"
+
 task :default => :test
+
+task "autotest" do
+  basedir = File.dirname(__FILE__)
+  libdir = File.join basedir, "lib"
+  testdir = File.join basedir, "test"
+
+  IO.popen(["fswatch", libdir, testdir]) do |io|
+    loop do
+      line = io.readline.chomp
+      case line
+      when /^#{libdir}/
+        # If the libdir changes, run all tests
+        begin
+          sh "gel exec rake test"
+        rescue
+        end
+      when /^#{testdir}/
+        # If the testdir changes, run the test
+        test_file = line.delete_prefix(testdir + "/")
+        begin
+          sh "gel exec rake test TESTS=#{test_file}" if test_file =~ /_test.rb/
+        rescue
+        end
+      else
+        raise "wat: #{line}"
+      end
+    end
+  end
+end

data/aarch64.gemspec

@@ -18,4 +18,5 @@ Gem::Specification.new do |s|
   s.add_development_dependency 'jit_buffer', '~> 1.0.0'
   s.add_development_dependency 'minitest', '~> 5.15'
   s.add_development_dependency 'rake', '~> 13.0'
+  s.add_development_dependency 'racc', '~> 1.6'
 end

data/lib/aarch64/instructions/adc.rb

@@ -4,26 +4,26 @@ module AArch64
     # Add with Carry
     # ADC  <Wd>, <Wn>, <Wm>
     # ADC  <Xd>, <Xn>, <Xm>
-    class ADC
+    class ADC < Instruction
       def initialize rd, rn, rm, sf
-        @rd = rd
-        @rn = rn
-        @rm = rm
-        @sf = sf
+        @rd = check_mask(rd, 0x1f)
+        @rn = check_mask(rn, 0x1f)
+        @rm = check_mask(rm, 0x1f)
+        @sf = check_mask(sf, 0x01)
       end
 
       def encode
-        ADC(@sf, @rm.to_i, @rn.to_i, @rd.to_i)
+        ADC(@sf, @rm, @rn, @rd)
       end
 
       private
 
       def ADC sf, rm, rn, rd
         insn = 0b0_0_0_11010000_00000_000000_00000_00000
-        insn |= ((sf & 0x1) << 31)
-        insn |= ((rm & 0x1f) << 16)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rd & 0x1f)
+        insn |= ((sf) << 31)
+        insn |= ((rm) << 16)
+        insn |= ((rn) << 5)
+        insn |= (rd)
         insn
       end
     end

data/lib/aarch64/instructions/adcs.rb

@@ -3,26 +3,26 @@ module AArch64
     # ADCS -- A64
     # Add with Carry, setting flags
     # ADCS  <Wd>, <Wn>, <Wm>
-    class ADCS
+    class ADCS < Instruction
       def initialize rd, rn, rm, sf
-        @rd = rd
-        @rn = rn
-        @rm = rm
-        @sf = sf
+        @rd = check_mask(rd, 0x1f)
+        @rn = check_mask(rn, 0x1f)
+        @rm = check_mask(rm, 0x1f)
+        @sf = check_mask(sf, 0x01)
       end
 
       def encode
-        ADCS(@sf, @rm.to_i, @rn.to_i, @rd.to_i)
+        ADCS(@sf, @rm, @rn, @rd)
       end
 
       private
 
       def ADCS sf, rm, rn, rd
         insn = 0b0_0_1_11010000_00000_000000_00000_00000
-        insn |= ((sf & 0x1) << 31)
-        insn |= ((rm & 0x1f) << 16)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rd & 0x1f)
+        insn |= ((sf) << 31)
+        insn |= ((rm) << 16)
+        insn |= ((rn) << 5)
+        insn |= (rd)
         insn
       end
     end

data/lib/aarch64/instructions/add_addsub_ext.rb

@@ -4,30 +4,30 @@ module AArch64
     # Add (extended register)
     # ADD  <Wd|WSP>, <Wn|WSP>, <Wm>{, <extend> {#<amount>}}
     # ADD  <Xd|SP>, <Xn|SP>, <R><m>{, <extend> {#<amount>}}
-    class ADD_addsub_ext
+    class ADD_addsub_ext < Instruction
       def initialize rd, rn, rm, extend, amount, sf
-        @rd     = rd
-        @rn     = rn
-        @rm     = rm
-        @extend = extend
-        @amount = amount
-        @sf     = sf
+        @rd     = check_mask(rd, 0x1f)
+        @rn     = check_mask(rn, 0x1f)
+        @rm     = check_mask(rm, 0x1f)
+        @extend = check_mask(extend, 0x07)
+        @amount = check_mask(amount, 0x07)
+        @sf     = check_mask(sf, 0x01)
       end
 
       def encode
-        ADD_addsub_ext(@sf, @rm.to_i, @extend, @amount, @rn.to_i, @rd.to_i)
+        ADD_addsub_ext(@sf, @rm, @extend, @amount, @rn, @rd)
       end
 
       private
 
       def ADD_addsub_ext sf, rm, option, imm3, rn, rd
         insn = 0b0_0_0_01011_00_1_00000_000_000_00000_00000
-        insn |= ((sf & 0x1) << 31)
-        insn |= ((rm & 0x1f) << 16)
-        insn |= ((option & 0x7) << 13)
-        insn |= ((imm3 & 0x7) << 10)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rd & 0x1f)
+        insn |= ((sf) << 31)
+        insn |= ((rm) << 16)
+        insn |= ((option) << 13)
+        insn |= ((imm3) << 10)
+        insn |= ((rn) << 5)
+        insn |= (rd)
         insn
       end
     end

data/lib/aarch64/instructions/add_addsub_imm.rb

@@ -3,28 +3,28 @@ module AArch64
     # ADD (immediate) -- A64
     # Add (immediate)
     # ADD  <Wd|WSP>, <Wn|WSP>, #<imm>{, <shift>}
-    class ADD_addsub_imm
+    class ADD_addsub_imm < Instruction
       def initialize rd, rn, imm12, sh, sf
-        @rd    = rd
-        @rn    = rn
-        @imm12 = imm12
-        @sh    = sh
-        @sf    = sf
+        @rd    = check_mask(rd, 0x1f)
+        @rn    = check_mask(rn, 0x1f)
+        @imm12 = check_mask(imm12, 0xfff)
+        @sh    = check_mask(sh, 0x01)
+        @sf    = check_mask(sf, 0x01)
       end
 
       def encode
-        ADD_addsub_imm(@sf, @sh, @imm12, @rn.to_i, @rd.to_i)
+        ADD_addsub_imm(@sf, @sh, @imm12, @rn, @rd)
       end
 
       private
 
       def ADD_addsub_imm sf, sh, imm12, rn, rd
         insn = 0b0_0_0_100010_0_000000000000_00000_00000
-        insn |= ((sf & 0x1) << 31)
-        insn |= ((sh & 0x1) << 22)
-        insn |= ((imm12 & 0xfff) << 10)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rd & 0x1f)
+        insn |= ((sf) << 31)
+        insn |= ((sh) << 22)
+        insn |= ((imm12) << 10)
+        insn |= ((rn) << 5)
+        insn |= (rd)
         insn
       end
     end

data/lib/aarch64/instructions/add_addsub_shift.rb

@@ -4,30 +4,30 @@ module AArch64
     # Add (shifted register)
     # ADD  <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
     # ADD  <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
-    class ADD_addsub_shift
+    class ADD_addsub_shift < Instruction
       def initialize xd, xn, xm, shift, amount, sf
-        @xd     = xd
-        @xn     = xn
-        @xm     = xm
-        @shift  = shift
-        @amount = amount
-        @sf     = sf
+        @xd     = check_mask(xd, 0x1f)
+        @xn     = check_mask(xn, 0x1f)
+        @xm     = check_mask(xm, 0x1f)
+        @shift  = check_mask(shift, 0x03)
+        @amount = check_mask(amount, 0x3f)
+        @sf     = check_mask(sf, 0x01)
       end
 
       def encode
-        ADD_addsub_shift(@sf, @shift, @xm.to_i, @amount, @xn.to_i, @xd.to_i)
+        ADD_addsub_shift(@sf, @shift, @xm, @amount, @xn, @xd)
       end
 
       private
 
       def ADD_addsub_shift sf, shift, rm, imm6, rn, rd
         insn = 0b0_0_0_01011_00_0_00000_000000_00000_00000
-        insn |= ((sf & 0x1) << 31)
-        insn |= ((shift & 0x3) << 22)
-        insn |= ((rm & 0x1f) << 16)
-        insn |= ((imm6 & 0x3f) << 10)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rd & 0x1f)
+        insn |= ((sf) << 31)
+        insn |= ((shift) << 22)
+        insn |= ((rm) << 16)
+        insn |= ((imm6) << 10)
+        insn |= ((rn) << 5)
+        insn |= (rd)
         insn
       end
     end

data/lib/aarch64/instructions/addg.rb

@@ -3,26 +3,26 @@ module AArch64
     # ADDG -- A64
     # Add with Tag
     # ADDG  <Xd|SP>, <Xn|SP>, #<uimm6>, #<uimm4>
-    class ADDG
+    class ADDG < Instruction
       def initialize xd, xn, imm6, imm4
-        @xd   = xd
-        @xn   = xn
-        @imm6 = imm6
-        @imm4 = imm4
+        @xd   = check_mask(xd, 0x1f)
+        @xn   = check_mask(xn, 0x1f)
+        @imm6 = check_mask(imm6, 0x3f)
+        @imm4 = check_mask(imm4, 0x0f)
       end
 
       def encode
-        ADDG(@imm6, @imm4, @xn.to_i, @xd.to_i)
+        ADDG(@imm6, @imm4, @xn, @xd)
       end
 
       private
 
       def ADDG uimm6, uimm4, xn, xd
         insn = 0b1_0_0_100011_0_000000_00_0000_00000_00000
-        insn |= ((uimm6 & 0x3f) << 16)
-        insn |= ((uimm4 & 0xf) << 10)
-        insn |= ((xn & 0x1f) << 5)
-        insn |= (xd & 0x1f)
+        insn |= ((uimm6) << 16)
+        insn |= ((uimm4) << 10)
+        insn |= ((xn) << 5)
+        insn |= (xd)
         insn
       end
     end

data/lib/aarch64/instructions/adds_addsub_ext.rb

@@ -4,30 +4,30 @@ module AArch64
     # Add (extended register), setting flags
     # ADDS  <Wd>, <Wn|WSP>, <Wm>{, <extend> {#<amount>}}
     # ADDS  <Xd>, <Xn|SP>, <R><m>{, <extend> {#<amount>}}
-    class ADDS_addsub_ext
+    class ADDS_addsub_ext < Instruction
       def initialize d, n, m, extend, amount, sf
-        @d      = d
-        @n      = n
-        @m      = m
-        @extend = extend
-        @amount = amount
-        @sf     = sf
+        @d      = check_mask(d, 0x1f)
+        @n      = check_mask(n, 0x1f)
+        @m      = check_mask(m, 0x1f)
+        @extend = check_mask(extend, 0x07)
+        @amount = check_mask(amount, 0x07)
+        @sf     = check_mask(sf, 0x01)
       end
 
       def encode
-        ADDS_addsub_ext(@sf, @m.to_i, @extend, @amount, @n.to_i, @d.to_i)
+        ADDS_addsub_ext(@sf, @m, @extend, @amount, @n, @d)
       end
 
       private
 
       def ADDS_addsub_ext sf, rm, option, imm3, rn, rd
         insn = 0b0_0_1_01011_00_1_00000_000_000_00000_00000
-        insn |= ((sf & 0x1) << 31)
-        insn |= ((rm & 0x1f) << 16)
-        insn |= ((option & 0x7) << 13)
-        insn |= ((imm3 & 0x7) << 10)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rd & 0x1f)
+        insn |= ((sf) << 31)
+        insn |= ((rm) << 16)
+        insn |= ((option) << 13)
+        insn |= ((imm3) << 10)
+        insn |= ((rn) << 5)
+        insn |= (rd)
         insn
       end
     end

data/lib/aarch64/instructions/adds_addsub_imm.rb

@@ -4,28 +4,28 @@ module AArch64
     # Add (immediate), setting flags
     # ADDS  <Wd>, <Wn|WSP>, #<imm>{, <shift>}
     # ADDS  <Xd>, <Xn|SP>, #<imm>{, <shift>}
-    class ADDS_addsub_imm
+    class ADDS_addsub_imm < Instruction
       def initialize d, n, imm, shift, sf
-        @d     = d
-        @n     = n
-        @imm   = imm
-        @shift = shift
-        @sf    = sf
+        @d     = check_mask(d, 0x1f)
+        @n     = check_mask(n, 0x1f)
+        @imm   = check_mask(imm, 0xfff)
+        @shift = check_mask(shift, 0x01)
+        @sf    = check_mask(sf, 0x01)
       end
 
       def encode
-        ADDS_addsub_imm(@sf, @shift, @imm, @n.to_i, @d.to_i)
+        ADDS_addsub_imm(@sf, @shift, @imm, @n, @d)
       end
 
       private
 
       def ADDS_addsub_imm sf, sh, imm12, rn, rd
         insn = 0b0_0_1_100010_0_000000000000_00000_00000
-        insn |= ((sf & 0x1) << 31)
-        insn |= ((sh & 0x1) << 22)
-        insn |= ((imm12 & 0xfff) << 10)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rd & 0x1f)
+        insn |= ((sf) << 31)
+        insn |= ((sh) << 22)
+        insn |= ((imm12) << 10)
+        insn |= ((rn) << 5)
+        insn |= (rd)
         insn
       end
     end

data/lib/aarch64/instructions/adds_addsub_shift.rb

@@ -4,30 +4,30 @@ module AArch64
     # Add (shifted register), setting flags
     # ADDS  <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
     # ADDS  <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
-    class ADDS_addsub_shift
+    class ADDS_addsub_shift < Instruction
       def initialize xd, xn, xm, shift, amount, sf
-        @xd     = xd
-        @xn     = xn
-        @xm     = xm
-        @shift  = shift
-        @amount = amount
-        @sf     = sf
+        @xd     = check_mask(xd, 0x1f)
+        @xn     = check_mask(xn, 0x1f)
+        @xm     = check_mask(xm, 0x1f)
+        @shift  = check_mask(shift, 0x03)
+        @amount = check_mask(amount, 0x3f)
+        @sf     = check_mask(sf, 0x01)
       end
 
       def encode
-        ADDS_addsub_shift(@sf, @shift, @xm.to_i, @amount, @xn.to_i, @xd.to_i)
+        ADDS_addsub_shift(@sf, @shift, @xm, @amount, @xn, @xd)
       end
 
       private
 
       def ADDS_addsub_shift sf, shift, rm, imm6, rn, rd
         insn = 0b0_0_1_01011_00_0_00000_000000_00000_00000
-        insn |= ((sf & 0x1) << 31)
-        insn |= ((shift & 0x3) << 22)
-        insn |= ((rm & 0x1f) << 16)
-        insn |= ((imm6 & 0x3f) << 10)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rd & 0x1f)
+        insn |= ((sf) << 31)
+        insn |= ((shift) << 22)
+        insn |= ((rm) << 16)
+        insn |= ((imm6) << 10)
+        insn |= ((rn) << 5)
+        insn |= (rd)
         insn
       end
     end

data/lib/aarch64/instructions/adr.rb

@@ -3,24 +3,24 @@ module AArch64
     # ADR -- A64
     # Form PC-relative address
     # ADR  <Xd>, <label>
-    class ADR
+    class ADR < Instruction
       def initialize xd, label
-        @xd    = xd
+        @xd    = check_mask(xd, 0x1f)
         @label = label
       end
 
       def encode
-        label = @label.to_i
-        ADR(label, label >> 2, @xd.to_i)
+        label = @label.unwrap_label
+        ADR(label & 0x3, check_mask((label >> 2), 0x7ffff), @xd)
       end
 
       private
 
       def ADR immlo, immhi, rd
         insn = 0b0_00_10000_0000000000000000000_00000
-        insn |= ((immlo & 0x3) << 29)
-        insn |= ((immhi & 0x7ffff) << 5)
-        insn |= (rd & 0x1f)
+        insn |= (immlo << 29)
+        insn |= (immhi << 5)
+        insn |= rd
         insn
       end
     end

data/lib/aarch64/instructions/adrp.rb

@@ -3,24 +3,24 @@ module AArch64
     # ADRP -- A64
     # Form PC-relative address to 4KB page
     # ADRP  <Xd>, <label>
-    class ADRP
+    class ADRP < Instruction
       def initialize xd, label
-        @xd    = xd
+        @xd    = check_mask(xd, 0x1f)
         @label = label
       end
 
       def encode
-        label = @label.to_i / 1000
-        ADRP(label, label >> 2, @xd.to_i)
+        label = @label / 4096
+        ADRP(label & 0x3, check_mask(label >> 2, 0x7ffff), @xd)
       end
 
       private
 
       def ADRP immlo, immhi, rd
         insn = 0b1_00_10000_0000000000000000000_00000
-        insn |= ((immlo & 0x3) << 29)
-        insn |= ((immhi & 0x7ffff) << 5)
-        insn |= (rd & 0x1f)
+        insn |= (immlo << 29)
+        insn |= (immhi << 5)
+        insn |= rd
         insn
       end
     end

data/lib/aarch64/instructions/and_log_imm.rb

@@ -4,30 +4,30 @@ module AArch64
     # Bitwise AND (immediate)
     # AND  <Wd|WSP>, <Wn>, #<imm>
     # AND  <Xd|SP>, <Xn>, #<imm>
-    class AND_log_imm
+    class AND_log_imm < Instruction
       def initialize rd, rn, immr, imms, n, sf
-        @rd   = rd
-        @rn   = rn
-        @immr = immr
-        @imms = imms
-        @n    = n
-        @sf   = sf
+        @rd   = check_mask(rd, 0x1f)
+        @rn   = check_mask(rn, 0x1f)
+        @immr = check_mask(immr, 0x3f)
+        @imms = check_mask(imms, 0x3f)
+        @n    = check_mask(n, 0x01)
+        @sf   = check_mask(sf, 0x01)
       end
 
       def encode
-        AND_log_imm(@sf, @n, @immr, @imms, @rn.to_i, @rd.to_i)
+        AND_log_imm(@sf, @n, @immr, @imms, @rn, @rd)
       end
 
       private
 
       def AND_log_imm sf, n, immr, imms, rn, rd
         insn = 0b0_00_100100_0_000000_000000_00000_00000
-        insn |= ((sf & 0x1) << 31)
-        insn |= ((n & 0x1) << 22)
-        insn |= ((immr & 0x3f) << 16)
-        insn |= ((imms & 0x3f) << 10)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rd & 0x1f)
+        insn |= ((sf) << 31)
+        insn |= ((n) << 22)
+        insn |= ((immr) << 16)
+        insn |= ((imms) << 10)
+        insn |= ((rn) << 5)
+        insn |= (rd)
         insn
       end
     end

data/lib/aarch64/instructions/and_log_shift.rb

@@ -4,30 +4,30 @@ module AArch64
     # Bitwise AND (shifted register)
     # AND  <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
     # AND  <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
-    class AND_log_shift
+    class AND_log_shift < Instruction
       def initialize xd, xn, xm, shift, amount, sf
-        @xd     = xd
-        @xn     = xn
-        @xm     = xm
-        @shift  = shift
-        @amount = amount
-        @sf     = sf
+        @xd     = check_mask(xd, 0x1f)
+        @xn     = check_mask(xn, 0x1f)
+        @xm     = check_mask(xm, 0x1f)
+        @shift  = check_mask(shift, 0x03)
+        @amount = check_mask(amount, 0x3f)
+        @sf     = check_mask(sf, 0x01)
       end
 
       def encode
-        AND_log_shift(@sf, @shift, @xm.to_i, @amount, @xn.to_i, @xd.to_i)
+        AND_log_shift(@sf, @shift, @xm, @amount, @xn, @xd)
       end
 
       private
 
       def AND_log_shift sf, shift, rm, imm6, rn, rd
         insn = 0b0_00_01010_00_0_00000_000000_00000_00000
-        insn |= ((sf & 0x1) << 31)
-        insn |= ((shift & 0x3) << 22)
-        insn |= ((rm & 0x1f) << 16)
-        insn |= ((imm6 & 0x3f) << 10)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rd & 0x1f)
+        insn |= ((sf) << 31)
+        insn |= ((shift) << 22)
+        insn |= ((rm) << 16)
+        insn |= ((imm6) << 10)
+        insn |= ((rn) << 5)
+        insn |= (rd)
         insn
       end
     end

data/lib/aarch64/instructions/ands_log_imm.rb

@@ -4,30 +4,30 @@ module AArch64
     # Bitwise AND (immediate), setting flags
     # ANDS  <Wd>, <Wn>, #<imm>
     # ANDS  <Xd>, <Xn>, #<imm>
-    class ANDS_log_imm
+    class ANDS_log_imm < Instruction
       def initialize rd, rn, immr, imms, n, sf
-        @rd   = rd
-        @rn   = rn
-        @immr = immr
-        @imms = imms
-        @n    = n
-        @sf   = sf
+        @rd   = check_mask(rd, 0x1f)
+        @rn   = check_mask(rn, 0x1f)
+        @immr = check_mask(immr, 0x3f)
+        @imms = check_mask(imms, 0x3f)
+        @n    = check_mask(n, 0x01)
+        @sf   = check_mask(sf, 0x01)
       end
 
       def encode
-        ANDS_log_imm(@sf, @n, @immr, @imms, @rn.to_i, @rd.to_i)
+        ANDS_log_imm(@sf, @n, @immr, @imms, @rn, @rd)
       end
 
       private
 
       def ANDS_log_imm sf, n, immr, imms, rn, rd
         insn = 0b0_11_100100_0_000000_000000_00000_00000
-        insn |= ((sf & 0x1) << 31)
-        insn |= ((n & 0x1) << 22)
-        insn |= ((immr & 0x3f) << 16)
-        insn |= ((imms & 0x3f) << 10)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rd & 0x1f)
+        insn |= ((sf) << 31)
+        insn |= ((n) << 22)
+        insn |= ((immr) << 16)
+        insn |= ((imms) << 10)
+        insn |= ((rn) << 5)
+        insn |= (rd)
         insn
       end
     end