aarch64 1.0.1 → 2.0.0
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- checksums.yaml +4 -4
- data/README.md +1 -1
- data/Rakefile +37 -0
- data/aarch64.gemspec +1 -0
- data/lib/aarch64/instructions/adc.rb +10 -10
- data/lib/aarch64/instructions/adcs.rb +10 -10
- data/lib/aarch64/instructions/add_addsub_ext.rb +14 -14
- data/lib/aarch64/instructions/add_addsub_imm.rb +12 -12
- data/lib/aarch64/instructions/add_addsub_shift.rb +14 -14
- data/lib/aarch64/instructions/addg.rb +10 -10
- data/lib/aarch64/instructions/adds_addsub_ext.rb +14 -14
- data/lib/aarch64/instructions/adds_addsub_imm.rb +12 -12
- data/lib/aarch64/instructions/adds_addsub_shift.rb +14 -14
- data/lib/aarch64/instructions/adr.rb +7 -7
- data/lib/aarch64/instructions/adrp.rb +7 -7
- data/lib/aarch64/instructions/and_log_imm.rb +14 -14
- data/lib/aarch64/instructions/and_log_shift.rb +14 -14
- data/lib/aarch64/instructions/ands_log_imm.rb +14 -14
- data/lib/aarch64/instructions/ands_log_shift.rb +14 -14
- data/lib/aarch64/instructions/asrv.rb +10 -10
- data/lib/aarch64/instructions/autda.rb +9 -12
- data/lib/aarch64/instructions/autdb.rb +9 -12
- data/lib/aarch64/instructions/autia.rb +9 -12
- data/lib/aarch64/instructions/autib.rb +9 -12
- data/lib/aarch64/instructions/axflag.rb +1 -1
- data/lib/aarch64/instructions/b_cond.rb +5 -5
- data/lib/aarch64/instructions/b_uncond.rb +3 -3
- data/lib/aarch64/instructions/bc_cond.rb +5 -5
- data/lib/aarch64/instructions/bfm.rb +13 -13
- data/lib/aarch64/instructions/bic_log_shift.rb +14 -14
- data/lib/aarch64/instructions/bics.rb +14 -14
- data/lib/aarch64/instructions/bl.rb +3 -3
- data/lib/aarch64/instructions/blr.rb +4 -4
- data/lib/aarch64/instructions/blra.rb +10 -10
- data/lib/aarch64/instructions/br.rb +4 -4
- data/lib/aarch64/instructions/bra.rb +10 -10
- data/lib/aarch64/instructions/brk.rb +3 -3
- data/lib/aarch64/instructions/bti.rb +3 -3
- data/lib/aarch64/instructions/cas.rb +14 -14
- data/lib/aarch64/instructions/casb.rb +12 -12
- data/lib/aarch64/instructions/cash.rb +12 -12
- data/lib/aarch64/instructions/casp.rb +14 -14
- data/lib/aarch64/instructions/cbnz.rb +7 -7
- data/lib/aarch64/instructions/cbz.rb +7 -7
- data/lib/aarch64/instructions/ccmn_imm.rb +12 -12
- data/lib/aarch64/instructions/ccmn_reg.rb +12 -12
- data/lib/aarch64/instructions/ccmp_imm.rb +12 -12
- data/lib/aarch64/instructions/ccmp_reg.rb +12 -12
- data/lib/aarch64/instructions/cfinv.rb +2 -9
- data/lib/aarch64/instructions/clrex.rb +3 -3
- data/lib/aarch64/instructions/cls_int.rb +8 -8
- data/lib/aarch64/instructions/clz_int.rb +8 -8
- data/lib/aarch64/instructions/crc32.rb +12 -12
- data/lib/aarch64/instructions/crc32c.rb +12 -12
- data/lib/aarch64/instructions/csdb.rb +1 -1
- data/lib/aarch64/instructions/csel.rb +12 -12
- data/lib/aarch64/instructions/csinc.rb +12 -12
- data/lib/aarch64/instructions/csinv.rb +12 -12
- data/lib/aarch64/instructions/csneg.rb +12 -12
- data/lib/aarch64/instructions/dcps.rb +5 -5
- data/lib/aarch64/instructions/dgh.rb +1 -1
- data/lib/aarch64/instructions/dmb.rb +3 -3
- data/lib/aarch64/instructions/drps.rb +2 -9
- data/lib/aarch64/instructions/dsb.rb +3 -3
- data/lib/aarch64/instructions/eon.rb +14 -14
- data/lib/aarch64/instructions/eor_log_imm.rb +14 -14
- data/lib/aarch64/instructions/eor_log_shift.rb +14 -14
- data/lib/aarch64/instructions/eret.rb +2 -9
- data/lib/aarch64/instructions/ereta.rb +3 -3
- data/lib/aarch64/instructions/esb.rb +1 -1
- data/lib/aarch64/instructions/extr.rb +13 -13
- data/lib/aarch64/instructions/gmi.rb +8 -8
- data/lib/aarch64/instructions/hint.rb +5 -5
- data/lib/aarch64/instructions/hlt.rb +3 -3
- data/lib/aarch64/instructions/hvc.rb +3 -3
- data/lib/aarch64/instructions/irg.rb +8 -8
- data/lib/aarch64/instructions/isb.rb +3 -3
- data/lib/aarch64/instructions/ld64b.rb +6 -6
- data/lib/aarch64/instructions/ldadd.rb +14 -14
- data/lib/aarch64/instructions/ldaddb.rb +12 -12
- data/lib/aarch64/instructions/ldaddh.rb +12 -12
- data/lib/aarch64/instructions/ldapr.rb +8 -8
- data/lib/aarch64/instructions/ldaprb.rb +6 -6
- data/lib/aarch64/instructions/ldaprh.rb +6 -6
- data/lib/aarch64/instructions/ldapur_gen.rb +12 -12
- data/lib/aarch64/instructions/ldar.rb +8 -8
- data/lib/aarch64/instructions/ldaxp.rb +10 -10
- data/lib/aarch64/instructions/ldaxr.rb +8 -8
- data/lib/aarch64/instructions/ldclr.rb +14 -14
- data/lib/aarch64/instructions/ldclrb.rb +14 -14
- data/lib/aarch64/instructions/ldeor.rb +14 -14
- data/lib/aarch64/instructions/ldg.rb +8 -8
- data/lib/aarch64/instructions/ldgm.rb +6 -6
- data/lib/aarch64/instructions/ldlar.rb +8 -8
- data/lib/aarch64/instructions/ldnp_gen.rb +12 -12
- data/lib/aarch64/instructions/ldp_gen.rb +14 -14
- data/lib/aarch64/instructions/ldpsw.rb +12 -12
- data/lib/aarch64/instructions/ldr_imm_gen.rb +12 -12
- data/lib/aarch64/instructions/ldr_imm_unsigned.rb +10 -10
- data/lib/aarch64/instructions/ldr_lit_gen.rb +7 -7
- data/lib/aarch64/instructions/ldr_reg_gen.rb +14 -14
- data/lib/aarch64/instructions/ldra.rb +14 -14
- data/lib/aarch64/instructions/ldrb_imm.rb +10 -10
- data/lib/aarch64/instructions/ldrb_reg.rb +12 -12
- data/lib/aarch64/instructions/ldrb_unsigned.rb +8 -8
- data/lib/aarch64/instructions/ldrh_imm.rb +10 -10
- data/lib/aarch64/instructions/ldrh_reg.rb +12 -12
- data/lib/aarch64/instructions/ldrh_unsigned.rb +8 -8
- data/lib/aarch64/instructions/ldrsb_imm.rb +12 -12
- data/lib/aarch64/instructions/ldrsb_reg.rb +14 -14
- data/lib/aarch64/instructions/ldrsb_unsigned.rb +10 -10
- data/lib/aarch64/instructions/ldrsh_imm.rb +12 -12
- data/lib/aarch64/instructions/ldrsh_reg.rb +14 -14
- data/lib/aarch64/instructions/ldrsh_unsigned.rb +10 -10
- data/lib/aarch64/instructions/ldrsw_imm.rb +10 -10
- data/lib/aarch64/instructions/ldrsw_lit.rb +5 -5
- data/lib/aarch64/instructions/ldrsw_reg.rb +12 -12
- data/lib/aarch64/instructions/ldrsw_unsigned.rb +8 -8
- data/lib/aarch64/instructions/ldset.rb +14 -14
- data/lib/aarch64/instructions/ldsetb.rb +12 -12
- data/lib/aarch64/instructions/ldseth.rb +12 -12
- data/lib/aarch64/instructions/ldsmax.rb +14 -14
- data/lib/aarch64/instructions/ldsmaxb.rb +12 -12
- data/lib/aarch64/instructions/ldsmaxh.rb +12 -12
- data/lib/aarch64/instructions/ldsmin.rb +14 -14
- data/lib/aarch64/instructions/ldsminb.rb +12 -12
- data/lib/aarch64/instructions/ldsminh.rb +12 -12
- data/lib/aarch64/instructions/ldtr.rb +10 -10
- data/lib/aarch64/instructions/ldtrb.rb +8 -8
- data/lib/aarch64/instructions/ldtrh.rb +8 -8
- data/lib/aarch64/instructions/ldtrsb.rb +10 -10
- data/lib/aarch64/instructions/ldtrsh.rb +10 -10
- data/lib/aarch64/instructions/ldtrsw.rb +8 -8
- data/lib/aarch64/instructions/ldumax.rb +14 -14
- data/lib/aarch64/instructions/ldumaxb.rb +12 -12
- data/lib/aarch64/instructions/ldumaxh.rb +12 -12
- data/lib/aarch64/instructions/ldumin.rb +14 -14
- data/lib/aarch64/instructions/lduminb.rb +12 -12
- data/lib/aarch64/instructions/lduminh.rb +12 -12
- data/lib/aarch64/instructions/ldur_gen.rb +10 -10
- data/lib/aarch64/instructions/ldursb.rb +10 -10
- data/lib/aarch64/instructions/ldursh.rb +10 -10
- data/lib/aarch64/instructions/ldursw.rb +8 -8
- data/lib/aarch64/instructions/ldxp.rb +10 -10
- data/lib/aarch64/instructions/ldxr.rb +8 -8
- data/lib/aarch64/instructions/lslv.rb +10 -10
- data/lib/aarch64/instructions/lsrv.rb +10 -10
- data/lib/aarch64/instructions/madd.rb +12 -12
- data/lib/aarch64/instructions/movk.rb +10 -10
- data/lib/aarch64/instructions/movn.rb +10 -10
- data/lib/aarch64/instructions/movz.rb +10 -10
- data/lib/aarch64/instructions/mrs.rb +14 -14
- data/lib/aarch64/instructions/msr_imm.rb +7 -7
- data/lib/aarch64/instructions/msr_reg.rb +14 -14
- data/lib/aarch64/instructions/msub.rb +12 -12
- data/lib/aarch64/instructions/nop.rb +1 -1
- data/lib/aarch64/instructions/orn_log_shift.rb +14 -14
- data/lib/aarch64/instructions/orr_log_imm.rb +14 -14
- data/lib/aarch64/instructions/orr_log_shift.rb +14 -14
- data/lib/aarch64/instructions/pacda.rb +8 -8
- data/lib/aarch64/instructions/pacdb.rb +8 -8
- data/lib/aarch64/instructions/pacga.rb +8 -8
- data/lib/aarch64/instructions/pacia.rb +8 -8
- data/lib/aarch64/instructions/pacia2.rb +5 -5
- data/lib/aarch64/instructions/pacib.rb +8 -8
- data/lib/aarch64/instructions/prfm_imm.rb +8 -8
- data/lib/aarch64/instructions/prfm_lit.rb +8 -8
- data/lib/aarch64/instructions/prfm_reg.rb +12 -12
- data/lib/aarch64/instructions/prfum.rb +8 -8
- data/lib/aarch64/instructions/psb.rb +2 -9
- data/lib/aarch64/instructions/rbit_int.rb +8 -8
- data/lib/aarch64/instructions/ret.rb +4 -4
- data/lib/aarch64/instructions/reta.rb +3 -3
- data/lib/aarch64/instructions/rev.rb +10 -10
- data/lib/aarch64/instructions/rmif.rb +8 -8
- data/lib/aarch64/instructions/rorv.rb +10 -10
- data/lib/aarch64/instructions/sb.rb +1 -1
- data/lib/aarch64/instructions/sbc.rb +10 -10
- data/lib/aarch64/instructions/sbcs.rb +10 -10
- data/lib/aarch64/instructions/sbfm.rb +13 -13
- data/lib/aarch64/instructions/sdiv.rb +10 -10
- data/lib/aarch64/instructions/setf.rb +6 -6
- data/lib/aarch64/instructions/sev.rb +1 -7
- data/lib/aarch64/instructions/sevl.rb +1 -1
- data/lib/aarch64/instructions/smaddl.rb +10 -10
- data/lib/aarch64/instructions/smc.rb +3 -3
- data/lib/aarch64/instructions/smsubl.rb +10 -10
- data/lib/aarch64/instructions/smulh.rb +8 -8
- data/lib/aarch64/instructions/st2g.rb +10 -10
- data/lib/aarch64/instructions/st64b.rb +6 -6
- data/lib/aarch64/instructions/st64bv.rb +8 -8
- data/lib/aarch64/instructions/st64bv0.rb +8 -8
- data/lib/aarch64/instructions/stg.rb +10 -10
- data/lib/aarch64/instructions/stgm.rb +6 -6
- data/lib/aarch64/instructions/stgp.rb +12 -12
- data/lib/aarch64/instructions/stllr.rb +8 -8
- data/lib/aarch64/instructions/stllrb.rb +6 -6
- data/lib/aarch64/instructions/stllrh.rb +6 -6
- data/lib/aarch64/instructions/stlr.rb +8 -8
- data/lib/aarch64/instructions/stlrb.rb +6 -6
- data/lib/aarch64/instructions/stlrh.rb +6 -6
- data/lib/aarch64/instructions/stlur_gen.rb +10 -10
- data/lib/aarch64/instructions/stlxp.rb +12 -12
- data/lib/aarch64/instructions/stlxr.rb +10 -10
- data/lib/aarch64/instructions/stlxrb.rb +8 -8
- data/lib/aarch64/instructions/stlxrh.rb +8 -8
- data/lib/aarch64/instructions/stnp_gen.rb +12 -12
- data/lib/aarch64/instructions/stp_gen.rb +14 -14
- data/lib/aarch64/instructions/str_imm_gen.rb +12 -12
- data/lib/aarch64/instructions/str_imm_unsigned.rb +10 -10
- data/lib/aarch64/instructions/str_reg_gen.rb +14 -14
- data/lib/aarch64/instructions/strb_imm.rb +10 -10
- data/lib/aarch64/instructions/strb_imm_unsigned.rb +8 -8
- data/lib/aarch64/instructions/strb_reg.rb +12 -12
- data/lib/aarch64/instructions/strh_imm.rb +10 -10
- data/lib/aarch64/instructions/strh_imm_unsigned.rb +8 -8
- data/lib/aarch64/instructions/strh_reg.rb +12 -12
- data/lib/aarch64/instructions/sttr.rb +10 -10
- data/lib/aarch64/instructions/stur_gen.rb +10 -10
- data/lib/aarch64/instructions/stxp.rb +12 -12
- data/lib/aarch64/instructions/stxr.rb +10 -10
- data/lib/aarch64/instructions/stxrb.rb +8 -8
- data/lib/aarch64/instructions/stxrh.rb +8 -8
- data/lib/aarch64/instructions/stz2g.rb +10 -10
- data/lib/aarch64/instructions/stzg.rb +10 -10
- data/lib/aarch64/instructions/stzgm.rb +6 -6
- data/lib/aarch64/instructions/sub_addsub_ext.rb +14 -14
- data/lib/aarch64/instructions/sub_addsub_imm.rb +12 -12
- data/lib/aarch64/instructions/sub_addsub_shift.rb +14 -14
- data/lib/aarch64/instructions/subg.rb +10 -10
- data/lib/aarch64/instructions/subp.rb +8 -8
- data/lib/aarch64/instructions/subps.rb +8 -8
- data/lib/aarch64/instructions/subs_addsub_ext.rb +14 -14
- data/lib/aarch64/instructions/subs_addsub_imm.rb +12 -12
- data/lib/aarch64/instructions/subs_addsub_shift.rb +14 -14
- data/lib/aarch64/instructions/svc.rb +3 -3
- data/lib/aarch64/instructions/swp.rb +14 -14
- data/lib/aarch64/instructions/swpb.rb +12 -12
- data/lib/aarch64/instructions/swph.rb +12 -12
- data/lib/aarch64/instructions/sys.rb +12 -12
- data/lib/aarch64/instructions/sysl.rb +12 -12
- data/lib/aarch64/instructions/tbnz.rb +9 -9
- data/lib/aarch64/instructions/tbz.rb +9 -9
- data/lib/aarch64/instructions/tsb.rb +1 -7
- data/lib/aarch64/instructions/ubfm.rb +13 -13
- data/lib/aarch64/instructions/udf_perm_undef.rb +3 -3
- data/lib/aarch64/instructions/udiv.rb +10 -10
- data/lib/aarch64/instructions/umaddl.rb +10 -10
- data/lib/aarch64/instructions/umsubl.rb +10 -10
- data/lib/aarch64/instructions/umulh.rb +8 -8
- data/lib/aarch64/instructions/wfe.rb +2 -9
- data/lib/aarch64/instructions/wfet.rb +4 -4
- data/lib/aarch64/instructions/wfi.rb +1 -1
- data/lib/aarch64/instructions/wfit.rb +4 -4
- data/lib/aarch64/instructions/xaflag.rb +1 -1
- data/lib/aarch64/instructions/xpac.rb +6 -6
- data/lib/aarch64/instructions/xpaclri.rb +1 -1
- data/lib/aarch64/instructions/yield.rb +2 -9
- data/lib/aarch64/instructions.rb +26 -8
- data/lib/aarch64/parser.rb +227 -0
- data/lib/aarch64/parser.tab.rb +6534 -0
- data/lib/aarch64/parser.y +1394 -0
- data/lib/aarch64/utils.rb +34 -0
- data/lib/aarch64/version.rb +1 -1
- data/lib/aarch64.rb +128 -58
- data/test/base_instructions_test.rb +34 -4
- data/test/helper.rb +48 -8
- data/test/parser_test.rb +1820 -0
- metadata +25 -14
- data/lib/aarch64/instructions/setgp.rb +0 -25
- data/lib/aarch64/instructions/setgpn.rb +0 -25
- data/lib/aarch64/instructions/setgpt.rb +0 -25
- data/lib/aarch64/instructions/setgptn.rb +0 -25
- data/lib/aarch64/instructions/setp.rb +0 -25
- data/lib/aarch64/instructions/setpn.rb +0 -25
- data/lib/aarch64/instructions/setpt.rb +0 -25
- data/lib/aarch64/instructions/setptn.rb +0 -25
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
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1
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---
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SHA256:
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-
metadata.gz:
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data.tar.gz:
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+
metadata.gz: e04700eac89cfbce749a76679b4e7d408bf59bc8eaec3e208b6ed5742dbad36a
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4
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+
data.tar.gz: 7cfd0854a30b04974127ab7f5ed53d36e1fd04742c4a36893195e00e3a973c9f
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SHA512:
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metadata.gz:
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data.tar.gz:
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+
metadata.gz: c3476189b664bdec820cf5c8fe5e1243c85aa5fd73f1e5994c71db193f32b00f24e32fb3892415a03c865fedc760f33a8e266681e688e4d4ff753a1c6ffab25e
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7
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+
data.tar.gz: 1d37e4223349cf1b6360f1704344dcde6812124684dbe23079d6c1d07d529707f4f89b281f5b724ae6ef65cdddd2ec111d984721033bf815dec61cdc92c60a62
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data/README.md
CHANGED
data/Rakefile
CHANGED
@@ -160,6 +160,12 @@ file SYSTEM_REGS_FILE do |t|
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download SYSTEM_REGS_URL, t.name
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end
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rule ".tab.rb" => [".y"] do |t|
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puts "#" * 90
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sh "gel exec racc -E -v #{t.source}"
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puts "#" * 90
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end
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Rake::TestTask.new(:test) do |t|
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t.libs << "test/lib" << "test"
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t.test_files = FileList['test/**/*_test.rb']
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@@ -167,4 +173,35 @@ Rake::TestTask.new(:test) do |t|
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t.warning = true
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174
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end
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+
task :test => "lib/aarch64/parser.tab.rb"
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task :default => :test
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task "autotest" do
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basedir = File.dirname(__FILE__)
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libdir = File.join basedir, "lib"
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testdir = File.join basedir, "test"
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IO.popen(["fswatch", libdir, testdir]) do |io|
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186
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loop do
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187
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line = io.readline.chomp
|
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case line
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189
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when /^#{libdir}/
|
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# If the libdir changes, run all tests
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+
begin
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sh "gel exec rake test"
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+
rescue
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end
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when /^#{testdir}/
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# If the testdir changes, run the test
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+
test_file = line.delete_prefix(testdir + "/")
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begin
|
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sh "gel exec rake test TESTS=#{test_file}" if test_file =~ /_test.rb/
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rescue
|
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end
|
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else
|
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raise "wat: #{line}"
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end
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end
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end
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end
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data/aarch64.gemspec
CHANGED
@@ -4,26 +4,26 @@ module AArch64
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4
4
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# Add with Carry
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5
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# ADC <Wd>, <Wn>, <Wm>
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6
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# ADC <Xd>, <Xn>, <Xm>
|
7
|
-
class ADC
|
7
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+
class ADC < Instruction
|
8
8
|
def initialize rd, rn, rm, sf
|
9
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-
@rd = rd
|
10
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-
@rn = rn
|
11
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-
@rm = rm
|
12
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-
@sf = sf
|
9
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+
@rd = check_mask(rd, 0x1f)
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10
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+
@rn = check_mask(rn, 0x1f)
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11
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+
@rm = check_mask(rm, 0x1f)
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12
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+
@sf = check_mask(sf, 0x01)
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13
|
end
|
14
14
|
|
15
15
|
def encode
|
16
|
-
ADC(@sf, @rm
|
16
|
+
ADC(@sf, @rm, @rn, @rd)
|
17
17
|
end
|
18
18
|
|
19
19
|
private
|
20
20
|
|
21
21
|
def ADC sf, rm, rn, rd
|
22
22
|
insn = 0b0_0_0_11010000_00000_000000_00000_00000
|
23
|
-
insn |= ((sf
|
24
|
-
insn |= ((rm
|
25
|
-
insn |= ((rn
|
26
|
-
insn |= (rd
|
23
|
+
insn |= ((sf) << 31)
|
24
|
+
insn |= ((rm) << 16)
|
25
|
+
insn |= ((rn) << 5)
|
26
|
+
insn |= (rd)
|
27
27
|
insn
|
28
28
|
end
|
29
29
|
end
|
@@ -3,26 +3,26 @@ module AArch64
|
|
3
3
|
# ADCS -- A64
|
4
4
|
# Add with Carry, setting flags
|
5
5
|
# ADCS <Wd>, <Wn>, <Wm>
|
6
|
-
class ADCS
|
6
|
+
class ADCS < Instruction
|
7
7
|
def initialize rd, rn, rm, sf
|
8
|
-
@rd = rd
|
9
|
-
@rn = rn
|
10
|
-
@rm = rm
|
11
|
-
@sf = sf
|
8
|
+
@rd = check_mask(rd, 0x1f)
|
9
|
+
@rn = check_mask(rn, 0x1f)
|
10
|
+
@rm = check_mask(rm, 0x1f)
|
11
|
+
@sf = check_mask(sf, 0x01)
|
12
12
|
end
|
13
13
|
|
14
14
|
def encode
|
15
|
-
ADCS(@sf, @rm
|
15
|
+
ADCS(@sf, @rm, @rn, @rd)
|
16
16
|
end
|
17
17
|
|
18
18
|
private
|
19
19
|
|
20
20
|
def ADCS sf, rm, rn, rd
|
21
21
|
insn = 0b0_0_1_11010000_00000_000000_00000_00000
|
22
|
-
insn |= ((sf
|
23
|
-
insn |= ((rm
|
24
|
-
insn |= ((rn
|
25
|
-
insn |= (rd
|
22
|
+
insn |= ((sf) << 31)
|
23
|
+
insn |= ((rm) << 16)
|
24
|
+
insn |= ((rn) << 5)
|
25
|
+
insn |= (rd)
|
26
26
|
insn
|
27
27
|
end
|
28
28
|
end
|
@@ -4,30 +4,30 @@ module AArch64
|
|
4
4
|
# Add (extended register)
|
5
5
|
# ADD <Wd|WSP>, <Wn|WSP>, <Wm>{, <extend> {#<amount>}}
|
6
6
|
# ADD <Xd|SP>, <Xn|SP>, <R><m>{, <extend> {#<amount>}}
|
7
|
-
class ADD_addsub_ext
|
7
|
+
class ADD_addsub_ext < Instruction
|
8
8
|
def initialize rd, rn, rm, extend, amount, sf
|
9
|
-
@rd = rd
|
10
|
-
@rn = rn
|
11
|
-
@rm = rm
|
12
|
-
@extend = extend
|
13
|
-
@amount = amount
|
14
|
-
@sf = sf
|
9
|
+
@rd = check_mask(rd, 0x1f)
|
10
|
+
@rn = check_mask(rn, 0x1f)
|
11
|
+
@rm = check_mask(rm, 0x1f)
|
12
|
+
@extend = check_mask(extend, 0x07)
|
13
|
+
@amount = check_mask(amount, 0x07)
|
14
|
+
@sf = check_mask(sf, 0x01)
|
15
15
|
end
|
16
16
|
|
17
17
|
def encode
|
18
|
-
ADD_addsub_ext(@sf, @rm
|
18
|
+
ADD_addsub_ext(@sf, @rm, @extend, @amount, @rn, @rd)
|
19
19
|
end
|
20
20
|
|
21
21
|
private
|
22
22
|
|
23
23
|
def ADD_addsub_ext sf, rm, option, imm3, rn, rd
|
24
24
|
insn = 0b0_0_0_01011_00_1_00000_000_000_00000_00000
|
25
|
-
insn |= ((sf
|
26
|
-
insn |= ((rm
|
27
|
-
insn |= ((option
|
28
|
-
insn |= ((imm3
|
29
|
-
insn |= ((rn
|
30
|
-
insn |= (rd
|
25
|
+
insn |= ((sf) << 31)
|
26
|
+
insn |= ((rm) << 16)
|
27
|
+
insn |= ((option) << 13)
|
28
|
+
insn |= ((imm3) << 10)
|
29
|
+
insn |= ((rn) << 5)
|
30
|
+
insn |= (rd)
|
31
31
|
insn
|
32
32
|
end
|
33
33
|
end
|
@@ -3,28 +3,28 @@ module AArch64
|
|
3
3
|
# ADD (immediate) -- A64
|
4
4
|
# Add (immediate)
|
5
5
|
# ADD <Wd|WSP>, <Wn|WSP>, #<imm>{, <shift>}
|
6
|
-
class ADD_addsub_imm
|
6
|
+
class ADD_addsub_imm < Instruction
|
7
7
|
def initialize rd, rn, imm12, sh, sf
|
8
|
-
@rd = rd
|
9
|
-
@rn = rn
|
10
|
-
@imm12 = imm12
|
11
|
-
@sh = sh
|
12
|
-
@sf = sf
|
8
|
+
@rd = check_mask(rd, 0x1f)
|
9
|
+
@rn = check_mask(rn, 0x1f)
|
10
|
+
@imm12 = check_mask(imm12, 0xfff)
|
11
|
+
@sh = check_mask(sh, 0x01)
|
12
|
+
@sf = check_mask(sf, 0x01)
|
13
13
|
end
|
14
14
|
|
15
15
|
def encode
|
16
|
-
ADD_addsub_imm(@sf, @sh, @imm12, @rn
|
16
|
+
ADD_addsub_imm(@sf, @sh, @imm12, @rn, @rd)
|
17
17
|
end
|
18
18
|
|
19
19
|
private
|
20
20
|
|
21
21
|
def ADD_addsub_imm sf, sh, imm12, rn, rd
|
22
22
|
insn = 0b0_0_0_100010_0_000000000000_00000_00000
|
23
|
-
insn |= ((sf
|
24
|
-
insn |= ((sh
|
25
|
-
insn |= ((imm12
|
26
|
-
insn |= ((rn
|
27
|
-
insn |= (rd
|
23
|
+
insn |= ((sf) << 31)
|
24
|
+
insn |= ((sh) << 22)
|
25
|
+
insn |= ((imm12) << 10)
|
26
|
+
insn |= ((rn) << 5)
|
27
|
+
insn |= (rd)
|
28
28
|
insn
|
29
29
|
end
|
30
30
|
end
|
@@ -4,30 +4,30 @@ module AArch64
|
|
4
4
|
# Add (shifted register)
|
5
5
|
# ADD <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
|
6
6
|
# ADD <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
|
7
|
-
class ADD_addsub_shift
|
7
|
+
class ADD_addsub_shift < Instruction
|
8
8
|
def initialize xd, xn, xm, shift, amount, sf
|
9
|
-
@xd = xd
|
10
|
-
@xn = xn
|
11
|
-
@xm = xm
|
12
|
-
@shift = shift
|
13
|
-
@amount = amount
|
14
|
-
@sf = sf
|
9
|
+
@xd = check_mask(xd, 0x1f)
|
10
|
+
@xn = check_mask(xn, 0x1f)
|
11
|
+
@xm = check_mask(xm, 0x1f)
|
12
|
+
@shift = check_mask(shift, 0x03)
|
13
|
+
@amount = check_mask(amount, 0x3f)
|
14
|
+
@sf = check_mask(sf, 0x01)
|
15
15
|
end
|
16
16
|
|
17
17
|
def encode
|
18
|
-
ADD_addsub_shift(@sf, @shift, @xm
|
18
|
+
ADD_addsub_shift(@sf, @shift, @xm, @amount, @xn, @xd)
|
19
19
|
end
|
20
20
|
|
21
21
|
private
|
22
22
|
|
23
23
|
def ADD_addsub_shift sf, shift, rm, imm6, rn, rd
|
24
24
|
insn = 0b0_0_0_01011_00_0_00000_000000_00000_00000
|
25
|
-
insn |= ((sf
|
26
|
-
insn |= ((shift
|
27
|
-
insn |= ((rm
|
28
|
-
insn |= ((imm6
|
29
|
-
insn |= ((rn
|
30
|
-
insn |= (rd
|
25
|
+
insn |= ((sf) << 31)
|
26
|
+
insn |= ((shift) << 22)
|
27
|
+
insn |= ((rm) << 16)
|
28
|
+
insn |= ((imm6) << 10)
|
29
|
+
insn |= ((rn) << 5)
|
30
|
+
insn |= (rd)
|
31
31
|
insn
|
32
32
|
end
|
33
33
|
end
|
@@ -3,26 +3,26 @@ module AArch64
|
|
3
3
|
# ADDG -- A64
|
4
4
|
# Add with Tag
|
5
5
|
# ADDG <Xd|SP>, <Xn|SP>, #<uimm6>, #<uimm4>
|
6
|
-
class ADDG
|
6
|
+
class ADDG < Instruction
|
7
7
|
def initialize xd, xn, imm6, imm4
|
8
|
-
@xd = xd
|
9
|
-
@xn = xn
|
10
|
-
@imm6 = imm6
|
11
|
-
@imm4 = imm4
|
8
|
+
@xd = check_mask(xd, 0x1f)
|
9
|
+
@xn = check_mask(xn, 0x1f)
|
10
|
+
@imm6 = check_mask(imm6, 0x3f)
|
11
|
+
@imm4 = check_mask(imm4, 0x0f)
|
12
12
|
end
|
13
13
|
|
14
14
|
def encode
|
15
|
-
ADDG(@imm6, @imm4, @xn
|
15
|
+
ADDG(@imm6, @imm4, @xn, @xd)
|
16
16
|
end
|
17
17
|
|
18
18
|
private
|
19
19
|
|
20
20
|
def ADDG uimm6, uimm4, xn, xd
|
21
21
|
insn = 0b1_0_0_100011_0_000000_00_0000_00000_00000
|
22
|
-
insn |= ((uimm6
|
23
|
-
insn |= ((uimm4
|
24
|
-
insn |= ((xn
|
25
|
-
insn |= (xd
|
22
|
+
insn |= ((uimm6) << 16)
|
23
|
+
insn |= ((uimm4) << 10)
|
24
|
+
insn |= ((xn) << 5)
|
25
|
+
insn |= (xd)
|
26
26
|
insn
|
27
27
|
end
|
28
28
|
end
|
@@ -4,30 +4,30 @@ module AArch64
|
|
4
4
|
# Add (extended register), setting flags
|
5
5
|
# ADDS <Wd>, <Wn|WSP>, <Wm>{, <extend> {#<amount>}}
|
6
6
|
# ADDS <Xd>, <Xn|SP>, <R><m>{, <extend> {#<amount>}}
|
7
|
-
class ADDS_addsub_ext
|
7
|
+
class ADDS_addsub_ext < Instruction
|
8
8
|
def initialize d, n, m, extend, amount, sf
|
9
|
-
@d = d
|
10
|
-
@n = n
|
11
|
-
@m = m
|
12
|
-
@extend = extend
|
13
|
-
@amount = amount
|
14
|
-
@sf = sf
|
9
|
+
@d = check_mask(d, 0x1f)
|
10
|
+
@n = check_mask(n, 0x1f)
|
11
|
+
@m = check_mask(m, 0x1f)
|
12
|
+
@extend = check_mask(extend, 0x07)
|
13
|
+
@amount = check_mask(amount, 0x07)
|
14
|
+
@sf = check_mask(sf, 0x01)
|
15
15
|
end
|
16
16
|
|
17
17
|
def encode
|
18
|
-
ADDS_addsub_ext(@sf, @m
|
18
|
+
ADDS_addsub_ext(@sf, @m, @extend, @amount, @n, @d)
|
19
19
|
end
|
20
20
|
|
21
21
|
private
|
22
22
|
|
23
23
|
def ADDS_addsub_ext sf, rm, option, imm3, rn, rd
|
24
24
|
insn = 0b0_0_1_01011_00_1_00000_000_000_00000_00000
|
25
|
-
insn |= ((sf
|
26
|
-
insn |= ((rm
|
27
|
-
insn |= ((option
|
28
|
-
insn |= ((imm3
|
29
|
-
insn |= ((rn
|
30
|
-
insn |= (rd
|
25
|
+
insn |= ((sf) << 31)
|
26
|
+
insn |= ((rm) << 16)
|
27
|
+
insn |= ((option) << 13)
|
28
|
+
insn |= ((imm3) << 10)
|
29
|
+
insn |= ((rn) << 5)
|
30
|
+
insn |= (rd)
|
31
31
|
insn
|
32
32
|
end
|
33
33
|
end
|
@@ -4,28 +4,28 @@ module AArch64
|
|
4
4
|
# Add (immediate), setting flags
|
5
5
|
# ADDS <Wd>, <Wn|WSP>, #<imm>{, <shift>}
|
6
6
|
# ADDS <Xd>, <Xn|SP>, #<imm>{, <shift>}
|
7
|
-
class ADDS_addsub_imm
|
7
|
+
class ADDS_addsub_imm < Instruction
|
8
8
|
def initialize d, n, imm, shift, sf
|
9
|
-
@d = d
|
10
|
-
@n = n
|
11
|
-
@imm = imm
|
12
|
-
@shift = shift
|
13
|
-
@sf = sf
|
9
|
+
@d = check_mask(d, 0x1f)
|
10
|
+
@n = check_mask(n, 0x1f)
|
11
|
+
@imm = check_mask(imm, 0xfff)
|
12
|
+
@shift = check_mask(shift, 0x01)
|
13
|
+
@sf = check_mask(sf, 0x01)
|
14
14
|
end
|
15
15
|
|
16
16
|
def encode
|
17
|
-
ADDS_addsub_imm(@sf, @shift, @imm, @n
|
17
|
+
ADDS_addsub_imm(@sf, @shift, @imm, @n, @d)
|
18
18
|
end
|
19
19
|
|
20
20
|
private
|
21
21
|
|
22
22
|
def ADDS_addsub_imm sf, sh, imm12, rn, rd
|
23
23
|
insn = 0b0_0_1_100010_0_000000000000_00000_00000
|
24
|
-
insn |= ((sf
|
25
|
-
insn |= ((sh
|
26
|
-
insn |= ((imm12
|
27
|
-
insn |= ((rn
|
28
|
-
insn |= (rd
|
24
|
+
insn |= ((sf) << 31)
|
25
|
+
insn |= ((sh) << 22)
|
26
|
+
insn |= ((imm12) << 10)
|
27
|
+
insn |= ((rn) << 5)
|
28
|
+
insn |= (rd)
|
29
29
|
insn
|
30
30
|
end
|
31
31
|
end
|
@@ -4,30 +4,30 @@ module AArch64
|
|
4
4
|
# Add (shifted register), setting flags
|
5
5
|
# ADDS <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
|
6
6
|
# ADDS <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
|
7
|
-
class ADDS_addsub_shift
|
7
|
+
class ADDS_addsub_shift < Instruction
|
8
8
|
def initialize xd, xn, xm, shift, amount, sf
|
9
|
-
@xd = xd
|
10
|
-
@xn = xn
|
11
|
-
@xm = xm
|
12
|
-
@shift = shift
|
13
|
-
@amount = amount
|
14
|
-
@sf = sf
|
9
|
+
@xd = check_mask(xd, 0x1f)
|
10
|
+
@xn = check_mask(xn, 0x1f)
|
11
|
+
@xm = check_mask(xm, 0x1f)
|
12
|
+
@shift = check_mask(shift, 0x03)
|
13
|
+
@amount = check_mask(amount, 0x3f)
|
14
|
+
@sf = check_mask(sf, 0x01)
|
15
15
|
end
|
16
16
|
|
17
17
|
def encode
|
18
|
-
ADDS_addsub_shift(@sf, @shift, @xm
|
18
|
+
ADDS_addsub_shift(@sf, @shift, @xm, @amount, @xn, @xd)
|
19
19
|
end
|
20
20
|
|
21
21
|
private
|
22
22
|
|
23
23
|
def ADDS_addsub_shift sf, shift, rm, imm6, rn, rd
|
24
24
|
insn = 0b0_0_1_01011_00_0_00000_000000_00000_00000
|
25
|
-
insn |= ((sf
|
26
|
-
insn |= ((shift
|
27
|
-
insn |= ((rm
|
28
|
-
insn |= ((imm6
|
29
|
-
insn |= ((rn
|
30
|
-
insn |= (rd
|
25
|
+
insn |= ((sf) << 31)
|
26
|
+
insn |= ((shift) << 22)
|
27
|
+
insn |= ((rm) << 16)
|
28
|
+
insn |= ((imm6) << 10)
|
29
|
+
insn |= ((rn) << 5)
|
30
|
+
insn |= (rd)
|
31
31
|
insn
|
32
32
|
end
|
33
33
|
end
|
@@ -3,24 +3,24 @@ module AArch64
|
|
3
3
|
# ADR -- A64
|
4
4
|
# Form PC-relative address
|
5
5
|
# ADR <Xd>, <label>
|
6
|
-
class ADR
|
6
|
+
class ADR < Instruction
|
7
7
|
def initialize xd, label
|
8
|
-
@xd = xd
|
8
|
+
@xd = check_mask(xd, 0x1f)
|
9
9
|
@label = label
|
10
10
|
end
|
11
11
|
|
12
12
|
def encode
|
13
|
-
label = @label.
|
14
|
-
ADR(label, label >> 2, @xd
|
13
|
+
label = @label.unwrap_label
|
14
|
+
ADR(label & 0x3, check_mask((label >> 2), 0x7ffff), @xd)
|
15
15
|
end
|
16
16
|
|
17
17
|
private
|
18
18
|
|
19
19
|
def ADR immlo, immhi, rd
|
20
20
|
insn = 0b0_00_10000_0000000000000000000_00000
|
21
|
-
insn |= (
|
22
|
-
insn |= (
|
23
|
-
insn |=
|
21
|
+
insn |= (immlo << 29)
|
22
|
+
insn |= (immhi << 5)
|
23
|
+
insn |= rd
|
24
24
|
insn
|
25
25
|
end
|
26
26
|
end
|
@@ -3,24 +3,24 @@ module AArch64
|
|
3
3
|
# ADRP -- A64
|
4
4
|
# Form PC-relative address to 4KB page
|
5
5
|
# ADRP <Xd>, <label>
|
6
|
-
class ADRP
|
6
|
+
class ADRP < Instruction
|
7
7
|
def initialize xd, label
|
8
|
-
@xd = xd
|
8
|
+
@xd = check_mask(xd, 0x1f)
|
9
9
|
@label = label
|
10
10
|
end
|
11
11
|
|
12
12
|
def encode
|
13
|
-
label = @label
|
14
|
-
ADRP(label, label >> 2, @xd
|
13
|
+
label = @label / 4096
|
14
|
+
ADRP(label & 0x3, check_mask(label >> 2, 0x7ffff), @xd)
|
15
15
|
end
|
16
16
|
|
17
17
|
private
|
18
18
|
|
19
19
|
def ADRP immlo, immhi, rd
|
20
20
|
insn = 0b1_00_10000_0000000000000000000_00000
|
21
|
-
insn |= (
|
22
|
-
insn |= (
|
23
|
-
insn |=
|
21
|
+
insn |= (immlo << 29)
|
22
|
+
insn |= (immhi << 5)
|
23
|
+
insn |= rd
|
24
24
|
insn
|
25
25
|
end
|
26
26
|
end
|
@@ -4,30 +4,30 @@ module AArch64
|
|
4
4
|
# Bitwise AND (immediate)
|
5
5
|
# AND <Wd|WSP>, <Wn>, #<imm>
|
6
6
|
# AND <Xd|SP>, <Xn>, #<imm>
|
7
|
-
class AND_log_imm
|
7
|
+
class AND_log_imm < Instruction
|
8
8
|
def initialize rd, rn, immr, imms, n, sf
|
9
|
-
@rd = rd
|
10
|
-
@rn = rn
|
11
|
-
@immr = immr
|
12
|
-
@imms = imms
|
13
|
-
@n = n
|
14
|
-
@sf = sf
|
9
|
+
@rd = check_mask(rd, 0x1f)
|
10
|
+
@rn = check_mask(rn, 0x1f)
|
11
|
+
@immr = check_mask(immr, 0x3f)
|
12
|
+
@imms = check_mask(imms, 0x3f)
|
13
|
+
@n = check_mask(n, 0x01)
|
14
|
+
@sf = check_mask(sf, 0x01)
|
15
15
|
end
|
16
16
|
|
17
17
|
def encode
|
18
|
-
AND_log_imm(@sf, @n, @immr, @imms, @rn
|
18
|
+
AND_log_imm(@sf, @n, @immr, @imms, @rn, @rd)
|
19
19
|
end
|
20
20
|
|
21
21
|
private
|
22
22
|
|
23
23
|
def AND_log_imm sf, n, immr, imms, rn, rd
|
24
24
|
insn = 0b0_00_100100_0_000000_000000_00000_00000
|
25
|
-
insn |= ((sf
|
26
|
-
insn |= ((n
|
27
|
-
insn |= ((immr
|
28
|
-
insn |= ((imms
|
29
|
-
insn |= ((rn
|
30
|
-
insn |= (rd
|
25
|
+
insn |= ((sf) << 31)
|
26
|
+
insn |= ((n) << 22)
|
27
|
+
insn |= ((immr) << 16)
|
28
|
+
insn |= ((imms) << 10)
|
29
|
+
insn |= ((rn) << 5)
|
30
|
+
insn |= (rd)
|
31
31
|
insn
|
32
32
|
end
|
33
33
|
end
|
@@ -4,30 +4,30 @@ module AArch64
|
|
4
4
|
# Bitwise AND (shifted register)
|
5
5
|
# AND <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
|
6
6
|
# AND <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
|
7
|
-
class AND_log_shift
|
7
|
+
class AND_log_shift < Instruction
|
8
8
|
def initialize xd, xn, xm, shift, amount, sf
|
9
|
-
@xd = xd
|
10
|
-
@xn = xn
|
11
|
-
@xm = xm
|
12
|
-
@shift = shift
|
13
|
-
@amount = amount
|
14
|
-
@sf = sf
|
9
|
+
@xd = check_mask(xd, 0x1f)
|
10
|
+
@xn = check_mask(xn, 0x1f)
|
11
|
+
@xm = check_mask(xm, 0x1f)
|
12
|
+
@shift = check_mask(shift, 0x03)
|
13
|
+
@amount = check_mask(amount, 0x3f)
|
14
|
+
@sf = check_mask(sf, 0x01)
|
15
15
|
end
|
16
16
|
|
17
17
|
def encode
|
18
|
-
AND_log_shift(@sf, @shift, @xm
|
18
|
+
AND_log_shift(@sf, @shift, @xm, @amount, @xn, @xd)
|
19
19
|
end
|
20
20
|
|
21
21
|
private
|
22
22
|
|
23
23
|
def AND_log_shift sf, shift, rm, imm6, rn, rd
|
24
24
|
insn = 0b0_00_01010_00_0_00000_000000_00000_00000
|
25
|
-
insn |= ((sf
|
26
|
-
insn |= ((shift
|
27
|
-
insn |= ((rm
|
28
|
-
insn |= ((imm6
|
29
|
-
insn |= ((rn
|
30
|
-
insn |= (rd
|
25
|
+
insn |= ((sf) << 31)
|
26
|
+
insn |= ((shift) << 22)
|
27
|
+
insn |= ((rm) << 16)
|
28
|
+
insn |= ((imm6) << 10)
|
29
|
+
insn |= ((rn) << 5)
|
30
|
+
insn |= (rd)
|
31
31
|
insn
|
32
32
|
end
|
33
33
|
end
|
@@ -4,30 +4,30 @@ module AArch64
|
|
4
4
|
# Bitwise AND (immediate), setting flags
|
5
5
|
# ANDS <Wd>, <Wn>, #<imm>
|
6
6
|
# ANDS <Xd>, <Xn>, #<imm>
|
7
|
-
class ANDS_log_imm
|
7
|
+
class ANDS_log_imm < Instruction
|
8
8
|
def initialize rd, rn, immr, imms, n, sf
|
9
|
-
@rd = rd
|
10
|
-
@rn = rn
|
11
|
-
@immr = immr
|
12
|
-
@imms = imms
|
13
|
-
@n = n
|
14
|
-
@sf = sf
|
9
|
+
@rd = check_mask(rd, 0x1f)
|
10
|
+
@rn = check_mask(rn, 0x1f)
|
11
|
+
@immr = check_mask(immr, 0x3f)
|
12
|
+
@imms = check_mask(imms, 0x3f)
|
13
|
+
@n = check_mask(n, 0x01)
|
14
|
+
@sf = check_mask(sf, 0x01)
|
15
15
|
end
|
16
16
|
|
17
17
|
def encode
|
18
|
-
ANDS_log_imm(@sf, @n, @immr, @imms, @rn
|
18
|
+
ANDS_log_imm(@sf, @n, @immr, @imms, @rn, @rd)
|
19
19
|
end
|
20
20
|
|
21
21
|
private
|
22
22
|
|
23
23
|
def ANDS_log_imm sf, n, immr, imms, rn, rd
|
24
24
|
insn = 0b0_11_100100_0_000000_000000_00000_00000
|
25
|
-
insn |= ((sf
|
26
|
-
insn |= ((n
|
27
|
-
insn |= ((immr
|
28
|
-
insn |= ((imms
|
29
|
-
insn |= ((rn
|
30
|
-
insn |= (rd
|
25
|
+
insn |= ((sf) << 31)
|
26
|
+
insn |= ((n) << 22)
|
27
|
+
insn |= ((immr) << 16)
|
28
|
+
insn |= ((imms) << 10)
|
29
|
+
insn |= ((rn) << 5)
|
30
|
+
insn |= (rd)
|
31
31
|
insn
|
32
32
|
end
|
33
33
|
end
|