aarch64 1.0.1 → 2.0.0

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Files changed (277) hide show
  1. checksums.yaml +4 -4
  2. data/README.md +1 -1
  3. data/Rakefile +37 -0
  4. data/aarch64.gemspec +1 -0
  5. data/lib/aarch64/instructions/adc.rb +10 -10
  6. data/lib/aarch64/instructions/adcs.rb +10 -10
  7. data/lib/aarch64/instructions/add_addsub_ext.rb +14 -14
  8. data/lib/aarch64/instructions/add_addsub_imm.rb +12 -12
  9. data/lib/aarch64/instructions/add_addsub_shift.rb +14 -14
  10. data/lib/aarch64/instructions/addg.rb +10 -10
  11. data/lib/aarch64/instructions/adds_addsub_ext.rb +14 -14
  12. data/lib/aarch64/instructions/adds_addsub_imm.rb +12 -12
  13. data/lib/aarch64/instructions/adds_addsub_shift.rb +14 -14
  14. data/lib/aarch64/instructions/adr.rb +7 -7
  15. data/lib/aarch64/instructions/adrp.rb +7 -7
  16. data/lib/aarch64/instructions/and_log_imm.rb +14 -14
  17. data/lib/aarch64/instructions/and_log_shift.rb +14 -14
  18. data/lib/aarch64/instructions/ands_log_imm.rb +14 -14
  19. data/lib/aarch64/instructions/ands_log_shift.rb +14 -14
  20. data/lib/aarch64/instructions/asrv.rb +10 -10
  21. data/lib/aarch64/instructions/autda.rb +9 -12
  22. data/lib/aarch64/instructions/autdb.rb +9 -12
  23. data/lib/aarch64/instructions/autia.rb +9 -12
  24. data/lib/aarch64/instructions/autib.rb +9 -12
  25. data/lib/aarch64/instructions/axflag.rb +1 -1
  26. data/lib/aarch64/instructions/b_cond.rb +5 -5
  27. data/lib/aarch64/instructions/b_uncond.rb +3 -3
  28. data/lib/aarch64/instructions/bc_cond.rb +5 -5
  29. data/lib/aarch64/instructions/bfm.rb +13 -13
  30. data/lib/aarch64/instructions/bic_log_shift.rb +14 -14
  31. data/lib/aarch64/instructions/bics.rb +14 -14
  32. data/lib/aarch64/instructions/bl.rb +3 -3
  33. data/lib/aarch64/instructions/blr.rb +4 -4
  34. data/lib/aarch64/instructions/blra.rb +10 -10
  35. data/lib/aarch64/instructions/br.rb +4 -4
  36. data/lib/aarch64/instructions/bra.rb +10 -10
  37. data/lib/aarch64/instructions/brk.rb +3 -3
  38. data/lib/aarch64/instructions/bti.rb +3 -3
  39. data/lib/aarch64/instructions/cas.rb +14 -14
  40. data/lib/aarch64/instructions/casb.rb +12 -12
  41. data/lib/aarch64/instructions/cash.rb +12 -12
  42. data/lib/aarch64/instructions/casp.rb +14 -14
  43. data/lib/aarch64/instructions/cbnz.rb +7 -7
  44. data/lib/aarch64/instructions/cbz.rb +7 -7
  45. data/lib/aarch64/instructions/ccmn_imm.rb +12 -12
  46. data/lib/aarch64/instructions/ccmn_reg.rb +12 -12
  47. data/lib/aarch64/instructions/ccmp_imm.rb +12 -12
  48. data/lib/aarch64/instructions/ccmp_reg.rb +12 -12
  49. data/lib/aarch64/instructions/cfinv.rb +2 -9
  50. data/lib/aarch64/instructions/clrex.rb +3 -3
  51. data/lib/aarch64/instructions/cls_int.rb +8 -8
  52. data/lib/aarch64/instructions/clz_int.rb +8 -8
  53. data/lib/aarch64/instructions/crc32.rb +12 -12
  54. data/lib/aarch64/instructions/crc32c.rb +12 -12
  55. data/lib/aarch64/instructions/csdb.rb +1 -1
  56. data/lib/aarch64/instructions/csel.rb +12 -12
  57. data/lib/aarch64/instructions/csinc.rb +12 -12
  58. data/lib/aarch64/instructions/csinv.rb +12 -12
  59. data/lib/aarch64/instructions/csneg.rb +12 -12
  60. data/lib/aarch64/instructions/dcps.rb +5 -5
  61. data/lib/aarch64/instructions/dgh.rb +1 -1
  62. data/lib/aarch64/instructions/dmb.rb +3 -3
  63. data/lib/aarch64/instructions/drps.rb +2 -9
  64. data/lib/aarch64/instructions/dsb.rb +3 -3
  65. data/lib/aarch64/instructions/eon.rb +14 -14
  66. data/lib/aarch64/instructions/eor_log_imm.rb +14 -14
  67. data/lib/aarch64/instructions/eor_log_shift.rb +14 -14
  68. data/lib/aarch64/instructions/eret.rb +2 -9
  69. data/lib/aarch64/instructions/ereta.rb +3 -3
  70. data/lib/aarch64/instructions/esb.rb +1 -1
  71. data/lib/aarch64/instructions/extr.rb +13 -13
  72. data/lib/aarch64/instructions/gmi.rb +8 -8
  73. data/lib/aarch64/instructions/hint.rb +5 -5
  74. data/lib/aarch64/instructions/hlt.rb +3 -3
  75. data/lib/aarch64/instructions/hvc.rb +3 -3
  76. data/lib/aarch64/instructions/irg.rb +8 -8
  77. data/lib/aarch64/instructions/isb.rb +3 -3
  78. data/lib/aarch64/instructions/ld64b.rb +6 -6
  79. data/lib/aarch64/instructions/ldadd.rb +14 -14
  80. data/lib/aarch64/instructions/ldaddb.rb +12 -12
  81. data/lib/aarch64/instructions/ldaddh.rb +12 -12
  82. data/lib/aarch64/instructions/ldapr.rb +8 -8
  83. data/lib/aarch64/instructions/ldaprb.rb +6 -6
  84. data/lib/aarch64/instructions/ldaprh.rb +6 -6
  85. data/lib/aarch64/instructions/ldapur_gen.rb +12 -12
  86. data/lib/aarch64/instructions/ldar.rb +8 -8
  87. data/lib/aarch64/instructions/ldaxp.rb +10 -10
  88. data/lib/aarch64/instructions/ldaxr.rb +8 -8
  89. data/lib/aarch64/instructions/ldclr.rb +14 -14
  90. data/lib/aarch64/instructions/ldclrb.rb +14 -14
  91. data/lib/aarch64/instructions/ldeor.rb +14 -14
  92. data/lib/aarch64/instructions/ldg.rb +8 -8
  93. data/lib/aarch64/instructions/ldgm.rb +6 -6
  94. data/lib/aarch64/instructions/ldlar.rb +8 -8
  95. data/lib/aarch64/instructions/ldnp_gen.rb +12 -12
  96. data/lib/aarch64/instructions/ldp_gen.rb +14 -14
  97. data/lib/aarch64/instructions/ldpsw.rb +12 -12
  98. data/lib/aarch64/instructions/ldr_imm_gen.rb +12 -12
  99. data/lib/aarch64/instructions/ldr_imm_unsigned.rb +10 -10
  100. data/lib/aarch64/instructions/ldr_lit_gen.rb +7 -7
  101. data/lib/aarch64/instructions/ldr_reg_gen.rb +14 -14
  102. data/lib/aarch64/instructions/ldra.rb +14 -14
  103. data/lib/aarch64/instructions/ldrb_imm.rb +10 -10
  104. data/lib/aarch64/instructions/ldrb_reg.rb +12 -12
  105. data/lib/aarch64/instructions/ldrb_unsigned.rb +8 -8
  106. data/lib/aarch64/instructions/ldrh_imm.rb +10 -10
  107. data/lib/aarch64/instructions/ldrh_reg.rb +12 -12
  108. data/lib/aarch64/instructions/ldrh_unsigned.rb +8 -8
  109. data/lib/aarch64/instructions/ldrsb_imm.rb +12 -12
  110. data/lib/aarch64/instructions/ldrsb_reg.rb +14 -14
  111. data/lib/aarch64/instructions/ldrsb_unsigned.rb +10 -10
  112. data/lib/aarch64/instructions/ldrsh_imm.rb +12 -12
  113. data/lib/aarch64/instructions/ldrsh_reg.rb +14 -14
  114. data/lib/aarch64/instructions/ldrsh_unsigned.rb +10 -10
  115. data/lib/aarch64/instructions/ldrsw_imm.rb +10 -10
  116. data/lib/aarch64/instructions/ldrsw_lit.rb +5 -5
  117. data/lib/aarch64/instructions/ldrsw_reg.rb +12 -12
  118. data/lib/aarch64/instructions/ldrsw_unsigned.rb +8 -8
  119. data/lib/aarch64/instructions/ldset.rb +14 -14
  120. data/lib/aarch64/instructions/ldsetb.rb +12 -12
  121. data/lib/aarch64/instructions/ldseth.rb +12 -12
  122. data/lib/aarch64/instructions/ldsmax.rb +14 -14
  123. data/lib/aarch64/instructions/ldsmaxb.rb +12 -12
  124. data/lib/aarch64/instructions/ldsmaxh.rb +12 -12
  125. data/lib/aarch64/instructions/ldsmin.rb +14 -14
  126. data/lib/aarch64/instructions/ldsminb.rb +12 -12
  127. data/lib/aarch64/instructions/ldsminh.rb +12 -12
  128. data/lib/aarch64/instructions/ldtr.rb +10 -10
  129. data/lib/aarch64/instructions/ldtrb.rb +8 -8
  130. data/lib/aarch64/instructions/ldtrh.rb +8 -8
  131. data/lib/aarch64/instructions/ldtrsb.rb +10 -10
  132. data/lib/aarch64/instructions/ldtrsh.rb +10 -10
  133. data/lib/aarch64/instructions/ldtrsw.rb +8 -8
  134. data/lib/aarch64/instructions/ldumax.rb +14 -14
  135. data/lib/aarch64/instructions/ldumaxb.rb +12 -12
  136. data/lib/aarch64/instructions/ldumaxh.rb +12 -12
  137. data/lib/aarch64/instructions/ldumin.rb +14 -14
  138. data/lib/aarch64/instructions/lduminb.rb +12 -12
  139. data/lib/aarch64/instructions/lduminh.rb +12 -12
  140. data/lib/aarch64/instructions/ldur_gen.rb +10 -10
  141. data/lib/aarch64/instructions/ldursb.rb +10 -10
  142. data/lib/aarch64/instructions/ldursh.rb +10 -10
  143. data/lib/aarch64/instructions/ldursw.rb +8 -8
  144. data/lib/aarch64/instructions/ldxp.rb +10 -10
  145. data/lib/aarch64/instructions/ldxr.rb +8 -8
  146. data/lib/aarch64/instructions/lslv.rb +10 -10
  147. data/lib/aarch64/instructions/lsrv.rb +10 -10
  148. data/lib/aarch64/instructions/madd.rb +12 -12
  149. data/lib/aarch64/instructions/movk.rb +10 -10
  150. data/lib/aarch64/instructions/movn.rb +10 -10
  151. data/lib/aarch64/instructions/movz.rb +10 -10
  152. data/lib/aarch64/instructions/mrs.rb +14 -14
  153. data/lib/aarch64/instructions/msr_imm.rb +7 -7
  154. data/lib/aarch64/instructions/msr_reg.rb +14 -14
  155. data/lib/aarch64/instructions/msub.rb +12 -12
  156. data/lib/aarch64/instructions/nop.rb +1 -1
  157. data/lib/aarch64/instructions/orn_log_shift.rb +14 -14
  158. data/lib/aarch64/instructions/orr_log_imm.rb +14 -14
  159. data/lib/aarch64/instructions/orr_log_shift.rb +14 -14
  160. data/lib/aarch64/instructions/pacda.rb +8 -8
  161. data/lib/aarch64/instructions/pacdb.rb +8 -8
  162. data/lib/aarch64/instructions/pacga.rb +8 -8
  163. data/lib/aarch64/instructions/pacia.rb +8 -8
  164. data/lib/aarch64/instructions/pacia2.rb +5 -5
  165. data/lib/aarch64/instructions/pacib.rb +8 -8
  166. data/lib/aarch64/instructions/prfm_imm.rb +8 -8
  167. data/lib/aarch64/instructions/prfm_lit.rb +8 -8
  168. data/lib/aarch64/instructions/prfm_reg.rb +12 -12
  169. data/lib/aarch64/instructions/prfum.rb +8 -8
  170. data/lib/aarch64/instructions/psb.rb +2 -9
  171. data/lib/aarch64/instructions/rbit_int.rb +8 -8
  172. data/lib/aarch64/instructions/ret.rb +4 -4
  173. data/lib/aarch64/instructions/reta.rb +3 -3
  174. data/lib/aarch64/instructions/rev.rb +10 -10
  175. data/lib/aarch64/instructions/rmif.rb +8 -8
  176. data/lib/aarch64/instructions/rorv.rb +10 -10
  177. data/lib/aarch64/instructions/sb.rb +1 -1
  178. data/lib/aarch64/instructions/sbc.rb +10 -10
  179. data/lib/aarch64/instructions/sbcs.rb +10 -10
  180. data/lib/aarch64/instructions/sbfm.rb +13 -13
  181. data/lib/aarch64/instructions/sdiv.rb +10 -10
  182. data/lib/aarch64/instructions/setf.rb +6 -6
  183. data/lib/aarch64/instructions/sev.rb +1 -7
  184. data/lib/aarch64/instructions/sevl.rb +1 -1
  185. data/lib/aarch64/instructions/smaddl.rb +10 -10
  186. data/lib/aarch64/instructions/smc.rb +3 -3
  187. data/lib/aarch64/instructions/smsubl.rb +10 -10
  188. data/lib/aarch64/instructions/smulh.rb +8 -8
  189. data/lib/aarch64/instructions/st2g.rb +10 -10
  190. data/lib/aarch64/instructions/st64b.rb +6 -6
  191. data/lib/aarch64/instructions/st64bv.rb +8 -8
  192. data/lib/aarch64/instructions/st64bv0.rb +8 -8
  193. data/lib/aarch64/instructions/stg.rb +10 -10
  194. data/lib/aarch64/instructions/stgm.rb +6 -6
  195. data/lib/aarch64/instructions/stgp.rb +12 -12
  196. data/lib/aarch64/instructions/stllr.rb +8 -8
  197. data/lib/aarch64/instructions/stllrb.rb +6 -6
  198. data/lib/aarch64/instructions/stllrh.rb +6 -6
  199. data/lib/aarch64/instructions/stlr.rb +8 -8
  200. data/lib/aarch64/instructions/stlrb.rb +6 -6
  201. data/lib/aarch64/instructions/stlrh.rb +6 -6
  202. data/lib/aarch64/instructions/stlur_gen.rb +10 -10
  203. data/lib/aarch64/instructions/stlxp.rb +12 -12
  204. data/lib/aarch64/instructions/stlxr.rb +10 -10
  205. data/lib/aarch64/instructions/stlxrb.rb +8 -8
  206. data/lib/aarch64/instructions/stlxrh.rb +8 -8
  207. data/lib/aarch64/instructions/stnp_gen.rb +12 -12
  208. data/lib/aarch64/instructions/stp_gen.rb +14 -14
  209. data/lib/aarch64/instructions/str_imm_gen.rb +12 -12
  210. data/lib/aarch64/instructions/str_imm_unsigned.rb +10 -10
  211. data/lib/aarch64/instructions/str_reg_gen.rb +14 -14
  212. data/lib/aarch64/instructions/strb_imm.rb +10 -10
  213. data/lib/aarch64/instructions/strb_imm_unsigned.rb +8 -8
  214. data/lib/aarch64/instructions/strb_reg.rb +12 -12
  215. data/lib/aarch64/instructions/strh_imm.rb +10 -10
  216. data/lib/aarch64/instructions/strh_imm_unsigned.rb +8 -8
  217. data/lib/aarch64/instructions/strh_reg.rb +12 -12
  218. data/lib/aarch64/instructions/sttr.rb +10 -10
  219. data/lib/aarch64/instructions/stur_gen.rb +10 -10
  220. data/lib/aarch64/instructions/stxp.rb +12 -12
  221. data/lib/aarch64/instructions/stxr.rb +10 -10
  222. data/lib/aarch64/instructions/stxrb.rb +8 -8
  223. data/lib/aarch64/instructions/stxrh.rb +8 -8
  224. data/lib/aarch64/instructions/stz2g.rb +10 -10
  225. data/lib/aarch64/instructions/stzg.rb +10 -10
  226. data/lib/aarch64/instructions/stzgm.rb +6 -6
  227. data/lib/aarch64/instructions/sub_addsub_ext.rb +14 -14
  228. data/lib/aarch64/instructions/sub_addsub_imm.rb +12 -12
  229. data/lib/aarch64/instructions/sub_addsub_shift.rb +14 -14
  230. data/lib/aarch64/instructions/subg.rb +10 -10
  231. data/lib/aarch64/instructions/subp.rb +8 -8
  232. data/lib/aarch64/instructions/subps.rb +8 -8
  233. data/lib/aarch64/instructions/subs_addsub_ext.rb +14 -14
  234. data/lib/aarch64/instructions/subs_addsub_imm.rb +12 -12
  235. data/lib/aarch64/instructions/subs_addsub_shift.rb +14 -14
  236. data/lib/aarch64/instructions/svc.rb +3 -3
  237. data/lib/aarch64/instructions/swp.rb +14 -14
  238. data/lib/aarch64/instructions/swpb.rb +12 -12
  239. data/lib/aarch64/instructions/swph.rb +12 -12
  240. data/lib/aarch64/instructions/sys.rb +12 -12
  241. data/lib/aarch64/instructions/sysl.rb +12 -12
  242. data/lib/aarch64/instructions/tbnz.rb +9 -9
  243. data/lib/aarch64/instructions/tbz.rb +9 -9
  244. data/lib/aarch64/instructions/tsb.rb +1 -7
  245. data/lib/aarch64/instructions/ubfm.rb +13 -13
  246. data/lib/aarch64/instructions/udf_perm_undef.rb +3 -3
  247. data/lib/aarch64/instructions/udiv.rb +10 -10
  248. data/lib/aarch64/instructions/umaddl.rb +10 -10
  249. data/lib/aarch64/instructions/umsubl.rb +10 -10
  250. data/lib/aarch64/instructions/umulh.rb +8 -8
  251. data/lib/aarch64/instructions/wfe.rb +2 -9
  252. data/lib/aarch64/instructions/wfet.rb +4 -4
  253. data/lib/aarch64/instructions/wfi.rb +1 -1
  254. data/lib/aarch64/instructions/wfit.rb +4 -4
  255. data/lib/aarch64/instructions/xaflag.rb +1 -1
  256. data/lib/aarch64/instructions/xpac.rb +6 -6
  257. data/lib/aarch64/instructions/xpaclri.rb +1 -1
  258. data/lib/aarch64/instructions/yield.rb +2 -9
  259. data/lib/aarch64/instructions.rb +26 -8
  260. data/lib/aarch64/parser.rb +227 -0
  261. data/lib/aarch64/parser.tab.rb +6534 -0
  262. data/lib/aarch64/parser.y +1394 -0
  263. data/lib/aarch64/utils.rb +34 -0
  264. data/lib/aarch64/version.rb +1 -1
  265. data/lib/aarch64.rb +128 -58
  266. data/test/base_instructions_test.rb +34 -4
  267. data/test/helper.rb +48 -8
  268. data/test/parser_test.rb +1820 -0
  269. metadata +25 -14
  270. data/lib/aarch64/instructions/setgp.rb +0 -25
  271. data/lib/aarch64/instructions/setgpn.rb +0 -25
  272. data/lib/aarch64/instructions/setgpt.rb +0 -25
  273. data/lib/aarch64/instructions/setgptn.rb +0 -25
  274. data/lib/aarch64/instructions/setp.rb +0 -25
  275. data/lib/aarch64/instructions/setpn.rb +0 -25
  276. data/lib/aarch64/instructions/setpt.rb +0 -25
  277. data/lib/aarch64/instructions/setptn.rb +0 -25
@@ -6,28 +6,28 @@ module AArch64
6
6
  # SWPALB <Ws>, <Wt>, [<Xn|SP>]
7
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  # SWPB <Ws>, <Wt>, [<Xn|SP>]
8
8
  # SWPLB <Ws>, <Wt>, [<Xn|SP>]
9
- class SWPB
9
+ class SWPB < Instruction
10
10
  def initialize rs, rt, rn, a, r
11
- @rs = rs
12
- @rt = rt
13
- @rn = rn
14
- @a = a
15
- @r = r
11
+ @rs = check_mask(rs, 0x1f)
12
+ @rt = check_mask(rt, 0x1f)
13
+ @rn = check_mask(rn, 0x1f)
14
+ @a = check_mask(a, 0x01)
15
+ @r = check_mask(r, 0x01)
16
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  end
17
17
 
18
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  def encode
19
- SWPB(@a, @r, @rs.to_i, @rn.to_i, @rt.to_i)
19
+ SWPB(@a, @r, @rs, @rn, @rt)
20
20
  end
21
21
 
22
22
  private
23
23
 
24
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  def SWPB a, r, rs, rn, rt
25
25
  insn = 0b00_111_0_00_0_0_1_00000_1_000_00_00000_00000
26
- insn |= ((a & 0x1) << 23)
27
- insn |= ((r & 0x1) << 22)
28
- insn |= ((rs & 0x1f) << 16)
29
- insn |= ((rn & 0x1f) << 5)
30
- insn |= (rt & 0x1f)
26
+ insn |= ((a) << 23)
27
+ insn |= ((r) << 22)
28
+ insn |= ((rs) << 16)
29
+ insn |= ((rn) << 5)
30
+ insn |= (rt)
31
31
  insn
32
32
  end
33
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  end
@@ -6,28 +6,28 @@ module AArch64
6
6
  # SWPALH <Ws>, <Wt>, [<Xn|SP>]
7
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  # SWPH <Ws>, <Wt>, [<Xn|SP>]
8
8
  # SWPLH <Ws>, <Wt>, [<Xn|SP>]
9
- class SWPH
9
+ class SWPH < Instruction
10
10
  def initialize rs, rt, rn, a, r
11
- @rs = rs
12
- @rt = rt
13
- @rn = rn
14
- @a = a
15
- @r = r
11
+ @rs = check_mask(rs, 0x1f)
12
+ @rt = check_mask(rt, 0x1f)
13
+ @rn = check_mask(rn, 0x1f)
14
+ @a = check_mask(a, 0x01)
15
+ @r = check_mask(r, 0x01)
16
16
  end
17
17
 
18
18
  def encode
19
- SWPH(@a, @r, @rs.to_i, @rn.to_i, @rt.to_i)
19
+ SWPH(@a, @r, @rs, @rn, @rt)
20
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  end
21
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22
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  private
23
23
 
24
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  def SWPH a, r, rs, rn, rt
25
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  insn = 0b01_111_0_00_0_0_1_00000_1_000_00_00000_00000
26
- insn |= ((a & 0x1) << 23)
27
- insn |= ((r & 0x1) << 22)
28
- insn |= ((rs & 0x1f) << 16)
29
- insn |= ((rn & 0x1f) << 5)
30
- insn |= (rt & 0x1f)
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+ insn |= ((a) << 23)
27
+ insn |= ((r) << 22)
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+ insn |= ((rs) << 16)
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+ insn |= ((rn) << 5)
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+ insn |= (rt)
31
31
  insn
32
32
  end
33
33
  end
@@ -3,28 +3,28 @@ module AArch64
3
3
  # SYS -- A64
4
4
  # System instruction
5
5
  # SYS #<op1>, <Cn>, <Cm>, #<op2>{, <Xt>}
6
- class SYS
6
+ class SYS < Instruction
7
7
  def initialize op1, cn, cm, op2, xt
8
- @op1 = op1
9
- @cn = cn
10
- @cm = cm
11
- @op2 = op2
12
- @xt = xt
8
+ @op1 = check_mask(op1, 0x07)
9
+ @cn = check_mask(cn, 0x0f)
10
+ @cm = check_mask(cm, 0x0f)
11
+ @op2 = check_mask(op2, 0x07)
12
+ @xt = check_mask(xt, 0x1f)
13
13
  end
14
14
 
15
15
  def encode
16
- SYS(@op1, @cn, @cm, @op2, @xt.to_i)
16
+ SYS(@op1, @cn, @cm, @op2, @xt)
17
17
  end
18
18
 
19
19
  private
20
20
 
21
21
  def SYS op1, crn, crm, op2, rt
22
22
  insn = 0b1101010100_0_01_000_0000_0000_000_00000
23
- insn |= ((op1 & 0x7) << 16)
24
- insn |= ((crn & 0xf) << 12)
25
- insn |= ((crm & 0xf) << 8)
26
- insn |= ((op2 & 0x7) << 5)
27
- insn |= (rt & 0x1f)
23
+ insn |= ((op1) << 16)
24
+ insn |= ((crn) << 12)
25
+ insn |= ((crm) << 8)
26
+ insn |= ((op2) << 5)
27
+ insn |= (rt)
28
28
  insn
29
29
  end
30
30
  end
@@ -3,28 +3,28 @@ module AArch64
3
3
  # SYSL -- A64
4
4
  # System instruction with result
5
5
  # SYSL <Xt>, #<op1>, <Cn>, <Cm>, #<op2>
6
- class SYSL
6
+ class SYSL < Instruction
7
7
  def initialize xt, op1, cn, cm, op2
8
- @xt = xt
9
- @op1 = op1
10
- @cn = cn
11
- @cm = cm
12
- @op2 = op2
8
+ @xt = check_mask(xt, 0x1f)
9
+ @op1 = check_mask(op1, 0x07)
10
+ @cn = check_mask(cn, 0x0f)
11
+ @cm = check_mask(cm, 0x0f)
12
+ @op2 = check_mask(op2, 0x07)
13
13
  end
14
14
 
15
15
  def encode
16
- SYSL(@op1, @cn.to_i, @cm.to_i, @op2, @xt.to_i)
16
+ SYSL(@op1, @cn, @cm, @op2, @xt)
17
17
  end
18
18
 
19
19
  private
20
20
 
21
21
  def SYSL op1, crn, crm, op2, rt
22
22
  insn = 0b1101010100_1_01_000_0000_0000_000_00000
23
- insn |= ((op1 & 0x7) << 16)
24
- insn |= ((crn & 0xf) << 12)
25
- insn |= ((crm & 0xf) << 8)
26
- insn |= ((op2 & 0x7) << 5)
27
- insn |= (rt & 0x1f)
23
+ insn |= ((op1) << 16)
24
+ insn |= ((crn) << 12)
25
+ insn |= ((crm) << 8)
26
+ insn |= ((op2) << 5)
27
+ insn |= (rt)
28
28
  insn
29
29
  end
30
30
  end
@@ -3,26 +3,26 @@ module AArch64
3
3
  # TBNZ -- A64
4
4
  # Test bit and Branch if Nonzero
5
5
  # TBNZ <R><t>, #<imm>, <label>
6
- class TBNZ
6
+ class TBNZ < Instruction
7
7
  def initialize rt, imm, label, sf
8
- @rt = rt
9
- @imm = imm
8
+ @rt = check_mask(rt, 0x1f)
9
+ @imm = check_mask(imm, 0x1f)
10
10
  @label = label
11
- @sf = sf
11
+ @sf = check_mask(sf, 0x1)
12
12
  end
13
13
 
14
14
  def encode
15
- TBNZ(@sf, @imm, @label.to_i / 4, @rt.to_i)
15
+ TBNZ(@sf, @imm, check_mask(unwrap_label(@label), 0x3fff), @rt)
16
16
  end
17
17
 
18
18
  private
19
19
 
20
20
  def TBNZ b5, b40, imm14, rt
21
21
  insn = 0b0_011011_1_00000_00000000000000_00000
22
- insn |= ((b5 & 0x1) << 31)
23
- insn |= ((b40 & 0x1f) << 19)
24
- insn |= ((imm14 & 0x3fff) << 5)
25
- insn |= (rt & 0x1f)
22
+ insn |= (b5 << 31)
23
+ insn |= (b40 << 19)
24
+ insn |= (imm14 << 5)
25
+ insn |= rt
26
26
  insn
27
27
  end
28
28
  end
@@ -3,26 +3,26 @@ module AArch64
3
3
  # TBZ -- A64
4
4
  # Test bit and Branch if Zero
5
5
  # TBZ <R><t>, #<imm>, <label>
6
- class TBZ
6
+ class TBZ < Instruction
7
7
  def initialize rt, imm, label, sf
8
- @rt = rt
9
- @imm = imm
8
+ @rt = check_mask(rt, 0x1f)
9
+ @imm = check_mask(imm, 0x1f)
10
10
  @label = label
11
- @sf = sf
11
+ @sf = check_mask(sf, 0x1)
12
12
  end
13
13
 
14
14
  def encode
15
- TBZ(@sf, @imm, @label.to_i / 4, @rt.to_i)
15
+ TBZ(@sf, @imm, check_mask(unwrap_label(@label), 0x3fff), @rt)
16
16
  end
17
17
 
18
18
  private
19
19
 
20
20
  def TBZ b5, b40, imm14, rt
21
21
  insn = 0b0_011011_0_00000_00000000000000_00000
22
- insn |= ((b5 & 0x1) << 31)
23
- insn |= ((b40 & 0x1f) << 19)
24
- insn |= ((imm14 & 0x3fff) << 5)
25
- insn |= (rt & 0x1f)
22
+ insn |= (b5 << 31)
23
+ insn |= (b40 << 19)
24
+ insn |= (imm14 << 5)
25
+ insn |= rt
26
26
  insn
27
27
  end
28
28
  end
@@ -3,14 +3,8 @@ module AArch64
3
3
  # TSB CSYNC -- A64
4
4
  # Trace Synchronization Barrier
5
5
  # TSB CSYNC
6
- class TSB
6
+ class TSB < Instruction
7
7
  def encode
8
- TSB()
9
- end
10
-
11
- private
12
-
13
- def TSB
14
8
  0b1101010100_0_00_011_0010_0010_010_11111
15
9
  end
16
10
  end
@@ -4,29 +4,29 @@ module AArch64
4
4
  # Unsigned Bitfield Move
5
5
  # UBFM <Wd>, <Wn>, #<immr>, #<imms>
6
6
  # UBFM <Xd>, <Xn>, #<immr>, #<imms>
7
- class UBFM
7
+ class UBFM < Instruction
8
8
  def initialize rd, rn, immr, imms, sf
9
- @rd = rd
10
- @rn = rn
11
- @immr = immr
12
- @imms = imms
13
- @sf = sf
9
+ @rd = check_mask(rd, 0x1f)
10
+ @rn = check_mask(rn, 0x1f)
11
+ @immr = check_mask(immr, 0x3f)
12
+ @imms = check_mask(imms, 0x3f)
13
+ @sf = check_mask(sf, 0x01)
14
14
  end
15
15
 
16
16
  def encode
17
- UBFM(@sf, @sf, @immr, @imms, @rn.to_i, @rd.to_i)
17
+ UBFM(@sf, @sf, @immr, @imms, @rn, @rd)
18
18
  end
19
19
 
20
20
  private
21
21
 
22
22
  def UBFM sf, n, immr, imms, rn, rd
23
23
  insn = 0b0_10_100110_0_000000_000000_00000_00000
24
- insn |= ((sf & 0x1) << 31)
25
- insn |= ((n & 0x1) << 22)
26
- insn |= ((immr & 0x3f) << 16)
27
- insn |= ((imms & 0x3f) << 10)
28
- insn |= ((rn & 0x1f) << 5)
29
- insn |= (rd & 0x1f)
24
+ insn |= ((sf) << 31)
25
+ insn |= ((n) << 22)
26
+ insn |= ((immr) << 16)
27
+ insn |= ((imms) << 10)
28
+ insn |= ((rn) << 5)
29
+ insn |= (rd)
30
30
  insn
31
31
  end
32
32
  end
@@ -3,9 +3,9 @@ module AArch64
3
3
  # UDF -- A64
4
4
  # Permanently Undefined
5
5
  # UDF #<imm>
6
- class UDF_perm_undef
6
+ class UDF_perm_undef < Instruction
7
7
  def initialize imm
8
- @imm = imm
8
+ @imm = check_mask(imm, 0xffff)
9
9
  end
10
10
 
11
11
  def encode
@@ -16,7 +16,7 @@ module AArch64
16
16
 
17
17
  def UDF_perm_undef imm16
18
18
  insn = 0b0000000000000000_0000000000000000
19
- insn |= (imm16 & 0xffff)
19
+ insn |= (imm16)
20
20
  insn
21
21
  end
22
22
  end
@@ -4,26 +4,26 @@ module AArch64
4
4
  # Unsigned Divide
5
5
  # UDIV <Wd>, <Wn>, <Wm>
6
6
  # UDIV <Xd>, <Xn>, <Xm>
7
- class UDIV
7
+ class UDIV < Instruction
8
8
  def initialize rd, rn, rm, sf
9
- @rd = rd
10
- @rn = rn
11
- @rm = rm
12
- @sf = sf
9
+ @rd = check_mask(rd, 0x1f)
10
+ @rn = check_mask(rn, 0x1f)
11
+ @rm = check_mask(rm, 0x1f)
12
+ @sf = check_mask(sf, 0x01)
13
13
  end
14
14
 
15
15
  def encode
16
- UDIV(@sf, @rm.to_i, @rn.to_i, @rd.to_i)
16
+ UDIV(@sf, @rm, @rn, @rd)
17
17
  end
18
18
 
19
19
  private
20
20
 
21
21
  def UDIV sf, rm, rn, rd
22
22
  insn = 0b0_0_0_11010110_00000_00001_0_00000_00000
23
- insn |= ((sf & 0x1) << 31)
24
- insn |= ((rm & 0x1f) << 16)
25
- insn |= ((rn & 0x1f) << 5)
26
- insn |= (rd & 0x1f)
23
+ insn |= ((sf) << 31)
24
+ insn |= ((rm) << 16)
25
+ insn |= ((rn) << 5)
26
+ insn |= (rd)
27
27
  insn
28
28
  end
29
29
  end
@@ -3,26 +3,26 @@ module AArch64
3
3
  # UMADDL -- A64
4
4
  # Unsigned Multiply-Add Long
5
5
  # UMADDL <Xd>, <Wn>, <Wm>, <Xa>
6
- class UMADDL
6
+ class UMADDL < Instruction
7
7
  def initialize xd, wn, wm, xa
8
- @xd = xd
9
- @wn = wn
10
- @wm = wm
11
- @xa = xa
8
+ @xd = check_mask(xd, 0x1f)
9
+ @wn = check_mask(wn, 0x1f)
10
+ @wm = check_mask(wm, 0x1f)
11
+ @xa = check_mask(xa, 0x1f)
12
12
  end
13
13
 
14
14
  def encode
15
- UMADDL(@wm.to_i, @xa.to_i, @wn.to_i, @xd.to_i)
15
+ UMADDL(@wm, @xa, @wn, @xd)
16
16
  end
17
17
 
18
18
  private
19
19
 
20
20
  def UMADDL rm, ra, rn, rd
21
21
  insn = 0b1_00_11011_1_01_00000_0_00000_00000_00000
22
- insn |= ((rm & 0x1f) << 16)
23
- insn |= ((ra & 0x1f) << 10)
24
- insn |= ((rn & 0x1f) << 5)
25
- insn |= (rd & 0x1f)
22
+ insn |= ((rm) << 16)
23
+ insn |= ((ra) << 10)
24
+ insn |= ((rn) << 5)
25
+ insn |= (rd)
26
26
  insn
27
27
  end
28
28
  end
@@ -3,26 +3,26 @@ module AArch64
3
3
  # UMSUBL -- A64
4
4
  # Unsigned Multiply-Subtract Long
5
5
  # UMSUBL <Xd>, <Wn>, <Wm>, <Xa>
6
- class UMSUBL
6
+ class UMSUBL < Instruction
7
7
  def initialize xd, wn, wm, xa
8
- @xd = xd
9
- @wn = wn
10
- @wm = wm
11
- @xa = xa
8
+ @xd = check_mask(xd, 0x1f)
9
+ @wn = check_mask(wn, 0x1f)
10
+ @wm = check_mask(wm, 0x1f)
11
+ @xa = check_mask(xa, 0x1f)
12
12
  end
13
13
 
14
14
  def encode
15
- UMSUBL(@wm.to_i, @xa.to_i, @wn.to_i, @xd.to_i)
15
+ UMSUBL(@wm, @xa, @wn, @xd)
16
16
  end
17
17
 
18
18
  private
19
19
 
20
20
  def UMSUBL rm, ra, rn, rd
21
21
  insn = 0b1_00_11011_1_01_00000_1_00000_00000_00000
22
- insn |= ((rm & 0x1f) << 16)
23
- insn |= ((ra & 0x1f) << 10)
24
- insn |= ((rn & 0x1f) << 5)
25
- insn |= (rd & 0x1f)
22
+ insn |= ((rm) << 16)
23
+ insn |= ((ra) << 10)
24
+ insn |= ((rn) << 5)
25
+ insn |= (rd)
26
26
  insn
27
27
  end
28
28
  end
@@ -3,24 +3,24 @@ module AArch64
3
3
  # UMULH -- A64
4
4
  # Unsigned Multiply High
5
5
  # UMULH <Xd>, <Xn>, <Xm>
6
- class UMULH
6
+ class UMULH < Instruction
7
7
  def initialize rd, rn, rm
8
- @rd = rd
9
- @rn = rn
10
- @rm = rm
8
+ @rd = check_mask(rd, 0x1f)
9
+ @rn = check_mask(rn, 0x1f)
10
+ @rm = check_mask(rm, 0x1f)
11
11
  end
12
12
 
13
13
  def encode
14
- UMULH(@rm.to_i, @rn.to_i, @rd.to_i)
14
+ UMULH(@rm, @rn, @rd)
15
15
  end
16
16
 
17
17
  private
18
18
 
19
19
  def UMULH rm, rn, rd
20
20
  insn = 0b1_00_11011_1_10_00000_0_11111_00000_00000
21
- insn |= ((rm & 0x1f) << 16)
22
- insn |= ((rn & 0x1f) << 5)
23
- insn |= (rd & 0x1f)
21
+ insn |= ((rm) << 16)
22
+ insn |= ((rn) << 5)
23
+ insn |= (rd)
24
24
  insn
25
25
  end
26
26
  end
@@ -3,16 +3,9 @@ module AArch64
3
3
  # WFE -- A64
4
4
  # Wait For Event
5
5
  # WFE
6
- class WFE
6
+ class WFE < Instruction
7
7
  def encode
8
- WFE()
9
- end
10
-
11
- private
12
-
13
- def WFE
14
- insn = 0b1101010100_0_00_011_0010_0000_010_11111
15
- insn
8
+ 0b1101010100_0_00_011_0010_0000_010_11111
16
9
  end
17
10
  end
18
11
  end
@@ -3,20 +3,20 @@ module AArch64
3
3
  # WFET -- A64
4
4
  # Wait For Event with Timeout
5
5
  # WFET <Xt>
6
- class WFET
6
+ class WFET < Instruction
7
7
  def initialize rd
8
- @rd = rd
8
+ @rd = check_mask(rd, 0x1f)
9
9
  end
10
10
 
11
11
  def encode
12
- WFET(@rd.to_i)
12
+ WFET(@rd)
13
13
  end
14
14
 
15
15
  private
16
16
 
17
17
  def WFET rd
18
18
  insn = 0b11010101000000110001_0000_000_00000
19
- insn |= (rd & 0x1f)
19
+ insn |= (rd)
20
20
  insn
21
21
  end
22
22
  end
@@ -3,7 +3,7 @@ module AArch64
3
3
  # WFI -- A64
4
4
  # Wait For Interrupt
5
5
  # WFI
6
- class WFI
6
+ class WFI < Instruction
7
7
  def encode
8
8
  0b1101010100_0_00_011_0010_0000_011_11111
9
9
  end
@@ -3,20 +3,20 @@ module AArch64
3
3
  # WFIT -- A64
4
4
  # Wait For Interrupt with Timeout
5
5
  # WFIT <Xt>
6
- class WFIT
6
+ class WFIT < Instruction
7
7
  def initialize rd
8
- @rd = rd
8
+ @rd = check_mask(rd, 0x1f)
9
9
  end
10
10
 
11
11
  def encode
12
- WFIT(@rd.to_i)
12
+ WFIT(@rd)
13
13
  end
14
14
 
15
15
  private
16
16
 
17
17
  def WFIT rd
18
18
  insn = 0b11010101000000110001_0000_001_00000
19
- insn |= (rd & 0x1f)
19
+ insn |= (rd)
20
20
  insn
21
21
  end
22
22
  end
@@ -3,7 +3,7 @@ module AArch64
3
3
  # XAFLAG -- A64
4
4
  # Convert floating-point condition flags from external format to Arm format
5
5
  # XAFLAG
6
- class XAFLAG
6
+ class XAFLAG < Instruction
7
7
  def encode
8
8
  0b1101010100_0_00_000_0100_0000_001_11111
9
9
  end
@@ -5,22 +5,22 @@ module AArch64
5
5
  # XPACD <Xd>
6
6
  # XPACI <Xd>
7
7
  # XPACLRI
8
- class XPAC
8
+ class XPAC < Instruction
9
9
  def initialize rd, d
10
- @rd = rd
11
- @d = d
10
+ @rd = check_mask(rd, 0x1f)
11
+ @d = check_mask(d, 0x01)
12
12
  end
13
13
 
14
14
  def encode
15
- XPAC(@d, @rd.to_i)
15
+ XPAC(@d, @rd)
16
16
  end
17
17
 
18
18
  private
19
19
 
20
20
  def XPAC d, rd
21
21
  insn = 0b1_1_0_11010110_00001_0_1_000_0_11111_00000
22
- insn |= ((d & 0x1) << 10)
23
- insn |= (rd & 0x1f)
22
+ insn |= ((d) << 10)
23
+ insn |= (rd)
24
24
  insn
25
25
  end
26
26
  end
@@ -3,7 +3,7 @@ module AArch64
3
3
  # XPACLRI -- A64
4
4
  # Strip Pointer Authentication Code
5
5
  # XPACLRI
6
- class XPACLRI
6
+ class XPACLRI < Instruction
7
7
  def encode
8
8
  0b11010101000000110010000011111111
9
9
  end
@@ -3,16 +3,9 @@ module AArch64
3
3
  # YIELD -- A64
4
4
  # YIELD
5
5
  # YIELD
6
- class YIELD
6
+ class YIELD < Instruction
7
7
  def encode
8
- YIELD()
9
- end
10
-
11
- private
12
-
13
- def YIELD
14
- insn = 0b1101010100_0_00_011_0010_0000_001_11111
15
- insn
8
+ 0b1101010100_0_00_011_0010_0000_001_11111
16
9
  end
17
10
  end
18
11
  end
@@ -1,5 +1,31 @@
1
1
  module AArch64
2
2
  module Instructions
3
+ class Instruction
4
+ private
5
+
6
+ def unwrap_label label
7
+ label.unwrap_label / 4
8
+ end
9
+
10
+ def check_mask val, mask
11
+ val = val.to_i
12
+
13
+ if val > mask
14
+ raise "Expected a #{popcount(mask)} bit number, but got 0x#{val.to_s(16)}"
15
+ end
16
+ val & mask
17
+ end
18
+
19
+ def popcount x
20
+ x -= ((x >> 1) & 0x55555555)
21
+ x = (x & 0x33333333) + ((x >> 2) & 0x33333333)
22
+ x = (x + (x >> 4)) & 0x0F0F0F0F
23
+ x += (x >> 8)
24
+ x += (x >> 16)
25
+ x & 0x3F
26
+ end
27
+ end
28
+
3
29
  autoload :ADC, "aarch64/instructions/adc"
4
30
  autoload :ADCS, "aarch64/instructions/adcs"
5
31
  autoload :ADD_addsub_ext, "aarch64/instructions/add_addsub_ext"
@@ -178,14 +204,6 @@ module AArch64
178
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  autoload :SBFM, "aarch64/instructions/sbfm"
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  autoload :SDIV, "aarch64/instructions/sdiv"
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  autoload :SETF, "aarch64/instructions/setf"
181
- autoload :SETGP, "aarch64/instructions/setgp"
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- autoload :SETGPN, "aarch64/instructions/setgpn"
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- autoload :SETGPT, "aarch64/instructions/setgpt"
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- autoload :SETGPTN, "aarch64/instructions/setgptn"
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- autoload :SETP, "aarch64/instructions/setp"
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- autoload :SETPN, "aarch64/instructions/setpn"
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- autoload :SETPT, "aarch64/instructions/setpt"
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- autoload :SETPTN, "aarch64/instructions/setptn"
189
207
  autoload :SEV, "aarch64/instructions/sev"
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  autoload :SEVL, "aarch64/instructions/sevl"
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  autoload :SMADDL, "aarch64/instructions/smaddl"