aarch64 1.0.1 → 2.0.0
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- checksums.yaml +4 -4
- data/README.md +1 -1
- data/Rakefile +37 -0
- data/aarch64.gemspec +1 -0
- data/lib/aarch64/instructions/adc.rb +10 -10
- data/lib/aarch64/instructions/adcs.rb +10 -10
- data/lib/aarch64/instructions/add_addsub_ext.rb +14 -14
- data/lib/aarch64/instructions/add_addsub_imm.rb +12 -12
- data/lib/aarch64/instructions/add_addsub_shift.rb +14 -14
- data/lib/aarch64/instructions/addg.rb +10 -10
- data/lib/aarch64/instructions/adds_addsub_ext.rb +14 -14
- data/lib/aarch64/instructions/adds_addsub_imm.rb +12 -12
- data/lib/aarch64/instructions/adds_addsub_shift.rb +14 -14
- data/lib/aarch64/instructions/adr.rb +7 -7
- data/lib/aarch64/instructions/adrp.rb +7 -7
- data/lib/aarch64/instructions/and_log_imm.rb +14 -14
- data/lib/aarch64/instructions/and_log_shift.rb +14 -14
- data/lib/aarch64/instructions/ands_log_imm.rb +14 -14
- data/lib/aarch64/instructions/ands_log_shift.rb +14 -14
- data/lib/aarch64/instructions/asrv.rb +10 -10
- data/lib/aarch64/instructions/autda.rb +9 -12
- data/lib/aarch64/instructions/autdb.rb +9 -12
- data/lib/aarch64/instructions/autia.rb +9 -12
- data/lib/aarch64/instructions/autib.rb +9 -12
- data/lib/aarch64/instructions/axflag.rb +1 -1
- data/lib/aarch64/instructions/b_cond.rb +5 -5
- data/lib/aarch64/instructions/b_uncond.rb +3 -3
- data/lib/aarch64/instructions/bc_cond.rb +5 -5
- data/lib/aarch64/instructions/bfm.rb +13 -13
- data/lib/aarch64/instructions/bic_log_shift.rb +14 -14
- data/lib/aarch64/instructions/bics.rb +14 -14
- data/lib/aarch64/instructions/bl.rb +3 -3
- data/lib/aarch64/instructions/blr.rb +4 -4
- data/lib/aarch64/instructions/blra.rb +10 -10
- data/lib/aarch64/instructions/br.rb +4 -4
- data/lib/aarch64/instructions/bra.rb +10 -10
- data/lib/aarch64/instructions/brk.rb +3 -3
- data/lib/aarch64/instructions/bti.rb +3 -3
- data/lib/aarch64/instructions/cas.rb +14 -14
- data/lib/aarch64/instructions/casb.rb +12 -12
- data/lib/aarch64/instructions/cash.rb +12 -12
- data/lib/aarch64/instructions/casp.rb +14 -14
- data/lib/aarch64/instructions/cbnz.rb +7 -7
- data/lib/aarch64/instructions/cbz.rb +7 -7
- data/lib/aarch64/instructions/ccmn_imm.rb +12 -12
- data/lib/aarch64/instructions/ccmn_reg.rb +12 -12
- data/lib/aarch64/instructions/ccmp_imm.rb +12 -12
- data/lib/aarch64/instructions/ccmp_reg.rb +12 -12
- data/lib/aarch64/instructions/cfinv.rb +2 -9
- data/lib/aarch64/instructions/clrex.rb +3 -3
- data/lib/aarch64/instructions/cls_int.rb +8 -8
- data/lib/aarch64/instructions/clz_int.rb +8 -8
- data/lib/aarch64/instructions/crc32.rb +12 -12
- data/lib/aarch64/instructions/crc32c.rb +12 -12
- data/lib/aarch64/instructions/csdb.rb +1 -1
- data/lib/aarch64/instructions/csel.rb +12 -12
- data/lib/aarch64/instructions/csinc.rb +12 -12
- data/lib/aarch64/instructions/csinv.rb +12 -12
- data/lib/aarch64/instructions/csneg.rb +12 -12
- data/lib/aarch64/instructions/dcps.rb +5 -5
- data/lib/aarch64/instructions/dgh.rb +1 -1
- data/lib/aarch64/instructions/dmb.rb +3 -3
- data/lib/aarch64/instructions/drps.rb +2 -9
- data/lib/aarch64/instructions/dsb.rb +3 -3
- data/lib/aarch64/instructions/eon.rb +14 -14
- data/lib/aarch64/instructions/eor_log_imm.rb +14 -14
- data/lib/aarch64/instructions/eor_log_shift.rb +14 -14
- data/lib/aarch64/instructions/eret.rb +2 -9
- data/lib/aarch64/instructions/ereta.rb +3 -3
- data/lib/aarch64/instructions/esb.rb +1 -1
- data/lib/aarch64/instructions/extr.rb +13 -13
- data/lib/aarch64/instructions/gmi.rb +8 -8
- data/lib/aarch64/instructions/hint.rb +5 -5
- data/lib/aarch64/instructions/hlt.rb +3 -3
- data/lib/aarch64/instructions/hvc.rb +3 -3
- data/lib/aarch64/instructions/irg.rb +8 -8
- data/lib/aarch64/instructions/isb.rb +3 -3
- data/lib/aarch64/instructions/ld64b.rb +6 -6
- data/lib/aarch64/instructions/ldadd.rb +14 -14
- data/lib/aarch64/instructions/ldaddb.rb +12 -12
- data/lib/aarch64/instructions/ldaddh.rb +12 -12
- data/lib/aarch64/instructions/ldapr.rb +8 -8
- data/lib/aarch64/instructions/ldaprb.rb +6 -6
- data/lib/aarch64/instructions/ldaprh.rb +6 -6
- data/lib/aarch64/instructions/ldapur_gen.rb +12 -12
- data/lib/aarch64/instructions/ldar.rb +8 -8
- data/lib/aarch64/instructions/ldaxp.rb +10 -10
- data/lib/aarch64/instructions/ldaxr.rb +8 -8
- data/lib/aarch64/instructions/ldclr.rb +14 -14
- data/lib/aarch64/instructions/ldclrb.rb +14 -14
- data/lib/aarch64/instructions/ldeor.rb +14 -14
- data/lib/aarch64/instructions/ldg.rb +8 -8
- data/lib/aarch64/instructions/ldgm.rb +6 -6
- data/lib/aarch64/instructions/ldlar.rb +8 -8
- data/lib/aarch64/instructions/ldnp_gen.rb +12 -12
- data/lib/aarch64/instructions/ldp_gen.rb +14 -14
- data/lib/aarch64/instructions/ldpsw.rb +12 -12
- data/lib/aarch64/instructions/ldr_imm_gen.rb +12 -12
- data/lib/aarch64/instructions/ldr_imm_unsigned.rb +10 -10
- data/lib/aarch64/instructions/ldr_lit_gen.rb +7 -7
- data/lib/aarch64/instructions/ldr_reg_gen.rb +14 -14
- data/lib/aarch64/instructions/ldra.rb +14 -14
- data/lib/aarch64/instructions/ldrb_imm.rb +10 -10
- data/lib/aarch64/instructions/ldrb_reg.rb +12 -12
- data/lib/aarch64/instructions/ldrb_unsigned.rb +8 -8
- data/lib/aarch64/instructions/ldrh_imm.rb +10 -10
- data/lib/aarch64/instructions/ldrh_reg.rb +12 -12
- data/lib/aarch64/instructions/ldrh_unsigned.rb +8 -8
- data/lib/aarch64/instructions/ldrsb_imm.rb +12 -12
- data/lib/aarch64/instructions/ldrsb_reg.rb +14 -14
- data/lib/aarch64/instructions/ldrsb_unsigned.rb +10 -10
- data/lib/aarch64/instructions/ldrsh_imm.rb +12 -12
- data/lib/aarch64/instructions/ldrsh_reg.rb +14 -14
- data/lib/aarch64/instructions/ldrsh_unsigned.rb +10 -10
- data/lib/aarch64/instructions/ldrsw_imm.rb +10 -10
- data/lib/aarch64/instructions/ldrsw_lit.rb +5 -5
- data/lib/aarch64/instructions/ldrsw_reg.rb +12 -12
- data/lib/aarch64/instructions/ldrsw_unsigned.rb +8 -8
- data/lib/aarch64/instructions/ldset.rb +14 -14
- data/lib/aarch64/instructions/ldsetb.rb +12 -12
- data/lib/aarch64/instructions/ldseth.rb +12 -12
- data/lib/aarch64/instructions/ldsmax.rb +14 -14
- data/lib/aarch64/instructions/ldsmaxb.rb +12 -12
- data/lib/aarch64/instructions/ldsmaxh.rb +12 -12
- data/lib/aarch64/instructions/ldsmin.rb +14 -14
- data/lib/aarch64/instructions/ldsminb.rb +12 -12
- data/lib/aarch64/instructions/ldsminh.rb +12 -12
- data/lib/aarch64/instructions/ldtr.rb +10 -10
- data/lib/aarch64/instructions/ldtrb.rb +8 -8
- data/lib/aarch64/instructions/ldtrh.rb +8 -8
- data/lib/aarch64/instructions/ldtrsb.rb +10 -10
- data/lib/aarch64/instructions/ldtrsh.rb +10 -10
- data/lib/aarch64/instructions/ldtrsw.rb +8 -8
- data/lib/aarch64/instructions/ldumax.rb +14 -14
- data/lib/aarch64/instructions/ldumaxb.rb +12 -12
- data/lib/aarch64/instructions/ldumaxh.rb +12 -12
- data/lib/aarch64/instructions/ldumin.rb +14 -14
- data/lib/aarch64/instructions/lduminb.rb +12 -12
- data/lib/aarch64/instructions/lduminh.rb +12 -12
- data/lib/aarch64/instructions/ldur_gen.rb +10 -10
- data/lib/aarch64/instructions/ldursb.rb +10 -10
- data/lib/aarch64/instructions/ldursh.rb +10 -10
- data/lib/aarch64/instructions/ldursw.rb +8 -8
- data/lib/aarch64/instructions/ldxp.rb +10 -10
- data/lib/aarch64/instructions/ldxr.rb +8 -8
- data/lib/aarch64/instructions/lslv.rb +10 -10
- data/lib/aarch64/instructions/lsrv.rb +10 -10
- data/lib/aarch64/instructions/madd.rb +12 -12
- data/lib/aarch64/instructions/movk.rb +10 -10
- data/lib/aarch64/instructions/movn.rb +10 -10
- data/lib/aarch64/instructions/movz.rb +10 -10
- data/lib/aarch64/instructions/mrs.rb +14 -14
- data/lib/aarch64/instructions/msr_imm.rb +7 -7
- data/lib/aarch64/instructions/msr_reg.rb +14 -14
- data/lib/aarch64/instructions/msub.rb +12 -12
- data/lib/aarch64/instructions/nop.rb +1 -1
- data/lib/aarch64/instructions/orn_log_shift.rb +14 -14
- data/lib/aarch64/instructions/orr_log_imm.rb +14 -14
- data/lib/aarch64/instructions/orr_log_shift.rb +14 -14
- data/lib/aarch64/instructions/pacda.rb +8 -8
- data/lib/aarch64/instructions/pacdb.rb +8 -8
- data/lib/aarch64/instructions/pacga.rb +8 -8
- data/lib/aarch64/instructions/pacia.rb +8 -8
- data/lib/aarch64/instructions/pacia2.rb +5 -5
- data/lib/aarch64/instructions/pacib.rb +8 -8
- data/lib/aarch64/instructions/prfm_imm.rb +8 -8
- data/lib/aarch64/instructions/prfm_lit.rb +8 -8
- data/lib/aarch64/instructions/prfm_reg.rb +12 -12
- data/lib/aarch64/instructions/prfum.rb +8 -8
- data/lib/aarch64/instructions/psb.rb +2 -9
- data/lib/aarch64/instructions/rbit_int.rb +8 -8
- data/lib/aarch64/instructions/ret.rb +4 -4
- data/lib/aarch64/instructions/reta.rb +3 -3
- data/lib/aarch64/instructions/rev.rb +10 -10
- data/lib/aarch64/instructions/rmif.rb +8 -8
- data/lib/aarch64/instructions/rorv.rb +10 -10
- data/lib/aarch64/instructions/sb.rb +1 -1
- data/lib/aarch64/instructions/sbc.rb +10 -10
- data/lib/aarch64/instructions/sbcs.rb +10 -10
- data/lib/aarch64/instructions/sbfm.rb +13 -13
- data/lib/aarch64/instructions/sdiv.rb +10 -10
- data/lib/aarch64/instructions/setf.rb +6 -6
- data/lib/aarch64/instructions/sev.rb +1 -7
- data/lib/aarch64/instructions/sevl.rb +1 -1
- data/lib/aarch64/instructions/smaddl.rb +10 -10
- data/lib/aarch64/instructions/smc.rb +3 -3
- data/lib/aarch64/instructions/smsubl.rb +10 -10
- data/lib/aarch64/instructions/smulh.rb +8 -8
- data/lib/aarch64/instructions/st2g.rb +10 -10
- data/lib/aarch64/instructions/st64b.rb +6 -6
- data/lib/aarch64/instructions/st64bv.rb +8 -8
- data/lib/aarch64/instructions/st64bv0.rb +8 -8
- data/lib/aarch64/instructions/stg.rb +10 -10
- data/lib/aarch64/instructions/stgm.rb +6 -6
- data/lib/aarch64/instructions/stgp.rb +12 -12
- data/lib/aarch64/instructions/stllr.rb +8 -8
- data/lib/aarch64/instructions/stllrb.rb +6 -6
- data/lib/aarch64/instructions/stllrh.rb +6 -6
- data/lib/aarch64/instructions/stlr.rb +8 -8
- data/lib/aarch64/instructions/stlrb.rb +6 -6
- data/lib/aarch64/instructions/stlrh.rb +6 -6
- data/lib/aarch64/instructions/stlur_gen.rb +10 -10
- data/lib/aarch64/instructions/stlxp.rb +12 -12
- data/lib/aarch64/instructions/stlxr.rb +10 -10
- data/lib/aarch64/instructions/stlxrb.rb +8 -8
- data/lib/aarch64/instructions/stlxrh.rb +8 -8
- data/lib/aarch64/instructions/stnp_gen.rb +12 -12
- data/lib/aarch64/instructions/stp_gen.rb +14 -14
- data/lib/aarch64/instructions/str_imm_gen.rb +12 -12
- data/lib/aarch64/instructions/str_imm_unsigned.rb +10 -10
- data/lib/aarch64/instructions/str_reg_gen.rb +14 -14
- data/lib/aarch64/instructions/strb_imm.rb +10 -10
- data/lib/aarch64/instructions/strb_imm_unsigned.rb +8 -8
- data/lib/aarch64/instructions/strb_reg.rb +12 -12
- data/lib/aarch64/instructions/strh_imm.rb +10 -10
- data/lib/aarch64/instructions/strh_imm_unsigned.rb +8 -8
- data/lib/aarch64/instructions/strh_reg.rb +12 -12
- data/lib/aarch64/instructions/sttr.rb +10 -10
- data/lib/aarch64/instructions/stur_gen.rb +10 -10
- data/lib/aarch64/instructions/stxp.rb +12 -12
- data/lib/aarch64/instructions/stxr.rb +10 -10
- data/lib/aarch64/instructions/stxrb.rb +8 -8
- data/lib/aarch64/instructions/stxrh.rb +8 -8
- data/lib/aarch64/instructions/stz2g.rb +10 -10
- data/lib/aarch64/instructions/stzg.rb +10 -10
- data/lib/aarch64/instructions/stzgm.rb +6 -6
- data/lib/aarch64/instructions/sub_addsub_ext.rb +14 -14
- data/lib/aarch64/instructions/sub_addsub_imm.rb +12 -12
- data/lib/aarch64/instructions/sub_addsub_shift.rb +14 -14
- data/lib/aarch64/instructions/subg.rb +10 -10
- data/lib/aarch64/instructions/subp.rb +8 -8
- data/lib/aarch64/instructions/subps.rb +8 -8
- data/lib/aarch64/instructions/subs_addsub_ext.rb +14 -14
- data/lib/aarch64/instructions/subs_addsub_imm.rb +12 -12
- data/lib/aarch64/instructions/subs_addsub_shift.rb +14 -14
- data/lib/aarch64/instructions/svc.rb +3 -3
- data/lib/aarch64/instructions/swp.rb +14 -14
- data/lib/aarch64/instructions/swpb.rb +12 -12
- data/lib/aarch64/instructions/swph.rb +12 -12
- data/lib/aarch64/instructions/sys.rb +12 -12
- data/lib/aarch64/instructions/sysl.rb +12 -12
- data/lib/aarch64/instructions/tbnz.rb +9 -9
- data/lib/aarch64/instructions/tbz.rb +9 -9
- data/lib/aarch64/instructions/tsb.rb +1 -7
- data/lib/aarch64/instructions/ubfm.rb +13 -13
- data/lib/aarch64/instructions/udf_perm_undef.rb +3 -3
- data/lib/aarch64/instructions/udiv.rb +10 -10
- data/lib/aarch64/instructions/umaddl.rb +10 -10
- data/lib/aarch64/instructions/umsubl.rb +10 -10
- data/lib/aarch64/instructions/umulh.rb +8 -8
- data/lib/aarch64/instructions/wfe.rb +2 -9
- data/lib/aarch64/instructions/wfet.rb +4 -4
- data/lib/aarch64/instructions/wfi.rb +1 -1
- data/lib/aarch64/instructions/wfit.rb +4 -4
- data/lib/aarch64/instructions/xaflag.rb +1 -1
- data/lib/aarch64/instructions/xpac.rb +6 -6
- data/lib/aarch64/instructions/xpaclri.rb +1 -1
- data/lib/aarch64/instructions/yield.rb +2 -9
- data/lib/aarch64/instructions.rb +26 -8
- data/lib/aarch64/parser.rb +227 -0
- data/lib/aarch64/parser.tab.rb +6534 -0
- data/lib/aarch64/parser.y +1394 -0
- data/lib/aarch64/utils.rb +34 -0
- data/lib/aarch64/version.rb +1 -1
- data/lib/aarch64.rb +128 -58
- data/test/base_instructions_test.rb +34 -4
- data/test/helper.rb +48 -8
- data/test/parser_test.rb +1820 -0
- metadata +25 -14
- data/lib/aarch64/instructions/setgp.rb +0 -25
- data/lib/aarch64/instructions/setgpn.rb +0 -25
- data/lib/aarch64/instructions/setgpt.rb +0 -25
- data/lib/aarch64/instructions/setgptn.rb +0 -25
- data/lib/aarch64/instructions/setp.rb +0 -25
- data/lib/aarch64/instructions/setpn.rb +0 -25
- data/lib/aarch64/instructions/setpt.rb +0 -25
- data/lib/aarch64/instructions/setptn.rb +0 -25
@@ -6,28 +6,28 @@ module AArch64
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# SWPALB <Ws>, <Wt>, [<Xn|SP>]
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# SWPB <Ws>, <Wt>, [<Xn|SP>]
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# SWPLB <Ws>, <Wt>, [<Xn|SP>]
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class SWPB
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class SWPB < Instruction
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def initialize rs, rt, rn, a, r
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@rs = rs
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@rt = rt
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@rn = rn
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@a = a
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@r = r
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@rs = check_mask(rs, 0x1f)
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@rt = check_mask(rt, 0x1f)
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@rn = check_mask(rn, 0x1f)
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@a = check_mask(a, 0x01)
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@r = check_mask(r, 0x01)
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end
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def encode
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SWPB(@a, @r, @rs
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SWPB(@a, @r, @rs, @rn, @rt)
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end
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private
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def SWPB a, r, rs, rn, rt
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insn = 0b00_111_0_00_0_0_1_00000_1_000_00_00000_00000
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insn |= ((a
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insn |= ((r
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insn |= ((rs
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insn |= ((rn
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insn |= (rt
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insn |= ((a) << 23)
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insn |= ((r) << 22)
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insn |= ((rs) << 16)
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insn |= ((rn) << 5)
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insn |= (rt)
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insn
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end
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end
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@@ -6,28 +6,28 @@ module AArch64
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# SWPALH <Ws>, <Wt>, [<Xn|SP>]
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# SWPH <Ws>, <Wt>, [<Xn|SP>]
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# SWPLH <Ws>, <Wt>, [<Xn|SP>]
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class SWPH
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class SWPH < Instruction
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def initialize rs, rt, rn, a, r
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@rs = rs
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@rt = rt
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@rn = rn
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@a = a
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@r = r
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@rs = check_mask(rs, 0x1f)
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@rt = check_mask(rt, 0x1f)
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@rn = check_mask(rn, 0x1f)
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@a = check_mask(a, 0x01)
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@r = check_mask(r, 0x01)
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end
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def encode
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SWPH(@a, @r, @rs
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SWPH(@a, @r, @rs, @rn, @rt)
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end
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private
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def SWPH a, r, rs, rn, rt
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insn = 0b01_111_0_00_0_0_1_00000_1_000_00_00000_00000
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insn |= ((a
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insn |= ((r
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insn |= ((rs
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insn |= ((rn
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insn |= (rt
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insn |= ((a) << 23)
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insn |= ((r) << 22)
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insn |= ((rs) << 16)
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insn |= ((rn) << 5)
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insn |= (rt)
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insn
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end
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end
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@@ -3,28 +3,28 @@ module AArch64
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# SYS -- A64
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# System instruction
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|
# SYS #<op1>, <Cn>, <Cm>, #<op2>{, <Xt>}
|
6
|
-
class SYS
|
6
|
+
class SYS < Instruction
|
7
7
|
def initialize op1, cn, cm, op2, xt
|
8
|
-
@op1 = op1
|
9
|
-
@cn = cn
|
10
|
-
@cm = cm
|
11
|
-
@op2 = op2
|
12
|
-
@xt = xt
|
8
|
+
@op1 = check_mask(op1, 0x07)
|
9
|
+
@cn = check_mask(cn, 0x0f)
|
10
|
+
@cm = check_mask(cm, 0x0f)
|
11
|
+
@op2 = check_mask(op2, 0x07)
|
12
|
+
@xt = check_mask(xt, 0x1f)
|
13
13
|
end
|
14
14
|
|
15
15
|
def encode
|
16
|
-
SYS(@op1, @cn, @cm, @op2, @xt
|
16
|
+
SYS(@op1, @cn, @cm, @op2, @xt)
|
17
17
|
end
|
18
18
|
|
19
19
|
private
|
20
20
|
|
21
21
|
def SYS op1, crn, crm, op2, rt
|
22
22
|
insn = 0b1101010100_0_01_000_0000_0000_000_00000
|
23
|
-
insn |= ((op1
|
24
|
-
insn |= ((crn
|
25
|
-
insn |= ((crm
|
26
|
-
insn |= ((op2
|
27
|
-
insn |= (rt
|
23
|
+
insn |= ((op1) << 16)
|
24
|
+
insn |= ((crn) << 12)
|
25
|
+
insn |= ((crm) << 8)
|
26
|
+
insn |= ((op2) << 5)
|
27
|
+
insn |= (rt)
|
28
28
|
insn
|
29
29
|
end
|
30
30
|
end
|
@@ -3,28 +3,28 @@ module AArch64
|
|
3
3
|
# SYSL -- A64
|
4
4
|
# System instruction with result
|
5
5
|
# SYSL <Xt>, #<op1>, <Cn>, <Cm>, #<op2>
|
6
|
-
class SYSL
|
6
|
+
class SYSL < Instruction
|
7
7
|
def initialize xt, op1, cn, cm, op2
|
8
|
-
@xt = xt
|
9
|
-
@op1 = op1
|
10
|
-
@cn = cn
|
11
|
-
@cm = cm
|
12
|
-
@op2 = op2
|
8
|
+
@xt = check_mask(xt, 0x1f)
|
9
|
+
@op1 = check_mask(op1, 0x07)
|
10
|
+
@cn = check_mask(cn, 0x0f)
|
11
|
+
@cm = check_mask(cm, 0x0f)
|
12
|
+
@op2 = check_mask(op2, 0x07)
|
13
13
|
end
|
14
14
|
|
15
15
|
def encode
|
16
|
-
SYSL(@op1, @cn
|
16
|
+
SYSL(@op1, @cn, @cm, @op2, @xt)
|
17
17
|
end
|
18
18
|
|
19
19
|
private
|
20
20
|
|
21
21
|
def SYSL op1, crn, crm, op2, rt
|
22
22
|
insn = 0b1101010100_1_01_000_0000_0000_000_00000
|
23
|
-
insn |= ((op1
|
24
|
-
insn |= ((crn
|
25
|
-
insn |= ((crm
|
26
|
-
insn |= ((op2
|
27
|
-
insn |= (rt
|
23
|
+
insn |= ((op1) << 16)
|
24
|
+
insn |= ((crn) << 12)
|
25
|
+
insn |= ((crm) << 8)
|
26
|
+
insn |= ((op2) << 5)
|
27
|
+
insn |= (rt)
|
28
28
|
insn
|
29
29
|
end
|
30
30
|
end
|
@@ -3,26 +3,26 @@ module AArch64
|
|
3
3
|
# TBNZ -- A64
|
4
4
|
# Test bit and Branch if Nonzero
|
5
5
|
# TBNZ <R><t>, #<imm>, <label>
|
6
|
-
class TBNZ
|
6
|
+
class TBNZ < Instruction
|
7
7
|
def initialize rt, imm, label, sf
|
8
|
-
@rt = rt
|
9
|
-
@imm = imm
|
8
|
+
@rt = check_mask(rt, 0x1f)
|
9
|
+
@imm = check_mask(imm, 0x1f)
|
10
10
|
@label = label
|
11
|
-
@sf = sf
|
11
|
+
@sf = check_mask(sf, 0x1)
|
12
12
|
end
|
13
13
|
|
14
14
|
def encode
|
15
|
-
TBNZ(@sf, @imm, @label
|
15
|
+
TBNZ(@sf, @imm, check_mask(unwrap_label(@label), 0x3fff), @rt)
|
16
16
|
end
|
17
17
|
|
18
18
|
private
|
19
19
|
|
20
20
|
def TBNZ b5, b40, imm14, rt
|
21
21
|
insn = 0b0_011011_1_00000_00000000000000_00000
|
22
|
-
insn |= (
|
23
|
-
insn |= (
|
24
|
-
insn |= (
|
25
|
-
insn |=
|
22
|
+
insn |= (b5 << 31)
|
23
|
+
insn |= (b40 << 19)
|
24
|
+
insn |= (imm14 << 5)
|
25
|
+
insn |= rt
|
26
26
|
insn
|
27
27
|
end
|
28
28
|
end
|
@@ -3,26 +3,26 @@ module AArch64
|
|
3
3
|
# TBZ -- A64
|
4
4
|
# Test bit and Branch if Zero
|
5
5
|
# TBZ <R><t>, #<imm>, <label>
|
6
|
-
class TBZ
|
6
|
+
class TBZ < Instruction
|
7
7
|
def initialize rt, imm, label, sf
|
8
|
-
@rt = rt
|
9
|
-
@imm = imm
|
8
|
+
@rt = check_mask(rt, 0x1f)
|
9
|
+
@imm = check_mask(imm, 0x1f)
|
10
10
|
@label = label
|
11
|
-
@sf = sf
|
11
|
+
@sf = check_mask(sf, 0x1)
|
12
12
|
end
|
13
13
|
|
14
14
|
def encode
|
15
|
-
TBZ(@sf, @imm, @label
|
15
|
+
TBZ(@sf, @imm, check_mask(unwrap_label(@label), 0x3fff), @rt)
|
16
16
|
end
|
17
17
|
|
18
18
|
private
|
19
19
|
|
20
20
|
def TBZ b5, b40, imm14, rt
|
21
21
|
insn = 0b0_011011_0_00000_00000000000000_00000
|
22
|
-
insn |= (
|
23
|
-
insn |= (
|
24
|
-
insn |= (
|
25
|
-
insn |=
|
22
|
+
insn |= (b5 << 31)
|
23
|
+
insn |= (b40 << 19)
|
24
|
+
insn |= (imm14 << 5)
|
25
|
+
insn |= rt
|
26
26
|
insn
|
27
27
|
end
|
28
28
|
end
|
@@ -4,29 +4,29 @@ module AArch64
|
|
4
4
|
# Unsigned Bitfield Move
|
5
5
|
# UBFM <Wd>, <Wn>, #<immr>, #<imms>
|
6
6
|
# UBFM <Xd>, <Xn>, #<immr>, #<imms>
|
7
|
-
class UBFM
|
7
|
+
class UBFM < Instruction
|
8
8
|
def initialize rd, rn, immr, imms, sf
|
9
|
-
@rd = rd
|
10
|
-
@rn = rn
|
11
|
-
@immr = immr
|
12
|
-
@imms = imms
|
13
|
-
@sf = sf
|
9
|
+
@rd = check_mask(rd, 0x1f)
|
10
|
+
@rn = check_mask(rn, 0x1f)
|
11
|
+
@immr = check_mask(immr, 0x3f)
|
12
|
+
@imms = check_mask(imms, 0x3f)
|
13
|
+
@sf = check_mask(sf, 0x01)
|
14
14
|
end
|
15
15
|
|
16
16
|
def encode
|
17
|
-
UBFM(@sf, @sf, @immr, @imms, @rn
|
17
|
+
UBFM(@sf, @sf, @immr, @imms, @rn, @rd)
|
18
18
|
end
|
19
19
|
|
20
20
|
private
|
21
21
|
|
22
22
|
def UBFM sf, n, immr, imms, rn, rd
|
23
23
|
insn = 0b0_10_100110_0_000000_000000_00000_00000
|
24
|
-
insn |= ((sf
|
25
|
-
insn |= ((n
|
26
|
-
insn |= ((immr
|
27
|
-
insn |= ((imms
|
28
|
-
insn |= ((rn
|
29
|
-
insn |= (rd
|
24
|
+
insn |= ((sf) << 31)
|
25
|
+
insn |= ((n) << 22)
|
26
|
+
insn |= ((immr) << 16)
|
27
|
+
insn |= ((imms) << 10)
|
28
|
+
insn |= ((rn) << 5)
|
29
|
+
insn |= (rd)
|
30
30
|
insn
|
31
31
|
end
|
32
32
|
end
|
@@ -3,9 +3,9 @@ module AArch64
|
|
3
3
|
# UDF -- A64
|
4
4
|
# Permanently Undefined
|
5
5
|
# UDF #<imm>
|
6
|
-
class UDF_perm_undef
|
6
|
+
class UDF_perm_undef < Instruction
|
7
7
|
def initialize imm
|
8
|
-
@imm = imm
|
8
|
+
@imm = check_mask(imm, 0xffff)
|
9
9
|
end
|
10
10
|
|
11
11
|
def encode
|
@@ -16,7 +16,7 @@ module AArch64
|
|
16
16
|
|
17
17
|
def UDF_perm_undef imm16
|
18
18
|
insn = 0b0000000000000000_0000000000000000
|
19
|
-
insn |= (imm16
|
19
|
+
insn |= (imm16)
|
20
20
|
insn
|
21
21
|
end
|
22
22
|
end
|
@@ -4,26 +4,26 @@ module AArch64
|
|
4
4
|
# Unsigned Divide
|
5
5
|
# UDIV <Wd>, <Wn>, <Wm>
|
6
6
|
# UDIV <Xd>, <Xn>, <Xm>
|
7
|
-
class UDIV
|
7
|
+
class UDIV < Instruction
|
8
8
|
def initialize rd, rn, rm, sf
|
9
|
-
@rd = rd
|
10
|
-
@rn = rn
|
11
|
-
@rm = rm
|
12
|
-
@sf = sf
|
9
|
+
@rd = check_mask(rd, 0x1f)
|
10
|
+
@rn = check_mask(rn, 0x1f)
|
11
|
+
@rm = check_mask(rm, 0x1f)
|
12
|
+
@sf = check_mask(sf, 0x01)
|
13
13
|
end
|
14
14
|
|
15
15
|
def encode
|
16
|
-
UDIV(@sf, @rm
|
16
|
+
UDIV(@sf, @rm, @rn, @rd)
|
17
17
|
end
|
18
18
|
|
19
19
|
private
|
20
20
|
|
21
21
|
def UDIV sf, rm, rn, rd
|
22
22
|
insn = 0b0_0_0_11010110_00000_00001_0_00000_00000
|
23
|
-
insn |= ((sf
|
24
|
-
insn |= ((rm
|
25
|
-
insn |= ((rn
|
26
|
-
insn |= (rd
|
23
|
+
insn |= ((sf) << 31)
|
24
|
+
insn |= ((rm) << 16)
|
25
|
+
insn |= ((rn) << 5)
|
26
|
+
insn |= (rd)
|
27
27
|
insn
|
28
28
|
end
|
29
29
|
end
|
@@ -3,26 +3,26 @@ module AArch64
|
|
3
3
|
# UMADDL -- A64
|
4
4
|
# Unsigned Multiply-Add Long
|
5
5
|
# UMADDL <Xd>, <Wn>, <Wm>, <Xa>
|
6
|
-
class UMADDL
|
6
|
+
class UMADDL < Instruction
|
7
7
|
def initialize xd, wn, wm, xa
|
8
|
-
@xd = xd
|
9
|
-
@wn = wn
|
10
|
-
@wm = wm
|
11
|
-
@xa = xa
|
8
|
+
@xd = check_mask(xd, 0x1f)
|
9
|
+
@wn = check_mask(wn, 0x1f)
|
10
|
+
@wm = check_mask(wm, 0x1f)
|
11
|
+
@xa = check_mask(xa, 0x1f)
|
12
12
|
end
|
13
13
|
|
14
14
|
def encode
|
15
|
-
UMADDL(@wm
|
15
|
+
UMADDL(@wm, @xa, @wn, @xd)
|
16
16
|
end
|
17
17
|
|
18
18
|
private
|
19
19
|
|
20
20
|
def UMADDL rm, ra, rn, rd
|
21
21
|
insn = 0b1_00_11011_1_01_00000_0_00000_00000_00000
|
22
|
-
insn |= ((rm
|
23
|
-
insn |= ((ra
|
24
|
-
insn |= ((rn
|
25
|
-
insn |= (rd
|
22
|
+
insn |= ((rm) << 16)
|
23
|
+
insn |= ((ra) << 10)
|
24
|
+
insn |= ((rn) << 5)
|
25
|
+
insn |= (rd)
|
26
26
|
insn
|
27
27
|
end
|
28
28
|
end
|
@@ -3,26 +3,26 @@ module AArch64
|
|
3
3
|
# UMSUBL -- A64
|
4
4
|
# Unsigned Multiply-Subtract Long
|
5
5
|
# UMSUBL <Xd>, <Wn>, <Wm>, <Xa>
|
6
|
-
class UMSUBL
|
6
|
+
class UMSUBL < Instruction
|
7
7
|
def initialize xd, wn, wm, xa
|
8
|
-
@xd = xd
|
9
|
-
@wn = wn
|
10
|
-
@wm = wm
|
11
|
-
@xa = xa
|
8
|
+
@xd = check_mask(xd, 0x1f)
|
9
|
+
@wn = check_mask(wn, 0x1f)
|
10
|
+
@wm = check_mask(wm, 0x1f)
|
11
|
+
@xa = check_mask(xa, 0x1f)
|
12
12
|
end
|
13
13
|
|
14
14
|
def encode
|
15
|
-
UMSUBL(@wm
|
15
|
+
UMSUBL(@wm, @xa, @wn, @xd)
|
16
16
|
end
|
17
17
|
|
18
18
|
private
|
19
19
|
|
20
20
|
def UMSUBL rm, ra, rn, rd
|
21
21
|
insn = 0b1_00_11011_1_01_00000_1_00000_00000_00000
|
22
|
-
insn |= ((rm
|
23
|
-
insn |= ((ra
|
24
|
-
insn |= ((rn
|
25
|
-
insn |= (rd
|
22
|
+
insn |= ((rm) << 16)
|
23
|
+
insn |= ((ra) << 10)
|
24
|
+
insn |= ((rn) << 5)
|
25
|
+
insn |= (rd)
|
26
26
|
insn
|
27
27
|
end
|
28
28
|
end
|
@@ -3,24 +3,24 @@ module AArch64
|
|
3
3
|
# UMULH -- A64
|
4
4
|
# Unsigned Multiply High
|
5
5
|
# UMULH <Xd>, <Xn>, <Xm>
|
6
|
-
class UMULH
|
6
|
+
class UMULH < Instruction
|
7
7
|
def initialize rd, rn, rm
|
8
|
-
@rd = rd
|
9
|
-
@rn = rn
|
10
|
-
@rm = rm
|
8
|
+
@rd = check_mask(rd, 0x1f)
|
9
|
+
@rn = check_mask(rn, 0x1f)
|
10
|
+
@rm = check_mask(rm, 0x1f)
|
11
11
|
end
|
12
12
|
|
13
13
|
def encode
|
14
|
-
UMULH(@rm
|
14
|
+
UMULH(@rm, @rn, @rd)
|
15
15
|
end
|
16
16
|
|
17
17
|
private
|
18
18
|
|
19
19
|
def UMULH rm, rn, rd
|
20
20
|
insn = 0b1_00_11011_1_10_00000_0_11111_00000_00000
|
21
|
-
insn |= ((rm
|
22
|
-
insn |= ((rn
|
23
|
-
insn |= (rd
|
21
|
+
insn |= ((rm) << 16)
|
22
|
+
insn |= ((rn) << 5)
|
23
|
+
insn |= (rd)
|
24
24
|
insn
|
25
25
|
end
|
26
26
|
end
|
@@ -3,16 +3,9 @@ module AArch64
|
|
3
3
|
# WFE -- A64
|
4
4
|
# Wait For Event
|
5
5
|
# WFE
|
6
|
-
class WFE
|
6
|
+
class WFE < Instruction
|
7
7
|
def encode
|
8
|
-
|
9
|
-
end
|
10
|
-
|
11
|
-
private
|
12
|
-
|
13
|
-
def WFE
|
14
|
-
insn = 0b1101010100_0_00_011_0010_0000_010_11111
|
15
|
-
insn
|
8
|
+
0b1101010100_0_00_011_0010_0000_010_11111
|
16
9
|
end
|
17
10
|
end
|
18
11
|
end
|
@@ -3,20 +3,20 @@ module AArch64
|
|
3
3
|
# WFET -- A64
|
4
4
|
# Wait For Event with Timeout
|
5
5
|
# WFET <Xt>
|
6
|
-
class WFET
|
6
|
+
class WFET < Instruction
|
7
7
|
def initialize rd
|
8
|
-
@rd = rd
|
8
|
+
@rd = check_mask(rd, 0x1f)
|
9
9
|
end
|
10
10
|
|
11
11
|
def encode
|
12
|
-
WFET(@rd
|
12
|
+
WFET(@rd)
|
13
13
|
end
|
14
14
|
|
15
15
|
private
|
16
16
|
|
17
17
|
def WFET rd
|
18
18
|
insn = 0b11010101000000110001_0000_000_00000
|
19
|
-
insn |= (rd
|
19
|
+
insn |= (rd)
|
20
20
|
insn
|
21
21
|
end
|
22
22
|
end
|
@@ -3,20 +3,20 @@ module AArch64
|
|
3
3
|
# WFIT -- A64
|
4
4
|
# Wait For Interrupt with Timeout
|
5
5
|
# WFIT <Xt>
|
6
|
-
class WFIT
|
6
|
+
class WFIT < Instruction
|
7
7
|
def initialize rd
|
8
|
-
@rd = rd
|
8
|
+
@rd = check_mask(rd, 0x1f)
|
9
9
|
end
|
10
10
|
|
11
11
|
def encode
|
12
|
-
WFIT(@rd
|
12
|
+
WFIT(@rd)
|
13
13
|
end
|
14
14
|
|
15
15
|
private
|
16
16
|
|
17
17
|
def WFIT rd
|
18
18
|
insn = 0b11010101000000110001_0000_001_00000
|
19
|
-
insn |= (rd
|
19
|
+
insn |= (rd)
|
20
20
|
insn
|
21
21
|
end
|
22
22
|
end
|
@@ -5,22 +5,22 @@ module AArch64
|
|
5
5
|
# XPACD <Xd>
|
6
6
|
# XPACI <Xd>
|
7
7
|
# XPACLRI
|
8
|
-
class XPAC
|
8
|
+
class XPAC < Instruction
|
9
9
|
def initialize rd, d
|
10
|
-
@rd = rd
|
11
|
-
@d = d
|
10
|
+
@rd = check_mask(rd, 0x1f)
|
11
|
+
@d = check_mask(d, 0x01)
|
12
12
|
end
|
13
13
|
|
14
14
|
def encode
|
15
|
-
XPAC(@d, @rd
|
15
|
+
XPAC(@d, @rd)
|
16
16
|
end
|
17
17
|
|
18
18
|
private
|
19
19
|
|
20
20
|
def XPAC d, rd
|
21
21
|
insn = 0b1_1_0_11010110_00001_0_1_000_0_11111_00000
|
22
|
-
insn |= ((d
|
23
|
-
insn |= (rd
|
22
|
+
insn |= ((d) << 10)
|
23
|
+
insn |= (rd)
|
24
24
|
insn
|
25
25
|
end
|
26
26
|
end
|
@@ -3,16 +3,9 @@ module AArch64
|
|
3
3
|
# YIELD -- A64
|
4
4
|
# YIELD
|
5
5
|
# YIELD
|
6
|
-
class YIELD
|
6
|
+
class YIELD < Instruction
|
7
7
|
def encode
|
8
|
-
|
9
|
-
end
|
10
|
-
|
11
|
-
private
|
12
|
-
|
13
|
-
def YIELD
|
14
|
-
insn = 0b1101010100_0_00_011_0010_0000_001_11111
|
15
|
-
insn
|
8
|
+
0b1101010100_0_00_011_0010_0000_001_11111
|
16
9
|
end
|
17
10
|
end
|
18
11
|
end
|
data/lib/aarch64/instructions.rb
CHANGED
@@ -1,5 +1,31 @@
|
|
1
1
|
module AArch64
|
2
2
|
module Instructions
|
3
|
+
class Instruction
|
4
|
+
private
|
5
|
+
|
6
|
+
def unwrap_label label
|
7
|
+
label.unwrap_label / 4
|
8
|
+
end
|
9
|
+
|
10
|
+
def check_mask val, mask
|
11
|
+
val = val.to_i
|
12
|
+
|
13
|
+
if val > mask
|
14
|
+
raise "Expected a #{popcount(mask)} bit number, but got 0x#{val.to_s(16)}"
|
15
|
+
end
|
16
|
+
val & mask
|
17
|
+
end
|
18
|
+
|
19
|
+
def popcount x
|
20
|
+
x -= ((x >> 1) & 0x55555555)
|
21
|
+
x = (x & 0x33333333) + ((x >> 2) & 0x33333333)
|
22
|
+
x = (x + (x >> 4)) & 0x0F0F0F0F
|
23
|
+
x += (x >> 8)
|
24
|
+
x += (x >> 16)
|
25
|
+
x & 0x3F
|
26
|
+
end
|
27
|
+
end
|
28
|
+
|
3
29
|
autoload :ADC, "aarch64/instructions/adc"
|
4
30
|
autoload :ADCS, "aarch64/instructions/adcs"
|
5
31
|
autoload :ADD_addsub_ext, "aarch64/instructions/add_addsub_ext"
|
@@ -178,14 +204,6 @@ module AArch64
|
|
178
204
|
autoload :SBFM, "aarch64/instructions/sbfm"
|
179
205
|
autoload :SDIV, "aarch64/instructions/sdiv"
|
180
206
|
autoload :SETF, "aarch64/instructions/setf"
|
181
|
-
autoload :SETGP, "aarch64/instructions/setgp"
|
182
|
-
autoload :SETGPN, "aarch64/instructions/setgpn"
|
183
|
-
autoload :SETGPT, "aarch64/instructions/setgpt"
|
184
|
-
autoload :SETGPTN, "aarch64/instructions/setgptn"
|
185
|
-
autoload :SETP, "aarch64/instructions/setp"
|
186
|
-
autoload :SETPN, "aarch64/instructions/setpn"
|
187
|
-
autoload :SETPT, "aarch64/instructions/setpt"
|
188
|
-
autoload :SETPTN, "aarch64/instructions/setptn"
|
189
207
|
autoload :SEV, "aarch64/instructions/sev"
|
190
208
|
autoload :SEVL, "aarch64/instructions/sevl"
|
191
209
|
autoload :SMADDL, "aarch64/instructions/smaddl"
|