aarch64 1.0.1 → 2.0.0

data/lib/aarch64/instructions/ands_log_shift.rb

@@ -4,30 +4,30 @@ module AArch64
     # Bitwise AND (shifted register), setting flags
     # ANDS  <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
     # ANDS  <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
-    class ANDS_log_shift
+    class ANDS_log_shift < Instruction
       def initialize xd, xn, xm, shift, amount, sf
-        @xd     = xd
-        @xn     = xn
-        @xm     = xm
-        @shift  = shift
-        @amount = amount
-        @sf     = sf
+        @xd     = check_mask(xd, 0x1f)
+        @xn     = check_mask(xn, 0x1f)
+        @xm     = check_mask(xm, 0x1f)
+        @shift  = check_mask(shift, 0x03)
+        @amount = check_mask(amount, 0x3f)
+        @sf     = check_mask(sf, 0x01)
       end
 
       def encode
-        ANDS_log_shift(@sf, @shift, @xm.to_i, @amount, @xn.to_i, @xd.to_i)
+        ANDS_log_shift(@sf, @shift, @xm, @amount, @xn, @xd)
       end
 
       private
 
       def ANDS_log_shift sf, shift, rm, imm6, rn, rd
         insn = 0b0_11_01010_00_0_00000_000000_00000_00000
-        insn |= ((sf & 0x1) << 31)
-        insn |= ((shift & 0x3) << 22)
-        insn |= ((rm & 0x1f) << 16)
-        insn |= ((imm6 & 0x3f) << 10)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rd & 0x1f)
+        insn |= ((sf) << 31)
+        insn |= ((shift) << 22)
+        insn |= ((rm) << 16)
+        insn |= ((imm6) << 10)
+        insn |= ((rn) << 5)
+        insn |= (rd)
         insn
       end
     end

data/lib/aarch64/instructions/asrv.rb

@@ -4,26 +4,26 @@ module AArch64
     # Arithmetic Shift Right Variable
     # ASRV  <Wd>, <Wn>, <Wm>
     # ASRV  <Xd>, <Xn>, <Xm>
-    class ASRV
+    class ASRV < Instruction
       def initialize rd, rn, rm, sf
-        @rd = rd
-        @rn = rn
-        @rm = rm
-        @sf = sf
+        @rd = check_mask(rd, 0x1f)
+        @rn = check_mask(rn, 0x1f)
+        @rm = check_mask(rm, 0x1f)
+        @sf = check_mask(sf, 0x01)
       end
 
       def encode
-        ASRV(@sf, @rm.to_i, @rn.to_i, @rd.to_i)
+        ASRV(@sf, @rm, @rn, @rd)
       end
 
       private
 
       def ASRV sf, rm, rn, rd
         insn = 0b0_0_0_11010110_00000_0010_10_00000_00000
-        insn |= ((sf & 0x1) << 31)
-        insn |= ((rm & 0x1f) << 16)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rd & 0x1f)
+        insn |= ((sf) << 31)
+        insn |= ((rm) << 16)
+        insn |= ((rn) << 5)
+        insn |= (rd)
         insn
       end
     end

data/lib/aarch64/instructions/autda.rb

@@ -4,27 +4,24 @@ module AArch64
     # Authenticate Data address, using key A
     # AUTDA  <Xd>, <Xn|SP>
     # AUTDZA  <Xd>
-    class AUTDA
-      def initialize d, n
-        @d = d
-        @n = n
+    class AUTDA < Instruction
+      def initialize z, rd, rn
+        @z  = check_mask(z, 0x01)
+        @rd = check_mask(rd, 0x1f)
+        @rn = check_mask(rn, 0x1f)
       end
 
       def encode
-        if @n.integer?
-          AUTDA(1, @n.to_i, @d.to_i)
-        else
-          AUTDA(0, @n.to_i, @d.to_i)
-        end
+        AUTDA(@z, @rn, @rd)
       end
 
       private
 
       def AUTDA z, rn, rd
         insn = 0b1_1_0_11010110_00001_0_0_0_110_00000_00000
-        insn |= ((z & 0x1) << 13)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rd & 0x1f)
+        insn |= ((z) << 13)
+        insn |= ((rn) << 5)
+        insn |= (rd)
         insn
       end
     end

data/lib/aarch64/instructions/autdb.rb

@@ -4,27 +4,24 @@ module AArch64
     # Authenticate Data address, using key B
     # AUTDB  <Xd>, <Xn|SP>
     # AUTDZB  <Xd>
-    class AUTDB
-      def initialize d, n
-        @d = d
-        @n = n
+    class AUTDB < Instruction
+      def initialize z, rd, rn
+        @z  = check_mask(z, 0x01)
+        @rd = check_mask(rd, 0x1f)
+        @rn = check_mask(rn, 0x1f)
       end
 
       def encode
-        if @n.integer?
-          AUTDB(1, @n.to_i, @d.to_i)
-        else
-          AUTDB(0, @n.to_i, @d.to_i)
-        end
+        AUTDB(@z, @rn, @rd)
       end
 
       private
 
       def AUTDB z, rn, rd
         insn = 0b1_1_0_11010110_00001_0_0_0_111_00000_00000
-        insn |= ((z & 0x1) << 13)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rd & 0x1f)
+        insn |= ((z) << 13)
+        insn |= ((rn) << 5)
+        insn |= (rd)
         insn
       end
     end

data/lib/aarch64/instructions/autia.rb

@@ -7,27 +7,24 @@ module AArch64
     # AUTIA1716
     # AUTIASP
     # AUTIAZ
-    class AUTIA
-      def initialize d, n
-        @d = d
-        @n = n
+    class AUTIA < Instruction
+      def initialize z, rd, rn
+        @z  = check_mask(z, 0x01)
+        @rd = check_mask(rd, 0x1f)
+        @rn = check_mask(rn, 0x1f)
       end
 
       def encode
-        if @n.integer?
-          AUTIA(1, @n.to_i, @d.to_i)
-        else
-          AUTIA(0, @n.to_i, @d.to_i)
-        end
+        AUTIA(@z, @rn, @rd)
       end
 
       private
 
       def AUTIA z, rn, rd
         insn = 0b1_1_0_11010110_00001_0_0_0_100_00000_00000
-        insn |= ((z & 0x1) << 13)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rd & 0x1f)
+        insn |= ((z) << 13)
+        insn |= ((rn) << 5)
+        insn |= (rd)
         insn
       end
     end

data/lib/aarch64/instructions/autib.rb

@@ -7,27 +7,24 @@ module AArch64
     # AUTIB1716
     # AUTIBSP
     # AUTIBZ
-    class AUTIB
-      def initialize d, n
-        @d = d
-        @n = n
+    class AUTIB < Instruction
+      def initialize z, rd, rn
+        @z  = check_mask(z, 0x01)
+        @rd = check_mask(rd, 0x1f)
+        @rn = check_mask(rn, 0x1f)
       end
 
       def encode
-        if @n.integer?
-          AUTIB(1, @n.to_i, @d.to_i)
-        else
-          AUTIB(0, @n.to_i, @d.to_i)
-        end
+        AUTIB(@z, @rn, @rd)
       end
 
       private
 
       def AUTIB z, rn, rd
         insn = 0b1_1_0_11010110_00001_0_0_0_101_00000_00000
-        insn |= ((z & 0x1) << 13)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rd & 0x1f)
+        insn |= ((z) << 13)
+        insn |= ((rn) << 5)
+        insn |= (rd)
         insn
       end
     end

data/lib/aarch64/instructions/axflag.rb

@@ -3,7 +3,7 @@ module AArch64
     # AXFLAG -- A64
     # Convert floating-point condition flags from Arm to external format
     # AXFLAG
-    class AXFLAG
+    class AXFLAG < Instruction
       def encode
         0b1101010100_0_00_000_0100_0000_010_11111
       end

data/lib/aarch64/instructions/b_cond.rb

@@ -3,22 +3,22 @@ module AArch64
     # B.cond -- A64
     # Branch conditionally
     # B.<cond>  <label>
-    class B_cond
+    class B_cond < Instruction
       def initialize cond, label
-        @cond  = cond
+        @cond  = check_mask(cond, 0xf)
         @label = label
       end
 
       def encode
-        B_cond(@label.to_i / 4, Utils.cond2bin(@cond))
+        B_cond(check_mask(unwrap_label(@label), 0x7ffff), @cond)
       end
 
       private
 
       def B_cond imm19, cond
         insn = 0b0101010_0_0000000000000000000_0_0000
-        insn |= ((imm19 & 0x7ffff) << 5)
-        insn |= (cond & 0xf)
+        insn |= (imm19 << 5)
+        insn |= cond
         insn
       end
     end

data/lib/aarch64/instructions/b_uncond.rb

@@ -3,20 +3,20 @@ module AArch64
     # B -- A64
     # Branch
     # B  <label>
-    class B_uncond
+    class B_uncond < Instruction
       def initialize label
         @label = label
       end
 
       def encode
-        B_uncond(@label.to_i / 4)
+        B_uncond(check_mask(unwrap_label(@label), 0x3ffffff))
       end
 
       private
 
       def B_uncond imm26
         insn = 0b0_00101_00000000000000000000000000
-        insn |= (imm26 & 0x3ffffff)
+        insn |= imm26
         insn
       end
     end

data/lib/aarch64/instructions/bc_cond.rb

@@ -3,22 +3,22 @@ module AArch64
     # BC.cond -- A64
     # Branch Consistent conditionally
     # BC.<cond>  <label>
-    class BC_cond
+    class BC_cond < Instruction
       def initialize cond, label
-        @cond  = cond
+        @cond  = check_mask(cond, 0xf)
         @label = label
       end
 
       def encode
-        BC_cond(@label.to_i / 4, Utils.cond2bin(@cond))
+        BC_cond(check_mask(unwrap_label(@label), 0x7ffff), @cond)
       end
 
       private
 
       def BC_cond imm19, cond
         insn = 0b0101010_0_0000000000000000000_1_0000
-        insn |= ((imm19 & 0x7ffff) << 5)
-        insn |= (cond & 0xf)
+        insn |= (imm19 << 5)
+        insn |= cond
         insn
       end
     end

data/lib/aarch64/instructions/bfm.rb

@@ -4,29 +4,29 @@ module AArch64
     # Bitfield Move
     # BFM  <Wd>, <Wn>, #<immr>, #<imms>
     # BFM  <Xd>, <Xn>, #<immr>, #<imms>
-    class BFM
+    class BFM < Instruction
       def initialize d, n, immr, imms, sf
-        @d    = d
-        @n    = n
-        @immr = immr
-        @imms = imms
-        @sf = sf
+        @d    = check_mask(d, 0x1f)
+        @n    = check_mask(n, 0x1f)
+        @immr = check_mask(immr, 0x3f)
+        @imms = check_mask(imms, 0x3f)
+        @sf   = check_mask(sf, 0x01)
       end
 
       def encode
-        BFM(@sf, @sf, @immr, @imms, @n.to_i, @d.to_i)
+        BFM(@sf, @sf, @immr, @imms, @n, @d)
       end
 
       private
 
       def BFM sf, n, immr, imms, rn, rd
         insn = 0b0_01_100110_0_000000_000000_00000_00000
-        insn |= ((sf & 0x1) << 31)
-        insn |= ((n & 0x1) << 22)
-        insn |= ((immr & 0x3f) << 16)
-        insn |= ((imms & 0x3f) << 10)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rd & 0x1f)
+        insn |= ((sf) << 31)
+        insn |= ((n) << 22)
+        insn |= ((immr) << 16)
+        insn |= ((imms) << 10)
+        insn |= ((rn) << 5)
+        insn |= (rd)
         insn
       end
     end

data/lib/aarch64/instructions/bic_log_shift.rb

@@ -4,30 +4,30 @@ module AArch64
     # Bitwise Bit Clear (shifted register)
     # BIC  <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
     # BIC  <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
-    class BIC_log_shift
+    class BIC_log_shift < Instruction
       def initialize d, n, m, shift, amount, sf
-        @d      = d
-        @n      = n
-        @m      = m
-        @shift  = shift
-        @amount = amount
-        @sf     = sf
+        @d      = check_mask(d, 0x1f)
+        @n      = check_mask(n, 0x1f)
+        @m      = check_mask(m, 0x1f)
+        @shift  = check_mask(shift, 0x03)
+        @amount = check_mask(amount, 0x3f)
+        @sf     = check_mask(sf, 0x01)
       end
 
       def encode
-        BIC_log_shift(@sf, @shift, @m.to_i, @amount, @n.to_i, @d.to_i)
+        BIC_log_shift(@sf, @shift, @m, @amount, @n, @d)
       end
 
       private
 
       def BIC_log_shift sf, shift, rm, imm6, rn, rd
         insn = 0b0_00_01010_00_1_00000_000000_00000_00000
-        insn |= ((sf & 0x1) << 31)
-        insn |= ((shift & 0x3) << 22)
-        insn |= ((rm & 0x1f) << 16)
-        insn |= ((imm6 & 0x3f) << 10)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rd & 0x1f)
+        insn |= ((sf) << 31)
+        insn |= ((shift) << 22)
+        insn |= ((rm) << 16)
+        insn |= ((imm6) << 10)
+        insn |= ((rn) << 5)
+        insn |= (rd)
         insn
       end
     end

data/lib/aarch64/instructions/bics.rb

@@ -4,30 +4,30 @@ module AArch64
     # Bitwise Bit Clear (shifted register), setting flags
     # BICS  <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
     # BICS  <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
-    class BICS
+    class BICS < Instruction
       def initialize d, n, m, shift, amount, sf
-        @d      = d
-        @n      = n
-        @m      = m
-        @shift  = shift
-        @amount = amount
-        @sf     = sf
+        @d      = check_mask(d, 0x1f)
+        @n      = check_mask(n, 0x1f)
+        @m      = check_mask(m, 0x1f)
+        @shift  = check_mask(shift, 0x03)
+        @amount = check_mask(amount, 0x3f)
+        @sf     = check_mask(sf, 0x01)
       end
 
       def encode
-        BICS(@sf, @shift, @m.to_i, @amount, @n.to_i, @d.to_i)
+        BICS(@sf, @shift, @m, @amount, @n, @d)
       end
 
       private
 
       def BICS sf, shift, rm, imm6, rn, rd
         insn = 0b0_11_01010_00_1_00000_000000_00000_00000
-        insn |= ((sf & 0x1) << 31)
-        insn |= ((shift & 0x3) << 22)
-        insn |= ((rm & 0x1f) << 16)
-        insn |= ((imm6 & 0x3f) << 10)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rd & 0x1f)
+        insn |= ((sf) << 31)
+        insn |= ((shift) << 22)
+        insn |= ((rm) << 16)
+        insn |= ((imm6) << 10)
+        insn |= ((rn) << 5)
+        insn |= (rd)
         insn
       end
     end

data/lib/aarch64/instructions/bl.rb

@@ -3,20 +3,20 @@ module AArch64
     # BL -- A64
     # Branch with Link
     # BL  <label>
-    class BL
+    class BL < Instruction
       def initialize label
         @label = label
       end
 
       def encode
-        BL(@label.to_i / 4)
+        BL(check_mask(unwrap_label(@label), 0x3ffffff))
       end
 
       private
 
       def BL imm26
         insn = 0b1_00101_00000000000000000000000000
-        insn |= (imm26 & 0x3ffffff)
+        insn |= imm26
         insn
       end
     end

data/lib/aarch64/instructions/blr.rb

@@ -3,20 +3,20 @@ module AArch64
     # BLR -- A64
     # Branch with Link to Register
     # BLR  <Xn>
-    class BLR
+    class BLR < Instruction
       def initialize n
-        @n = n
+        @n = check_mask(n, 0x1f)
       end
 
       def encode
-        BLR(@n.to_i)
+        BLR(@n)
       end
 
       private
 
       def BLR rn
         insn = 0b1101011_0_0_01_11111_0000_0_0_00000_00000
-        insn |= ((rn & 0x1f) << 5)
+        insn |= ((rn) << 5)
         insn
       end
     end

data/lib/aarch64/instructions/blra.rb

@@ -6,26 +6,26 @@ module AArch64
     # BLRAA  <Xn>, <Xm|SP>
     # BLRABZ  <Xn>
     # BLRAB  <Xn>, <Xm|SP>
-    class BLRA
+    class BLRA < Instruction
       def initialize rn, rm, z, m
-        @rn = rn
-        @rm = rm
-        @z  = z
-        @m  = m
+        @rn = check_mask(rn, 0x1f)
+        @rm = check_mask(rm, 0x1f)
+        @z  = check_mask(z, 0x01)
+        @m  = check_mask(m, 0x01)
       end
 
       def encode
-        BLRA(@z, @m, @rn.to_i, @rm.to_i)
+        BLRA(@z, @m, @rn, @rm)
       end
 
       private
 
       def BLRA z, m, rn, rm
         insn = 0b1101011_0_0_01_11111_0000_1_0_00000_00000
-        insn |= ((z & 0x1) << 24)
-        insn |= ((m & 0x1) << 10)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rm & 0x1f)
+        insn |= ((z) << 24)
+        insn |= ((m) << 10)
+        insn |= ((rn) << 5)
+        insn |= (rm)
         insn
       end
     end

data/lib/aarch64/instructions/br.rb

@@ -3,20 +3,20 @@ module AArch64
     # BR -- A64
     # Branch to Register
     # BR  <Xn>
-    class BR
+    class BR < Instruction
       def initialize rn
-        @rn = rn
+        @rn = check_mask(rn, 0x1f)
       end
 
       def encode
-        BR(@rn.to_i)
+        BR(@rn)
       end
 
       private
 
       def BR rn
         insn = 0b1101011_0_0_00_11111_0000_0_0_00000_00000
-        insn |= ((rn & 0x1f) << 5)
+        insn |= ((rn) << 5)
         insn
       end
     end

data/lib/aarch64/instructions/bra.rb

@@ -6,26 +6,26 @@ module AArch64
     # BRAA  <Xn>, <Xm|SP>
     # BRABZ  <Xn>
     # BRAB  <Xn>, <Xm|SP>
-    class BRA
+    class BRA < Instruction
       def initialize rn, rm, z, m
-        @rn = rn
-        @rm = rm
-        @z  = z
-        @m  = m
+        @rn = check_mask(rn, 0x1f)
+        @rm = check_mask(rm, 0x1f)
+        @z  = check_mask(z, 0x01)
+        @m  = check_mask(m, 0x01)
       end
 
       def encode
-        BRA(@z, @m, @rn.to_i, @rm.to_i)
+        BRA(@z, @m, @rn, @rm)
       end
 
       private
 
       def BRA z, m, rn, rm
         insn = 0b1101011_0_0_00_11111_0000_1_0_00000_00000
-        insn |= ((z & 0x1) << 24)
-        insn |= ((m & 0x1) << 10)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rm & 0x1f)
+        insn |= ((z) << 24)
+        insn |= ((m) << 10)
+        insn |= ((rn) << 5)
+        insn |= (rm)
         insn
       end
     end

data/lib/aarch64/instructions/brk.rb

@@ -3,9 +3,9 @@ module AArch64
     # BRK -- A64
     # Breakpoint instruction
     # BRK  #<imm>
-    class BRK
+    class BRK < Instruction
       def initialize imm
-        @imm = imm
+        @imm = check_mask(imm, 0xffff)
       end
 
       def encode
@@ -16,7 +16,7 @@ module AArch64
 
       def BRK imm16
         insn = 0b11010100_001_0000000000000000_000_00
-        insn |= ((imm16 & 0xffff) << 5)
+        insn |= ((imm16) << 5)
         insn
       end
     end

data/lib/aarch64/instructions/bti.rb

@@ -3,9 +3,9 @@ module AArch64
     # BTI -- A64
     # Branch Target Identification
     # BTI  {<targets>}
-    class BTI
+    class BTI < Instruction
       def initialize target
-        @target = target
+        @target = check_mask(target, 0x03)
       end
 
       def encode
@@ -16,7 +16,7 @@ module AArch64
 
       def BTI target
         insn = 0b1101010100_0_00_011_0010_0100_000_11111
-        insn |= ((target & 0x3) << 5)
+        insn |= ((target) << 5)
         insn
       end
     end