aarch64 1.0.1 → 2.0.0
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- checksums.yaml +4 -4
- data/README.md +1 -1
- data/Rakefile +37 -0
- data/aarch64.gemspec +1 -0
- data/lib/aarch64/instructions/adc.rb +10 -10
- data/lib/aarch64/instructions/adcs.rb +10 -10
- data/lib/aarch64/instructions/add_addsub_ext.rb +14 -14
- data/lib/aarch64/instructions/add_addsub_imm.rb +12 -12
- data/lib/aarch64/instructions/add_addsub_shift.rb +14 -14
- data/lib/aarch64/instructions/addg.rb +10 -10
- data/lib/aarch64/instructions/adds_addsub_ext.rb +14 -14
- data/lib/aarch64/instructions/adds_addsub_imm.rb +12 -12
- data/lib/aarch64/instructions/adds_addsub_shift.rb +14 -14
- data/lib/aarch64/instructions/adr.rb +7 -7
- data/lib/aarch64/instructions/adrp.rb +7 -7
- data/lib/aarch64/instructions/and_log_imm.rb +14 -14
- data/lib/aarch64/instructions/and_log_shift.rb +14 -14
- data/lib/aarch64/instructions/ands_log_imm.rb +14 -14
- data/lib/aarch64/instructions/ands_log_shift.rb +14 -14
- data/lib/aarch64/instructions/asrv.rb +10 -10
- data/lib/aarch64/instructions/autda.rb +9 -12
- data/lib/aarch64/instructions/autdb.rb +9 -12
- data/lib/aarch64/instructions/autia.rb +9 -12
- data/lib/aarch64/instructions/autib.rb +9 -12
- data/lib/aarch64/instructions/axflag.rb +1 -1
- data/lib/aarch64/instructions/b_cond.rb +5 -5
- data/lib/aarch64/instructions/b_uncond.rb +3 -3
- data/lib/aarch64/instructions/bc_cond.rb +5 -5
- data/lib/aarch64/instructions/bfm.rb +13 -13
- data/lib/aarch64/instructions/bic_log_shift.rb +14 -14
- data/lib/aarch64/instructions/bics.rb +14 -14
- data/lib/aarch64/instructions/bl.rb +3 -3
- data/lib/aarch64/instructions/blr.rb +4 -4
- data/lib/aarch64/instructions/blra.rb +10 -10
- data/lib/aarch64/instructions/br.rb +4 -4
- data/lib/aarch64/instructions/bra.rb +10 -10
- data/lib/aarch64/instructions/brk.rb +3 -3
- data/lib/aarch64/instructions/bti.rb +3 -3
- data/lib/aarch64/instructions/cas.rb +14 -14
- data/lib/aarch64/instructions/casb.rb +12 -12
- data/lib/aarch64/instructions/cash.rb +12 -12
- data/lib/aarch64/instructions/casp.rb +14 -14
- data/lib/aarch64/instructions/cbnz.rb +7 -7
- data/lib/aarch64/instructions/cbz.rb +7 -7
- data/lib/aarch64/instructions/ccmn_imm.rb +12 -12
- data/lib/aarch64/instructions/ccmn_reg.rb +12 -12
- data/lib/aarch64/instructions/ccmp_imm.rb +12 -12
- data/lib/aarch64/instructions/ccmp_reg.rb +12 -12
- data/lib/aarch64/instructions/cfinv.rb +2 -9
- data/lib/aarch64/instructions/clrex.rb +3 -3
- data/lib/aarch64/instructions/cls_int.rb +8 -8
- data/lib/aarch64/instructions/clz_int.rb +8 -8
- data/lib/aarch64/instructions/crc32.rb +12 -12
- data/lib/aarch64/instructions/crc32c.rb +12 -12
- data/lib/aarch64/instructions/csdb.rb +1 -1
- data/lib/aarch64/instructions/csel.rb +12 -12
- data/lib/aarch64/instructions/csinc.rb +12 -12
- data/lib/aarch64/instructions/csinv.rb +12 -12
- data/lib/aarch64/instructions/csneg.rb +12 -12
- data/lib/aarch64/instructions/dcps.rb +5 -5
- data/lib/aarch64/instructions/dgh.rb +1 -1
- data/lib/aarch64/instructions/dmb.rb +3 -3
- data/lib/aarch64/instructions/drps.rb +2 -9
- data/lib/aarch64/instructions/dsb.rb +3 -3
- data/lib/aarch64/instructions/eon.rb +14 -14
- data/lib/aarch64/instructions/eor_log_imm.rb +14 -14
- data/lib/aarch64/instructions/eor_log_shift.rb +14 -14
- data/lib/aarch64/instructions/eret.rb +2 -9
- data/lib/aarch64/instructions/ereta.rb +3 -3
- data/lib/aarch64/instructions/esb.rb +1 -1
- data/lib/aarch64/instructions/extr.rb +13 -13
- data/lib/aarch64/instructions/gmi.rb +8 -8
- data/lib/aarch64/instructions/hint.rb +5 -5
- data/lib/aarch64/instructions/hlt.rb +3 -3
- data/lib/aarch64/instructions/hvc.rb +3 -3
- data/lib/aarch64/instructions/irg.rb +8 -8
- data/lib/aarch64/instructions/isb.rb +3 -3
- data/lib/aarch64/instructions/ld64b.rb +6 -6
- data/lib/aarch64/instructions/ldadd.rb +14 -14
- data/lib/aarch64/instructions/ldaddb.rb +12 -12
- data/lib/aarch64/instructions/ldaddh.rb +12 -12
- data/lib/aarch64/instructions/ldapr.rb +8 -8
- data/lib/aarch64/instructions/ldaprb.rb +6 -6
- data/lib/aarch64/instructions/ldaprh.rb +6 -6
- data/lib/aarch64/instructions/ldapur_gen.rb +12 -12
- data/lib/aarch64/instructions/ldar.rb +8 -8
- data/lib/aarch64/instructions/ldaxp.rb +10 -10
- data/lib/aarch64/instructions/ldaxr.rb +8 -8
- data/lib/aarch64/instructions/ldclr.rb +14 -14
- data/lib/aarch64/instructions/ldclrb.rb +14 -14
- data/lib/aarch64/instructions/ldeor.rb +14 -14
- data/lib/aarch64/instructions/ldg.rb +8 -8
- data/lib/aarch64/instructions/ldgm.rb +6 -6
- data/lib/aarch64/instructions/ldlar.rb +8 -8
- data/lib/aarch64/instructions/ldnp_gen.rb +12 -12
- data/lib/aarch64/instructions/ldp_gen.rb +14 -14
- data/lib/aarch64/instructions/ldpsw.rb +12 -12
- data/lib/aarch64/instructions/ldr_imm_gen.rb +12 -12
- data/lib/aarch64/instructions/ldr_imm_unsigned.rb +10 -10
- data/lib/aarch64/instructions/ldr_lit_gen.rb +7 -7
- data/lib/aarch64/instructions/ldr_reg_gen.rb +14 -14
- data/lib/aarch64/instructions/ldra.rb +14 -14
- data/lib/aarch64/instructions/ldrb_imm.rb +10 -10
- data/lib/aarch64/instructions/ldrb_reg.rb +12 -12
- data/lib/aarch64/instructions/ldrb_unsigned.rb +8 -8
- data/lib/aarch64/instructions/ldrh_imm.rb +10 -10
- data/lib/aarch64/instructions/ldrh_reg.rb +12 -12
- data/lib/aarch64/instructions/ldrh_unsigned.rb +8 -8
- data/lib/aarch64/instructions/ldrsb_imm.rb +12 -12
- data/lib/aarch64/instructions/ldrsb_reg.rb +14 -14
- data/lib/aarch64/instructions/ldrsb_unsigned.rb +10 -10
- data/lib/aarch64/instructions/ldrsh_imm.rb +12 -12
- data/lib/aarch64/instructions/ldrsh_reg.rb +14 -14
- data/lib/aarch64/instructions/ldrsh_unsigned.rb +10 -10
- data/lib/aarch64/instructions/ldrsw_imm.rb +10 -10
- data/lib/aarch64/instructions/ldrsw_lit.rb +5 -5
- data/lib/aarch64/instructions/ldrsw_reg.rb +12 -12
- data/lib/aarch64/instructions/ldrsw_unsigned.rb +8 -8
- data/lib/aarch64/instructions/ldset.rb +14 -14
- data/lib/aarch64/instructions/ldsetb.rb +12 -12
- data/lib/aarch64/instructions/ldseth.rb +12 -12
- data/lib/aarch64/instructions/ldsmax.rb +14 -14
- data/lib/aarch64/instructions/ldsmaxb.rb +12 -12
- data/lib/aarch64/instructions/ldsmaxh.rb +12 -12
- data/lib/aarch64/instructions/ldsmin.rb +14 -14
- data/lib/aarch64/instructions/ldsminb.rb +12 -12
- data/lib/aarch64/instructions/ldsminh.rb +12 -12
- data/lib/aarch64/instructions/ldtr.rb +10 -10
- data/lib/aarch64/instructions/ldtrb.rb +8 -8
- data/lib/aarch64/instructions/ldtrh.rb +8 -8
- data/lib/aarch64/instructions/ldtrsb.rb +10 -10
- data/lib/aarch64/instructions/ldtrsh.rb +10 -10
- data/lib/aarch64/instructions/ldtrsw.rb +8 -8
- data/lib/aarch64/instructions/ldumax.rb +14 -14
- data/lib/aarch64/instructions/ldumaxb.rb +12 -12
- data/lib/aarch64/instructions/ldumaxh.rb +12 -12
- data/lib/aarch64/instructions/ldumin.rb +14 -14
- data/lib/aarch64/instructions/lduminb.rb +12 -12
- data/lib/aarch64/instructions/lduminh.rb +12 -12
- data/lib/aarch64/instructions/ldur_gen.rb +10 -10
- data/lib/aarch64/instructions/ldursb.rb +10 -10
- data/lib/aarch64/instructions/ldursh.rb +10 -10
- data/lib/aarch64/instructions/ldursw.rb +8 -8
- data/lib/aarch64/instructions/ldxp.rb +10 -10
- data/lib/aarch64/instructions/ldxr.rb +8 -8
- data/lib/aarch64/instructions/lslv.rb +10 -10
- data/lib/aarch64/instructions/lsrv.rb +10 -10
- data/lib/aarch64/instructions/madd.rb +12 -12
- data/lib/aarch64/instructions/movk.rb +10 -10
- data/lib/aarch64/instructions/movn.rb +10 -10
- data/lib/aarch64/instructions/movz.rb +10 -10
- data/lib/aarch64/instructions/mrs.rb +14 -14
- data/lib/aarch64/instructions/msr_imm.rb +7 -7
- data/lib/aarch64/instructions/msr_reg.rb +14 -14
- data/lib/aarch64/instructions/msub.rb +12 -12
- data/lib/aarch64/instructions/nop.rb +1 -1
- data/lib/aarch64/instructions/orn_log_shift.rb +14 -14
- data/lib/aarch64/instructions/orr_log_imm.rb +14 -14
- data/lib/aarch64/instructions/orr_log_shift.rb +14 -14
- data/lib/aarch64/instructions/pacda.rb +8 -8
- data/lib/aarch64/instructions/pacdb.rb +8 -8
- data/lib/aarch64/instructions/pacga.rb +8 -8
- data/lib/aarch64/instructions/pacia.rb +8 -8
- data/lib/aarch64/instructions/pacia2.rb +5 -5
- data/lib/aarch64/instructions/pacib.rb +8 -8
- data/lib/aarch64/instructions/prfm_imm.rb +8 -8
- data/lib/aarch64/instructions/prfm_lit.rb +8 -8
- data/lib/aarch64/instructions/prfm_reg.rb +12 -12
- data/lib/aarch64/instructions/prfum.rb +8 -8
- data/lib/aarch64/instructions/psb.rb +2 -9
- data/lib/aarch64/instructions/rbit_int.rb +8 -8
- data/lib/aarch64/instructions/ret.rb +4 -4
- data/lib/aarch64/instructions/reta.rb +3 -3
- data/lib/aarch64/instructions/rev.rb +10 -10
- data/lib/aarch64/instructions/rmif.rb +8 -8
- data/lib/aarch64/instructions/rorv.rb +10 -10
- data/lib/aarch64/instructions/sb.rb +1 -1
- data/lib/aarch64/instructions/sbc.rb +10 -10
- data/lib/aarch64/instructions/sbcs.rb +10 -10
- data/lib/aarch64/instructions/sbfm.rb +13 -13
- data/lib/aarch64/instructions/sdiv.rb +10 -10
- data/lib/aarch64/instructions/setf.rb +6 -6
- data/lib/aarch64/instructions/sev.rb +1 -7
- data/lib/aarch64/instructions/sevl.rb +1 -1
- data/lib/aarch64/instructions/smaddl.rb +10 -10
- data/lib/aarch64/instructions/smc.rb +3 -3
- data/lib/aarch64/instructions/smsubl.rb +10 -10
- data/lib/aarch64/instructions/smulh.rb +8 -8
- data/lib/aarch64/instructions/st2g.rb +10 -10
- data/lib/aarch64/instructions/st64b.rb +6 -6
- data/lib/aarch64/instructions/st64bv.rb +8 -8
- data/lib/aarch64/instructions/st64bv0.rb +8 -8
- data/lib/aarch64/instructions/stg.rb +10 -10
- data/lib/aarch64/instructions/stgm.rb +6 -6
- data/lib/aarch64/instructions/stgp.rb +12 -12
- data/lib/aarch64/instructions/stllr.rb +8 -8
- data/lib/aarch64/instructions/stllrb.rb +6 -6
- data/lib/aarch64/instructions/stllrh.rb +6 -6
- data/lib/aarch64/instructions/stlr.rb +8 -8
- data/lib/aarch64/instructions/stlrb.rb +6 -6
- data/lib/aarch64/instructions/stlrh.rb +6 -6
- data/lib/aarch64/instructions/stlur_gen.rb +10 -10
- data/lib/aarch64/instructions/stlxp.rb +12 -12
- data/lib/aarch64/instructions/stlxr.rb +10 -10
- data/lib/aarch64/instructions/stlxrb.rb +8 -8
- data/lib/aarch64/instructions/stlxrh.rb +8 -8
- data/lib/aarch64/instructions/stnp_gen.rb +12 -12
- data/lib/aarch64/instructions/stp_gen.rb +14 -14
- data/lib/aarch64/instructions/str_imm_gen.rb +12 -12
- data/lib/aarch64/instructions/str_imm_unsigned.rb +10 -10
- data/lib/aarch64/instructions/str_reg_gen.rb +14 -14
- data/lib/aarch64/instructions/strb_imm.rb +10 -10
- data/lib/aarch64/instructions/strb_imm_unsigned.rb +8 -8
- data/lib/aarch64/instructions/strb_reg.rb +12 -12
- data/lib/aarch64/instructions/strh_imm.rb +10 -10
- data/lib/aarch64/instructions/strh_imm_unsigned.rb +8 -8
- data/lib/aarch64/instructions/strh_reg.rb +12 -12
- data/lib/aarch64/instructions/sttr.rb +10 -10
- data/lib/aarch64/instructions/stur_gen.rb +10 -10
- data/lib/aarch64/instructions/stxp.rb +12 -12
- data/lib/aarch64/instructions/stxr.rb +10 -10
- data/lib/aarch64/instructions/stxrb.rb +8 -8
- data/lib/aarch64/instructions/stxrh.rb +8 -8
- data/lib/aarch64/instructions/stz2g.rb +10 -10
- data/lib/aarch64/instructions/stzg.rb +10 -10
- data/lib/aarch64/instructions/stzgm.rb +6 -6
- data/lib/aarch64/instructions/sub_addsub_ext.rb +14 -14
- data/lib/aarch64/instructions/sub_addsub_imm.rb +12 -12
- data/lib/aarch64/instructions/sub_addsub_shift.rb +14 -14
- data/lib/aarch64/instructions/subg.rb +10 -10
- data/lib/aarch64/instructions/subp.rb +8 -8
- data/lib/aarch64/instructions/subps.rb +8 -8
- data/lib/aarch64/instructions/subs_addsub_ext.rb +14 -14
- data/lib/aarch64/instructions/subs_addsub_imm.rb +12 -12
- data/lib/aarch64/instructions/subs_addsub_shift.rb +14 -14
- data/lib/aarch64/instructions/svc.rb +3 -3
- data/lib/aarch64/instructions/swp.rb +14 -14
- data/lib/aarch64/instructions/swpb.rb +12 -12
- data/lib/aarch64/instructions/swph.rb +12 -12
- data/lib/aarch64/instructions/sys.rb +12 -12
- data/lib/aarch64/instructions/sysl.rb +12 -12
- data/lib/aarch64/instructions/tbnz.rb +9 -9
- data/lib/aarch64/instructions/tbz.rb +9 -9
- data/lib/aarch64/instructions/tsb.rb +1 -7
- data/lib/aarch64/instructions/ubfm.rb +13 -13
- data/lib/aarch64/instructions/udf_perm_undef.rb +3 -3
- data/lib/aarch64/instructions/udiv.rb +10 -10
- data/lib/aarch64/instructions/umaddl.rb +10 -10
- data/lib/aarch64/instructions/umsubl.rb +10 -10
- data/lib/aarch64/instructions/umulh.rb +8 -8
- data/lib/aarch64/instructions/wfe.rb +2 -9
- data/lib/aarch64/instructions/wfet.rb +4 -4
- data/lib/aarch64/instructions/wfi.rb +1 -1
- data/lib/aarch64/instructions/wfit.rb +4 -4
- data/lib/aarch64/instructions/xaflag.rb +1 -1
- data/lib/aarch64/instructions/xpac.rb +6 -6
- data/lib/aarch64/instructions/xpaclri.rb +1 -1
- data/lib/aarch64/instructions/yield.rb +2 -9
- data/lib/aarch64/instructions.rb +26 -8
- data/lib/aarch64/parser.rb +227 -0
- data/lib/aarch64/parser.tab.rb +6534 -0
- data/lib/aarch64/parser.y +1394 -0
- data/lib/aarch64/utils.rb +34 -0
- data/lib/aarch64/version.rb +1 -1
- data/lib/aarch64.rb +128 -58
- data/test/base_instructions_test.rb +34 -4
- data/test/helper.rb +48 -8
- data/test/parser_test.rb +1820 -0
- metadata +25 -14
- data/lib/aarch64/instructions/setgp.rb +0 -25
- data/lib/aarch64/instructions/setgpn.rb +0 -25
- data/lib/aarch64/instructions/setgpt.rb +0 -25
- data/lib/aarch64/instructions/setgptn.rb +0 -25
- data/lib/aarch64/instructions/setp.rb +0 -25
- data/lib/aarch64/instructions/setpn.rb +0 -25
- data/lib/aarch64/instructions/setpt.rb +0 -25
- data/lib/aarch64/instructions/setptn.rb +0 -25
@@ -4,30 +4,30 @@ module AArch64
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# Bitwise AND (shifted register), setting flags
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# ANDS <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
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# ANDS <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
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class ANDS_log_shift
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class ANDS_log_shift < Instruction
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def initialize xd, xn, xm, shift, amount, sf
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@xd = xd
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@xn = xn
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@xm = xm
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@shift = shift
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@amount = amount
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@sf = sf
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@xd = check_mask(xd, 0x1f)
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@xn = check_mask(xn, 0x1f)
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@xm = check_mask(xm, 0x1f)
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@shift = check_mask(shift, 0x03)
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@amount = check_mask(amount, 0x3f)
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@sf = check_mask(sf, 0x01)
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end
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def encode
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ANDS_log_shift(@sf, @shift, @xm
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ANDS_log_shift(@sf, @shift, @xm, @amount, @xn, @xd)
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end
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private
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def ANDS_log_shift sf, shift, rm, imm6, rn, rd
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insn = 0b0_11_01010_00_0_00000_000000_00000_00000
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insn |= ((sf
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insn |= ((shift
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insn |= ((rm
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insn |= ((imm6
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insn |= ((rn
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insn |= (rd
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insn |= ((sf) << 31)
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insn |= ((shift) << 22)
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insn |= ((rm) << 16)
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insn |= ((imm6) << 10)
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insn |= ((rn) << 5)
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insn |= (rd)
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insn
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end
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end
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@@ -4,26 +4,26 @@ module AArch64
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# Arithmetic Shift Right Variable
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# ASRV <Wd>, <Wn>, <Wm>
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# ASRV <Xd>, <Xn>, <Xm>
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class ASRV
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class ASRV < Instruction
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def initialize rd, rn, rm, sf
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@rd = rd
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@rn = rn
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@rm = rm
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@sf = sf
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@rd = check_mask(rd, 0x1f)
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@rn = check_mask(rn, 0x1f)
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@rm = check_mask(rm, 0x1f)
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@sf = check_mask(sf, 0x01)
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end
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def encode
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ASRV(@sf, @rm
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ASRV(@sf, @rm, @rn, @rd)
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end
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private
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def ASRV sf, rm, rn, rd
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insn = 0b0_0_0_11010110_00000_0010_10_00000_00000
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insn |= ((sf
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insn |= ((rm
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insn |= ((rn
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insn |= (rd
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insn |= ((sf) << 31)
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insn |= ((rm) << 16)
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insn |= ((rn) << 5)
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insn |= (rd)
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insn
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end
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end
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@@ -4,27 +4,24 @@ module AArch64
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# Authenticate Data address, using key A
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# AUTDA <Xd>, <Xn|SP>
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6
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# AUTDZA <Xd>
|
7
|
-
class AUTDA
|
8
|
-
def initialize
|
9
|
-
@
|
10
|
-
@
|
7
|
+
class AUTDA < Instruction
|
8
|
+
def initialize z, rd, rn
|
9
|
+
@z = check_mask(z, 0x01)
|
10
|
+
@rd = check_mask(rd, 0x1f)
|
11
|
+
@rn = check_mask(rn, 0x1f)
|
11
12
|
end
|
12
13
|
|
13
14
|
def encode
|
14
|
-
|
15
|
-
AUTDA(1, @n.to_i, @d.to_i)
|
16
|
-
else
|
17
|
-
AUTDA(0, @n.to_i, @d.to_i)
|
18
|
-
end
|
15
|
+
AUTDA(@z, @rn, @rd)
|
19
16
|
end
|
20
17
|
|
21
18
|
private
|
22
19
|
|
23
20
|
def AUTDA z, rn, rd
|
24
21
|
insn = 0b1_1_0_11010110_00001_0_0_0_110_00000_00000
|
25
|
-
insn |= ((z
|
26
|
-
insn |= ((rn
|
27
|
-
insn |= (rd
|
22
|
+
insn |= ((z) << 13)
|
23
|
+
insn |= ((rn) << 5)
|
24
|
+
insn |= (rd)
|
28
25
|
insn
|
29
26
|
end
|
30
27
|
end
|
@@ -4,27 +4,24 @@ module AArch64
|
|
4
4
|
# Authenticate Data address, using key B
|
5
5
|
# AUTDB <Xd>, <Xn|SP>
|
6
6
|
# AUTDZB <Xd>
|
7
|
-
class AUTDB
|
8
|
-
def initialize
|
9
|
-
@
|
10
|
-
@
|
7
|
+
class AUTDB < Instruction
|
8
|
+
def initialize z, rd, rn
|
9
|
+
@z = check_mask(z, 0x01)
|
10
|
+
@rd = check_mask(rd, 0x1f)
|
11
|
+
@rn = check_mask(rn, 0x1f)
|
11
12
|
end
|
12
13
|
|
13
14
|
def encode
|
14
|
-
|
15
|
-
AUTDB(1, @n.to_i, @d.to_i)
|
16
|
-
else
|
17
|
-
AUTDB(0, @n.to_i, @d.to_i)
|
18
|
-
end
|
15
|
+
AUTDB(@z, @rn, @rd)
|
19
16
|
end
|
20
17
|
|
21
18
|
private
|
22
19
|
|
23
20
|
def AUTDB z, rn, rd
|
24
21
|
insn = 0b1_1_0_11010110_00001_0_0_0_111_00000_00000
|
25
|
-
insn |= ((z
|
26
|
-
insn |= ((rn
|
27
|
-
insn |= (rd
|
22
|
+
insn |= ((z) << 13)
|
23
|
+
insn |= ((rn) << 5)
|
24
|
+
insn |= (rd)
|
28
25
|
insn
|
29
26
|
end
|
30
27
|
end
|
@@ -7,27 +7,24 @@ module AArch64
|
|
7
7
|
# AUTIA1716
|
8
8
|
# AUTIASP
|
9
9
|
# AUTIAZ
|
10
|
-
class AUTIA
|
11
|
-
def initialize
|
12
|
-
@
|
13
|
-
@
|
10
|
+
class AUTIA < Instruction
|
11
|
+
def initialize z, rd, rn
|
12
|
+
@z = check_mask(z, 0x01)
|
13
|
+
@rd = check_mask(rd, 0x1f)
|
14
|
+
@rn = check_mask(rn, 0x1f)
|
14
15
|
end
|
15
16
|
|
16
17
|
def encode
|
17
|
-
|
18
|
-
AUTIA(1, @n.to_i, @d.to_i)
|
19
|
-
else
|
20
|
-
AUTIA(0, @n.to_i, @d.to_i)
|
21
|
-
end
|
18
|
+
AUTIA(@z, @rn, @rd)
|
22
19
|
end
|
23
20
|
|
24
21
|
private
|
25
22
|
|
26
23
|
def AUTIA z, rn, rd
|
27
24
|
insn = 0b1_1_0_11010110_00001_0_0_0_100_00000_00000
|
28
|
-
insn |= ((z
|
29
|
-
insn |= ((rn
|
30
|
-
insn |= (rd
|
25
|
+
insn |= ((z) << 13)
|
26
|
+
insn |= ((rn) << 5)
|
27
|
+
insn |= (rd)
|
31
28
|
insn
|
32
29
|
end
|
33
30
|
end
|
@@ -7,27 +7,24 @@ module AArch64
|
|
7
7
|
# AUTIB1716
|
8
8
|
# AUTIBSP
|
9
9
|
# AUTIBZ
|
10
|
-
class AUTIB
|
11
|
-
def initialize
|
12
|
-
@
|
13
|
-
@
|
10
|
+
class AUTIB < Instruction
|
11
|
+
def initialize z, rd, rn
|
12
|
+
@z = check_mask(z, 0x01)
|
13
|
+
@rd = check_mask(rd, 0x1f)
|
14
|
+
@rn = check_mask(rn, 0x1f)
|
14
15
|
end
|
15
16
|
|
16
17
|
def encode
|
17
|
-
|
18
|
-
AUTIB(1, @n.to_i, @d.to_i)
|
19
|
-
else
|
20
|
-
AUTIB(0, @n.to_i, @d.to_i)
|
21
|
-
end
|
18
|
+
AUTIB(@z, @rn, @rd)
|
22
19
|
end
|
23
20
|
|
24
21
|
private
|
25
22
|
|
26
23
|
def AUTIB z, rn, rd
|
27
24
|
insn = 0b1_1_0_11010110_00001_0_0_0_101_00000_00000
|
28
|
-
insn |= ((z
|
29
|
-
insn |= ((rn
|
30
|
-
insn |= (rd
|
25
|
+
insn |= ((z) << 13)
|
26
|
+
insn |= ((rn) << 5)
|
27
|
+
insn |= (rd)
|
31
28
|
insn
|
32
29
|
end
|
33
30
|
end
|
@@ -3,22 +3,22 @@ module AArch64
|
|
3
3
|
# B.cond -- A64
|
4
4
|
# Branch conditionally
|
5
5
|
# B.<cond> <label>
|
6
|
-
class B_cond
|
6
|
+
class B_cond < Instruction
|
7
7
|
def initialize cond, label
|
8
|
-
@cond = cond
|
8
|
+
@cond = check_mask(cond, 0xf)
|
9
9
|
@label = label
|
10
10
|
end
|
11
11
|
|
12
12
|
def encode
|
13
|
-
B_cond(@label
|
13
|
+
B_cond(check_mask(unwrap_label(@label), 0x7ffff), @cond)
|
14
14
|
end
|
15
15
|
|
16
16
|
private
|
17
17
|
|
18
18
|
def B_cond imm19, cond
|
19
19
|
insn = 0b0101010_0_0000000000000000000_0_0000
|
20
|
-
insn |= (
|
21
|
-
insn |=
|
20
|
+
insn |= (imm19 << 5)
|
21
|
+
insn |= cond
|
22
22
|
insn
|
23
23
|
end
|
24
24
|
end
|
@@ -3,20 +3,20 @@ module AArch64
|
|
3
3
|
# B -- A64
|
4
4
|
# Branch
|
5
5
|
# B <label>
|
6
|
-
class B_uncond
|
6
|
+
class B_uncond < Instruction
|
7
7
|
def initialize label
|
8
8
|
@label = label
|
9
9
|
end
|
10
10
|
|
11
11
|
def encode
|
12
|
-
B_uncond(@label
|
12
|
+
B_uncond(check_mask(unwrap_label(@label), 0x3ffffff))
|
13
13
|
end
|
14
14
|
|
15
15
|
private
|
16
16
|
|
17
17
|
def B_uncond imm26
|
18
18
|
insn = 0b0_00101_00000000000000000000000000
|
19
|
-
insn |=
|
19
|
+
insn |= imm26
|
20
20
|
insn
|
21
21
|
end
|
22
22
|
end
|
@@ -3,22 +3,22 @@ module AArch64
|
|
3
3
|
# BC.cond -- A64
|
4
4
|
# Branch Consistent conditionally
|
5
5
|
# BC.<cond> <label>
|
6
|
-
class BC_cond
|
6
|
+
class BC_cond < Instruction
|
7
7
|
def initialize cond, label
|
8
|
-
@cond = cond
|
8
|
+
@cond = check_mask(cond, 0xf)
|
9
9
|
@label = label
|
10
10
|
end
|
11
11
|
|
12
12
|
def encode
|
13
|
-
BC_cond(@label
|
13
|
+
BC_cond(check_mask(unwrap_label(@label), 0x7ffff), @cond)
|
14
14
|
end
|
15
15
|
|
16
16
|
private
|
17
17
|
|
18
18
|
def BC_cond imm19, cond
|
19
19
|
insn = 0b0101010_0_0000000000000000000_1_0000
|
20
|
-
insn |= (
|
21
|
-
insn |=
|
20
|
+
insn |= (imm19 << 5)
|
21
|
+
insn |= cond
|
22
22
|
insn
|
23
23
|
end
|
24
24
|
end
|
@@ -4,29 +4,29 @@ module AArch64
|
|
4
4
|
# Bitfield Move
|
5
5
|
# BFM <Wd>, <Wn>, #<immr>, #<imms>
|
6
6
|
# BFM <Xd>, <Xn>, #<immr>, #<imms>
|
7
|
-
class BFM
|
7
|
+
class BFM < Instruction
|
8
8
|
def initialize d, n, immr, imms, sf
|
9
|
-
@d = d
|
10
|
-
@n = n
|
11
|
-
@immr = immr
|
12
|
-
@imms = imms
|
13
|
-
@sf
|
9
|
+
@d = check_mask(d, 0x1f)
|
10
|
+
@n = check_mask(n, 0x1f)
|
11
|
+
@immr = check_mask(immr, 0x3f)
|
12
|
+
@imms = check_mask(imms, 0x3f)
|
13
|
+
@sf = check_mask(sf, 0x01)
|
14
14
|
end
|
15
15
|
|
16
16
|
def encode
|
17
|
-
BFM(@sf, @sf, @immr, @imms, @n
|
17
|
+
BFM(@sf, @sf, @immr, @imms, @n, @d)
|
18
18
|
end
|
19
19
|
|
20
20
|
private
|
21
21
|
|
22
22
|
def BFM sf, n, immr, imms, rn, rd
|
23
23
|
insn = 0b0_01_100110_0_000000_000000_00000_00000
|
24
|
-
insn |= ((sf
|
25
|
-
insn |= ((n
|
26
|
-
insn |= ((immr
|
27
|
-
insn |= ((imms
|
28
|
-
insn |= ((rn
|
29
|
-
insn |= (rd
|
24
|
+
insn |= ((sf) << 31)
|
25
|
+
insn |= ((n) << 22)
|
26
|
+
insn |= ((immr) << 16)
|
27
|
+
insn |= ((imms) << 10)
|
28
|
+
insn |= ((rn) << 5)
|
29
|
+
insn |= (rd)
|
30
30
|
insn
|
31
31
|
end
|
32
32
|
end
|
@@ -4,30 +4,30 @@ module AArch64
|
|
4
4
|
# Bitwise Bit Clear (shifted register)
|
5
5
|
# BIC <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
|
6
6
|
# BIC <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
|
7
|
-
class BIC_log_shift
|
7
|
+
class BIC_log_shift < Instruction
|
8
8
|
def initialize d, n, m, shift, amount, sf
|
9
|
-
@d = d
|
10
|
-
@n = n
|
11
|
-
@m = m
|
12
|
-
@shift = shift
|
13
|
-
@amount = amount
|
14
|
-
@sf = sf
|
9
|
+
@d = check_mask(d, 0x1f)
|
10
|
+
@n = check_mask(n, 0x1f)
|
11
|
+
@m = check_mask(m, 0x1f)
|
12
|
+
@shift = check_mask(shift, 0x03)
|
13
|
+
@amount = check_mask(amount, 0x3f)
|
14
|
+
@sf = check_mask(sf, 0x01)
|
15
15
|
end
|
16
16
|
|
17
17
|
def encode
|
18
|
-
BIC_log_shift(@sf, @shift, @m
|
18
|
+
BIC_log_shift(@sf, @shift, @m, @amount, @n, @d)
|
19
19
|
end
|
20
20
|
|
21
21
|
private
|
22
22
|
|
23
23
|
def BIC_log_shift sf, shift, rm, imm6, rn, rd
|
24
24
|
insn = 0b0_00_01010_00_1_00000_000000_00000_00000
|
25
|
-
insn |= ((sf
|
26
|
-
insn |= ((shift
|
27
|
-
insn |= ((rm
|
28
|
-
insn |= ((imm6
|
29
|
-
insn |= ((rn
|
30
|
-
insn |= (rd
|
25
|
+
insn |= ((sf) << 31)
|
26
|
+
insn |= ((shift) << 22)
|
27
|
+
insn |= ((rm) << 16)
|
28
|
+
insn |= ((imm6) << 10)
|
29
|
+
insn |= ((rn) << 5)
|
30
|
+
insn |= (rd)
|
31
31
|
insn
|
32
32
|
end
|
33
33
|
end
|
@@ -4,30 +4,30 @@ module AArch64
|
|
4
4
|
# Bitwise Bit Clear (shifted register), setting flags
|
5
5
|
# BICS <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
|
6
6
|
# BICS <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
|
7
|
-
class BICS
|
7
|
+
class BICS < Instruction
|
8
8
|
def initialize d, n, m, shift, amount, sf
|
9
|
-
@d = d
|
10
|
-
@n = n
|
11
|
-
@m = m
|
12
|
-
@shift = shift
|
13
|
-
@amount = amount
|
14
|
-
@sf = sf
|
9
|
+
@d = check_mask(d, 0x1f)
|
10
|
+
@n = check_mask(n, 0x1f)
|
11
|
+
@m = check_mask(m, 0x1f)
|
12
|
+
@shift = check_mask(shift, 0x03)
|
13
|
+
@amount = check_mask(amount, 0x3f)
|
14
|
+
@sf = check_mask(sf, 0x01)
|
15
15
|
end
|
16
16
|
|
17
17
|
def encode
|
18
|
-
BICS(@sf, @shift, @m
|
18
|
+
BICS(@sf, @shift, @m, @amount, @n, @d)
|
19
19
|
end
|
20
20
|
|
21
21
|
private
|
22
22
|
|
23
23
|
def BICS sf, shift, rm, imm6, rn, rd
|
24
24
|
insn = 0b0_11_01010_00_1_00000_000000_00000_00000
|
25
|
-
insn |= ((sf
|
26
|
-
insn |= ((shift
|
27
|
-
insn |= ((rm
|
28
|
-
insn |= ((imm6
|
29
|
-
insn |= ((rn
|
30
|
-
insn |= (rd
|
25
|
+
insn |= ((sf) << 31)
|
26
|
+
insn |= ((shift) << 22)
|
27
|
+
insn |= ((rm) << 16)
|
28
|
+
insn |= ((imm6) << 10)
|
29
|
+
insn |= ((rn) << 5)
|
30
|
+
insn |= (rd)
|
31
31
|
insn
|
32
32
|
end
|
33
33
|
end
|
@@ -3,20 +3,20 @@ module AArch64
|
|
3
3
|
# BL -- A64
|
4
4
|
# Branch with Link
|
5
5
|
# BL <label>
|
6
|
-
class BL
|
6
|
+
class BL < Instruction
|
7
7
|
def initialize label
|
8
8
|
@label = label
|
9
9
|
end
|
10
10
|
|
11
11
|
def encode
|
12
|
-
BL(@label
|
12
|
+
BL(check_mask(unwrap_label(@label), 0x3ffffff))
|
13
13
|
end
|
14
14
|
|
15
15
|
private
|
16
16
|
|
17
17
|
def BL imm26
|
18
18
|
insn = 0b1_00101_00000000000000000000000000
|
19
|
-
insn |=
|
19
|
+
insn |= imm26
|
20
20
|
insn
|
21
21
|
end
|
22
22
|
end
|
@@ -3,20 +3,20 @@ module AArch64
|
|
3
3
|
# BLR -- A64
|
4
4
|
# Branch with Link to Register
|
5
5
|
# BLR <Xn>
|
6
|
-
class BLR
|
6
|
+
class BLR < Instruction
|
7
7
|
def initialize n
|
8
|
-
@n = n
|
8
|
+
@n = check_mask(n, 0x1f)
|
9
9
|
end
|
10
10
|
|
11
11
|
def encode
|
12
|
-
BLR(@n
|
12
|
+
BLR(@n)
|
13
13
|
end
|
14
14
|
|
15
15
|
private
|
16
16
|
|
17
17
|
def BLR rn
|
18
18
|
insn = 0b1101011_0_0_01_11111_0000_0_0_00000_00000
|
19
|
-
insn |= ((rn
|
19
|
+
insn |= ((rn) << 5)
|
20
20
|
insn
|
21
21
|
end
|
22
22
|
end
|
@@ -6,26 +6,26 @@ module AArch64
|
|
6
6
|
# BLRAA <Xn>, <Xm|SP>
|
7
7
|
# BLRABZ <Xn>
|
8
8
|
# BLRAB <Xn>, <Xm|SP>
|
9
|
-
class BLRA
|
9
|
+
class BLRA < Instruction
|
10
10
|
def initialize rn, rm, z, m
|
11
|
-
@rn = rn
|
12
|
-
@rm = rm
|
13
|
-
@z = z
|
14
|
-
@m = m
|
11
|
+
@rn = check_mask(rn, 0x1f)
|
12
|
+
@rm = check_mask(rm, 0x1f)
|
13
|
+
@z = check_mask(z, 0x01)
|
14
|
+
@m = check_mask(m, 0x01)
|
15
15
|
end
|
16
16
|
|
17
17
|
def encode
|
18
|
-
BLRA(@z, @m, @rn
|
18
|
+
BLRA(@z, @m, @rn, @rm)
|
19
19
|
end
|
20
20
|
|
21
21
|
private
|
22
22
|
|
23
23
|
def BLRA z, m, rn, rm
|
24
24
|
insn = 0b1101011_0_0_01_11111_0000_1_0_00000_00000
|
25
|
-
insn |= ((z
|
26
|
-
insn |= ((m
|
27
|
-
insn |= ((rn
|
28
|
-
insn |= (rm
|
25
|
+
insn |= ((z) << 24)
|
26
|
+
insn |= ((m) << 10)
|
27
|
+
insn |= ((rn) << 5)
|
28
|
+
insn |= (rm)
|
29
29
|
insn
|
30
30
|
end
|
31
31
|
end
|
@@ -3,20 +3,20 @@ module AArch64
|
|
3
3
|
# BR -- A64
|
4
4
|
# Branch to Register
|
5
5
|
# BR <Xn>
|
6
|
-
class BR
|
6
|
+
class BR < Instruction
|
7
7
|
def initialize rn
|
8
|
-
@rn = rn
|
8
|
+
@rn = check_mask(rn, 0x1f)
|
9
9
|
end
|
10
10
|
|
11
11
|
def encode
|
12
|
-
BR(@rn
|
12
|
+
BR(@rn)
|
13
13
|
end
|
14
14
|
|
15
15
|
private
|
16
16
|
|
17
17
|
def BR rn
|
18
18
|
insn = 0b1101011_0_0_00_11111_0000_0_0_00000_00000
|
19
|
-
insn |= ((rn
|
19
|
+
insn |= ((rn) << 5)
|
20
20
|
insn
|
21
21
|
end
|
22
22
|
end
|
@@ -6,26 +6,26 @@ module AArch64
|
|
6
6
|
# BRAA <Xn>, <Xm|SP>
|
7
7
|
# BRABZ <Xn>
|
8
8
|
# BRAB <Xn>, <Xm|SP>
|
9
|
-
class BRA
|
9
|
+
class BRA < Instruction
|
10
10
|
def initialize rn, rm, z, m
|
11
|
-
@rn = rn
|
12
|
-
@rm = rm
|
13
|
-
@z = z
|
14
|
-
@m = m
|
11
|
+
@rn = check_mask(rn, 0x1f)
|
12
|
+
@rm = check_mask(rm, 0x1f)
|
13
|
+
@z = check_mask(z, 0x01)
|
14
|
+
@m = check_mask(m, 0x01)
|
15
15
|
end
|
16
16
|
|
17
17
|
def encode
|
18
|
-
BRA(@z, @m, @rn
|
18
|
+
BRA(@z, @m, @rn, @rm)
|
19
19
|
end
|
20
20
|
|
21
21
|
private
|
22
22
|
|
23
23
|
def BRA z, m, rn, rm
|
24
24
|
insn = 0b1101011_0_0_00_11111_0000_1_0_00000_00000
|
25
|
-
insn |= ((z
|
26
|
-
insn |= ((m
|
27
|
-
insn |= ((rn
|
28
|
-
insn |= (rm
|
25
|
+
insn |= ((z) << 24)
|
26
|
+
insn |= ((m) << 10)
|
27
|
+
insn |= ((rn) << 5)
|
28
|
+
insn |= (rm)
|
29
29
|
insn
|
30
30
|
end
|
31
31
|
end
|
@@ -3,9 +3,9 @@ module AArch64
|
|
3
3
|
# BRK -- A64
|
4
4
|
# Breakpoint instruction
|
5
5
|
# BRK #<imm>
|
6
|
-
class BRK
|
6
|
+
class BRK < Instruction
|
7
7
|
def initialize imm
|
8
|
-
@imm = imm
|
8
|
+
@imm = check_mask(imm, 0xffff)
|
9
9
|
end
|
10
10
|
|
11
11
|
def encode
|
@@ -16,7 +16,7 @@ module AArch64
|
|
16
16
|
|
17
17
|
def BRK imm16
|
18
18
|
insn = 0b11010100_001_0000000000000000_000_00
|
19
|
-
insn |= ((imm16
|
19
|
+
insn |= ((imm16) << 5)
|
20
20
|
insn
|
21
21
|
end
|
22
22
|
end
|
@@ -3,9 +3,9 @@ module AArch64
|
|
3
3
|
# BTI -- A64
|
4
4
|
# Branch Target Identification
|
5
5
|
# BTI {<targets>}
|
6
|
-
class BTI
|
6
|
+
class BTI < Instruction
|
7
7
|
def initialize target
|
8
|
-
@target = target
|
8
|
+
@target = check_mask(target, 0x03)
|
9
9
|
end
|
10
10
|
|
11
11
|
def encode
|
@@ -16,7 +16,7 @@ module AArch64
|
|
16
16
|
|
17
17
|
def BTI target
|
18
18
|
insn = 0b1101010100_0_00_011_0010_0100_000_11111
|
19
|
-
insn |= ((target
|
19
|
+
insn |= ((target) << 5)
|
20
20
|
insn
|
21
21
|
end
|
22
22
|
end
|