aarch64 1.0.1 → 2.0.0

data/lib/aarch64/instructions/ldp_gen.rb

@@ -8,30 +8,30 @@ module AArch64
     # LDP  <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]!
     # LDP  <Wt1>, <Wt2>, [<Xn|SP>{, #<imm>}]
     # LDP  <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]
-    class LDP_gen
+    class LDP_gen < Instruction
       def initialize rt, rt2, rn, imm7, mode, opc
-        @rt   = rt
-        @rt2  = rt2
-        @rn   = rn
-        @imm7 = imm7
-        @mode = mode
-        @opc  = opc
+        @rt   = check_mask(rt, 0x1f)
+        @rt2  = check_mask(rt2, 0x1f)
+        @rn   = check_mask(rn, 0x1f)
+        @imm7 = check_mask(imm7, 0x7f)
+        @mode = check_mask(mode, 0x07)
+        @opc  = check_mask(opc, 0x03)
       end
 
       def encode
-        LDP_gen(@opc, @mode, @imm7, @rt2.to_i, @rn.to_i, @rt.to_i)
+        LDP_gen(@opc, @mode, @imm7, @rt2, @rn, @rt)
       end
 
       private
 
       def LDP_gen opc, mode, imm7, rt2, rn, rt
         insn = 0b00_101_0_000_1_0000000_00000_00000_00000
-        insn |= ((opc & 0x3) << 30)
-        insn |= ((mode & 0x7) << 23)
-        insn |= ((imm7 & 0x7f) << 15)
-        insn |= ((rt2 & 0x1f) << 10)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((opc) << 30)
+        insn |= ((mode) << 23)
+        insn |= ((imm7) << 15)
+        insn |= ((rt2) << 10)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/ldpsw.rb

@@ -5,28 +5,28 @@ module AArch64
     # LDPSW  <Xt1>, <Xt2>, [<Xn|SP>], #<imm>
     # LDPSW  <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]!
     # LDPSW  <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]
-    class LDPSW
+    class LDPSW < Instruction
       def initialize rt, rt2, rn, imm7, mode
-        @rt   = rt
-        @rt2  = rt2
-        @rn   = rn
-        @imm7 = imm7
-        @mode = mode
+        @rt   = check_mask(rt, 0x1f)
+        @rt2  = check_mask(rt2, 0x1f)
+        @rn   = check_mask(rn, 0x1f)
+        @imm7 = check_mask(imm7, 0x7f)
+        @mode = check_mask(mode, 0x07)
       end
 
       def encode
-        LDPSW(@mode, @imm7, @rt2.to_i, @rn.to_i, @rt.to_i)
+        LDPSW(@mode, @imm7, @rt2, @rn, @rt)
       end
 
       private
 
       def LDPSW mode, imm7, rt2, rn, rt
         insn = 0b01_101_0_000_1_0000000_00000_00000_00000
-        insn |= ((mode & 0x7) << 23)
-        insn |= ((imm7 & 0x7f) << 15)
-        insn |= ((rt2 & 0x1f) << 10)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((mode) << 23)
+        insn |= ((imm7) << 15)
+        insn |= ((rt2) << 10)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/ldr_imm_gen.rb

@@ -6,28 +6,28 @@ module AArch64
     # LDR  <Xt>, [<Xn|SP>], #<simm>
     # LDR  <Wt>, [<Xn|SP>, #<simm>]!
     # LDR  <Xt>, [<Xn|SP>, #<simm>]!
-    class LDR_imm_gen
+    class LDR_imm_gen < Instruction
       def initialize rt, rn, imm9, size, mode
-        @rt   = rt
-        @rn   = rn
-        @imm9 = imm9
-        @size = size
-        @mode = mode
+        @rt   = check_mask(rt, 0x1f)
+        @rn   = check_mask(rn, 0x1f)
+        @imm9 = check_mask(imm9, 0x1ff)
+        @size = check_mask(size, 0x03)
+        @mode = check_mask(mode, 0x03)
       end
 
       def encode
-        LDR_imm_gen(@size, @imm9, @mode, @rn.to_i, @rt.to_i)
+        LDR_imm_gen(@size, @imm9, @mode, @rn, @rt)
       end
 
       private
 
       def LDR_imm_gen size, imm9, mode, rn, rt
         insn = 0b00_111_0_00_01_0_000000000_00_00000_00000
-        insn |= ((size & 0x3) << 30)
-        insn |= ((imm9 & 0x1ff) << 12)
-        insn |= ((mode & 0x3) << 10)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((size) << 30)
+        insn |= ((imm9) << 12)
+        insn |= ((mode) << 10)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/ldr_imm_unsigned.rb

@@ -4,26 +4,26 @@ module AArch64
     # Load Register (immediate)
     # LDR  <Wt>, [<Xn|SP>{, #<pimm>}]
     # LDR  <Xt>, [<Xn|SP>{, #<pimm>}]
-    class LDR_imm_unsigned
+    class LDR_imm_unsigned < Instruction
       def initialize rt, rn, imm12, size
-        @rt    = rt
-        @rn    = rn
-        @imm12 = imm12
-        @size  = size
+        @rt    = check_mask(rt, 0x1f)
+        @rn    = check_mask(rn, 0x1f)
+        @imm12 = check_mask(imm12, 0xfff)
+        @size  = check_mask(size, 0x03)
       end
 
       def encode
-        LDR_imm_gen(@size, @imm12, @rn.to_i, @rt.to_i)
+        LDR_imm_gen(@size, @imm12, @rn, @rt)
       end
 
       private
 
       def LDR_imm_gen size, imm12, rn, rt
         insn = 0b00_111_0_01_01_000000000000_00000_00000
-        insn |= ((size & 0x3) << 30)
-        insn |= ((imm12 & 0xfff) << 10)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((size) << 30)
+        insn |= ((imm12) << 10)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/ldr_lit_gen.rb

@@ -4,24 +4,24 @@ module AArch64
     # Load Register (literal)
     # LDR  <Wt>, <label>
     # LDR  <Xt>, <label>
-    class LDR_lit_gen
+    class LDR_lit_gen < Instruction
       def initialize rt, imm19, size
-        @rt    = rt
+        @rt    = check_mask(rt, 0x1f)
         @imm19 = imm19
-        @size  = size
+        @size  = check_mask(size, 0x3)
       end
 
       def encode
-        LDR_lit_gen(@size, @imm19.to_i / 4, @rt.to_i)
+        LDR_lit_gen(@size, check_mask(unwrap_label(@imm19), 0x7ffff), @rt)
       end
 
       private
 
       def LDR_lit_gen size, imm19, rt
         insn = 0b00_011_0_00_0000000000000000000_00000
-        insn |= ((size & 0x3) << 30)
-        insn |= ((imm19 & 0x7ffff) << 5)
-        insn |= (rt & 0x1f)
+        insn |= (size << 30)
+        insn |= (imm19 << 5)
+        insn |= rt
         insn
       end
     end

data/lib/aarch64/instructions/ldr_reg_gen.rb

@@ -4,30 +4,30 @@ module AArch64
     # Load Register (register)
     # LDR  <Wt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
     # LDR  <Xt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
-    class LDR_reg_gen
+    class LDR_reg_gen < Instruction
       def initialize rt, rn, rm, size, option, s
-        @rt     = rt
-        @rn     = rn
-        @rm     = rm
-        @size   = size
-        @option = option
-        @s      = s
+        @rt     = check_mask(rt, 0x1f)
+        @rn     = check_mask(rn, 0x1f)
+        @rm     = check_mask(rm, 0x1f)
+        @size   = check_mask(size, 0x03)
+        @option = check_mask(option, 0x07)
+        @s      = check_mask(s, 0x01)
       end
 
       def encode
-        LDR_reg_gen(@size, @rm.to_i, @option, @s, @rn.to_i, @rt.to_i)
+        LDR_reg_gen(@size, @rm, @option, @s, @rn, @rt)
       end
 
       private
 
       def LDR_reg_gen size, rm, option, s, rn, rt
         insn = 0b00_111_0_00_01_1_00000_000_0_10_00000_00000
-        insn |= ((size & 0x3) << 30)
-        insn |= ((rm & 0x1f) << 16)
-        insn |= ((option & 0x7) << 13)
-        insn |= ((s & 0x1) << 12)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((size) << 30)
+        insn |= ((rm) << 16)
+        insn |= ((option) << 13)
+        insn |= ((s) << 12)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/ldra.rb

@@ -6,30 +6,30 @@ module AArch64
     # LDRAA  <Xt>, [<Xn|SP>{, #<simm>}]!
     # LDRAB  <Xt>, [<Xn|SP>{, #<simm>}]
     # LDRAB  <Xt>, [<Xn|SP>{, #<simm>}]!
-    class LDRA
+    class LDRA < Instruction
       def initialize rt, rn, imm9, m, w, s
-        @rt   = rt
-        @rn   = rn
-        @imm9 = imm9
-        @m    = m
-        @w    = w
-        @s    = s
+        @rt   = check_mask(rt, 0x1f)
+        @rn   = check_mask(rn, 0x1f)
+        @imm9 = check_mask(imm9, 0x1ff)
+        @m    = check_mask(m, 0x01)
+        @w    = check_mask(w, 0x01)
+        @s    = check_mask(s, 0x01)
       end
 
       def encode
-        LDRA(@m, @s, @imm9, @w, @rn.to_i, @rt.to_i)
+        LDRA(@m, @s, @imm9, @w, @rn, @rt)
       end
 
       private
 
       def LDRA m, s, imm9, w, rn, rt
         insn = 0b11_111_0_00_0_0_1_000000000_0_1_00000_00000
-        insn |= ((m & 0x1) << 23)
-        insn |= ((s & 0x1) << 22)
-        insn |= ((imm9 & 0x1ff) << 12)
-        insn |= ((w & 0x1) << 11)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((m) << 23)
+        insn |= ((s) << 22)
+        insn |= ((imm9) << 12)
+        insn |= ((w) << 11)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/ldrb_imm.rb

@@ -5,26 +5,26 @@ module AArch64
     # LDRB  <Wt>, [<Xn|SP>], #<simm>
     # LDRB  <Wt>, [<Xn|SP>, #<simm>]!
     # LDRB  <Wt>, [<Xn|SP>{, #<pimm>}]
-    class LDRB_imm
+    class LDRB_imm < Instruction
       def initialize rt, rn, imm9, option
-        @rt     = rt
-        @rn     = rn
-        @imm9   = imm9
-        @option = option
+        @rt     = check_mask(rt, 0x1f)
+        @rn     = check_mask(rn, 0x1f)
+        @imm9   = check_mask(imm9, 0x1ff)
+        @option = check_mask(option, 0x03)
       end
 
       def encode
-        LDRB_imm(@imm9, @option, @rn.to_i, @rt.to_i)
+        LDRB_imm(@imm9, @option, @rn, @rt)
       end
 
       private
 
       def LDRB_imm imm9, option, rn, rt
         insn = 0b00_111_0_00_01_0_000000000_01_00000_00000
-        insn |= ((imm9 & 0x1ff) << 12)
-        insn |= ((option & 0x3) << 10)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((imm9) << 12)
+        insn |= ((option) << 10)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/ldrb_reg.rb

@@ -4,28 +4,28 @@ module AArch64
     # Load Register Byte (register)
     # LDRB  <Wt>, [<Xn|SP>, (<Wm>|<Xm>), <extend> {<amount>}]
     # LDRB  <Wt>, [<Xn|SP>, <Xm>{, LSL <amount>}]
-    class LDRB_reg
+    class LDRB_reg < Instruction
       def initialize rt, rn, rm, s, option
-        @rt     = rt
-        @rn     = rn
-        @rm     = rm
-        @s      = s
-        @option = option
+        @rt     = check_mask(rt, 0x1f)
+        @rn     = check_mask(rn, 0x1f)
+        @rm     = check_mask(rm, 0x1f)
+        @s      = check_mask(s, 0x01)
+        @option = check_mask(option, 0x07)
       end
 
       def encode
-        LDRB_reg(@rm.to_i, @option, @s, @rn.to_i, @rt.to_i)
+        LDRB_reg(@rm, @option, @s, @rn, @rt)
       end
 
       private
 
       def LDRB_reg rm, option, s, rn, rt
         insn = 0b00_111_0_00_01_1_00000_000_0_10_00000_00000
-        insn |= ((rm & 0x1f) << 16)
-        insn |= ((option & 0x7) << 13)
-        insn |= ((s & 0x1) << 12)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((rm) << 16)
+        insn |= ((option) << 13)
+        insn |= ((s) << 12)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/ldrb_unsigned.rb

@@ -3,24 +3,24 @@ module AArch64
     # LDRB (immediate) -- A64
     # Load Register Byte (immediate)
     # LDRB  <Wt>, [<Xn|SP>{, #<pimm>}]
-    class LDRB_unsigned
+    class LDRB_unsigned < Instruction
       def initialize rt, rn, imm12
-        @rt    = rt
-        @rn    = rn
-        @imm12 = imm12
+        @rt    = check_mask(rt, 0x1f)
+        @rn    = check_mask(rn, 0x1f)
+        @imm12 = check_mask(imm12, 0xfff)
       end
 
       def encode
-        LDRB_imm(@imm12, @rn.to_i, @rt.to_i)
+        LDRB_imm(@imm12, @rn, @rt)
       end
 
       private
 
       def LDRB_imm imm12, rn, rt
         insn = 0b00_111_0_01_01_0_00000000000_00000_00000
-        insn |= ((imm12 & 0xfff) << 10)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((imm12) << 10)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/ldrh_imm.rb

@@ -5,26 +5,26 @@ module AArch64
     # LDRH  <Wt>, [<Xn|SP>], #<simm>
     # LDRH  <Wt>, [<Xn|SP>, #<simm>]!
     # LDRH  <Wt>, [<Xn|SP>{, #<pimm>}]
-    class LDRH_imm
+    class LDRH_imm < Instruction
       def initialize rt, rn, imm9, option
-        @rt     = rt
-        @rn     = rn
-        @imm9   = imm9
-        @option = option
+        @rt     = check_mask(rt, 0x1f)
+        @rn     = check_mask(rn, 0x1f)
+        @imm9   = check_mask(imm9, 0x1ff)
+        @option = check_mask(option, 0x03)
       end
 
       def encode
-        LDRH_imm(@imm9, @option, @rn.to_i, @rt.to_i)
+        LDRH_imm(@imm9, @option, @rn, @rt)
       end
 
       private
 
       def LDRH_imm imm9, option, rn, rt
         insn = 0b01_111_0_00_01_0_000000000_01_00000_00000
-        insn |= ((imm9 & 0x1ff) << 12)
-        insn |= ((option & 0x3) << 10)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((imm9) << 12)
+        insn |= ((option) << 10)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/ldrh_reg.rb

@@ -3,28 +3,28 @@ module AArch64
     # LDRH (register) -- A64
     # Load Register Halfword (register)
     # LDRH  <Wt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
-    class LDRH_reg
+    class LDRH_reg < Instruction
       def initialize rt, rn, rm, s, option
-        @rt     = rt
-        @rn     = rn
-        @rm     = rm
-        @s      = s
-        @option = option
+        @rt     = check_mask(rt, 0x1f)
+        @rn     = check_mask(rn, 0x1f)
+        @rm     = check_mask(rm, 0x1f)
+        @s      = check_mask(s, 0x01)
+        @option = check_mask(option, 0x07)
       end
 
       def encode
-        LDRH_reg(@rm.to_i, @option, @s, @rn.to_i, @rt.to_i)
+        LDRH_reg(@rm, @option, @s, @rn, @rt)
       end
 
       private
 
       def LDRH_reg rm, option, s, rn, rt
         insn = 0b01_111_0_00_01_1_00000_000_0_10_00000_00000
-        insn |= ((rm & 0x1f) << 16)
-        insn |= ((option & 0x7) << 13)
-        insn |= ((s & 0x1) << 12)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((rm) << 16)
+        insn |= ((option) << 13)
+        insn |= ((s) << 12)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/ldrh_unsigned.rb

@@ -3,24 +3,24 @@ module AArch64
     # LDRH (immediate) -- A64
     # Load Register Halfword (immediate)
     # LDRH  <Wt>, [<Xn|SP>{, #<pimm>}]
-    class LDRH_unsigned
+    class LDRH_unsigned < Instruction
       def initialize rt, rn, imm12
-        @rt    = rt
-        @rn    = rn
-        @imm12 = imm12
+        @rt    = check_mask(rt, 0x1f)
+        @rn    = check_mask(rn, 0x1f)
+        @imm12 = check_mask(imm12, 0xfff)
       end
 
       def encode
-        LDRH_unsigned(@imm12, @rn.to_i, @rt.to_i)
+        LDRH_unsigned(@imm12, @rn, @rt)
       end
 
       private
 
       def LDRH_unsigned imm12, rn, rt
         insn = 0b01_111_0_01_01_0_00000000000_00000_00000
-        insn |= ((imm12 & 0xfff) << 9)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((imm12) << 9)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/ldrsb_imm.rb

@@ -8,28 +8,28 @@ module AArch64
     # LDRSB  <Xt>, [<Xn|SP>, #<simm>]!
     # LDRSB  <Wt>, [<Xn|SP>{, #<pimm>}]
     # LDRSB  <Xt>, [<Xn|SP>{, #<pimm>}]
-    class LDRSB_imm
+    class LDRSB_imm < Instruction
       def initialize rt, rn, imm9, option, opc
-        @rt     = rt
-        @rn     = rn
-        @imm9   = imm9
-        @option = option
-        @opc    = opc
+        @rt     = check_mask(rt, 0x1f)
+        @rn     = check_mask(rn, 0x1f)
+        @imm9   = check_mask(imm9, 0x1ff)
+        @option = check_mask(option, 0x03)
+        @opc    = check_mask(opc, 0x03)
       end
 
       def encode
-        LDRSB_imm(@opc, @imm9, @option, @rn.to_i, @rt.to_i)
+        LDRSB_imm(@opc, @imm9, @option, @rn, @rt)
       end
 
       private
 
       def LDRSB_imm opc, imm9, option, rn, rt
         insn = 0b00_111_0_00_00_0_000000000_01_00000_00000
-        insn |= ((opc & 0x3) << 22)
-        insn |= ((imm9 & 0x1ff) << 12)
-        insn |= ((option & 0x3) << 10)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((opc) << 22)
+        insn |= ((imm9) << 12)
+        insn |= ((option) << 10)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/ldrsb_reg.rb

@@ -6,30 +6,30 @@ module AArch64
     # LDRSB  <Wt>, [<Xn|SP>, <Xm>{, LSL <amount>}]
     # LDRSB  <Xt>, [<Xn|SP>, (<Wm>|<Xm>), <extend> {<amount>}]
     # LDRSB  <Xt>, [<Xn|SP>, <Xm>{, LSL <amount>}]
-    class LDRSB_reg
+    class LDRSB_reg < Instruction
       def initialize rt, rn, rm, s, option, opc
-        @rt     = rt
-        @rn     = rn
-        @rm     = rm
-        @s      = s
-        @option = option
-        @opc    = opc
+        @rt     = check_mask(rt, 0x1f)
+        @rn     = check_mask(rn, 0x1f)
+        @rm     = check_mask(rm, 0x1f)
+        @s      = check_mask(s, 0x01)
+        @option = check_mask(option, 0x07)
+        @opc    = check_mask(opc, 0x03)
       end
 
       def encode
-        LDRSB_reg(@opc, @rm.to_i, @option, @s, @rn.to_i, @rt.to_i)
+        LDRSB_reg(@opc, @rm, @option, @s, @rn, @rt)
       end
 
       private
 
       def LDRSB_reg opc, rm, option, s, rn, rt
         insn = 0b00_111_0_00_00_1_00000_000_0_10_00000_00000
-        insn |= ((opc & 0x3) << 22)
-        insn |= ((rm & 0x1f) << 16)
-        insn |= ((option & 0x7) << 13)
-        insn |= ((s & 0x1) << 12)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((opc) << 22)
+        insn |= ((rm) << 16)
+        insn |= ((option) << 13)
+        insn |= ((s) << 12)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/ldrsb_unsigned.rb

@@ -8,26 +8,26 @@ module AArch64
     # LDRSB  <Xt>, [<Xn|SP>, #<simm>]!
     # LDRSB  <Wt>, [<Xn|SP>{, #<pimm>}]
     # LDRSB  <Xt>, [<Xn|SP>{, #<pimm>}]
-    class LDRSB_unsigned
+    class LDRSB_unsigned < Instruction
       def initialize rt, rn, imm12, opc
-        @rt    = rt
-        @rn    = rn
-        @imm12 = imm12
-        @opc   = opc
+        @rt    = check_mask(rt, 0x1f)
+        @rn    = check_mask(rn, 0x1f)
+        @imm12 = check_mask(imm12, 0xfff)
+        @opc   = check_mask(opc, 0x03)
       end
 
       def encode
-        LDRSB_unsigned(@opc, @imm12, @rn.to_i, @rt.to_i)
+        LDRSB_unsigned(@opc, @imm12, @rn, @rt)
       end
 
       private
 
       def LDRSB_unsigned opc, imm12, rn, rt
         insn = 0b00_111_0_01_00_0_00000000000_00000_00000
-        insn |= ((opc & 0x3) << 22)
-        insn |= ((imm12 & 0xfff) << 10)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((opc) << 22)
+        insn |= ((imm12) << 10)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end