aarch64 1.0.1 → 2.0.0

data/lib/aarch64/instructions/ldtr.rb

@@ -4,26 +4,26 @@ module AArch64
     # Load Register (unprivileged)
     # LDTR  <Wt>, [<Xn|SP>{, #<simm>}]
     # LDTR  <Xt>, [<Xn|SP>{, #<simm>}]
-    class LDTR
+    class LDTR < Instruction
       def initialize rt, rn, imm9, size
-        @rt   = rt
-        @rn   = rn
-        @imm9 = imm9
-        @size = size
+        @rt   = check_mask(rt, 0x1f)
+        @rn   = check_mask(rn, 0x1f)
+        @imm9 = check_mask(imm9, 0x1ff)
+        @size = check_mask(size, 0x03)
       end
 
       def encode
-        LDTR(@size, @imm9, @rn.to_i, @rt.to_i)
+        LDTR(@size, @imm9, @rn, @rt)
       end
 
       private
 
       def LDTR size, imm9, rn, rt
         insn = 0b00_111_0_00_01_0_000000000_10_00000_00000
-        insn |= ((size & 0x3) << 30)
-        insn |= ((imm9 & 0x1ff) << 12)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((size) << 30)
+        insn |= ((imm9) << 12)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/ldtrb.rb

@@ -3,24 +3,24 @@ module AArch64
     # LDTRB -- A64
     # Load Register Byte (unprivileged)
     # LDTRB  <Wt>, [<Xn|SP>{, #<simm>}]
-    class LDTRB
+    class LDTRB < Instruction
       def initialize rt, rn, imm9
-        @rt   = rt
-        @rn   = rn
-        @imm9 = imm9
+        @rt   = check_mask(rt, 0x1f)
+        @rn   = check_mask(rn, 0x1f)
+        @imm9 = check_mask(imm9, 0x1ff)
       end
 
       def encode
-        LDTRB(@imm9, @rn.to_i, @rt.to_i)
+        LDTRB(@imm9, @rn, @rt)
       end
 
       private
 
       def LDTRB imm9, rn, rt
         insn = 0b00_111_0_00_01_0_000000000_10_00000_00000
-        insn |= ((imm9 & 0x1ff) << 12)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((imm9) << 12)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/ldtrh.rb

@@ -3,24 +3,24 @@ module AArch64
     # LDTRH -- A64
     # Load Register Halfword (unprivileged)
     # LDTRH  <Wt>, [<Xn|SP>{, #<simm>}]
-    class LDTRH
+    class LDTRH < Instruction
       def initialize rt, rn, imm9
-        @rt   = rt
-        @rn   = rn
-        @imm9 = imm9
+        @rt   = check_mask(rt, 0x1f)
+        @rn   = check_mask(rn, 0x1f)
+        @imm9 = check_mask(imm9, 0x1ff)
       end
 
       def encode
-        LDTRH(@imm9, @rn.to_i, @rt.to_i)
+        LDTRH(@imm9, @rn, @rt)
       end
 
       private
 
       def LDTRH imm9, rn, rt
         insn = 0b01_111_0_00_01_0_000000000_10_00000_00000
-        insn |= ((imm9 & 0x1ff) << 12)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((imm9) << 12)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/ldtrsb.rb

@@ -4,26 +4,26 @@ module AArch64
     # Load Register Signed Byte (unprivileged)
     # LDTRSB  <Wt>, [<Xn|SP>{, #<simm>}]
     # LDTRSB  <Xt>, [<Xn|SP>{, #<simm>}]
-    class LDTRSB
+    class LDTRSB < Instruction
       def initialize rt, rn, imm9, opc
-        @rt   = rt
-        @rn   = rn
-        @imm9 = imm9
-        @opc  = opc
+        @rt   = check_mask(rt, 0x1f)
+        @rn   = check_mask(rn, 0x1f)
+        @imm9 = check_mask(imm9, 0x1ff)
+        @opc  = check_mask(opc, 0x03)
       end
 
       def encode
-        LDTRSB(@opc, @imm9, @rn.to_i, @rt.to_i)
+        LDTRSB(@opc, @imm9, @rn, @rt)
       end
 
       private
 
       def LDTRSB opc, imm9, rn, rt
         insn = 0b00_111_0_00_00_0_000000000_10_00000_00000
-        insn |= ((opc & 0x3) << 22)
-        insn |= ((imm9 & 0x1ff) << 12)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((opc) << 22)
+        insn |= ((imm9) << 12)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/ldtrsh.rb

@@ -4,26 +4,26 @@ module AArch64
     # Load Register Signed Halfword (unprivileged)
     # LDTRSH  <Wt>, [<Xn|SP>{, #<simm>}]
     # LDTRSH  <Xt>, [<Xn|SP>{, #<simm>}]
-    class LDTRSH
+    class LDTRSH < Instruction
       def initialize rt, rn, imm9, opc
-        @rt   = rt
-        @rn   = rn
-        @imm9 = imm9
-        @opc  = opc
+        @rt   = check_mask(rt, 0x1f)
+        @rn   = check_mask(rn, 0x1f)
+        @imm9 = check_mask(imm9, 0x1ff)
+        @opc  = check_mask(opc, 0x03)
       end
 
       def encode
-        LDTRSH(@opc, @imm9, @rn.to_i, @rt.to_i)
+        LDTRSH(@opc, @imm9, @rn, @rt)
       end
 
       private
 
       def LDTRSH opc, imm9, rn, rt
         insn = 0b01_111_0_00_00_0_000000000_10_00000_00000
-        insn |= ((opc & 0x3) << 22)
-        insn |= ((imm9 & 0x1ff) << 12)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((opc) << 22)
+        insn |= ((imm9) << 12)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/ldtrsw.rb

@@ -3,24 +3,24 @@ module AArch64
     # LDTRSW -- A64
     # Load Register Signed Word (unprivileged)
     # LDTRSW  <Xt>, [<Xn|SP>{, #<simm>}]
-    class LDTRSW
+    class LDTRSW < Instruction
       def initialize rt, rn, imm9
-        @rt   = rt
-        @rn   = rn
-        @imm9 = imm9
+        @rt   = check_mask(rt, 0x1f)
+        @rn   = check_mask(rn, 0x1f)
+        @imm9 = check_mask(imm9, 0x1ff)
       end
 
       def encode
-        LDTRSW(@imm9, @rn.to_i, @rt.to_i)
+        LDTRSW(@imm9, @rn, @rt)
       end
 
       private
 
       def LDTRSW imm9, rn, rt
         insn = 0b10_111_0_00_10_0_000000000_10_00000_00000
-        insn |= ((imm9 & 0x1ff) << 12)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((imm9) << 12)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/ldumax.rb

@@ -10,30 +10,30 @@ module AArch64
     # LDUMAXA  <Xs>, <Xt>, [<Xn|SP>]
     # LDUMAXAL  <Xs>, <Xt>, [<Xn|SP>]
     # LDUMAXL  <Xs>, <Xt>, [<Xn|SP>]
-    class LDUMAX
+    class LDUMAX < Instruction
       def initialize rs, rt, rn, size, a, r
-        @rs   = rs
-        @rt   = rt
-        @rn   = rn
-        @size = size
-        @a    = a
-        @r    = r
+        @rs   = check_mask(rs, 0x1f)
+        @rt   = check_mask(rt, 0x1f)
+        @rn   = check_mask(rn, 0x1f)
+        @size = check_mask(size, 0x03)
+        @a    = check_mask(a, 0x01)
+        @r    = check_mask(r, 0x01)
       end
 
       def encode
-        LDUMAX(@size, @a, @r.to_i, @rs.to_i, @rn.to_i, @rt.to_i)
+        LDUMAX(@size, @a, @r, @rs, @rn, @rt)
       end
 
       private
 
       def LDUMAX size, a, r, rs, rn, rt
         insn = 0b00_111_0_00_0_0_1_00000_0_110_00_00000_00000
-        insn |= ((size & 0x3) << 30)
-        insn |= ((a & 0x1) << 23)
-        insn |= ((r & 0x1) << 22)
-        insn |= ((rs & 0x1f) << 16)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((size) << 30)
+        insn |= ((a) << 23)
+        insn |= ((r) << 22)
+        insn |= ((rs) << 16)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/ldumaxb.rb

@@ -6,28 +6,28 @@ module AArch64
     # LDUMAXALB  <Ws>, <Wt>, [<Xn|SP>]
     # LDUMAXB  <Ws>, <Wt>, [<Xn|SP>]
     # LDUMAXLB  <Ws>, <Wt>, [<Xn|SP>]
-    class LDUMAXB
+    class LDUMAXB < Instruction
       def initialize rs, rt, rn, a, r
-        @rs = rs
-        @rt = rt
-        @rn = rn
-        @a  = a
-        @r  = r
+        @rs = check_mask(rs, 0x1f)
+        @rt = check_mask(rt, 0x1f)
+        @rn = check_mask(rn, 0x1f)
+        @a  = check_mask(a, 0x01)
+        @r  = check_mask(r, 0x01)
       end
 
       def encode
-        LDUMAXB(@a, @r.to_i, @rs.to_i, @rn.to_i, @rt.to_i)
+        LDUMAXB(@a, @r, @rs, @rn, @rt)
       end
 
       private
 
       def LDUMAXB a, r, rs, rn, rt
         insn = 0b00_111_0_00_0_0_1_00000_0_110_00_00000_00000
-        insn |= ((a & 0x1) << 23)
-        insn |= ((r & 0x1) << 22)
-        insn |= ((rs & 0x1f) << 16)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((a) << 23)
+        insn |= ((r) << 22)
+        insn |= ((rs) << 16)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/ldumaxh.rb

@@ -6,28 +6,28 @@ module AArch64
     # LDUMAXALH  <Ws>, <Wt>, [<Xn|SP>]
     # LDUMAXH  <Ws>, <Wt>, [<Xn|SP>]
     # LDUMAXLH  <Ws>, <Wt>, [<Xn|SP>]
-    class LDUMAXH
+    class LDUMAXH < Instruction
       def initialize rs, rt, rn, a, r
-        @rs = rs
-        @rt = rt
-        @rn = rn
-        @a  = a
-        @r  = r
+        @rs = check_mask(rs, 0x1f)
+        @rt = check_mask(rt, 0x1f)
+        @rn = check_mask(rn, 0x1f)
+        @a  = check_mask(a, 0x01)
+        @r  = check_mask(r, 0x01)
       end
 
       def encode
-        LDUMAXH(@a, @r.to_i, @rs.to_i, @rn.to_i, @rt.to_i)
+        LDUMAXH(@a, @r, @rs, @rn, @rt)
       end
 
       private
 
       def LDUMAXH a, r, rs, rn, rt
         insn = 0b01_111_0_00_0_0_1_00000_0_110_00_00000_00000
-        insn |= ((a & 0x1) << 23)
-        insn |= ((r & 0x1) << 22)
-        insn |= ((rs & 0x1f) << 16)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((a) << 23)
+        insn |= ((r) << 22)
+        insn |= ((rs) << 16)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/ldumin.rb

@@ -10,30 +10,30 @@ module AArch64
     # LDUMINA  <Xs>, <Xt>, [<Xn|SP>]
     # LDUMINAL  <Xs>, <Xt>, [<Xn|SP>]
     # LDUMINL  <Xs>, <Xt>, [<Xn|SP>]
-    class LDUMIN
+    class LDUMIN < Instruction
       def initialize rs, rt, rn, size, a, r
-        @rs   = rs
-        @rt   = rt
-        @rn   = rn
-        @size = size
-        @a    = a
-        @r    = r
+        @rs   = check_mask(rs, 0x1f)
+        @rt   = check_mask(rt, 0x1f)
+        @rn   = check_mask(rn, 0x1f)
+        @size = check_mask(size, 0x03)
+        @a    = check_mask(a, 0x01)
+        @r    = check_mask(r, 0x01)
       end
 
       def encode
-        LDUMIN(@size, @a, @r.to_i, @rs.to_i, @rn.to_i, @rt.to_i)
+        LDUMIN(@size, @a, @r, @rs, @rn, @rt)
       end
 
       private
 
       def LDUMIN size, a, r, rs, rn, rt
         insn = 0b00_111_0_00_0_0_1_00000_0_111_00_00000_00000
-        insn |= ((size & 0x3) << 30)
-        insn |= ((a & 0x1) << 23)
-        insn |= ((r & 0x1) << 22)
-        insn |= ((rs & 0x1f) << 16)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((size) << 30)
+        insn |= ((a) << 23)
+        insn |= ((r) << 22)
+        insn |= ((rs) << 16)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/lduminb.rb

@@ -6,28 +6,28 @@ module AArch64
     # LDUMINALB  <Ws>, <Wt>, [<Xn|SP>]
     # LDUMINB  <Ws>, <Wt>, [<Xn|SP>]
     # LDUMINLB  <Ws>, <Wt>, [<Xn|SP>]
-    class LDUMINB
+    class LDUMINB < Instruction
       def initialize rs, rt, rn, a, r
-        @rs = rs
-        @rt = rt
-        @rn = rn
-        @a  = a
-        @r  = r
+        @rs = check_mask(rs, 0x1f)
+        @rt = check_mask(rt, 0x1f)
+        @rn = check_mask(rn, 0x1f)
+        @a  = check_mask(a, 0x01)
+        @r  = check_mask(r, 0x01)
       end
 
       def encode
-        LDUMINB(@a, @r.to_i, @rs.to_i, @rn.to_i, @rt.to_i)
+        LDUMINB(@a, @r, @rs, @rn, @rt)
       end
 
       private
 
       def LDUMINB a, r, rs, rn, rt
         insn = 0b00_111_0_00_0_0_1_00000_0_111_00_00000_00000
-        insn |= ((a & 0x1) << 23)
-        insn |= ((r & 0x1) << 22)
-        insn |= ((rs & 0x1f) << 16)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((a) << 23)
+        insn |= ((r) << 22)
+        insn |= ((rs) << 16)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/lduminh.rb

@@ -6,28 +6,28 @@ module AArch64
     # LDUMINALH  <Ws>, <Wt>, [<Xn|SP>]
     # LDUMINH  <Ws>, <Wt>, [<Xn|SP>]
     # LDUMINLH  <Ws>, <Wt>, [<Xn|SP>]
-    class LDUMINH
+    class LDUMINH < Instruction
       def initialize rs, rt, rn, a, r
-        @rs = rs
-        @rt = rt
-        @rn = rn
-        @a  = a
-        @r  = r
+        @rs = check_mask(rs, 0x1f)
+        @rt = check_mask(rt, 0x1f)
+        @rn = check_mask(rn, 0x1f)
+        @a  = check_mask(a, 0x01)
+        @r  = check_mask(r, 0x01)
       end
 
       def encode
-        LDUMINH(@a, @r.to_i, @rs.to_i, @rn.to_i, @rt.to_i)
+        LDUMINH(@a, @r, @rs, @rn, @rt)
       end
 
       private
 
       def LDUMINH a, r, rs, rn, rt
         insn = 0b01_111_0_00_0_0_1_00000_0_111_00_00000_00000
-        insn |= ((a & 0x1) << 23)
-        insn |= ((r & 0x1) << 22)
-        insn |= ((rs & 0x1f) << 16)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((a) << 23)
+        insn |= ((r) << 22)
+        insn |= ((rs) << 16)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/ldur_gen.rb

@@ -4,26 +4,26 @@ module AArch64
     # Load Register (unscaled)
     # LDUR  <Wt>, [<Xn|SP>{, #<simm>}]
     # LDUR  <Xt>, [<Xn|SP>{, #<simm>}]
-    class LDUR_gen
+    class LDUR_gen < Instruction
       def initialize rt, rn, imm9, size
-        @rt   = rt
-        @rn   = rn
-        @imm9 = imm9
-        @size = size
+        @rt   = check_mask(rt, 0x1f)
+        @rn   = check_mask(rn, 0x1f)
+        @imm9 = check_mask(imm9, 0x1ff)
+        @size = check_mask(size, 0x03)
       end
 
       def encode
-        LDUR_gen(@size, @imm9, @rn.to_i, @rt.to_i)
+        LDUR_gen(@size, @imm9, @rn, @rt)
       end
 
       private
 
       def LDUR_gen size, imm9, rn, rt
         insn = 0b00_111_0_00_01_0_000000000_00_00000_00000
-        insn |= ((size & 0x3) << 30)
-        insn |= ((imm9 & 0x1ff) << 12)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((size) << 30)
+        insn |= ((imm9) << 12)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/ldursb.rb

@@ -4,26 +4,26 @@ module AArch64
     # Load Register Signed Byte (unscaled)
     # LDURSB  <Wt>, [<Xn|SP>{, #<simm>}]
     # LDURSB  <Xt>, [<Xn|SP>{, #<simm>}]
-    class LDURSB
+    class LDURSB < Instruction
       def initialize rt, rn, imm9, opc
-        @rt   = rt
-        @rn   = rn
-        @imm9 = imm9
-        @opc  = opc
+        @rt   = check_mask(rt, 0x1f)
+        @rn   = check_mask(rn, 0x1f)
+        @imm9 = check_mask(imm9, 0x1ff)
+        @opc  = check_mask(opc, 0x03)
       end
 
       def encode
-        LDURSB(@opc, @imm9, @rn.to_i, @rt.to_i)
+        LDURSB(@opc, @imm9, @rn, @rt)
       end
 
       private
 
       def LDURSB opc, imm9, rn, rt
         insn = 0b00_111_0_00_00_0_000000000_00_00000_00000
-        insn |= ((opc & 0x3) << 22)
-        insn |= ((imm9 & 0x1ff) << 12)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((opc) << 22)
+        insn |= ((imm9) << 12)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/ldursh.rb

@@ -4,26 +4,26 @@ module AArch64
     # Load Register Signed Halfword (unscaled)
     # LDURSH  <Wt>, [<Xn|SP>{, #<simm>}]
     # LDURSH  <Xt>, [<Xn|SP>{, #<simm>}]
-    class LDURSH
+    class LDURSH < Instruction
       def initialize rt, rn, imm9, opc
-        @rt   = rt
-        @rn   = rn
-        @imm9 = imm9
-        @opc  = opc
+        @rt   = check_mask(rt, 0x1f)
+        @rn   = check_mask(rn, 0x1f)
+        @imm9 = check_mask(imm9, 0x1ff)
+        @opc  = check_mask(opc, 0x03)
       end
 
       def encode
-        LDURSH(@opc, @imm9, @rn.to_i, @rt.to_i)
+        LDURSH(@opc, @imm9, @rn, @rt)
       end
 
       private
 
       def LDURSH opc, imm9, rn, rt
         insn = 0b01_111_0_00_00_0_000000000_00_00000_00000
-        insn |= ((opc & 0x3) << 22)
-        insn |= ((imm9 & 0x1ff) << 12)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((opc) << 22)
+        insn |= ((imm9) << 12)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/ldursw.rb

@@ -3,24 +3,24 @@ module AArch64
     # LDURSW -- A64
     # Load Register Signed Word (unscaled)
     # LDURSW  <Xt>, [<Xn|SP>{, #<simm>}]
-    class LDURSW
+    class LDURSW < Instruction
       def initialize rt, rn, imm9
-        @rt   = rt
-        @rn   = rn
-        @imm9 = imm9
+        @rt   = check_mask(rt, 0x1f)
+        @rn   = check_mask(rn, 0x1f)
+        @imm9 = check_mask(imm9, 0x1ff)
       end
 
       def encode
-        LDURSW(@imm9, @rn.to_i, @rt.to_i)
+        LDURSW(@imm9, @rn, @rt)
       end
 
       private
 
       def LDURSW imm9, rn, rt
         insn = 0b10_111_0_00_10_0_000000000_00_00000_00000
-        insn |= ((imm9 & 0x1ff) << 12)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((imm9) << 12)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/ldxp.rb

@@ -4,26 +4,26 @@ module AArch64
     # Load Exclusive Pair of Registers
     # LDXP  <Wt1>, <Wt2>, [<Xn|SP>{,#0}]
     # LDXP  <Xt1>, <Xt2>, [<Xn|SP>{,#0}]
-    class LDXP
+    class LDXP < Instruction
       def initialize rt, rt2, rn, sz
-        @rt  = rt
-        @rt2 = rt2
-        @rn  = rn
-        @sz  = sz
+        @rt  = check_mask(rt, 0x1f)
+        @rt2 = check_mask(rt2, 0x1f)
+        @rn  = check_mask(rn, 0x1f)
+        @sz  = check_mask(sz, 0x01)
       end
 
       def encode
-        LDXP(@sz, @rt2.to_i, @rn.to_i, @rt.to_i)
+        LDXP(@sz, @rt2, @rn, @rt)
       end
 
       private
 
       def LDXP sz, rt2, rn, rt
         insn = 0b1_0_001000_0_1_1_11111_0_00000_00000_00000
-        insn |= ((sz & 0x1) << 30)
-        insn |= ((rt2 & 0x1f) << 10)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((sz) << 30)
+        insn |= ((rt2) << 10)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end