aarch64 1.0.1 → 2.0.0

data/lib/aarch64/instructions/stlxr.rb

@@ -4,26 +4,26 @@ module AArch64
     # Store-Release Exclusive Register
     # STLXR  <Ws>, <Wt>, [<Xn|SP>{,#0}]
     # STLXR  <Ws>, <Xt>, [<Xn|SP>{,#0}]
-    class STLXR
+    class STLXR < Instruction
       def initialize rs, rt, rn, size
-        @rs   = rs
-        @rt   = rt
-        @rn   = rn
-        @size = size
+        @rs   = check_mask(rs, 0x1f)
+        @rt   = check_mask(rt, 0x1f)
+        @rn   = check_mask(rn, 0x1f)
+        @size = check_mask(size, 0x03)
       end
 
       def encode
-        STLXR(@size, @rs.to_i, @rn.to_i, @rt.to_i)
+        STLXR(@size, @rs, @rn, @rt)
       end
 
       private
 
       def STLXR size, rs, rn, rt
         insn = 0b00_001000_0_0_0_00000_1_11111_00000_00000
-        insn |= ((size & 0x3) << 30)
-        insn |= ((rs & 0x1f) << 16)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((size) << 30)
+        insn |= ((rs) << 16)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/stlxrb.rb

@@ -3,24 +3,24 @@ module AArch64
     # STLXRB -- A64
     # Store-Release Exclusive Register Byte
     # STLXRB  <Ws>, <Wt>, [<Xn|SP>{,#0}]
-    class STLXRB
+    class STLXRB < Instruction
       def initialize rs, rt, rn
-        @rs = rs
-        @rt = rt
-        @rn = rn
+        @rs = check_mask(rs, 0x1f)
+        @rt = check_mask(rt, 0x1f)
+        @rn = check_mask(rn, 0x1f)
       end
 
       def encode
-        STLXRB(@rs.to_i, @rn.to_i, @rt.to_i)
+        STLXRB(@rs, @rn, @rt)
       end
 
       private
 
       def STLXRB rs, rn, rt
         insn = 0b00_001000_0_0_0_00000_1_11111_00000_00000
-        insn |= ((rs & 0x1f) << 16)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((rs) << 16)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/stlxrh.rb

@@ -3,24 +3,24 @@ module AArch64
     # STLXRH -- A64
     # Store-Release Exclusive Register Halfword
     # STLXRH  <Ws>, <Wt>, [<Xn|SP>{,#0}]
-    class STLXRH
+    class STLXRH < Instruction
       def initialize rs, rt, rn
-        @rs = rs
-        @rt = rt
-        @rn = rn
+        @rs = check_mask(rs, 0x1f)
+        @rt = check_mask(rt, 0x1f)
+        @rn = check_mask(rn, 0x1f)
       end
 
       def encode
-        STLXRH(@rs.to_i, @rn.to_i, @rt.to_i)
+        STLXRH(@rs, @rn, @rt)
       end
 
       private
 
       def STLXRH rs, rn, rt
         insn = 0b01_001000_0_0_0_00000_1_11111_00000_00000
-        insn |= ((rs & 0x1f) << 16)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((rs) << 16)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/stnp_gen.rb

@@ -4,28 +4,28 @@ module AArch64
     # Store Pair of Registers, with non-temporal hint
     # STNP  <Wt1>, <Wt2>, [<Xn|SP>{, #<imm>}]
     # STNP  <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]
-    class STNP_gen
+    class STNP_gen < Instruction
       def initialize rt, rt2, rn, imm7, opc
-        @rt   = rt
-        @rt2  = rt2
-        @rn   = rn
-        @imm7 = imm7
-        @opc  = opc
+        @rt   = check_mask(rt, 0x1f)
+        @rt2  = check_mask(rt2, 0x1f)
+        @rn   = check_mask(rn, 0x1f)
+        @imm7 = check_mask(imm7, 0x7f)
+        @opc  = check_mask(opc, 0x03)
       end
 
       def encode
-        STNP_gen(@opc, @imm7, @rt2.to_i, @rn.to_i, @rt.to_i)
+        STNP_gen(@opc, @imm7, @rt2, @rn, @rt)
       end
 
       private
 
       def STNP_gen opc, imm7, rt2, rn, rt
         insn = 0b00_101_0_000_0_0000000_00000_00000_00000
-        insn |= ((opc & 0x3) << 30)
-        insn |= ((imm7 & 0x7f) << 15)
-        insn |= ((rt2 & 0x1f) << 10)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((opc) << 30)
+        insn |= ((imm7) << 15)
+        insn |= ((rt2) << 10)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/stp_gen.rb

@@ -8,30 +8,30 @@ module AArch64
     # STP  <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]!
     # STP  <Wt1>, <Wt2>, [<Xn|SP>{, #<imm>}]
     # STP  <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]
-    class STP_gen
+    class STP_gen < Instruction
       def initialize rt, rt2, rn, imm7, opc, option
-        @rt     = rt
-        @rt2    = rt2
-        @rn     = rn
-        @imm7   = imm7
-        @opc    = opc
-        @option = option
+        @rt     = check_mask(rt, 0x1f)
+        @rt2    = check_mask(rt2, 0x1f)
+        @rn     = check_mask(rn, 0x1f)
+        @imm7   = check_mask(imm7, 0x7f)
+        @opc    = check_mask(opc, 0x03)
+        @option = check_mask(option, 0x07)
       end
 
       def encode
-        STP_gen(@opc, @option, @imm7, @rt2.to_i, @rn.to_i, @rt.to_i)
+        STP_gen(@opc, @option, @imm7, @rt2, @rn, @rt)
       end
 
       private
 
       def STP_gen opc, option, imm7, rt2, rn, rt
         insn = 0b00_101_0_000_0_0000000_00000_00000_00000
-        insn |= ((opc & 0x3) << 30)
-        insn |= ((option & 0x7) << 23)
-        insn |= ((imm7 & 0x7f) << 15)
-        insn |= ((rt2 & 0x1f) << 10)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((opc) << 30)
+        insn |= ((option) << 23)
+        insn |= ((imm7) << 15)
+        insn |= ((rt2) << 10)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/str_imm_gen.rb

@@ -8,28 +8,28 @@ module AArch64
     # STR  <Xt>, [<Xn|SP>, #<simm>]!
     # STR  <Wt>, [<Xn|SP>{, #<pimm>}]
     # STR  <Xt>, [<Xn|SP>{, #<pimm>}]
-    class STR_imm_gen
+    class STR_imm_gen < Instruction
       def initialize rt, rn, imm9, opt, size
-        @rt   = rt
-        @rn   = rn
-        @imm9 = imm9
-        @opt  = opt
-        @size = size
+        @rt   = check_mask(rt, 0x1f)
+        @rn   = check_mask(rn, 0x1f)
+        @imm9 = check_mask(imm9, 0x1ff)
+        @opt  = check_mask(opt, 0x03)
+        @size = check_mask(size, 0x03)
       end
 
       def encode
-        STR_imm_gen(@size, @imm9, @opt, @rn.to_i, @rt.to_i)
+        STR_imm_gen(@size, @imm9, @opt, @rn, @rt)
       end
 
       private
 
       def STR_imm_gen size, imm9, opt, rn, rt
         insn = 0b00_111_0_00_00_0_000000000_00_00000_00000
-        insn |= ((size & 0x3) << 30)
-        insn |= ((imm9 & 0x1ff) << 12)
-        insn |= ((opt & 0x3) << 10)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((size) << 30)
+        insn |= ((imm9) << 12)
+        insn |= ((opt) << 10)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/str_imm_unsigned.rb

@@ -4,26 +4,26 @@ module AArch64
     # Store Register (immediate)
     # STR  <Wt>, [<Xn|SP>{, #<pimm>}]
     # STR  <Xt>, [<Xn|SP>{, #<pimm>}]
-    class STR_imm_unsigned
+    class STR_imm_unsigned < Instruction
       def initialize rt, rn, imm12, size
-        @rt    = rt
-        @rn    = rn
-        @imm12 = imm12
-        @size  = size
+        @rt    = check_mask(rt, 0x1f)
+        @rn    = check_mask(rn, 0x1f)
+        @imm12 = check_mask(imm12, 0xfff)
+        @size  = check_mask(size, 0x03)
       end
 
       def encode
-        STR_imm_gen(@size, @imm12, @rn.to_i, @rt.to_i)
+        STR_imm_gen(@size, @imm12, @rn, @rt)
       end
 
       private
 
       def STR_imm_gen size, imm12, rn, rt
         insn = 0b00_111_0_01_00_0_000000000_00_00000_00000
-        insn |= ((size & 0x3) << 30)
-        insn |= ((imm12 & 0xfff) << 10)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((size) << 30)
+        insn |= ((imm12) << 10)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/str_reg_gen.rb

@@ -4,30 +4,30 @@ module AArch64
     # Store Register (register)
     # STR  <Wt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
     # STR  <Xt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
-    class STR_reg_gen
+    class STR_reg_gen < Instruction
       def initialize rt, rn, rm, option, s, size
-        @rt     = rt
-        @rn     = rn
-        @rm     = rm
-        @option = option
-        @s      = s
-        @size   = size
+        @rt     = check_mask(rt, 0x1f)
+        @rn     = check_mask(rn, 0x1f)
+        @rm     = check_mask(rm, 0x1f)
+        @option = check_mask(option, 0x07)
+        @s      = check_mask(s, 0x01)
+        @size   = check_mask(size, 0x03)
       end
 
       def encode
-        STR_reg_gen(@size, @rm.to_i, @option, @s, @rn.to_i, @rt.to_i)
+        STR_reg_gen(@size, @rm, @option, @s, @rn, @rt)
       end
 
       private
 
       def STR_reg_gen size, rm, option, s, rn, rt
         insn = 0b00_111_0_00_00_1_00000_000_0_10_00000_00000
-        insn |= ((size & 0x3) << 30)
-        insn |= ((rm & 0x1f) << 16)
-        insn |= ((option & 0x7) << 13)
-        insn |= ((s & 0x1) << 12)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((size) << 30)
+        insn |= ((rm) << 16)
+        insn |= ((option) << 13)
+        insn |= ((s) << 12)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/strb_imm.rb

@@ -5,26 +5,26 @@ module AArch64
     # STRB  <Wt>, [<Xn|SP>], #<simm>
     # STRB  <Wt>, [<Xn|SP>, #<simm>]!
     # STRB  <Wt>, [<Xn|SP>{, #<pimm>}]
-    class STRB_imm
+    class STRB_imm < Instruction
       def initialize rt, rn, imm9, opt
-        @rt   = rt
-        @rn   = rn
-        @imm9 = imm9
-        @opt  = opt
+        @rt   = check_mask(rt, 0x1f)
+        @rn   = check_mask(rn, 0x1f)
+        @imm9 = check_mask(imm9, 0x1ff)
+        @opt  = check_mask(opt, 0x03)
       end
 
       def encode
-        STRB_imm(@imm9, @opt, @rn.to_i, @rt.to_i)
+        STRB_imm(@imm9, @opt, @rn, @rt)
       end
 
       private
 
       def STRB_imm imm9, opt, rn, rt
         insn = 0b00_111_0_00_00_0_000000000_00_00000_00000
-        insn |= ((imm9 & 0x1ff) << 12)
-        insn |= ((opt & 0x3) << 10)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((imm9) << 12)
+        insn |= ((opt) << 10)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/strb_imm_unsigned.rb

@@ -3,24 +3,24 @@ module AArch64
     # STRB (immediate) -- A64
     # Store Register Byte (immediate)
     # STRB  <Wt>, [<Xn|SP>{, #<pimm>}]
-    class STRB_imm_unsigned
+    class STRB_imm_unsigned < Instruction
       def initialize rt, rn, imm12
-        @rt    = rt
-        @rn    = rn
-        @imm12 = imm12
+        @rt    = check_mask(rt, 0x1f)
+        @rn    = check_mask(rn, 0x1f)
+        @imm12 = check_mask(imm12, 0xfff)
       end
 
       def encode
-        STRB_imm_unsigned(@imm12, @rn.to_i, @rt.to_i)
+        STRB_imm_unsigned(@imm12, @rn, @rt)
       end
 
       private
 
       def STRB_imm_unsigned imm12, rn, rt
         insn = 0b00_111_0_01_00_0_000000000_00_00000_00000
-        insn |= ((imm12 & 0xfff) << 10)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((imm12) << 10)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/strb_reg.rb

@@ -4,28 +4,28 @@ module AArch64
     # Store Register Byte (register)
     # STRB  <Wt>, [<Xn|SP>, (<Wm>|<Xm>), <extend> {<amount>}]
     # STRB  <Wt>, [<Xn|SP>, <Xm>{, LSL <amount>}]
-    class STRB_reg
+    class STRB_reg < Instruction
       def initialize rt, rn, rm, option, s
-        @rt     = rt
-        @rn     = rn
-        @rm     = rm
-        @option = option
-        @s      = s
+        @rt     = check_mask(rt, 0x1f)
+        @rn     = check_mask(rn, 0x1f)
+        @rm     = check_mask(rm, 0x1f)
+        @option = check_mask(option, 0x07)
+        @s      = check_mask(s, 0x01)
       end
 
       def encode
-        STRB_reg(@rm.to_i, @option, @s, @rn.to_i, @rt.to_i)
+        STRB_reg(@rm, @option, @s, @rn, @rt)
       end
 
       private
 
       def STRB_reg rm, option, s, rn, rt
         insn = 0b00_111_0_00_00_1_00000_000_0_10_00000_00000
-        insn |= ((rm & 0x1f) << 16)
-        insn |= ((option & 0x7) << 13)
-        insn |= ((s & 0x1) << 12)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((rm) << 16)
+        insn |= ((option) << 13)
+        insn |= ((s) << 12)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/strh_imm.rb

@@ -5,26 +5,26 @@ module AArch64
     # STRH  <Wt>, [<Xn|SP>], #<simm>
     # STRH  <Wt>, [<Xn|SP>, #<simm>]!
     # STRH  <Wt>, [<Xn|SP>{, #<pimm>}]
-    class STRH_imm
+    class STRH_imm < Instruction
       def initialize rt, rn, imm9, opt
-        @rt   = rt
-        @rn   = rn
-        @imm9 = imm9
-        @opt  = opt
+        @rt   = check_mask(rt, 0x1f)
+        @rn   = check_mask(rn, 0x1f)
+        @imm9 = check_mask(imm9, 0x1ff)
+        @opt  = check_mask(opt, 0x03)
       end
 
       def encode
-        STRH_imm(@imm9, @opt, @rn.to_i, @rt.to_i)
+        STRH_imm(@imm9, @opt, @rn, @rt)
       end
 
       private
 
       def STRH_imm imm9, opt, rn, rt
         insn = 0b01_111_0_00_00_0_000000000_00_00000_00000
-        insn |= ((imm9 & 0x1ff) << 12)
-        insn |= ((opt & 0x3) << 10)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((imm9) << 12)
+        insn |= ((opt) << 10)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/strh_imm_unsigned.rb

@@ -3,24 +3,24 @@ module AArch64
     # STRH (immediate) -- A64
     # Store Register Halfword (immediate)
     # STRH  <Wt>, [<Xn|SP>{, #<pimm>}]
-    class STRH_imm_unsigned
+    class STRH_imm_unsigned < Instruction
       def initialize rt, rn, imm12
-        @rt    = rt
-        @rn    = rn
-        @imm12 = imm12
+        @rt    = check_mask(rt, 0x1f)
+        @rn    = check_mask(rn, 0x1f)
+        @imm12 = check_mask(imm12, 0xfff)
       end
 
       def encode
-        STRH_imm_unsigned(@imm12, @rn.to_i, @rt.to_i)
+        STRH_imm_unsigned(@imm12, @rn, @rt)
       end
 
       private
 
       def STRH_imm_unsigned imm12, rn, rt
         insn = 0b01_111_0_01_00_0_000000000_00_00000_00000
-        insn |= ((imm12 & 0xfff) << 10)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((imm12) << 10)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/strh_reg.rb

@@ -3,28 +3,28 @@ module AArch64
     # STRH (register) -- A64
     # Store Register Halfword (register)
     # STRH  <Wt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
-    class STRH_reg
+    class STRH_reg < Instruction
       def initialize rt, rn, rm, option, s
-        @rt     = rt
-        @rn     = rn
-        @rm     = rm
-        @option = option
-        @s      = s
+        @rt     = check_mask(rt, 0x1f)
+        @rn     = check_mask(rn, 0x1f)
+        @rm     = check_mask(rm, 0x1f)
+        @option = check_mask(option, 0x07)
+        @s      = check_mask(s, 0x01)
       end
 
       def encode
-        STRH_reg(@rm.to_i, @option, @s, @rn.to_i, @rt.to_i)
+        STRH_reg(@rm, @option, @s, @rn, @rt)
       end
 
       private
 
       def STRH_reg rm, option, s, rn, rt
         insn = 0b01_111_0_00_00_1_00000_000_0_10_00000_00000
-        insn |= ((rm & 0x1f) << 16)
-        insn |= ((option & 0x7) << 13)
-        insn |= ((s & 0x1) << 12)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((rm) << 16)
+        insn |= ((option) << 13)
+        insn |= ((s) << 12)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/sttr.rb

@@ -4,26 +4,26 @@ module AArch64
     # Store Register (unprivileged)
     # STTR  <Wt>, [<Xn|SP>{, #<simm>}]
     # STTR  <Xt>, [<Xn|SP>{, #<simm>}]
-    class STTR
+    class STTR < Instruction
       def initialize rt, rn, imm9, size
-        @rt   = rt
-        @rn   = rn
-        @imm9 = imm9
-        @size = size
+        @rt   = check_mask(rt, 0x1f)
+        @rn   = check_mask(rn, 0x1f)
+        @imm9 = check_mask(imm9, 0x1ff)
+        @size = check_mask(size, 0x03)
       end
 
       def encode
-        STTR(@size, @imm9, @rn.to_i, @rt.to_i)
+        STTR(@size, @imm9, @rn, @rt)
       end
 
       private
 
       def STTR size, imm9, rn, rt
         insn = 0b00_111_0_00_00_0_000000000_10_00000_00000
-        insn |= ((size & 0x3) << 30)
-        insn |= ((imm9 & 0x1ff) << 12)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((size) << 30)
+        insn |= ((imm9) << 12)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/stur_gen.rb

@@ -4,26 +4,26 @@ module AArch64
     # Store Register (unscaled)
     # STUR  <Wt>, [<Xn|SP>{, #<simm>}]
     # STUR  <Xt>, [<Xn|SP>{, #<simm>}]
-    class STUR_gen
+    class STUR_gen < Instruction
       def initialize rt, rn, imm9, size
-        @rt   = rt
-        @rn   = rn
-        @imm9 = imm9
-        @size = size
+        @rt   = check_mask(rt, 0x1f)
+        @rn   = check_mask(rn, 0x1f)
+        @imm9 = check_mask(imm9, 0x1ff)
+        @size = check_mask(size, 0x03)
       end
 
       def encode
-        STUR_gen(@size, @imm9, @rn.to_i, @rt.to_i)
+        STUR_gen(@size, @imm9, @rn, @rt)
       end
 
       private
 
       def STUR_gen size, imm9, rn, rt
         insn = 0b00_111_0_00_00_0_000000000_00_00000_00000
-        insn |= ((size & 0x3) << 30)
-        insn |= ((imm9 & 0x1ff) << 12)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((size) << 30)
+        insn |= ((imm9) << 12)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/stxp.rb

@@ -4,28 +4,28 @@ module AArch64
     # Store Exclusive Pair of registers
     # STXP  <Ws>, <Wt1>, <Wt2>, [<Xn|SP>{,#0}]
     # STXP  <Ws>, <Xt1>, <Xt2>, [<Xn|SP>{,#0}]
-    class STXP
+    class STXP < Instruction
       def initialize rs, rt1, rt2, rn, sf
-        @rs  = rs
-        @rt1 = rt1
-        @rt2 = rt2
-        @rn  = rn
-        @sf  = sf
+        @rs  = check_mask(rs, 0x1f)
+        @rt1 = check_mask(rt1, 0x1f)
+        @rt2 = check_mask(rt2, 0x1f)
+        @rn  = check_mask(rn, 0x1f)
+        @sf  = check_mask(sf, 0x01)
       end
 
       def encode
-        STXP(@sf, @rs.to_i, @rt2.to_i, @rn.to_i, @rt1.to_i)
+        STXP(@sf, @rs, @rt2, @rn, @rt1)
       end
 
       private
 
       def STXP sz, rs, rt2, rn, rt
         insn = 0b1_0_001000_0_0_1_00000_0_00000_00000_00000
-        insn |= ((sz & 0x1) << 30)
-        insn |= ((rs & 0x1f) << 16)
-        insn |= ((rt2 & 0x1f) << 10)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((sz) << 30)
+        insn |= ((rs) << 16)
+        insn |= ((rt2) << 10)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end