aarch64 1.0.1 → 2.0.0
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- checksums.yaml +4 -4
- data/README.md +1 -1
- data/Rakefile +37 -0
- data/aarch64.gemspec +1 -0
- data/lib/aarch64/instructions/adc.rb +10 -10
- data/lib/aarch64/instructions/adcs.rb +10 -10
- data/lib/aarch64/instructions/add_addsub_ext.rb +14 -14
- data/lib/aarch64/instructions/add_addsub_imm.rb +12 -12
- data/lib/aarch64/instructions/add_addsub_shift.rb +14 -14
- data/lib/aarch64/instructions/addg.rb +10 -10
- data/lib/aarch64/instructions/adds_addsub_ext.rb +14 -14
- data/lib/aarch64/instructions/adds_addsub_imm.rb +12 -12
- data/lib/aarch64/instructions/adds_addsub_shift.rb +14 -14
- data/lib/aarch64/instructions/adr.rb +7 -7
- data/lib/aarch64/instructions/adrp.rb +7 -7
- data/lib/aarch64/instructions/and_log_imm.rb +14 -14
- data/lib/aarch64/instructions/and_log_shift.rb +14 -14
- data/lib/aarch64/instructions/ands_log_imm.rb +14 -14
- data/lib/aarch64/instructions/ands_log_shift.rb +14 -14
- data/lib/aarch64/instructions/asrv.rb +10 -10
- data/lib/aarch64/instructions/autda.rb +9 -12
- data/lib/aarch64/instructions/autdb.rb +9 -12
- data/lib/aarch64/instructions/autia.rb +9 -12
- data/lib/aarch64/instructions/autib.rb +9 -12
- data/lib/aarch64/instructions/axflag.rb +1 -1
- data/lib/aarch64/instructions/b_cond.rb +5 -5
- data/lib/aarch64/instructions/b_uncond.rb +3 -3
- data/lib/aarch64/instructions/bc_cond.rb +5 -5
- data/lib/aarch64/instructions/bfm.rb +13 -13
- data/lib/aarch64/instructions/bic_log_shift.rb +14 -14
- data/lib/aarch64/instructions/bics.rb +14 -14
- data/lib/aarch64/instructions/bl.rb +3 -3
- data/lib/aarch64/instructions/blr.rb +4 -4
- data/lib/aarch64/instructions/blra.rb +10 -10
- data/lib/aarch64/instructions/br.rb +4 -4
- data/lib/aarch64/instructions/bra.rb +10 -10
- data/lib/aarch64/instructions/brk.rb +3 -3
- data/lib/aarch64/instructions/bti.rb +3 -3
- data/lib/aarch64/instructions/cas.rb +14 -14
- data/lib/aarch64/instructions/casb.rb +12 -12
- data/lib/aarch64/instructions/cash.rb +12 -12
- data/lib/aarch64/instructions/casp.rb +14 -14
- data/lib/aarch64/instructions/cbnz.rb +7 -7
- data/lib/aarch64/instructions/cbz.rb +7 -7
- data/lib/aarch64/instructions/ccmn_imm.rb +12 -12
- data/lib/aarch64/instructions/ccmn_reg.rb +12 -12
- data/lib/aarch64/instructions/ccmp_imm.rb +12 -12
- data/lib/aarch64/instructions/ccmp_reg.rb +12 -12
- data/lib/aarch64/instructions/cfinv.rb +2 -9
- data/lib/aarch64/instructions/clrex.rb +3 -3
- data/lib/aarch64/instructions/cls_int.rb +8 -8
- data/lib/aarch64/instructions/clz_int.rb +8 -8
- data/lib/aarch64/instructions/crc32.rb +12 -12
- data/lib/aarch64/instructions/crc32c.rb +12 -12
- data/lib/aarch64/instructions/csdb.rb +1 -1
- data/lib/aarch64/instructions/csel.rb +12 -12
- data/lib/aarch64/instructions/csinc.rb +12 -12
- data/lib/aarch64/instructions/csinv.rb +12 -12
- data/lib/aarch64/instructions/csneg.rb +12 -12
- data/lib/aarch64/instructions/dcps.rb +5 -5
- data/lib/aarch64/instructions/dgh.rb +1 -1
- data/lib/aarch64/instructions/dmb.rb +3 -3
- data/lib/aarch64/instructions/drps.rb +2 -9
- data/lib/aarch64/instructions/dsb.rb +3 -3
- data/lib/aarch64/instructions/eon.rb +14 -14
- data/lib/aarch64/instructions/eor_log_imm.rb +14 -14
- data/lib/aarch64/instructions/eor_log_shift.rb +14 -14
- data/lib/aarch64/instructions/eret.rb +2 -9
- data/lib/aarch64/instructions/ereta.rb +3 -3
- data/lib/aarch64/instructions/esb.rb +1 -1
- data/lib/aarch64/instructions/extr.rb +13 -13
- data/lib/aarch64/instructions/gmi.rb +8 -8
- data/lib/aarch64/instructions/hint.rb +5 -5
- data/lib/aarch64/instructions/hlt.rb +3 -3
- data/lib/aarch64/instructions/hvc.rb +3 -3
- data/lib/aarch64/instructions/irg.rb +8 -8
- data/lib/aarch64/instructions/isb.rb +3 -3
- data/lib/aarch64/instructions/ld64b.rb +6 -6
- data/lib/aarch64/instructions/ldadd.rb +14 -14
- data/lib/aarch64/instructions/ldaddb.rb +12 -12
- data/lib/aarch64/instructions/ldaddh.rb +12 -12
- data/lib/aarch64/instructions/ldapr.rb +8 -8
- data/lib/aarch64/instructions/ldaprb.rb +6 -6
- data/lib/aarch64/instructions/ldaprh.rb +6 -6
- data/lib/aarch64/instructions/ldapur_gen.rb +12 -12
- data/lib/aarch64/instructions/ldar.rb +8 -8
- data/lib/aarch64/instructions/ldaxp.rb +10 -10
- data/lib/aarch64/instructions/ldaxr.rb +8 -8
- data/lib/aarch64/instructions/ldclr.rb +14 -14
- data/lib/aarch64/instructions/ldclrb.rb +14 -14
- data/lib/aarch64/instructions/ldeor.rb +14 -14
- data/lib/aarch64/instructions/ldg.rb +8 -8
- data/lib/aarch64/instructions/ldgm.rb +6 -6
- data/lib/aarch64/instructions/ldlar.rb +8 -8
- data/lib/aarch64/instructions/ldnp_gen.rb +12 -12
- data/lib/aarch64/instructions/ldp_gen.rb +14 -14
- data/lib/aarch64/instructions/ldpsw.rb +12 -12
- data/lib/aarch64/instructions/ldr_imm_gen.rb +12 -12
- data/lib/aarch64/instructions/ldr_imm_unsigned.rb +10 -10
- data/lib/aarch64/instructions/ldr_lit_gen.rb +7 -7
- data/lib/aarch64/instructions/ldr_reg_gen.rb +14 -14
- data/lib/aarch64/instructions/ldra.rb +14 -14
- data/lib/aarch64/instructions/ldrb_imm.rb +10 -10
- data/lib/aarch64/instructions/ldrb_reg.rb +12 -12
- data/lib/aarch64/instructions/ldrb_unsigned.rb +8 -8
- data/lib/aarch64/instructions/ldrh_imm.rb +10 -10
- data/lib/aarch64/instructions/ldrh_reg.rb +12 -12
- data/lib/aarch64/instructions/ldrh_unsigned.rb +8 -8
- data/lib/aarch64/instructions/ldrsb_imm.rb +12 -12
- data/lib/aarch64/instructions/ldrsb_reg.rb +14 -14
- data/lib/aarch64/instructions/ldrsb_unsigned.rb +10 -10
- data/lib/aarch64/instructions/ldrsh_imm.rb +12 -12
- data/lib/aarch64/instructions/ldrsh_reg.rb +14 -14
- data/lib/aarch64/instructions/ldrsh_unsigned.rb +10 -10
- data/lib/aarch64/instructions/ldrsw_imm.rb +10 -10
- data/lib/aarch64/instructions/ldrsw_lit.rb +5 -5
- data/lib/aarch64/instructions/ldrsw_reg.rb +12 -12
- data/lib/aarch64/instructions/ldrsw_unsigned.rb +8 -8
- data/lib/aarch64/instructions/ldset.rb +14 -14
- data/lib/aarch64/instructions/ldsetb.rb +12 -12
- data/lib/aarch64/instructions/ldseth.rb +12 -12
- data/lib/aarch64/instructions/ldsmax.rb +14 -14
- data/lib/aarch64/instructions/ldsmaxb.rb +12 -12
- data/lib/aarch64/instructions/ldsmaxh.rb +12 -12
- data/lib/aarch64/instructions/ldsmin.rb +14 -14
- data/lib/aarch64/instructions/ldsminb.rb +12 -12
- data/lib/aarch64/instructions/ldsminh.rb +12 -12
- data/lib/aarch64/instructions/ldtr.rb +10 -10
- data/lib/aarch64/instructions/ldtrb.rb +8 -8
- data/lib/aarch64/instructions/ldtrh.rb +8 -8
- data/lib/aarch64/instructions/ldtrsb.rb +10 -10
- data/lib/aarch64/instructions/ldtrsh.rb +10 -10
- data/lib/aarch64/instructions/ldtrsw.rb +8 -8
- data/lib/aarch64/instructions/ldumax.rb +14 -14
- data/lib/aarch64/instructions/ldumaxb.rb +12 -12
- data/lib/aarch64/instructions/ldumaxh.rb +12 -12
- data/lib/aarch64/instructions/ldumin.rb +14 -14
- data/lib/aarch64/instructions/lduminb.rb +12 -12
- data/lib/aarch64/instructions/lduminh.rb +12 -12
- data/lib/aarch64/instructions/ldur_gen.rb +10 -10
- data/lib/aarch64/instructions/ldursb.rb +10 -10
- data/lib/aarch64/instructions/ldursh.rb +10 -10
- data/lib/aarch64/instructions/ldursw.rb +8 -8
- data/lib/aarch64/instructions/ldxp.rb +10 -10
- data/lib/aarch64/instructions/ldxr.rb +8 -8
- data/lib/aarch64/instructions/lslv.rb +10 -10
- data/lib/aarch64/instructions/lsrv.rb +10 -10
- data/lib/aarch64/instructions/madd.rb +12 -12
- data/lib/aarch64/instructions/movk.rb +10 -10
- data/lib/aarch64/instructions/movn.rb +10 -10
- data/lib/aarch64/instructions/movz.rb +10 -10
- data/lib/aarch64/instructions/mrs.rb +14 -14
- data/lib/aarch64/instructions/msr_imm.rb +7 -7
- data/lib/aarch64/instructions/msr_reg.rb +14 -14
- data/lib/aarch64/instructions/msub.rb +12 -12
- data/lib/aarch64/instructions/nop.rb +1 -1
- data/lib/aarch64/instructions/orn_log_shift.rb +14 -14
- data/lib/aarch64/instructions/orr_log_imm.rb +14 -14
- data/lib/aarch64/instructions/orr_log_shift.rb +14 -14
- data/lib/aarch64/instructions/pacda.rb +8 -8
- data/lib/aarch64/instructions/pacdb.rb +8 -8
- data/lib/aarch64/instructions/pacga.rb +8 -8
- data/lib/aarch64/instructions/pacia.rb +8 -8
- data/lib/aarch64/instructions/pacia2.rb +5 -5
- data/lib/aarch64/instructions/pacib.rb +8 -8
- data/lib/aarch64/instructions/prfm_imm.rb +8 -8
- data/lib/aarch64/instructions/prfm_lit.rb +8 -8
- data/lib/aarch64/instructions/prfm_reg.rb +12 -12
- data/lib/aarch64/instructions/prfum.rb +8 -8
- data/lib/aarch64/instructions/psb.rb +2 -9
- data/lib/aarch64/instructions/rbit_int.rb +8 -8
- data/lib/aarch64/instructions/ret.rb +4 -4
- data/lib/aarch64/instructions/reta.rb +3 -3
- data/lib/aarch64/instructions/rev.rb +10 -10
- data/lib/aarch64/instructions/rmif.rb +8 -8
- data/lib/aarch64/instructions/rorv.rb +10 -10
- data/lib/aarch64/instructions/sb.rb +1 -1
- data/lib/aarch64/instructions/sbc.rb +10 -10
- data/lib/aarch64/instructions/sbcs.rb +10 -10
- data/lib/aarch64/instructions/sbfm.rb +13 -13
- data/lib/aarch64/instructions/sdiv.rb +10 -10
- data/lib/aarch64/instructions/setf.rb +6 -6
- data/lib/aarch64/instructions/sev.rb +1 -7
- data/lib/aarch64/instructions/sevl.rb +1 -1
- data/lib/aarch64/instructions/smaddl.rb +10 -10
- data/lib/aarch64/instructions/smc.rb +3 -3
- data/lib/aarch64/instructions/smsubl.rb +10 -10
- data/lib/aarch64/instructions/smulh.rb +8 -8
- data/lib/aarch64/instructions/st2g.rb +10 -10
- data/lib/aarch64/instructions/st64b.rb +6 -6
- data/lib/aarch64/instructions/st64bv.rb +8 -8
- data/lib/aarch64/instructions/st64bv0.rb +8 -8
- data/lib/aarch64/instructions/stg.rb +10 -10
- data/lib/aarch64/instructions/stgm.rb +6 -6
- data/lib/aarch64/instructions/stgp.rb +12 -12
- data/lib/aarch64/instructions/stllr.rb +8 -8
- data/lib/aarch64/instructions/stllrb.rb +6 -6
- data/lib/aarch64/instructions/stllrh.rb +6 -6
- data/lib/aarch64/instructions/stlr.rb +8 -8
- data/lib/aarch64/instructions/stlrb.rb +6 -6
- data/lib/aarch64/instructions/stlrh.rb +6 -6
- data/lib/aarch64/instructions/stlur_gen.rb +10 -10
- data/lib/aarch64/instructions/stlxp.rb +12 -12
- data/lib/aarch64/instructions/stlxr.rb +10 -10
- data/lib/aarch64/instructions/stlxrb.rb +8 -8
- data/lib/aarch64/instructions/stlxrh.rb +8 -8
- data/lib/aarch64/instructions/stnp_gen.rb +12 -12
- data/lib/aarch64/instructions/stp_gen.rb +14 -14
- data/lib/aarch64/instructions/str_imm_gen.rb +12 -12
- data/lib/aarch64/instructions/str_imm_unsigned.rb +10 -10
- data/lib/aarch64/instructions/str_reg_gen.rb +14 -14
- data/lib/aarch64/instructions/strb_imm.rb +10 -10
- data/lib/aarch64/instructions/strb_imm_unsigned.rb +8 -8
- data/lib/aarch64/instructions/strb_reg.rb +12 -12
- data/lib/aarch64/instructions/strh_imm.rb +10 -10
- data/lib/aarch64/instructions/strh_imm_unsigned.rb +8 -8
- data/lib/aarch64/instructions/strh_reg.rb +12 -12
- data/lib/aarch64/instructions/sttr.rb +10 -10
- data/lib/aarch64/instructions/stur_gen.rb +10 -10
- data/lib/aarch64/instructions/stxp.rb +12 -12
- data/lib/aarch64/instructions/stxr.rb +10 -10
- data/lib/aarch64/instructions/stxrb.rb +8 -8
- data/lib/aarch64/instructions/stxrh.rb +8 -8
- data/lib/aarch64/instructions/stz2g.rb +10 -10
- data/lib/aarch64/instructions/stzg.rb +10 -10
- data/lib/aarch64/instructions/stzgm.rb +6 -6
- data/lib/aarch64/instructions/sub_addsub_ext.rb +14 -14
- data/lib/aarch64/instructions/sub_addsub_imm.rb +12 -12
- data/lib/aarch64/instructions/sub_addsub_shift.rb +14 -14
- data/lib/aarch64/instructions/subg.rb +10 -10
- data/lib/aarch64/instructions/subp.rb +8 -8
- data/lib/aarch64/instructions/subps.rb +8 -8
- data/lib/aarch64/instructions/subs_addsub_ext.rb +14 -14
- data/lib/aarch64/instructions/subs_addsub_imm.rb +12 -12
- data/lib/aarch64/instructions/subs_addsub_shift.rb +14 -14
- data/lib/aarch64/instructions/svc.rb +3 -3
- data/lib/aarch64/instructions/swp.rb +14 -14
- data/lib/aarch64/instructions/swpb.rb +12 -12
- data/lib/aarch64/instructions/swph.rb +12 -12
- data/lib/aarch64/instructions/sys.rb +12 -12
- data/lib/aarch64/instructions/sysl.rb +12 -12
- data/lib/aarch64/instructions/tbnz.rb +9 -9
- data/lib/aarch64/instructions/tbz.rb +9 -9
- data/lib/aarch64/instructions/tsb.rb +1 -7
- data/lib/aarch64/instructions/ubfm.rb +13 -13
- data/lib/aarch64/instructions/udf_perm_undef.rb +3 -3
- data/lib/aarch64/instructions/udiv.rb +10 -10
- data/lib/aarch64/instructions/umaddl.rb +10 -10
- data/lib/aarch64/instructions/umsubl.rb +10 -10
- data/lib/aarch64/instructions/umulh.rb +8 -8
- data/lib/aarch64/instructions/wfe.rb +2 -9
- data/lib/aarch64/instructions/wfet.rb +4 -4
- data/lib/aarch64/instructions/wfi.rb +1 -1
- data/lib/aarch64/instructions/wfit.rb +4 -4
- data/lib/aarch64/instructions/xaflag.rb +1 -1
- data/lib/aarch64/instructions/xpac.rb +6 -6
- data/lib/aarch64/instructions/xpaclri.rb +1 -1
- data/lib/aarch64/instructions/yield.rb +2 -9
- data/lib/aarch64/instructions.rb +26 -8
- data/lib/aarch64/parser.rb +227 -0
- data/lib/aarch64/parser.tab.rb +6534 -0
- data/lib/aarch64/parser.y +1394 -0
- data/lib/aarch64/utils.rb +34 -0
- data/lib/aarch64/version.rb +1 -1
- data/lib/aarch64.rb +128 -58
- data/test/base_instructions_test.rb +34 -4
- data/test/helper.rb +48 -8
- data/test/parser_test.rb +1820 -0
- metadata +25 -14
- data/lib/aarch64/instructions/setgp.rb +0 -25
- data/lib/aarch64/instructions/setgpn.rb +0 -25
- data/lib/aarch64/instructions/setgpt.rb +0 -25
- data/lib/aarch64/instructions/setgptn.rb +0 -25
- data/lib/aarch64/instructions/setp.rb +0 -25
- data/lib/aarch64/instructions/setpn.rb +0 -25
- data/lib/aarch64/instructions/setpt.rb +0 -25
- data/lib/aarch64/instructions/setptn.rb +0 -25
@@ -10,30 +10,30 @@ module AArch64
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# CASA <Xs>, <Xt>, [<Xn|SP>{,#0}]
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# CASAL <Xs>, <Xt>, [<Xn|SP>{,#0}]
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# CASL <Xs>, <Xt>, [<Xn|SP>{,#0}]
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class CAS
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class CAS < Instruction
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def initialize s, t, n, l, o0, sf
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@s = s
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@t = t
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@n = n
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@l = l
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@o0 = o0
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@sf = sf
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@s = check_mask(s, 0x1f)
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@t = check_mask(t, 0x1f)
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@n = check_mask(n, 0x1f)
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@l = check_mask(l, 0x01)
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@o0 = check_mask(o0, 0x01)
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@sf = check_mask(sf, 0x01)
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end
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def encode
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CAS(@sf, @l, @s
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CAS(@sf, @l, @s, @o0, @n, @t)
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end
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private
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def CAS x, l, rs, o0, rn, rt
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insn = 0b10_0010001_0_1_00000_0_11111_00000_00000
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insn |= ((x
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insn |= ((l
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insn |= ((rs
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insn |= ((o0
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insn |= ((rn
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insn |= (rt
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insn |= ((x) << 30)
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insn |= ((l) << 22)
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insn |= ((rs) << 16)
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insn |= ((o0) << 15)
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insn |= ((rn) << 5)
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insn |= (rt)
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insn
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end
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end
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@@ -6,28 +6,28 @@ module AArch64
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# CASALB <Ws>, <Wt>, [<Xn|SP>{,#0}]
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# CASB <Ws>, <Wt>, [<Xn|SP>{,#0}]
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# CASLB <Ws>, <Wt>, [<Xn|SP>{,#0}]
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class CASB
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class CASB < Instruction
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def initialize rs, rt, rn, l, o0
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@rs = rs
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@rt = rt
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@rn = rn
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@l = l
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@o0 = o0
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@rs = check_mask(rs, 0x1f)
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@rt = check_mask(rt, 0x1f)
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@rn = check_mask(rn, 0x1f)
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@l = check_mask(l, 0x01)
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@o0 = check_mask(o0, 0x01)
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end
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def encode
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CASB(@l, @rs
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CASB(@l, @rs, @o0, @rn, @rt)
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end
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private
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def CASB l, rs, o0, rn, rt
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insn = 0b00_0010001_0_1_00000_0_11111_00000_00000
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insn |= ((l
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insn |= ((rs
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insn |= ((o0
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insn |= ((rn
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insn |= (rt
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insn |= ((l) << 22)
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insn |= ((rs) << 16)
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insn |= ((o0) << 15)
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insn |= ((rn) << 5)
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insn |= (rt)
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insn
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end
|
33
33
|
end
|
@@ -6,28 +6,28 @@ module AArch64
|
|
6
6
|
# CASALH <Ws>, <Wt>, [<Xn|SP>{,#0}]
|
7
7
|
# CASH <Ws>, <Wt>, [<Xn|SP>{,#0}]
|
8
8
|
# CASLH <Ws>, <Wt>, [<Xn|SP>{,#0}]
|
9
|
-
class CASH
|
9
|
+
class CASH < Instruction
|
10
10
|
def initialize rs, rt, rn, l, o0
|
11
|
-
@rs = rs
|
12
|
-
@rt = rt
|
13
|
-
@rn = rn
|
14
|
-
@l = l
|
15
|
-
@o0 = o0
|
11
|
+
@rs = check_mask(rs, 0x1f)
|
12
|
+
@rt = check_mask(rt, 0x1f)
|
13
|
+
@rn = check_mask(rn, 0x1f)
|
14
|
+
@l = check_mask(l, 0x01)
|
15
|
+
@o0 = check_mask(o0, 0x01)
|
16
16
|
end
|
17
17
|
|
18
18
|
def encode
|
19
|
-
CASH(@l, @rs
|
19
|
+
CASH(@l, @rs, @o0, @rn, @rt)
|
20
20
|
end
|
21
21
|
|
22
22
|
private
|
23
23
|
|
24
24
|
def CASH l, rs, o0, rn, rt
|
25
25
|
insn = 0b01_0010001_0_1_00000_0_11111_00000_00000
|
26
|
-
insn |= ((l
|
27
|
-
insn |= ((rs
|
28
|
-
insn |= ((o0
|
29
|
-
insn |= ((rn
|
30
|
-
insn |= (rt
|
26
|
+
insn |= ((l) << 22)
|
27
|
+
insn |= ((rs) << 16)
|
28
|
+
insn |= ((o0) << 15)
|
29
|
+
insn |= ((rn) << 5)
|
30
|
+
insn |= (rt)
|
31
31
|
insn
|
32
32
|
end
|
33
33
|
end
|
@@ -10,30 +10,30 @@ module AArch64
|
|
10
10
|
# CASPA <Xs>, <X(s+1)>, <Xt>, <X(t+1)>, [<Xn|SP>{,#0}]
|
11
11
|
# CASPAL <Xs>, <X(s+1)>, <Xt>, <X(t+1)>, [<Xn|SP>{,#0}]
|
12
12
|
# CASPL <Xs>, <X(s+1)>, <Xt>, <X(t+1)>, [<Xn|SP>{,#0}]
|
13
|
-
class CASP
|
13
|
+
class CASP < Instruction
|
14
14
|
def initialize rs, rt, rn, l, o0, sf
|
15
|
-
@rs = rs
|
16
|
-
@rt = rt
|
17
|
-
@rn = rn
|
18
|
-
@l = l
|
19
|
-
@o0 = o0
|
20
|
-
@sf = sf
|
15
|
+
@rs = check_mask(rs, 0x1f)
|
16
|
+
@rt = check_mask(rt, 0x1f)
|
17
|
+
@rn = check_mask(rn, 0x1f)
|
18
|
+
@l = check_mask(l, 0x01)
|
19
|
+
@o0 = check_mask(o0, 0x01)
|
20
|
+
@sf = check_mask(sf, 0x01)
|
21
21
|
end
|
22
22
|
|
23
23
|
def encode
|
24
|
-
CASP(@sf, @l, @rs
|
24
|
+
CASP(@sf, @l, @rs, @o0, @rn, @rt)
|
25
25
|
end
|
26
26
|
|
27
27
|
private
|
28
28
|
|
29
29
|
def CASP sz, l, rs, o0, rn, rt
|
30
30
|
insn = 0b0_0_001000_0_0_1_00000_0_11111_00000_00000
|
31
|
-
insn |= ((sz
|
32
|
-
insn |= ((l
|
33
|
-
insn |= ((rs
|
34
|
-
insn |= ((o0
|
35
|
-
insn |= ((rn
|
36
|
-
insn |= (rt
|
31
|
+
insn |= ((sz) << 30)
|
32
|
+
insn |= ((l) << 22)
|
33
|
+
insn |= ((rs) << 16)
|
34
|
+
insn |= ((o0) << 15)
|
35
|
+
insn |= ((rn) << 5)
|
36
|
+
insn |= (rt)
|
37
37
|
insn
|
38
38
|
end
|
39
39
|
end
|
@@ -4,24 +4,24 @@ module AArch64
|
|
4
4
|
# Compare and Branch on Nonzero
|
5
5
|
# CBNZ <Wt>, <label>
|
6
6
|
# CBNZ <Xt>, <label>
|
7
|
-
class CBNZ
|
7
|
+
class CBNZ < Instruction
|
8
8
|
def initialize rt, label, sf
|
9
|
-
@rt = rt
|
9
|
+
@rt = check_mask(rt, 0x1f)
|
10
10
|
@label = label
|
11
|
-
@sf = sf
|
11
|
+
@sf = check_mask(sf, 0x1)
|
12
12
|
end
|
13
13
|
|
14
14
|
def encode
|
15
|
-
CBNZ(@sf, @label
|
15
|
+
CBNZ(@sf, check_mask(unwrap_label(@label), 0x7ffff), @rt)
|
16
16
|
end
|
17
17
|
|
18
18
|
private
|
19
19
|
|
20
20
|
def CBNZ sf, imm19, rt
|
21
21
|
insn = 0b0_011010_1_0000000000000000000_00000
|
22
|
-
insn |= (
|
23
|
-
insn |= (
|
24
|
-
insn |=
|
22
|
+
insn |= (sf << 31)
|
23
|
+
insn |= (imm19 << 5)
|
24
|
+
insn |= rt
|
25
25
|
insn
|
26
26
|
end
|
27
27
|
end
|
@@ -4,24 +4,24 @@ module AArch64
|
|
4
4
|
# Compare and Branch on Zero
|
5
5
|
# CBZ <Wt>, <label>
|
6
6
|
# CBZ <Xt>, <label>
|
7
|
-
class CBZ
|
7
|
+
class CBZ < Instruction
|
8
8
|
def initialize rt, label, sf
|
9
|
-
@rt = rt
|
9
|
+
@rt = check_mask(rt, 0x1f)
|
10
10
|
@label = label
|
11
|
-
@sf = sf
|
11
|
+
@sf = check_mask(sf, 0x1)
|
12
12
|
end
|
13
13
|
|
14
14
|
def encode
|
15
|
-
CBZ(@sf, @label
|
15
|
+
CBZ(@sf, check_mask(unwrap_label(@label), 0x7ffff), @rt)
|
16
16
|
end
|
17
17
|
|
18
18
|
private
|
19
19
|
|
20
20
|
def CBZ sf, imm19, rt
|
21
21
|
insn = 0b0_011010_0_0000000000000000000_00000
|
22
|
-
insn |= (
|
23
|
-
insn |= (
|
24
|
-
insn |=
|
22
|
+
insn |= (sf << 31)
|
23
|
+
insn |= (imm19 << 5)
|
24
|
+
insn |= rt
|
25
25
|
insn
|
26
26
|
end
|
27
27
|
end
|
@@ -4,28 +4,28 @@ module AArch64
|
|
4
4
|
# Conditional Compare Negative (immediate)
|
5
5
|
# CCMN <Wn>, #<imm>, #<nzcv>, <cond>
|
6
6
|
# CCMN <Xn>, #<imm>, #<nzcv>, <cond>
|
7
|
-
class CCMN_imm
|
7
|
+
class CCMN_imm < Instruction
|
8
8
|
def initialize rn, imm, nzcv, cond, sf
|
9
|
-
@rn = rn
|
10
|
-
@imm = imm
|
11
|
-
@nzcv = nzcv
|
12
|
-
@cond = cond
|
13
|
-
@sf = sf
|
9
|
+
@rn = check_mask(rn, 0x1f)
|
10
|
+
@imm = check_mask(imm, 0x1f)
|
11
|
+
@nzcv = check_mask(nzcv, 0x0f)
|
12
|
+
@cond = check_mask(cond, 0x0f)
|
13
|
+
@sf = check_mask(sf, 0x01)
|
14
14
|
end
|
15
15
|
|
16
16
|
def encode
|
17
|
-
CCMN_imm(@sf, @imm, @cond, @rn
|
17
|
+
CCMN_imm(@sf, @imm, @cond, @rn, @nzcv)
|
18
18
|
end
|
19
19
|
|
20
20
|
private
|
21
21
|
|
22
22
|
def CCMN_imm sf, imm5, cond, rn, nzcv
|
23
23
|
insn = 0b0_0_1_11010010_00000_0000_1_0_00000_0_0000
|
24
|
-
insn |= ((sf
|
25
|
-
insn |= ((imm5
|
26
|
-
insn |= ((cond
|
27
|
-
insn |= ((rn
|
28
|
-
insn |= (nzcv
|
24
|
+
insn |= ((sf) << 31)
|
25
|
+
insn |= ((imm5) << 16)
|
26
|
+
insn |= ((cond) << 12)
|
27
|
+
insn |= ((rn) << 5)
|
28
|
+
insn |= (nzcv)
|
29
29
|
insn
|
30
30
|
end
|
31
31
|
end
|
@@ -4,28 +4,28 @@ module AArch64
|
|
4
4
|
# Conditional Compare Negative (register)
|
5
5
|
# CCMN <Wn>, <Wm>, #<nzcv>, <cond>
|
6
6
|
# CCMN <Xn>, <Xm>, #<nzcv>, <cond>
|
7
|
-
class CCMN_reg
|
7
|
+
class CCMN_reg < Instruction
|
8
8
|
def initialize rn, rm, nzcv, cond, sf
|
9
|
-
@rn = rn
|
10
|
-
@rm = rm
|
11
|
-
@nzcv = nzcv
|
12
|
-
@cond = cond
|
13
|
-
@sf = sf
|
9
|
+
@rn = check_mask(rn, 0x1f)
|
10
|
+
@rm = check_mask(rm, 0x1f)
|
11
|
+
@nzcv = check_mask(nzcv, 0x0f)
|
12
|
+
@cond = check_mask(cond, 0x0f)
|
13
|
+
@sf = check_mask(sf, 0x01)
|
14
14
|
end
|
15
15
|
|
16
16
|
def encode
|
17
|
-
CCMN_reg(@sf, @rm
|
17
|
+
CCMN_reg(@sf, @rm, @cond, @rn, @nzcv)
|
18
18
|
end
|
19
19
|
|
20
20
|
private
|
21
21
|
|
22
22
|
def CCMN_reg sf, rm, cond, rn, nzcv
|
23
23
|
insn = 0b0_0_1_11010010_00000_0000_0_0_00000_0_0000
|
24
|
-
insn |= ((sf
|
25
|
-
insn |= ((rm
|
26
|
-
insn |= ((cond
|
27
|
-
insn |= ((rn
|
28
|
-
insn |= (nzcv
|
24
|
+
insn |= ((sf) << 31)
|
25
|
+
insn |= ((rm) << 16)
|
26
|
+
insn |= ((cond) << 12)
|
27
|
+
insn |= ((rn) << 5)
|
28
|
+
insn |= (nzcv)
|
29
29
|
insn
|
30
30
|
end
|
31
31
|
end
|
@@ -4,28 +4,28 @@ module AArch64
|
|
4
4
|
# Conditional Compare (immediate)
|
5
5
|
# CCMP <Wn>, #<imm>, #<nzcv>, <cond>
|
6
6
|
# CCMP <Xn>, #<imm>, #<nzcv>, <cond>
|
7
|
-
class CCMP_imm
|
7
|
+
class CCMP_imm < Instruction
|
8
8
|
def initialize rn, imm, nzcv, cond, sf
|
9
|
-
@rn = rn
|
10
|
-
@imm = imm
|
11
|
-
@nzcv = nzcv
|
12
|
-
@cond = cond
|
13
|
-
@sf = sf
|
9
|
+
@rn = check_mask(rn, 0x1f)
|
10
|
+
@imm = check_mask(imm, 0x1f)
|
11
|
+
@nzcv = check_mask(nzcv, 0x0f)
|
12
|
+
@cond = check_mask(cond, 0x0f)
|
13
|
+
@sf = check_mask(sf, 0x01)
|
14
14
|
end
|
15
15
|
|
16
16
|
def encode
|
17
|
-
CCMP_imm(@sf, @imm, @cond, @rn
|
17
|
+
CCMP_imm(@sf, @imm, @cond, @rn, @nzcv)
|
18
18
|
end
|
19
19
|
|
20
20
|
private
|
21
21
|
|
22
22
|
def CCMP_imm sf, imm5, cond, rn, nzcv
|
23
23
|
insn = 0b0_1_1_11010010_00000_0000_1_0_00000_0_0000
|
24
|
-
insn |= ((sf
|
25
|
-
insn |= ((imm5
|
26
|
-
insn |= ((cond
|
27
|
-
insn |= ((rn
|
28
|
-
insn |= (nzcv
|
24
|
+
insn |= ((sf) << 31)
|
25
|
+
insn |= ((imm5) << 16)
|
26
|
+
insn |= ((cond) << 12)
|
27
|
+
insn |= ((rn) << 5)
|
28
|
+
insn |= (nzcv)
|
29
29
|
insn
|
30
30
|
end
|
31
31
|
end
|
@@ -4,28 +4,28 @@ module AArch64
|
|
4
4
|
# Conditional Compare (register)
|
5
5
|
# CCMP <Wn>, <Wm>, #<nzcv>, <cond>
|
6
6
|
# CCMP <Xn>, <Xm>, #<nzcv>, <cond>
|
7
|
-
class CCMP_reg
|
7
|
+
class CCMP_reg < Instruction
|
8
8
|
def initialize rn, rm, nzcv, cond, sf
|
9
|
-
@rn = rn
|
10
|
-
@rm = rm
|
11
|
-
@nzcv = nzcv
|
12
|
-
@cond = cond
|
13
|
-
@sf = sf
|
9
|
+
@rn = check_mask(rn, 0x1f)
|
10
|
+
@rm = check_mask(rm, 0x1f)
|
11
|
+
@nzcv = check_mask(nzcv, 0x0f)
|
12
|
+
@cond = check_mask(cond, 0x0f)
|
13
|
+
@sf = check_mask(sf, 0x01)
|
14
14
|
end
|
15
15
|
|
16
16
|
def encode
|
17
|
-
CCMP_reg(@sf, @rm
|
17
|
+
CCMP_reg(@sf, @rm, @cond, @rn, @nzcv)
|
18
18
|
end
|
19
19
|
|
20
20
|
private
|
21
21
|
|
22
22
|
def CCMP_reg sf, rm, cond, rn, nzcv
|
23
23
|
insn = 0b0_1_1_11010010_00000_0000_0_0_00000_0_0000
|
24
|
-
insn |= ((sf
|
25
|
-
insn |= ((rm
|
26
|
-
insn |= ((cond
|
27
|
-
insn |= ((rn
|
28
|
-
insn |= (nzcv
|
24
|
+
insn |= ((sf) << 31)
|
25
|
+
insn |= ((rm) << 16)
|
26
|
+
insn |= ((cond) << 12)
|
27
|
+
insn |= ((rn) << 5)
|
28
|
+
insn |= (nzcv)
|
29
29
|
insn
|
30
30
|
end
|
31
31
|
end
|
@@ -3,16 +3,9 @@ module AArch64
|
|
3
3
|
# CFINV -- A64
|
4
4
|
# Invert Carry Flag
|
5
5
|
# CFINV
|
6
|
-
class CFINV
|
6
|
+
class CFINV < Instruction
|
7
7
|
def encode
|
8
|
-
|
9
|
-
end
|
10
|
-
|
11
|
-
private
|
12
|
-
|
13
|
-
def CFINV
|
14
|
-
insn = 0b1101010100_0_0_0_000_0100_0000_000_11111
|
15
|
-
insn
|
8
|
+
0b1101010100_0_0_0_000_0100_0000_000_11111
|
16
9
|
end
|
17
10
|
end
|
18
11
|
end
|
@@ -3,9 +3,9 @@ module AArch64
|
|
3
3
|
# CLREX -- A64
|
4
4
|
# Clear Exclusive
|
5
5
|
# CLREX {#<imm>}
|
6
|
-
class CLREX
|
6
|
+
class CLREX < Instruction
|
7
7
|
def initialize imm
|
8
|
-
@imm = imm
|
8
|
+
@imm = check_mask(imm, 0x0f)
|
9
9
|
end
|
10
10
|
|
11
11
|
def encode
|
@@ -16,7 +16,7 @@ module AArch64
|
|
16
16
|
|
17
17
|
def CLREX crm
|
18
18
|
insn = 0b1101010100_0_00_011_0011_0000_010_11111
|
19
|
-
insn |= ((crm
|
19
|
+
insn |= ((crm) << 8)
|
20
20
|
insn
|
21
21
|
end
|
22
22
|
end
|
@@ -4,24 +4,24 @@ module AArch64
|
|
4
4
|
# Count Leading Sign bits
|
5
5
|
# CLS <Wd>, <Wn>
|
6
6
|
# CLS <Xd>, <Xn>
|
7
|
-
class CLS_int
|
7
|
+
class CLS_int < Instruction
|
8
8
|
def initialize rd, rn, sf
|
9
|
-
@rd = rd
|
10
|
-
@rn = rn
|
11
|
-
@sf = sf
|
9
|
+
@rd = check_mask(rd, 0x1f)
|
10
|
+
@rn = check_mask(rn, 0x1f)
|
11
|
+
@sf = check_mask(sf, 0x01)
|
12
12
|
end
|
13
13
|
|
14
14
|
def encode
|
15
|
-
CLS_int(@sf, @rn
|
15
|
+
CLS_int(@sf, @rn, @rd)
|
16
16
|
end
|
17
17
|
|
18
18
|
private
|
19
19
|
|
20
20
|
def CLS_int sf, rn, rd
|
21
21
|
insn = 0b0_1_0_11010110_00000_00010_1_00000_00000
|
22
|
-
insn |= ((sf
|
23
|
-
insn |= ((rn
|
24
|
-
insn |= (rd
|
22
|
+
insn |= ((sf) << 31)
|
23
|
+
insn |= ((rn) << 5)
|
24
|
+
insn |= (rd)
|
25
25
|
insn
|
26
26
|
end
|
27
27
|
end
|
@@ -4,24 +4,24 @@ module AArch64
|
|
4
4
|
# Count Leading Zeros
|
5
5
|
# CLZ <Wd>, <Wn>
|
6
6
|
# CLZ <Xd>, <Xn>
|
7
|
-
class CLZ_int
|
7
|
+
class CLZ_int < Instruction
|
8
8
|
def initialize rd, rn, sf
|
9
|
-
@rd = rd
|
10
|
-
@rn = rn
|
11
|
-
@sf = sf
|
9
|
+
@rd = check_mask(rd, 0x1f)
|
10
|
+
@rn = check_mask(rn, 0x1f)
|
11
|
+
@sf = check_mask(sf, 0x01)
|
12
12
|
end
|
13
13
|
|
14
14
|
def encode
|
15
|
-
CLZ_int(@sf, @rn
|
15
|
+
CLZ_int(@sf, @rn, @rd)
|
16
16
|
end
|
17
17
|
|
18
18
|
private
|
19
19
|
|
20
20
|
def CLZ_int sf, rn, rd
|
21
21
|
insn = 0b0_1_0_11010110_00000_00010_0_00000_00000
|
22
|
-
insn |= ((sf
|
23
|
-
insn |= ((rn
|
24
|
-
insn |= (rd
|
22
|
+
insn |= ((sf) << 31)
|
23
|
+
insn |= ((rn) << 5)
|
24
|
+
insn |= (rd)
|
25
25
|
insn
|
26
26
|
end
|
27
27
|
end
|
@@ -6,28 +6,28 @@ module AArch64
|
|
6
6
|
# CRC32H <Wd>, <Wn>, <Wm>
|
7
7
|
# CRC32W <Wd>, <Wn>, <Wm>
|
8
8
|
# CRC32X <Wd>, <Wn>, <Xm>
|
9
|
-
class CRC32
|
9
|
+
class CRC32 < Instruction
|
10
10
|
def initialize rd, rn, rm, sz, sf
|
11
|
-
@rd = rd
|
12
|
-
@rn = rn
|
13
|
-
@rm = rm
|
14
|
-
@sz = sz
|
15
|
-
@sf = sf
|
11
|
+
@rd = check_mask(rd, 0x1f)
|
12
|
+
@rn = check_mask(rn, 0x1f)
|
13
|
+
@rm = check_mask(rm, 0x1f)
|
14
|
+
@sz = check_mask(sz, 0x03)
|
15
|
+
@sf = check_mask(sf, 0x01)
|
16
16
|
end
|
17
17
|
|
18
18
|
def encode
|
19
|
-
CRC32(@sf, @rm
|
19
|
+
CRC32(@sf, @rm, @sz, @rn, @rd)
|
20
20
|
end
|
21
21
|
|
22
22
|
private
|
23
23
|
|
24
24
|
def CRC32 sf, rm, sz, rn, rd
|
25
25
|
insn = 0b0_0_0_11010110_00000_010_0_00_00000_00000
|
26
|
-
insn |= ((sf
|
27
|
-
insn |= ((rm
|
28
|
-
insn |= ((sz
|
29
|
-
insn |= ((rn
|
30
|
-
insn |= (rd
|
26
|
+
insn |= ((sf) << 31)
|
27
|
+
insn |= ((rm) << 16)
|
28
|
+
insn |= ((sz) << 10)
|
29
|
+
insn |= ((rn) << 5)
|
30
|
+
insn |= (rd)
|
31
31
|
insn
|
32
32
|
end
|
33
33
|
end
|
@@ -6,28 +6,28 @@ module AArch64
|
|
6
6
|
# CRC32CH <Wd>, <Wn>, <Wm>
|
7
7
|
# CRC32CW <Wd>, <Wn>, <Wm>
|
8
8
|
# CRC32CX <Wd>, <Wn>, <Xm>
|
9
|
-
class CRC32C
|
9
|
+
class CRC32C < Instruction
|
10
10
|
def initialize rd, rn, rm, sz, sf
|
11
|
-
@rd = rd
|
12
|
-
@rn = rn
|
13
|
-
@rm = rm
|
14
|
-
@sz = sz
|
15
|
-
@sf = sf
|
11
|
+
@rd = check_mask(rd, 0x1f)
|
12
|
+
@rn = check_mask(rn, 0x1f)
|
13
|
+
@rm = check_mask(rm, 0x1f)
|
14
|
+
@sz = check_mask(sz, 0x03)
|
15
|
+
@sf = check_mask(sf, 0x01)
|
16
16
|
end
|
17
17
|
|
18
18
|
def encode
|
19
|
-
CRC32C(@sf, @rm
|
19
|
+
CRC32C(@sf, @rm, @sz, @rn, @rd)
|
20
20
|
end
|
21
21
|
|
22
22
|
private
|
23
23
|
|
24
24
|
def CRC32C sf, rm, sz, rn, rd
|
25
25
|
insn = 0b0_0_0_11010110_00000_010_1_00_00000_00000
|
26
|
-
insn |= ((sf
|
27
|
-
insn |= ((rm
|
28
|
-
insn |= ((sz
|
29
|
-
insn |= ((rn
|
30
|
-
insn |= (rd
|
26
|
+
insn |= ((sf) << 31)
|
27
|
+
insn |= ((rm) << 16)
|
28
|
+
insn |= ((sz) << 10)
|
29
|
+
insn |= ((rn) << 5)
|
30
|
+
insn |= (rd)
|
31
31
|
insn
|
32
32
|
end
|
33
33
|
end
|
@@ -4,28 +4,28 @@ module AArch64
|
|
4
4
|
# Conditional Select
|
5
5
|
# CSEL <Wd>, <Wn>, <Wm>, <cond>
|
6
6
|
# CSEL <Xd>, <Xn>, <Xm>, <cond>
|
7
|
-
class CSEL
|
7
|
+
class CSEL < Instruction
|
8
8
|
def initialize rd, rn, rm, cond, sf
|
9
|
-
@rd = rd
|
10
|
-
@rn = rn
|
11
|
-
@rm = rm
|
12
|
-
@cond = cond
|
13
|
-
@sf = sf
|
9
|
+
@rd = check_mask(rd, 0x1f)
|
10
|
+
@rn = check_mask(rn, 0x1f)
|
11
|
+
@rm = check_mask(rm, 0x1f)
|
12
|
+
@cond = check_mask(cond, 0x0f)
|
13
|
+
@sf = check_mask(sf, 0x01)
|
14
14
|
end
|
15
15
|
|
16
16
|
def encode
|
17
|
-
CSEL @sf, @rm
|
17
|
+
CSEL @sf, @rm, @cond, @rn, @rd
|
18
18
|
end
|
19
19
|
|
20
20
|
private
|
21
21
|
|
22
22
|
def CSEL sf, rm, cond, rn, rd
|
23
23
|
insn = 0b0_0_0_11010100_00000_0000_0_0_00000_00000
|
24
|
-
insn |= ((sf
|
25
|
-
insn |= ((rm
|
26
|
-
insn |= ((cond
|
27
|
-
insn |= ((rn
|
28
|
-
insn |= (rd
|
24
|
+
insn |= ((sf) << 31)
|
25
|
+
insn |= ((rm) << 16)
|
26
|
+
insn |= ((cond) << 12)
|
27
|
+
insn |= ((rn) << 5)
|
28
|
+
insn |= (rd)
|
29
29
|
insn
|
30
30
|
end
|
31
31
|
end
|