aarch64 1.0.1 → 2.0.0
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/README.md +1 -1
- data/Rakefile +37 -0
- data/aarch64.gemspec +1 -0
- data/lib/aarch64/instructions/adc.rb +10 -10
- data/lib/aarch64/instructions/adcs.rb +10 -10
- data/lib/aarch64/instructions/add_addsub_ext.rb +14 -14
- data/lib/aarch64/instructions/add_addsub_imm.rb +12 -12
- data/lib/aarch64/instructions/add_addsub_shift.rb +14 -14
- data/lib/aarch64/instructions/addg.rb +10 -10
- data/lib/aarch64/instructions/adds_addsub_ext.rb +14 -14
- data/lib/aarch64/instructions/adds_addsub_imm.rb +12 -12
- data/lib/aarch64/instructions/adds_addsub_shift.rb +14 -14
- data/lib/aarch64/instructions/adr.rb +7 -7
- data/lib/aarch64/instructions/adrp.rb +7 -7
- data/lib/aarch64/instructions/and_log_imm.rb +14 -14
- data/lib/aarch64/instructions/and_log_shift.rb +14 -14
- data/lib/aarch64/instructions/ands_log_imm.rb +14 -14
- data/lib/aarch64/instructions/ands_log_shift.rb +14 -14
- data/lib/aarch64/instructions/asrv.rb +10 -10
- data/lib/aarch64/instructions/autda.rb +9 -12
- data/lib/aarch64/instructions/autdb.rb +9 -12
- data/lib/aarch64/instructions/autia.rb +9 -12
- data/lib/aarch64/instructions/autib.rb +9 -12
- data/lib/aarch64/instructions/axflag.rb +1 -1
- data/lib/aarch64/instructions/b_cond.rb +5 -5
- data/lib/aarch64/instructions/b_uncond.rb +3 -3
- data/lib/aarch64/instructions/bc_cond.rb +5 -5
- data/lib/aarch64/instructions/bfm.rb +13 -13
- data/lib/aarch64/instructions/bic_log_shift.rb +14 -14
- data/lib/aarch64/instructions/bics.rb +14 -14
- data/lib/aarch64/instructions/bl.rb +3 -3
- data/lib/aarch64/instructions/blr.rb +4 -4
- data/lib/aarch64/instructions/blra.rb +10 -10
- data/lib/aarch64/instructions/br.rb +4 -4
- data/lib/aarch64/instructions/bra.rb +10 -10
- data/lib/aarch64/instructions/brk.rb +3 -3
- data/lib/aarch64/instructions/bti.rb +3 -3
- data/lib/aarch64/instructions/cas.rb +14 -14
- data/lib/aarch64/instructions/casb.rb +12 -12
- data/lib/aarch64/instructions/cash.rb +12 -12
- data/lib/aarch64/instructions/casp.rb +14 -14
- data/lib/aarch64/instructions/cbnz.rb +7 -7
- data/lib/aarch64/instructions/cbz.rb +7 -7
- data/lib/aarch64/instructions/ccmn_imm.rb +12 -12
- data/lib/aarch64/instructions/ccmn_reg.rb +12 -12
- data/lib/aarch64/instructions/ccmp_imm.rb +12 -12
- data/lib/aarch64/instructions/ccmp_reg.rb +12 -12
- data/lib/aarch64/instructions/cfinv.rb +2 -9
- data/lib/aarch64/instructions/clrex.rb +3 -3
- data/lib/aarch64/instructions/cls_int.rb +8 -8
- data/lib/aarch64/instructions/clz_int.rb +8 -8
- data/lib/aarch64/instructions/crc32.rb +12 -12
- data/lib/aarch64/instructions/crc32c.rb +12 -12
- data/lib/aarch64/instructions/csdb.rb +1 -1
- data/lib/aarch64/instructions/csel.rb +12 -12
- data/lib/aarch64/instructions/csinc.rb +12 -12
- data/lib/aarch64/instructions/csinv.rb +12 -12
- data/lib/aarch64/instructions/csneg.rb +12 -12
- data/lib/aarch64/instructions/dcps.rb +5 -5
- data/lib/aarch64/instructions/dgh.rb +1 -1
- data/lib/aarch64/instructions/dmb.rb +3 -3
- data/lib/aarch64/instructions/drps.rb +2 -9
- data/lib/aarch64/instructions/dsb.rb +3 -3
- data/lib/aarch64/instructions/eon.rb +14 -14
- data/lib/aarch64/instructions/eor_log_imm.rb +14 -14
- data/lib/aarch64/instructions/eor_log_shift.rb +14 -14
- data/lib/aarch64/instructions/eret.rb +2 -9
- data/lib/aarch64/instructions/ereta.rb +3 -3
- data/lib/aarch64/instructions/esb.rb +1 -1
- data/lib/aarch64/instructions/extr.rb +13 -13
- data/lib/aarch64/instructions/gmi.rb +8 -8
- data/lib/aarch64/instructions/hint.rb +5 -5
- data/lib/aarch64/instructions/hlt.rb +3 -3
- data/lib/aarch64/instructions/hvc.rb +3 -3
- data/lib/aarch64/instructions/irg.rb +8 -8
- data/lib/aarch64/instructions/isb.rb +3 -3
- data/lib/aarch64/instructions/ld64b.rb +6 -6
- data/lib/aarch64/instructions/ldadd.rb +14 -14
- data/lib/aarch64/instructions/ldaddb.rb +12 -12
- data/lib/aarch64/instructions/ldaddh.rb +12 -12
- data/lib/aarch64/instructions/ldapr.rb +8 -8
- data/lib/aarch64/instructions/ldaprb.rb +6 -6
- data/lib/aarch64/instructions/ldaprh.rb +6 -6
- data/lib/aarch64/instructions/ldapur_gen.rb +12 -12
- data/lib/aarch64/instructions/ldar.rb +8 -8
- data/lib/aarch64/instructions/ldaxp.rb +10 -10
- data/lib/aarch64/instructions/ldaxr.rb +8 -8
- data/lib/aarch64/instructions/ldclr.rb +14 -14
- data/lib/aarch64/instructions/ldclrb.rb +14 -14
- data/lib/aarch64/instructions/ldeor.rb +14 -14
- data/lib/aarch64/instructions/ldg.rb +8 -8
- data/lib/aarch64/instructions/ldgm.rb +6 -6
- data/lib/aarch64/instructions/ldlar.rb +8 -8
- data/lib/aarch64/instructions/ldnp_gen.rb +12 -12
- data/lib/aarch64/instructions/ldp_gen.rb +14 -14
- data/lib/aarch64/instructions/ldpsw.rb +12 -12
- data/lib/aarch64/instructions/ldr_imm_gen.rb +12 -12
- data/lib/aarch64/instructions/ldr_imm_unsigned.rb +10 -10
- data/lib/aarch64/instructions/ldr_lit_gen.rb +7 -7
- data/lib/aarch64/instructions/ldr_reg_gen.rb +14 -14
- data/lib/aarch64/instructions/ldra.rb +14 -14
- data/lib/aarch64/instructions/ldrb_imm.rb +10 -10
- data/lib/aarch64/instructions/ldrb_reg.rb +12 -12
- data/lib/aarch64/instructions/ldrb_unsigned.rb +8 -8
- data/lib/aarch64/instructions/ldrh_imm.rb +10 -10
- data/lib/aarch64/instructions/ldrh_reg.rb +12 -12
- data/lib/aarch64/instructions/ldrh_unsigned.rb +8 -8
- data/lib/aarch64/instructions/ldrsb_imm.rb +12 -12
- data/lib/aarch64/instructions/ldrsb_reg.rb +14 -14
- data/lib/aarch64/instructions/ldrsb_unsigned.rb +10 -10
- data/lib/aarch64/instructions/ldrsh_imm.rb +12 -12
- data/lib/aarch64/instructions/ldrsh_reg.rb +14 -14
- data/lib/aarch64/instructions/ldrsh_unsigned.rb +10 -10
- data/lib/aarch64/instructions/ldrsw_imm.rb +10 -10
- data/lib/aarch64/instructions/ldrsw_lit.rb +5 -5
- data/lib/aarch64/instructions/ldrsw_reg.rb +12 -12
- data/lib/aarch64/instructions/ldrsw_unsigned.rb +8 -8
- data/lib/aarch64/instructions/ldset.rb +14 -14
- data/lib/aarch64/instructions/ldsetb.rb +12 -12
- data/lib/aarch64/instructions/ldseth.rb +12 -12
- data/lib/aarch64/instructions/ldsmax.rb +14 -14
- data/lib/aarch64/instructions/ldsmaxb.rb +12 -12
- data/lib/aarch64/instructions/ldsmaxh.rb +12 -12
- data/lib/aarch64/instructions/ldsmin.rb +14 -14
- data/lib/aarch64/instructions/ldsminb.rb +12 -12
- data/lib/aarch64/instructions/ldsminh.rb +12 -12
- data/lib/aarch64/instructions/ldtr.rb +10 -10
- data/lib/aarch64/instructions/ldtrb.rb +8 -8
- data/lib/aarch64/instructions/ldtrh.rb +8 -8
- data/lib/aarch64/instructions/ldtrsb.rb +10 -10
- data/lib/aarch64/instructions/ldtrsh.rb +10 -10
- data/lib/aarch64/instructions/ldtrsw.rb +8 -8
- data/lib/aarch64/instructions/ldumax.rb +14 -14
- data/lib/aarch64/instructions/ldumaxb.rb +12 -12
- data/lib/aarch64/instructions/ldumaxh.rb +12 -12
- data/lib/aarch64/instructions/ldumin.rb +14 -14
- data/lib/aarch64/instructions/lduminb.rb +12 -12
- data/lib/aarch64/instructions/lduminh.rb +12 -12
- data/lib/aarch64/instructions/ldur_gen.rb +10 -10
- data/lib/aarch64/instructions/ldursb.rb +10 -10
- data/lib/aarch64/instructions/ldursh.rb +10 -10
- data/lib/aarch64/instructions/ldursw.rb +8 -8
- data/lib/aarch64/instructions/ldxp.rb +10 -10
- data/lib/aarch64/instructions/ldxr.rb +8 -8
- data/lib/aarch64/instructions/lslv.rb +10 -10
- data/lib/aarch64/instructions/lsrv.rb +10 -10
- data/lib/aarch64/instructions/madd.rb +12 -12
- data/lib/aarch64/instructions/movk.rb +10 -10
- data/lib/aarch64/instructions/movn.rb +10 -10
- data/lib/aarch64/instructions/movz.rb +10 -10
- data/lib/aarch64/instructions/mrs.rb +14 -14
- data/lib/aarch64/instructions/msr_imm.rb +7 -7
- data/lib/aarch64/instructions/msr_reg.rb +14 -14
- data/lib/aarch64/instructions/msub.rb +12 -12
- data/lib/aarch64/instructions/nop.rb +1 -1
- data/lib/aarch64/instructions/orn_log_shift.rb +14 -14
- data/lib/aarch64/instructions/orr_log_imm.rb +14 -14
- data/lib/aarch64/instructions/orr_log_shift.rb +14 -14
- data/lib/aarch64/instructions/pacda.rb +8 -8
- data/lib/aarch64/instructions/pacdb.rb +8 -8
- data/lib/aarch64/instructions/pacga.rb +8 -8
- data/lib/aarch64/instructions/pacia.rb +8 -8
- data/lib/aarch64/instructions/pacia2.rb +5 -5
- data/lib/aarch64/instructions/pacib.rb +8 -8
- data/lib/aarch64/instructions/prfm_imm.rb +8 -8
- data/lib/aarch64/instructions/prfm_lit.rb +8 -8
- data/lib/aarch64/instructions/prfm_reg.rb +12 -12
- data/lib/aarch64/instructions/prfum.rb +8 -8
- data/lib/aarch64/instructions/psb.rb +2 -9
- data/lib/aarch64/instructions/rbit_int.rb +8 -8
- data/lib/aarch64/instructions/ret.rb +4 -4
- data/lib/aarch64/instructions/reta.rb +3 -3
- data/lib/aarch64/instructions/rev.rb +10 -10
- data/lib/aarch64/instructions/rmif.rb +8 -8
- data/lib/aarch64/instructions/rorv.rb +10 -10
- data/lib/aarch64/instructions/sb.rb +1 -1
- data/lib/aarch64/instructions/sbc.rb +10 -10
- data/lib/aarch64/instructions/sbcs.rb +10 -10
- data/lib/aarch64/instructions/sbfm.rb +13 -13
- data/lib/aarch64/instructions/sdiv.rb +10 -10
- data/lib/aarch64/instructions/setf.rb +6 -6
- data/lib/aarch64/instructions/sev.rb +1 -7
- data/lib/aarch64/instructions/sevl.rb +1 -1
- data/lib/aarch64/instructions/smaddl.rb +10 -10
- data/lib/aarch64/instructions/smc.rb +3 -3
- data/lib/aarch64/instructions/smsubl.rb +10 -10
- data/lib/aarch64/instructions/smulh.rb +8 -8
- data/lib/aarch64/instructions/st2g.rb +10 -10
- data/lib/aarch64/instructions/st64b.rb +6 -6
- data/lib/aarch64/instructions/st64bv.rb +8 -8
- data/lib/aarch64/instructions/st64bv0.rb +8 -8
- data/lib/aarch64/instructions/stg.rb +10 -10
- data/lib/aarch64/instructions/stgm.rb +6 -6
- data/lib/aarch64/instructions/stgp.rb +12 -12
- data/lib/aarch64/instructions/stllr.rb +8 -8
- data/lib/aarch64/instructions/stllrb.rb +6 -6
- data/lib/aarch64/instructions/stllrh.rb +6 -6
- data/lib/aarch64/instructions/stlr.rb +8 -8
- data/lib/aarch64/instructions/stlrb.rb +6 -6
- data/lib/aarch64/instructions/stlrh.rb +6 -6
- data/lib/aarch64/instructions/stlur_gen.rb +10 -10
- data/lib/aarch64/instructions/stlxp.rb +12 -12
- data/lib/aarch64/instructions/stlxr.rb +10 -10
- data/lib/aarch64/instructions/stlxrb.rb +8 -8
- data/lib/aarch64/instructions/stlxrh.rb +8 -8
- data/lib/aarch64/instructions/stnp_gen.rb +12 -12
- data/lib/aarch64/instructions/stp_gen.rb +14 -14
- data/lib/aarch64/instructions/str_imm_gen.rb +12 -12
- data/lib/aarch64/instructions/str_imm_unsigned.rb +10 -10
- data/lib/aarch64/instructions/str_reg_gen.rb +14 -14
- data/lib/aarch64/instructions/strb_imm.rb +10 -10
- data/lib/aarch64/instructions/strb_imm_unsigned.rb +8 -8
- data/lib/aarch64/instructions/strb_reg.rb +12 -12
- data/lib/aarch64/instructions/strh_imm.rb +10 -10
- data/lib/aarch64/instructions/strh_imm_unsigned.rb +8 -8
- data/lib/aarch64/instructions/strh_reg.rb +12 -12
- data/lib/aarch64/instructions/sttr.rb +10 -10
- data/lib/aarch64/instructions/stur_gen.rb +10 -10
- data/lib/aarch64/instructions/stxp.rb +12 -12
- data/lib/aarch64/instructions/stxr.rb +10 -10
- data/lib/aarch64/instructions/stxrb.rb +8 -8
- data/lib/aarch64/instructions/stxrh.rb +8 -8
- data/lib/aarch64/instructions/stz2g.rb +10 -10
- data/lib/aarch64/instructions/stzg.rb +10 -10
- data/lib/aarch64/instructions/stzgm.rb +6 -6
- data/lib/aarch64/instructions/sub_addsub_ext.rb +14 -14
- data/lib/aarch64/instructions/sub_addsub_imm.rb +12 -12
- data/lib/aarch64/instructions/sub_addsub_shift.rb +14 -14
- data/lib/aarch64/instructions/subg.rb +10 -10
- data/lib/aarch64/instructions/subp.rb +8 -8
- data/lib/aarch64/instructions/subps.rb +8 -8
- data/lib/aarch64/instructions/subs_addsub_ext.rb +14 -14
- data/lib/aarch64/instructions/subs_addsub_imm.rb +12 -12
- data/lib/aarch64/instructions/subs_addsub_shift.rb +14 -14
- data/lib/aarch64/instructions/svc.rb +3 -3
- data/lib/aarch64/instructions/swp.rb +14 -14
- data/lib/aarch64/instructions/swpb.rb +12 -12
- data/lib/aarch64/instructions/swph.rb +12 -12
- data/lib/aarch64/instructions/sys.rb +12 -12
- data/lib/aarch64/instructions/sysl.rb +12 -12
- data/lib/aarch64/instructions/tbnz.rb +9 -9
- data/lib/aarch64/instructions/tbz.rb +9 -9
- data/lib/aarch64/instructions/tsb.rb +1 -7
- data/lib/aarch64/instructions/ubfm.rb +13 -13
- data/lib/aarch64/instructions/udf_perm_undef.rb +3 -3
- data/lib/aarch64/instructions/udiv.rb +10 -10
- data/lib/aarch64/instructions/umaddl.rb +10 -10
- data/lib/aarch64/instructions/umsubl.rb +10 -10
- data/lib/aarch64/instructions/umulh.rb +8 -8
- data/lib/aarch64/instructions/wfe.rb +2 -9
- data/lib/aarch64/instructions/wfet.rb +4 -4
- data/lib/aarch64/instructions/wfi.rb +1 -1
- data/lib/aarch64/instructions/wfit.rb +4 -4
- data/lib/aarch64/instructions/xaflag.rb +1 -1
- data/lib/aarch64/instructions/xpac.rb +6 -6
- data/lib/aarch64/instructions/xpaclri.rb +1 -1
- data/lib/aarch64/instructions/yield.rb +2 -9
- data/lib/aarch64/instructions.rb +26 -8
- data/lib/aarch64/parser.rb +227 -0
- data/lib/aarch64/parser.tab.rb +6534 -0
- data/lib/aarch64/parser.y +1394 -0
- data/lib/aarch64/utils.rb +34 -0
- data/lib/aarch64/version.rb +1 -1
- data/lib/aarch64.rb +128 -58
- data/test/base_instructions_test.rb +34 -4
- data/test/helper.rb +48 -8
- data/test/parser_test.rb +1820 -0
- metadata +25 -14
- data/lib/aarch64/instructions/setgp.rb +0 -25
- data/lib/aarch64/instructions/setgpn.rb +0 -25
- data/lib/aarch64/instructions/setgpt.rb +0 -25
- data/lib/aarch64/instructions/setgptn.rb +0 -25
- data/lib/aarch64/instructions/setp.rb +0 -25
- data/lib/aarch64/instructions/setpn.rb +0 -25
- data/lib/aarch64/instructions/setpt.rb +0 -25
- data/lib/aarch64/instructions/setptn.rb +0 -25
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class AArch64::Parser
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rule
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instructions
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: instructions instruction
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| instruction
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;
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instruction
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: insn EOL;
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insn
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: adc
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| adcs
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| ADD add_body { val[1].apply(@asm, val[0]) }
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| ADDS add_body { val[1].apply(@asm, val[0]) }
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| ADR Xd COMMA imm { @asm.adr(val[1], val[3]) }
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| ADRP Xd COMMA imm { @asm.adrp(val[1], val[3]) }
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| AND and_body { val[1].apply(@asm, val[0]) }
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| ANDS and_body { val[1].apply(@asm, val[0]) }
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| asr { val[0].apply(@asm, :asr) }
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| at
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| b
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| bl
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| br
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| BRK imm { @asm.brk(val[1]) }
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| CBNZ reg_imm { val[1].apply(@asm, val[0]) }
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| CBZ reg_imm { val[1].apply(@asm, val[0]) }
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| cinc
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| cinv
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| clrex
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| CLS reg_reg { val[1].apply(@asm, val[0]) }
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| CLZ reg_reg { val[1].apply(@asm, val[0]) }
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| cmn
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| cmp
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| cneg
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| crc32
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| cset
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| dc
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| DCPS1 { @asm.dcps1 }
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| DCPS2 { @asm.dcps2 }
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| DCPS3 { @asm.dcps3 }
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| dmb
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| DRPS { @asm.drps }
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| dsb
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| eor
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| eon
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| ERET { @asm.eret }
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| HINT imm { @asm.hint(val[1]) }
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| HLT imm { @asm.hlt(val[1]) }
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| HVC imm { @asm.hvc(val[1]) }
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| extr
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| ic
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| isb
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| loads
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| mov
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| MOVN movz_body { val[1].apply(@asm, val[0]) }
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| MOVK movz_body { val[1].apply(@asm, val[0]) }
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| NGCS reg_reg { val[1].apply(@asm, val[0]) }
|
82
|
+
| NOP { @asm.nop }
|
83
|
+
| orn
|
84
|
+
| orr
|
85
|
+
| prfm
|
86
|
+
| prfum
|
87
|
+
| PSSBB { @asm.pssbb }
|
88
|
+
| RBIT reg_reg { val[1].apply(@asm, val[0]) }
|
89
|
+
| ret
|
90
|
+
| REV reg_reg { val[1].apply(@asm, val[0]) }
|
91
|
+
| REV16 reg_reg { val[1].apply(@asm, val[0]) }
|
92
|
+
| REV32 xd_xd { val[1].apply(@asm, val[0]) }
|
93
|
+
| ror
|
94
|
+
| SBC reg_reg_reg { val[1].apply(@asm, val[0]) }
|
95
|
+
| SBCS reg_reg_reg { val[1].apply(@asm, val[0]) }
|
96
|
+
| SBFIZ reg_reg_imm_imm { val[1].apply(@asm, val[0]) }
|
97
|
+
| SBFX reg_reg_imm_imm { val[1].apply(@asm, val[0]) }
|
98
|
+
| SDIV reg_reg_reg { val[1].apply(@asm, val[0]) }
|
99
|
+
| SEV { @asm.sev }
|
100
|
+
| SEVL { @asm.sevl }
|
101
|
+
| SMADDL smaddl_params { val[1].apply(@asm, val[0]) }
|
102
|
+
| SMC imm { @asm.smc(val[1]) }
|
103
|
+
| SMNEGL xd_wd_wd { val[1].apply(@asm, val[0]) }
|
104
|
+
| SMSUBL smaddl_params { val[1].apply(@asm, val[0]) }
|
105
|
+
| SMULH xd_xd_xd { val[1].apply(@asm, val[0]) }
|
106
|
+
| SMULL xd_wd_wd { val[1].apply(@asm, val[0]) }
|
107
|
+
| SSBB { @asm.ssbb }
|
108
|
+
| stlr
|
109
|
+
| stlrb
|
110
|
+
| stlrh
|
111
|
+
| STLXP stlxp_body { val[1].apply(@asm, val[0]) }
|
112
|
+
| STLXR stlxr_body { val[1].apply(@asm, val[0]) }
|
113
|
+
| STLXRB wd_wd_read_reg { val[1].apply(@asm, val[0]) }
|
114
|
+
| STLXRH wd_wd_read_reg { val[1].apply(@asm, val[0]) }
|
115
|
+
| stnp
|
116
|
+
| stp
|
117
|
+
| str
|
118
|
+
| strb
|
119
|
+
| strh
|
120
|
+
| sttr
|
121
|
+
| sttrb
|
122
|
+
| sttrh
|
123
|
+
| stur
|
124
|
+
| stxp
|
125
|
+
| stxr
|
126
|
+
| stxrb
|
127
|
+
| stxrh
|
128
|
+
| SUB add_body { val[1].apply(@asm, :sub) }
|
129
|
+
| SUBS add_body { val[1].apply(@asm, :subs) }
|
130
|
+
| SVC imm { @asm.svc val[1] }
|
131
|
+
| SXTB sxtb_body { val[1].apply(@asm, :sxtb) }
|
132
|
+
| SXTH sxtb_body { val[1].apply(@asm, :sxth) }
|
133
|
+
| SXTW xd_wd { val[1].apply(@asm, :sxtw) }
|
134
|
+
| sys
|
135
|
+
| sysl
|
136
|
+
| TBZ reg_imm_imm { val[1].apply(@asm, val[0]) }
|
137
|
+
| TBNZ reg_imm_imm { val[1].apply(@asm, val[0]) }
|
138
|
+
| tlbi
|
139
|
+
| tst
|
140
|
+
| UBFIZ ubfiz_body { val[1].apply(@asm, val[0]) }
|
141
|
+
| UBFX ubfiz_body { val[1].apply(@asm, val[0]) }
|
142
|
+
| UDIV reg_reg_reg { val[1].apply(@asm, val[0]) }
|
143
|
+
| UMADDL xd_wd_wd_xd { val[1].apply(@asm, val[0]) }
|
144
|
+
| UMNEGL xd_wd_wd { val[1].apply(@asm, val[0]) }
|
145
|
+
| UMSUBL xd_wd_wd_xd { val[1].apply(@asm, val[0]) }
|
146
|
+
| UMULH xd_xd_xd { val[1].apply(@asm, val[0]) }
|
147
|
+
| UMULL xd_wd_wd { val[1].apply(@asm, val[0]) }
|
148
|
+
| UXTB wd_wd { val[1].apply(@asm, val[0]) }
|
149
|
+
| UXTH wd_wd { val[1].apply(@asm, val[0]) }
|
150
|
+
| WFE { @asm.wfe }
|
151
|
+
| WFI { @asm.wfi }
|
152
|
+
| YIELD { @asm.yield }
|
153
|
+
;
|
154
|
+
|
155
|
+
adc
|
156
|
+
: ADC reg_reg_reg { val[1].apply(@asm, val[0]) }
|
157
|
+
;
|
158
|
+
|
159
|
+
adcs
|
160
|
+
: ADCS reg_reg_reg { val[1].apply(@asm, val[0]) }
|
161
|
+
;
|
162
|
+
|
163
|
+
add_immediate
|
164
|
+
: WSP COMMA Wd COMMA imm COMMA LSL imm {
|
165
|
+
result = [[val[0], val[2], val[4]], { lsl: val[7] }]
|
166
|
+
}
|
167
|
+
| Wd COMMA Wd COMMA imm COMMA LSL imm {
|
168
|
+
result = [[val[0], val[2], val[4]], { lsl: val[7] }]
|
169
|
+
}
|
170
|
+
| Xd COMMA Xd COMMA imm COMMA LSL imm {
|
171
|
+
result = [[val[0], val[2], val[4]], { lsl: val[7] }]
|
172
|
+
}
|
173
|
+
| Xd COMMA SP COMMA imm COMMA LSL imm {
|
174
|
+
result = [[val[0], val[2], val[4]], { lsl: val[7] }]
|
175
|
+
}
|
176
|
+
| SP COMMA SP COMMA imm COMMA LSL imm {
|
177
|
+
result = [[val[0], val[2], val[4]], { lsl: val[7] }]
|
178
|
+
}
|
179
|
+
| SP COMMA SP COMMA imm {
|
180
|
+
result = [[val[0], val[2], val[4]], { lsl: val[7] }]
|
181
|
+
}
|
182
|
+
;
|
183
|
+
|
184
|
+
add_extended
|
185
|
+
: add_extend extend imm {
|
186
|
+
result = [val[0], { extend: val[1].to_sym, amount: val[2] }]
|
187
|
+
}
|
188
|
+
| add_extend extend {
|
189
|
+
result = [val[0], { extend: val[1].to_sym, amount: 0 }]
|
190
|
+
}
|
191
|
+
| add_extend_with_sp COMMA LSL imm {
|
192
|
+
result = [val[0], { extend: val[2].to_sym, amount: val[3] }]
|
193
|
+
}
|
194
|
+
;
|
195
|
+
|
196
|
+
add_extend
|
197
|
+
: add_extend_with_sp COMMA
|
198
|
+
| add_extend_without_sp
|
199
|
+
;
|
200
|
+
|
201
|
+
add_extend_with_sp
|
202
|
+
: SP COMMA Xd COMMA Wd {
|
203
|
+
result = [val[0], val[2], val[4]]
|
204
|
+
}
|
205
|
+
| SP COMMA Xd COMMA Xd {
|
206
|
+
result = [val[0], val[2], val[4]]
|
207
|
+
}
|
208
|
+
| Xd COMMA SP COMMA Wd {
|
209
|
+
result = [val[0], val[2], val[4]]
|
210
|
+
}
|
211
|
+
| Xd COMMA SP COMMA Xd {
|
212
|
+
result = [val[0], val[2], val[4]]
|
213
|
+
}
|
214
|
+
| WSP COMMA Wd COMMA Wd {
|
215
|
+
result = [val[0], val[2], val[4]]
|
216
|
+
}
|
217
|
+
| Wd COMMA WSP COMMA Wd {
|
218
|
+
result = [val[0], val[2], val[4]]
|
219
|
+
}
|
220
|
+
;
|
221
|
+
|
222
|
+
add_extend_without_sp
|
223
|
+
: Xd COMMA Xd COMMA Wd COMMA {
|
224
|
+
result = [val[0], val[2], val[4]]
|
225
|
+
}
|
226
|
+
| Xd COMMA Xd COMMA Xd COMMA {
|
227
|
+
result = [val[0], val[2], val[4]]
|
228
|
+
}
|
229
|
+
| Wd COMMA Wd COMMA Wd COMMA {
|
230
|
+
result = [val[0], val[2], val[4]]
|
231
|
+
}
|
232
|
+
;
|
233
|
+
|
234
|
+
add_body
|
235
|
+
: shifted { result = val[0] }
|
236
|
+
| add_extended {
|
237
|
+
regs, opts = *val[0]
|
238
|
+
result = ThreeWithExtend.new(*regs, extend: opts[:extend], amount: opts[:amount])
|
239
|
+
}
|
240
|
+
| add_immediate {
|
241
|
+
regs, opts = *val[0]
|
242
|
+
result = ThreeWithLsl.new(*regs, lsl: opts[:lsl])
|
243
|
+
}
|
244
|
+
| reg_reg_imm { result = val[0] }
|
245
|
+
;
|
246
|
+
|
247
|
+
reg_reg_shift
|
248
|
+
: Wd COMMA Wd COMMA shift imm {
|
249
|
+
result = RegRegShift.new(val[0], val[2], shift: val[4], amount: val[5])
|
250
|
+
}
|
251
|
+
| Xd COMMA Xd COMMA shift imm {
|
252
|
+
result = RegRegShift.new(val[0], val[2], shift: val[4], amount: val[5])
|
253
|
+
}
|
254
|
+
;
|
255
|
+
|
256
|
+
reg_reg_reg_shift
|
257
|
+
: Wd COMMA Wd COMMA Wd COMMA shift imm {
|
258
|
+
result = RegsWithShift.new(val[0], val[2], val[4], shift: val[6], amount: val[7])
|
259
|
+
}
|
260
|
+
| Xd COMMA Xd COMMA Xd COMMA shift imm {
|
261
|
+
result = RegsWithShift.new(val[0], val[2], val[4], shift: val[6], amount: val[7])
|
262
|
+
}
|
263
|
+
;
|
264
|
+
|
265
|
+
shifted
|
266
|
+
: reg_reg_reg_shift
|
267
|
+
| reg_reg_reg
|
268
|
+
;
|
269
|
+
|
270
|
+
and_body
|
271
|
+
: reg_reg_imm
|
272
|
+
| shifted
|
273
|
+
;
|
274
|
+
|
275
|
+
asr
|
276
|
+
: ASR reg_reg_reg { result = val[1] }
|
277
|
+
| ASR reg_reg_imm { result = val[1] }
|
278
|
+
;
|
279
|
+
|
280
|
+
at: AT at_op COMMA Xd { @asm.at(val[1].to_sym, val[3]) };
|
281
|
+
|
282
|
+
b
|
283
|
+
: B imm { @asm.b(val[1]) }
|
284
|
+
| B DOT cond imm { @asm.b(val[3], cond: val[2]) }
|
285
|
+
;
|
286
|
+
|
287
|
+
bfi
|
288
|
+
: BFI Wd COMMA Wd COMMA imm COMMA imm {
|
289
|
+
@asm.bfi(val[1], val[3], val[5], val[7])
|
290
|
+
}
|
291
|
+
| BFI Xd COMMA Xd COMMA imm COMMA imm {
|
292
|
+
@asm.bfi(val[1], val[3], val[5], val[7])
|
293
|
+
}
|
294
|
+
;
|
295
|
+
|
296
|
+
bfxil
|
297
|
+
: BFXIL Wd COMMA Wd COMMA imm COMMA imm {
|
298
|
+
@asm.bfxil(val[1], val[3], val[5], val[7])
|
299
|
+
}
|
300
|
+
| BFXIL Xd COMMA Xd COMMA imm COMMA imm {
|
301
|
+
@asm.bfxil(val[1], val[3], val[5], val[7])
|
302
|
+
}
|
303
|
+
;
|
304
|
+
|
305
|
+
bic
|
306
|
+
: BIC shifted { val[1].apply(@asm, :bic) } ;
|
307
|
+
|
308
|
+
bics
|
309
|
+
: BICS shifted { val[1].apply(@asm, :bics) } ;
|
310
|
+
|
311
|
+
autda
|
312
|
+
: AUTDA Xd COMMA Xd { @asm.autda(val[1], val[3]) }
|
313
|
+
| AUTDA Xd COMMA SP { @asm.autda(val[1], val[3]) }
|
314
|
+
;
|
315
|
+
|
316
|
+
bl : BL imm { @asm.bl(val[1]) } ;
|
317
|
+
blr : BLR Xd { @asm.blr(val[1]) } ;
|
318
|
+
br : BR Xd { @asm.br(val[1]) } ;
|
319
|
+
|
320
|
+
cond_four
|
321
|
+
: Wd COMMA imm COMMA imm COMMA cond {
|
322
|
+
result = FourArg.new(val[0], val[2], val[4], val[6])
|
323
|
+
}
|
324
|
+
| Wd COMMA Wd COMMA imm COMMA cond {
|
325
|
+
result = FourArg.new(val[0], val[2], val[4], val[6])
|
326
|
+
}
|
327
|
+
| Xd COMMA imm COMMA imm COMMA cond {
|
328
|
+
result = FourArg.new(val[0], val[2], val[4], val[6])
|
329
|
+
}
|
330
|
+
| Xd COMMA Xd COMMA imm COMMA cond {
|
331
|
+
result = FourArg.new(val[0], val[2], val[4], val[6])
|
332
|
+
}
|
333
|
+
| Wd COMMA Wd COMMA Wd COMMA cond {
|
334
|
+
result = FourArg.new(val[0], val[2], val[4], val[6])
|
335
|
+
}
|
336
|
+
| Xd COMMA Xd COMMA Xd COMMA cond {
|
337
|
+
result = FourArg.new(val[0], val[2], val[4], val[6])
|
338
|
+
}
|
339
|
+
;
|
340
|
+
|
341
|
+
cond_three
|
342
|
+
: Wd COMMA Wd COMMA cond { result = ThreeArg.new(val[0], val[2], val[4]) }
|
343
|
+
| Xd COMMA Xd COMMA cond { result = ThreeArg.new(val[0], val[2], val[4]) }
|
344
|
+
;
|
345
|
+
|
346
|
+
cond_two
|
347
|
+
: Wd COMMA cond { result = TwoArg.new(val[0], val[2]) }
|
348
|
+
| Xd COMMA cond { result = TwoArg.new(val[0], val[2]) }
|
349
|
+
|
350
|
+
cinc : CINC cond_three { val[1].apply(@asm, :cinc) };
|
351
|
+
cinv : CINV cond_three { val[1].apply(@asm, :cinv) };
|
352
|
+
|
353
|
+
clrex
|
354
|
+
: CLREX { @asm.clrex(15) }
|
355
|
+
| CLREX imm { @asm.clrex(val[1]) }
|
356
|
+
;
|
357
|
+
|
358
|
+
cmn_immediate
|
359
|
+
: SP COMMA imm COMMA LSL imm {
|
360
|
+
result = TwoWithLsl.new(val[0], val[2], lsl: val[5])
|
361
|
+
}
|
362
|
+
| WSP COMMA imm COMMA LSL imm {
|
363
|
+
result = TwoWithLsl.new(val[0], val[2], lsl: val[5])
|
364
|
+
}
|
365
|
+
| Wd COMMA imm COMMA LSL imm {
|
366
|
+
result = TwoWithLsl.new(val[0], val[2], lsl: val[5])
|
367
|
+
}
|
368
|
+
| Xd COMMA imm COMMA LSL imm {
|
369
|
+
result = TwoWithLsl.new(val[0], val[2], lsl: val[5])
|
370
|
+
}
|
371
|
+
| WSP COMMA imm {
|
372
|
+
result = TwoArg.new(val[0], val[2])
|
373
|
+
}
|
374
|
+
| Xd COMMA imm {
|
375
|
+
result = TwoArg.new(val[0], val[2])
|
376
|
+
}
|
377
|
+
| Wd COMMA imm {
|
378
|
+
result = TwoArg.new(val[0], val[2])
|
379
|
+
}
|
380
|
+
| SP COMMA imm {
|
381
|
+
result = TwoArg.new(val[0], val[2])
|
382
|
+
}
|
383
|
+
;
|
384
|
+
|
385
|
+
cmn_extend_with_sp
|
386
|
+
: SP COMMA Wd { result = [val[0], val[2]] }
|
387
|
+
| SP COMMA Xd { result = [val[0], val[2]] }
|
388
|
+
| WSP COMMA Wd { result = [val[0], val[2]] }
|
389
|
+
;
|
390
|
+
|
391
|
+
cmn_extend_without_sp
|
392
|
+
: Wd COMMA Wd COMMA { result = [val[0], val[2]] }
|
393
|
+
| Xd COMMA Xd COMMA { result = [val[0], val[2]] }
|
394
|
+
| Xd COMMA Wd COMMA { result = [val[0], val[2]] }
|
395
|
+
;
|
396
|
+
|
397
|
+
cmn_extended
|
398
|
+
: cmn_extend_with_sp COMMA extend {
|
399
|
+
result = TwoWithExtend.new(*val[0], extend: val[2].to_sym, amount: 0)
|
400
|
+
}
|
401
|
+
| cmn_extend_with_sp COMMA extend imm {
|
402
|
+
result = TwoWithExtend.new(*val[0], extend: val[2].to_sym, amount: val[3])
|
403
|
+
}
|
404
|
+
| cmn_extend_with_sp COMMA LSL imm {
|
405
|
+
result = TwoWithExtend.new(*val[0], extend: :lsl, amount: val[3])
|
406
|
+
}
|
407
|
+
| cmn_extend_with_sp {
|
408
|
+
result = TwoWithExtend.new(*val[0], extend: nil, amount: 0)
|
409
|
+
}
|
410
|
+
| cmn_extend_without_sp extend {
|
411
|
+
result = TwoWithExtend.new(*val[0], extend: val[1].to_sym, amount: 0)
|
412
|
+
}
|
413
|
+
| cmn_extend_without_sp extend imm {
|
414
|
+
result = TwoWithExtend.new(*val[0], extend: val[1].to_sym, amount: val[2])
|
415
|
+
}
|
416
|
+
;
|
417
|
+
|
418
|
+
cmn_shift
|
419
|
+
: Wd COMMA Wd { result = TwoWithShift.new(val[0], val[2], shift: :lsl, amount: 0) }
|
420
|
+
| Xd COMMA Xd { result = TwoWithShift.new(val[0], val[2], shift: :lsl, amount: 0) }
|
421
|
+
| Wd COMMA Wd COMMA shift imm {
|
422
|
+
result = TwoWithShift.new(val[0], val[2], shift: val[4], amount: val[5])
|
423
|
+
}
|
424
|
+
| Xd COMMA Xd COMMA shift imm {
|
425
|
+
result = TwoWithShift.new(val[0], val[2], shift: val[4], amount: val[5])
|
426
|
+
}
|
427
|
+
;
|
428
|
+
|
429
|
+
cmn_body
|
430
|
+
: cmn_shift
|
431
|
+
| cmn_immediate
|
432
|
+
| cmn_extended
|
433
|
+
;
|
434
|
+
|
435
|
+
cmn : CMN cmn_body { val[1].apply(@asm, :cmn) }
|
436
|
+
|
437
|
+
cmp : CMP cmn_body { val[1].apply(@asm, :cmp) }
|
438
|
+
|
439
|
+
cneg : CNEG cond_three { val[1].apply(@asm, :cneg) } ;
|
440
|
+
|
441
|
+
crc32w_insns
|
442
|
+
: CRC32B
|
443
|
+
| CRC32H
|
444
|
+
| CRC32W
|
445
|
+
;
|
446
|
+
|
447
|
+
crc32
|
448
|
+
: crc32w_insns wd_wd_wd { val[1].apply(@asm, val[0]) }
|
449
|
+
| CRC32X wd_wd_xd { val[1].apply(@asm, val[0]) }
|
450
|
+
;
|
451
|
+
|
452
|
+
crc32c_insns
|
453
|
+
: CRC32CB
|
454
|
+
| CRC32CH
|
455
|
+
| CRC32CW
|
456
|
+
;
|
457
|
+
|
458
|
+
crc32c
|
459
|
+
: crc32c_insns wd_wd_wd { val[1].apply(@asm, val[0]) }
|
460
|
+
| CRC32CX wd_wd_xd { val[1].apply(@asm, val[0]) }
|
461
|
+
;
|
462
|
+
|
463
|
+
cond_four_instructions
|
464
|
+
: CSINV
|
465
|
+
| CSINC
|
466
|
+
| CSEL
|
467
|
+
| CCMN
|
468
|
+
| CCMP
|
469
|
+
| CSNEG
|
470
|
+
;
|
471
|
+
|
472
|
+
cond_fours
|
473
|
+
: cond_four_instructions cond_four {
|
474
|
+
val[1].apply(@asm, val[0].downcase.to_sym)
|
475
|
+
}
|
476
|
+
;
|
477
|
+
|
478
|
+
cset : CSET cond_two { val[1].apply(@asm, :cset) } ;
|
479
|
+
|
480
|
+
csetm : CSETM cond_two { val[1].apply(@asm, :csetm) } ;
|
481
|
+
|
482
|
+
dc
|
483
|
+
: DC dc_op COMMA xt { @asm.dc(val[1], val[3]) }
|
484
|
+
;
|
485
|
+
|
486
|
+
dmb
|
487
|
+
: DMB imm { @asm.dmb(val[1]) }
|
488
|
+
| DMB dmb_option { @asm.dmb(val[1]) }
|
489
|
+
;
|
490
|
+
|
491
|
+
dsb
|
492
|
+
: DSB imm { @asm.dsb(val[1]) }
|
493
|
+
| DSB dmb_option { @asm.dsb(val[1]) }
|
494
|
+
;
|
495
|
+
|
496
|
+
eor
|
497
|
+
: EOR reg_reg_imm { val[1].apply(@asm, :eor) }
|
498
|
+
| EOR reg_reg_reg { val[1].apply(@asm, val[0]) }
|
499
|
+
| EOR reg_reg_reg_shift { val[1].apply(@asm, val[0]) }
|
500
|
+
;
|
501
|
+
|
502
|
+
eon
|
503
|
+
: EON reg_reg_reg { val[1].apply(@asm, val[0]) }
|
504
|
+
| EON reg_reg_reg_shift { val[1].apply(@asm, val[0]) }
|
505
|
+
;
|
506
|
+
|
507
|
+
extr : EXTR reg_reg_reg_imm { val[1].apply(@asm, :extr) } ;
|
508
|
+
|
509
|
+
ic
|
510
|
+
: IC ic_op { @asm.ic(val[1]) }
|
511
|
+
| IC ic_op COMMA xt { @asm.ic(val[1], val[3]) }
|
512
|
+
;
|
513
|
+
|
514
|
+
isb
|
515
|
+
: ISB { @asm.isb }
|
516
|
+
| ISB imm { @asm.isb(val[1]) }
|
517
|
+
;
|
518
|
+
|
519
|
+
loads
|
520
|
+
: ldaxp
|
521
|
+
| ldnp
|
522
|
+
| ldp
|
523
|
+
| ldpsw
|
524
|
+
| ldr
|
525
|
+
| ldtr
|
526
|
+
| ldxp
|
527
|
+
| ldxr
|
528
|
+
| ldxrb
|
529
|
+
| ldxrh
|
530
|
+
| w_loads
|
531
|
+
| x_loads
|
532
|
+
;
|
533
|
+
|
534
|
+
load_to_w
|
535
|
+
: Wd COMMA read_reg RSQ { result = TwoArg.new(val[0], val[2]) }
|
536
|
+
;
|
537
|
+
|
538
|
+
load_to_x
|
539
|
+
: Xd COMMA read_reg RSQ { result = TwoArg.new(val[0], val[2]) }
|
540
|
+
;
|
541
|
+
|
542
|
+
w_load_insns
|
543
|
+
: LDARB
|
544
|
+
| LDARH
|
545
|
+
| LDAR
|
546
|
+
| LDAXR
|
547
|
+
| LDAXRB
|
548
|
+
| LDAXRH
|
549
|
+
;
|
550
|
+
|
551
|
+
w_loads
|
552
|
+
: w_load_insns load_to_w { val[1].apply(@asm, val[0].to_sym) }
|
553
|
+
;
|
554
|
+
|
555
|
+
x_load_insns
|
556
|
+
: LDAR
|
557
|
+
| LDAXR
|
558
|
+
;
|
559
|
+
|
560
|
+
x_loads
|
561
|
+
: x_load_insns load_to_x { val[1].apply(@asm, val[0].to_sym) }
|
562
|
+
;
|
563
|
+
|
564
|
+
read_reg
|
565
|
+
: LSQ Xd { result = val[1] }
|
566
|
+
| LSQ SP { result = val[1] }
|
567
|
+
;
|
568
|
+
|
569
|
+
read_reg_imm
|
570
|
+
: read_reg COMMA imm { result = [val[0], val[2]] }
|
571
|
+
;
|
572
|
+
|
573
|
+
w_w_load
|
574
|
+
: Wd COMMA Wd COMMA read_reg { result = val.values_at(0, 2, 4) }
|
575
|
+
;
|
576
|
+
|
577
|
+
x_x_load
|
578
|
+
: Xd COMMA Xd COMMA read_reg { result = val.values_at(0, 2, 4) }
|
579
|
+
;
|
580
|
+
|
581
|
+
reg_reg_load
|
582
|
+
: x_x_load RSQ { result = ThreeArg.new(*val[0]) }
|
583
|
+
| w_w_load RSQ { result = ThreeArg.new(*val[0]) }
|
584
|
+
;
|
585
|
+
|
586
|
+
ldaxp
|
587
|
+
: LDAXP reg_reg_load { val[1].apply(@asm, val[0].to_sym) }
|
588
|
+
;
|
589
|
+
|
590
|
+
reg_reg_load_offset
|
591
|
+
: w_w_load COMMA imm RSQ {
|
592
|
+
reg1, reg2, reg3 = *val[0]
|
593
|
+
result = ThreeArg.new(reg1, reg2, [reg3, val[2]])
|
594
|
+
}
|
595
|
+
| x_x_load COMMA imm RSQ {
|
596
|
+
reg1, reg2, reg3 = *val[0]
|
597
|
+
result = ThreeArg.new(reg1, reg2, [reg3, val[2]])
|
598
|
+
}
|
599
|
+
| w_w_load RSQ { result = ThreeArg.new(*val[0].first(2), [val[0].last]) }
|
600
|
+
| x_x_load RSQ { result = ThreeArg.new(*val[0].first(2), [val[0].last]) }
|
601
|
+
;
|
602
|
+
|
603
|
+
ldnp
|
604
|
+
: LDNP reg_reg_load_offset { val[1].apply(@asm, val[0].to_sym) }
|
605
|
+
;
|
606
|
+
|
607
|
+
ldp
|
608
|
+
: LDP ldp_body { val[1].apply(@asm, val[0].to_sym) }
|
609
|
+
;
|
610
|
+
|
611
|
+
ldpsw
|
612
|
+
: LDPSW ldp_body { val[1].apply(@asm, val[0].to_sym) }
|
613
|
+
;
|
614
|
+
|
615
|
+
ldp_body
|
616
|
+
: ldp_signed_offset { result = ThreeArg.new(*val[0]) }
|
617
|
+
| ldp_signed_offset BANG { result = FourArg.new(*val[0], :!) }
|
618
|
+
| reg_reg_load COMMA imm {
|
619
|
+
rt1, rt2, rn = *val[0].to_a
|
620
|
+
result = FourArg.new(rt1, rt2, [rn], val[2])
|
621
|
+
}
|
622
|
+
| reg_reg_load {
|
623
|
+
rt1, rt2, rn = *val[0].to_a
|
624
|
+
result = ThreeArg.new(rt1, rt2, [rn])
|
625
|
+
}
|
626
|
+
;
|
627
|
+
|
628
|
+
ldp_signed_offset
|
629
|
+
: Wd COMMA Wd COMMA read_reg_imm RSQ {
|
630
|
+
result = [val[0], val[2], val[4]]
|
631
|
+
}
|
632
|
+
| Xd COMMA Xd COMMA read_reg_imm RSQ {
|
633
|
+
result = [val[0], val[2], val[4]]
|
634
|
+
}
|
635
|
+
;
|
636
|
+
|
637
|
+
read_reg_reg
|
638
|
+
: read_reg COMMA Xd { result = [val[0], val[2]] }
|
639
|
+
| read_reg COMMA Wd { result = [val[0], val[2]] }
|
640
|
+
;
|
641
|
+
|
642
|
+
read_reg_reg_extend_amount
|
643
|
+
: read_reg_reg COMMA ldr_extend imm {
|
644
|
+
result = [val[0], Shifts::Shift.new(val[3], 0, val[2].to_sym)].flatten
|
645
|
+
}
|
646
|
+
| read_reg_reg COMMA ldr_extend {
|
647
|
+
result = [val[0], Shifts::Shift.new(nil, 0, val[2].to_sym)].flatten
|
648
|
+
}
|
649
|
+
;
|
650
|
+
|
651
|
+
ldr_32
|
652
|
+
: Wd COMMA read_reg_reg_extend_amount RSQ { result = TwoArg.new(val[0], val[2]) }
|
653
|
+
| Wd COMMA read_reg_imm RSQ { result = TwoArg.new(val[0], val[2]) }
|
654
|
+
| Wd COMMA read_reg_imm RSQ BANG { result = ThreeArg.new(val[0], val[2], :!) }
|
655
|
+
| Wd COMMA read_reg RSQ COMMA imm { result = ThreeArg.new(val[0], [val[2]], val[5]) }
|
656
|
+
| Wd COMMA read_reg RSQ { result = TwoArg.new(val[0], [val[2]]) }
|
657
|
+
| Wd COMMA read_reg_reg RSQ { result = TwoArg.new(val[0], val[2]) }
|
658
|
+
| Wd COMMA imm { result = TwoArg.new(val[0], val[2]) }
|
659
|
+
;
|
660
|
+
|
661
|
+
ldr_64
|
662
|
+
: Xd COMMA read_reg_reg_extend_amount RSQ { result = TwoArg.new(val[0], val[2]) }
|
663
|
+
| Xd COMMA read_reg_imm RSQ { result = TwoArg.new(val[0], val[2]) }
|
664
|
+
| Xd COMMA read_reg_imm RSQ BANG { result = ThreeArg.new(val[0], val[2], :!) }
|
665
|
+
| Xd COMMA read_reg RSQ COMMA imm { result = ThreeArg.new(val[0], [val[2]], val[5]) }
|
666
|
+
| Xd COMMA read_reg RSQ { result = TwoArg.new(val[0], [val[2]]) }
|
667
|
+
| Xd COMMA read_reg_reg RSQ { result = TwoArg.new(val[0], val[2]) }
|
668
|
+
| Xd COMMA imm { result = TwoArg.new(val[0], val[2]) }
|
669
|
+
;
|
670
|
+
|
671
|
+
ldr_64s
|
672
|
+
: LDR
|
673
|
+
| LDRSB
|
674
|
+
| LDRSH
|
675
|
+
| LDRSW
|
676
|
+
;
|
677
|
+
|
678
|
+
ldr_32s
|
679
|
+
: LDR
|
680
|
+
| LDRSB
|
681
|
+
| LDRB
|
682
|
+
| LDRH
|
683
|
+
| LDRSH
|
684
|
+
;
|
685
|
+
|
686
|
+
ldr
|
687
|
+
: ldr_32s ldr_32 { val[1].apply(@asm, val[0]) }
|
688
|
+
| ldr_64s ldr_64 { val[1].apply(@asm, val[0]) }
|
689
|
+
;
|
690
|
+
|
691
|
+
ldtr_32
|
692
|
+
: Wd COMMA read_reg_imm RSQ { result = TwoArg.new(val[0], val[2]) }
|
693
|
+
| Wd COMMA read_reg RSQ { result = TwoArg.new(val[0], val[2]) }
|
694
|
+
;
|
695
|
+
|
696
|
+
ldtr_64
|
697
|
+
: Xd COMMA read_reg_imm RSQ { result = TwoArg.new(val[0], val[2]) }
|
698
|
+
| Xd COMMA read_reg RSQ { result = TwoArg.new(val[0], val[2]) }
|
699
|
+
;
|
700
|
+
|
701
|
+
ldtr_32s
|
702
|
+
: LDTR
|
703
|
+
| LDTRB
|
704
|
+
| LDTRH
|
705
|
+
| LDTRSB
|
706
|
+
| LDTRSH
|
707
|
+
| LDUR
|
708
|
+
| LDURB
|
709
|
+
| LDURSB
|
710
|
+
| LDURSH
|
711
|
+
| LDURH
|
712
|
+
;
|
713
|
+
|
714
|
+
ldtr_64s
|
715
|
+
: LDTR
|
716
|
+
| LDTRSB
|
717
|
+
| LDTRSH
|
718
|
+
| LDTRSW
|
719
|
+
| LDUR
|
720
|
+
| LDURSB
|
721
|
+
| LDURSH
|
722
|
+
| LDURSW
|
723
|
+
;
|
724
|
+
|
725
|
+
ldtr
|
726
|
+
: ldtr_32s ldtr_32 { val[1].apply(@asm, val[0]) }
|
727
|
+
| ldtr_64s ldtr_64 { val[1].apply(@asm, val[0]) }
|
728
|
+
;
|
729
|
+
|
730
|
+
ldxp
|
731
|
+
: LDXP Wd COMMA Wd COMMA read_reg RSQ { @asm.ldxp(val[1], val[3], val[5]) }
|
732
|
+
| LDXP Xd COMMA Xd COMMA read_reg RSQ { @asm.ldxp(val[1], val[3], val[5]) }
|
733
|
+
;
|
734
|
+
|
735
|
+
ldxr
|
736
|
+
: LDXR Wd COMMA read_reg RSQ { @asm.ldxr(val[1], val[3]) }
|
737
|
+
| LDXR Xd COMMA read_reg RSQ { @asm.ldxr(val[1], val[3]) }
|
738
|
+
;
|
739
|
+
|
740
|
+
ldxrb
|
741
|
+
: LDXRB Wd COMMA read_reg RSQ { @asm.ldxrb(val[1], val[3]) }
|
742
|
+
;
|
743
|
+
|
744
|
+
ldxrh
|
745
|
+
: LDXRH Wd COMMA read_reg RSQ { @asm.ldxrh(val[1], val[3]) }
|
746
|
+
;
|
747
|
+
|
748
|
+
lsl
|
749
|
+
: LSL reg_reg_reg { val[1].apply(@asm, val[0]) }
|
750
|
+
| LSL reg_reg_imm { val[1].apply(@asm, val[0]) }
|
751
|
+
;
|
752
|
+
|
753
|
+
lsr
|
754
|
+
: LSR reg_reg_reg { val[1].apply(@asm, val[0]) }
|
755
|
+
| LSR reg_reg_imm { val[1].apply(@asm, val[0]) }
|
756
|
+
;
|
757
|
+
|
758
|
+
mov_sp
|
759
|
+
: Xd COMMA SP { result = TwoArg.new(val[0], val[2]) }
|
760
|
+
| SP COMMA Xd { result = TwoArg.new(val[0], val[2]) }
|
761
|
+
| Wd COMMA WSP { result = TwoArg.new(val[0], val[2]) }
|
762
|
+
| WSP COMMA Wd { result = TwoArg.new(val[0], val[2]) }
|
763
|
+
;
|
764
|
+
|
765
|
+
mov
|
766
|
+
: MOV mov_sp { val[1].apply(@asm, val[0]) }
|
767
|
+
| MOV reg_reg { val[1].apply(@asm, val[0]) }
|
768
|
+
| MOV reg_imm { val[1].apply(@asm, val[0]) }
|
769
|
+
;
|
770
|
+
|
771
|
+
movz_body
|
772
|
+
: register COMMA imm { result = TwoArg.new(val[0], val[2]) }
|
773
|
+
| register COMMA imm COMMA LSL imm {
|
774
|
+
result = TwoWithLsl.new(val[0], val[2], lsl: val[5])
|
775
|
+
}
|
776
|
+
;
|
777
|
+
|
778
|
+
msr
|
779
|
+
: MSR SYSTEMREG COMMA Xd {
|
780
|
+
TwoArg.new(val[1], val[3]).apply(@asm, val[0])
|
781
|
+
}
|
782
|
+
;
|
783
|
+
|
784
|
+
mrs
|
785
|
+
: MRS Xd COMMA SYSTEMREG {
|
786
|
+
TwoArg.new(val[1], val[3]).apply(@asm, val[0])
|
787
|
+
}
|
788
|
+
;
|
789
|
+
|
790
|
+
mvn
|
791
|
+
: MVN reg_reg_shift { val[1].apply(@asm, val[0]) }
|
792
|
+
| MVN reg_reg { val[1].apply(@asm, val[0]) }
|
793
|
+
;
|
794
|
+
|
795
|
+
neg
|
796
|
+
: NEG reg_reg_shift { val[1].apply(@asm, val[0]) }
|
797
|
+
| NEG reg_reg { val[1].apply(@asm, val[0]) }
|
798
|
+
;
|
799
|
+
|
800
|
+
negs
|
801
|
+
: NEGS reg_reg_shift { val[1].apply(@asm, val[0]) }
|
802
|
+
| NEGS reg_reg { val[1].apply(@asm, val[0]) }
|
803
|
+
;
|
804
|
+
|
805
|
+
orn
|
806
|
+
: ORN reg_reg_reg { val[1].apply(@asm, val[0]) }
|
807
|
+
| ORN reg_reg_reg_shift { val[1].apply(@asm, val[0]) }
|
808
|
+
;
|
809
|
+
|
810
|
+
orr
|
811
|
+
: ORR reg_reg_imm { val[1].apply(@asm, val[0]) }
|
812
|
+
| ORR reg_reg_reg_shift { val[1].apply(@asm, val[0]) }
|
813
|
+
| ORR reg_reg_reg { val[1].apply(@asm, val[0]) }
|
814
|
+
;
|
815
|
+
|
816
|
+
prfm_register
|
817
|
+
: PRFOP COMMA read_reg_reg_extend_amount RSQ {
|
818
|
+
result = TwoArg.new(val[0].to_sym, val[2])
|
819
|
+
}
|
820
|
+
;
|
821
|
+
|
822
|
+
prfm_imm
|
823
|
+
: PRFOP COMMA read_reg_imm RSQ {
|
824
|
+
result = TwoArg.new(val[0].to_sym, val[2])
|
825
|
+
}
|
826
|
+
| PRFOP COMMA read_reg RSQ {
|
827
|
+
result = TwoArg.new(val[0].to_sym, [val[2]])
|
828
|
+
}
|
829
|
+
| PRFOP COMMA imm {
|
830
|
+
result = TwoArg.new(val[0].to_sym, val[2])
|
831
|
+
}
|
832
|
+
;
|
833
|
+
|
834
|
+
prfm
|
835
|
+
: PRFM prfm_register { val[1].apply(@asm, val[0]) }
|
836
|
+
| PRFM prfm_imm { val[1].apply(@asm, val[0]) }
|
837
|
+
| PRFM imm COMMA read_reg_imm RSQ { TwoArg.new(val[1], val[3]).apply(@asm, val[0]) }
|
838
|
+
;
|
839
|
+
|
840
|
+
prfum
|
841
|
+
: PRFUM prfm_imm { val[1].apply(@asm, val[0]) }
|
842
|
+
;
|
843
|
+
|
844
|
+
ret
|
845
|
+
: RET { @asm.ret }
|
846
|
+
| RET Xd { @asm.ret(val[1]) }
|
847
|
+
;
|
848
|
+
|
849
|
+
ror
|
850
|
+
: ROR reg_reg_reg { val[1].apply(@asm, val[0]) }
|
851
|
+
| ROR reg_reg_imm { val[1].apply(@asm, val[0]) }
|
852
|
+
;
|
853
|
+
|
854
|
+
stlr
|
855
|
+
: STLR Wd COMMA read_reg RSQ { @asm.stlr(val[1], val[3]) }
|
856
|
+
| STLR Xd COMMA read_reg RSQ { @asm.stlr(val[1], val[3]) }
|
857
|
+
;
|
858
|
+
|
859
|
+
stlrb
|
860
|
+
: STLRB Wd COMMA read_reg RSQ { @asm.stlrb(val[1], val[3]) }
|
861
|
+
;
|
862
|
+
|
863
|
+
stlrh
|
864
|
+
: STLRH Wd COMMA read_reg RSQ { @asm.stlrh(val[1], val[3]) }
|
865
|
+
;
|
866
|
+
|
867
|
+
smaddl_params
|
868
|
+
: Xd COMMA Wd COMMA Wd COMMA Xd {
|
869
|
+
result = FourArg.new(*val.values_at(0, 2, 4, 6))
|
870
|
+
}
|
871
|
+
;
|
872
|
+
|
873
|
+
stlxp_body
|
874
|
+
: Wd COMMA Xd COMMA Xd COMMA read_reg RSQ {
|
875
|
+
result = FourArg.new(*val.values_at(0, 2, 4, 6))
|
876
|
+
}
|
877
|
+
| Wd COMMA Wd COMMA Wd COMMA read_reg RSQ {
|
878
|
+
result = FourArg.new(*val.values_at(0, 2, 4, 6))
|
879
|
+
}
|
880
|
+
;
|
881
|
+
|
882
|
+
stlxr_body
|
883
|
+
: wd_wd_read_reg
|
884
|
+
| Wd COMMA Xd COMMA read_reg RSQ {
|
885
|
+
result = ThreeArg.new(*val.values_at(0, 2, 4))
|
886
|
+
}
|
887
|
+
;
|
888
|
+
|
889
|
+
stnp
|
890
|
+
: STNP reg_reg_read_reg_imm RSQ {
|
891
|
+
val[1].apply(@asm, val[0])
|
892
|
+
}
|
893
|
+
;
|
894
|
+
|
895
|
+
stp
|
896
|
+
: STP reg_reg_read_reg_imm RSQ { val[1].apply(@asm, val[0]) }
|
897
|
+
| STP reg_reg_read_reg_imm RSQ BANG {
|
898
|
+
FourArg.new(*val[1].to_a, :!).apply(@asm, val[0])
|
899
|
+
}
|
900
|
+
| STP reg_reg_read_reg RSQ COMMA imm {
|
901
|
+
FourArg.new(*val[1].to_a, val[4]).apply(@asm, val[0])
|
902
|
+
}
|
903
|
+
| STP reg_reg_read_reg RSQ {
|
904
|
+
a, b, c = *val[1].to_a
|
905
|
+
ThreeArg.new(a, b, [c]).apply(@asm, val[0])
|
906
|
+
}
|
907
|
+
;
|
908
|
+
|
909
|
+
str_body
|
910
|
+
: register COMMA read_reg_reg_extend_amount RSQ {
|
911
|
+
result = TwoArg.new(val[0], val[2])
|
912
|
+
}
|
913
|
+
| register COMMA read_reg_imm RSQ {
|
914
|
+
result = TwoArg.new(val[0], val[2])
|
915
|
+
}
|
916
|
+
| register COMMA read_reg_imm RSQ BANG {
|
917
|
+
result = ThreeArg.new(val[0], val[2], :!)
|
918
|
+
}
|
919
|
+
| register COMMA read_reg RSQ COMMA imm {
|
920
|
+
result = ThreeArg.new(val[0], val[2], val[5])
|
921
|
+
}
|
922
|
+
| register COMMA read_reg RSQ {
|
923
|
+
result = TwoArg.new(val[0], [val[2]])
|
924
|
+
}
|
925
|
+
| register COMMA read_reg_reg RSQ {
|
926
|
+
result = TwoArg.new(val[0], val[2])
|
927
|
+
}
|
928
|
+
;
|
929
|
+
|
930
|
+
str
|
931
|
+
: STR str_body { val[1].apply(@asm, val[0]) }
|
932
|
+
;
|
933
|
+
|
934
|
+
strb_body
|
935
|
+
: Wd COMMA read_reg_reg_extend_amount RSQ {
|
936
|
+
result = TwoArg.new(val[0], val[2])
|
937
|
+
}
|
938
|
+
| Wd COMMA read_reg_reg RSQ {
|
939
|
+
result = TwoArg.new(val[0], val[2])
|
940
|
+
}
|
941
|
+
| Wd COMMA read_reg_imm RSQ {
|
942
|
+
result = TwoArg.new(val[0], val[2])
|
943
|
+
}
|
944
|
+
| Wd COMMA read_reg_imm RSQ BANG {
|
945
|
+
result = ThreeArg.new(val[0], val[2], :!)
|
946
|
+
}
|
947
|
+
| Wd COMMA read_reg_imm RSQ COMMA imm {
|
948
|
+
result = ThreeArg.new(val[0], val[2], val[5])
|
949
|
+
}
|
950
|
+
| Wd COMMA read_reg RSQ {
|
951
|
+
result = TwoArg.new(val[0], [val[2]])
|
952
|
+
}
|
953
|
+
| Wd COMMA read_reg RSQ COMMA imm {
|
954
|
+
result = ThreeArg.new(val[0], val[2], val[5])
|
955
|
+
}
|
956
|
+
;
|
957
|
+
|
958
|
+
strb
|
959
|
+
: STRB strb_body { val[1].apply(@asm, val[0]) }
|
960
|
+
;
|
961
|
+
|
962
|
+
strh
|
963
|
+
: STRH strb_body { val[1].apply(@asm, val[0]) }
|
964
|
+
;
|
965
|
+
|
966
|
+
strr_32
|
967
|
+
: Wd COMMA read_reg RSQ { result = TwoArg.new(val[0], [val[2]]) }
|
968
|
+
| Wd COMMA read_reg_imm RSQ { result = TwoArg.new(val[0], val[2]) }
|
969
|
+
;
|
970
|
+
|
971
|
+
strr_64
|
972
|
+
: Xd COMMA read_reg RSQ { result = TwoArg.new(val[0], [val[2]]) }
|
973
|
+
| Xd COMMA read_reg_imm RSQ { result = TwoArg.new(val[0], val[2]) }
|
974
|
+
;
|
975
|
+
|
976
|
+
sttr
|
977
|
+
: STTR strr_32 { val[1].apply(@asm, val[0]) }
|
978
|
+
| STTR strr_64 { val[1].apply(@asm, val[0]) }
|
979
|
+
;
|
980
|
+
|
981
|
+
sttrb : STTRB strr_32 { val[1].apply(@asm, val[0]) };
|
982
|
+
|
983
|
+
sttrh : STTRH strr_32 { val[1].apply(@asm, val[0]) };
|
984
|
+
|
985
|
+
stur
|
986
|
+
: STUR strr_32 { val[1].apply(@asm, val[0]) }
|
987
|
+
| STUR strr_64 { val[1].apply(@asm, val[0]) }
|
988
|
+
| STURH strr_32 { val[1].apply(@asm, val[0]) }
|
989
|
+
| STURB strr_32 { val[1].apply(@asm, val[0]) }
|
990
|
+
;
|
991
|
+
|
992
|
+
stxp
|
993
|
+
: STXP wd_wd_wd COMMA read_reg RSQ {
|
994
|
+
FourArg.new(*val[1].to_a, val[3]).apply(@asm, val[0])
|
995
|
+
}
|
996
|
+
| STXP wd_xd_xd COMMA read_reg RSQ {
|
997
|
+
FourArg.new(*val[1].to_a, val[3]).apply(@asm, val[0])
|
998
|
+
}
|
999
|
+
;
|
1000
|
+
|
1001
|
+
stxr
|
1002
|
+
: STXR wd_wd COMMA read_reg RSQ {
|
1003
|
+
ThreeArg.new(*val[1].to_a, val[3]).apply(@asm, val[0])
|
1004
|
+
}
|
1005
|
+
| STXR wd_xd COMMA read_reg RSQ {
|
1006
|
+
ThreeArg.new(*val[1].to_a, val[3]).apply(@asm, val[0])
|
1007
|
+
}
|
1008
|
+
;
|
1009
|
+
|
1010
|
+
stxrb
|
1011
|
+
: STXRB wd_wd COMMA read_reg RSQ {
|
1012
|
+
ThreeArg.new(*val[1].to_a, val[3]).apply(@asm, val[0])
|
1013
|
+
}
|
1014
|
+
;
|
1015
|
+
|
1016
|
+
stxrh
|
1017
|
+
: STXRH wd_wd COMMA read_reg RSQ {
|
1018
|
+
ThreeArg.new(*val[1].to_a, val[3]).apply(@asm, val[0])
|
1019
|
+
}
|
1020
|
+
;
|
1021
|
+
|
1022
|
+
sxtb_body
|
1023
|
+
: wd_wd
|
1024
|
+
| xd_wd
|
1025
|
+
;
|
1026
|
+
|
1027
|
+
sys
|
1028
|
+
: SYS imm COMMA Cd COMMA Cd COMMA imm {
|
1029
|
+
@asm.sys(val[1], val[3], val[5], val[7])
|
1030
|
+
}
|
1031
|
+
| SYS imm COMMA Cd COMMA Cd COMMA imm COMMA Xd {
|
1032
|
+
@asm.sys(val[1], val[3], val[5], val[7], val[9])
|
1033
|
+
}
|
1034
|
+
;
|
1035
|
+
sysl
|
1036
|
+
: SYSL Xd COMMA imm COMMA Cd COMMA Cd COMMA imm {
|
1037
|
+
@asm.sysl(val[1], val[3], val[5], val[7], val[9])
|
1038
|
+
}
|
1039
|
+
;
|
1040
|
+
|
1041
|
+
reg_imm_imm
|
1042
|
+
: Xd COMMA imm COMMA imm {
|
1043
|
+
result = ThreeArg.new(val[0], val[2], val[4])
|
1044
|
+
}
|
1045
|
+
| Wd COMMA imm COMMA imm {
|
1046
|
+
result = ThreeArg.new(val[0], val[2], val[4])
|
1047
|
+
}
|
1048
|
+
;
|
1049
|
+
|
1050
|
+
tlbi
|
1051
|
+
: TLBI tlbi_op { @asm.tlbi(val[1].to_sym) }
|
1052
|
+
| TLBI tlbi_op COMMA Xd { @asm.tlbi(val[1].to_sym, val[3]) }
|
1053
|
+
;
|
1054
|
+
|
1055
|
+
tst
|
1056
|
+
: TST reg_imm { val[1].apply(@asm, val[0]) }
|
1057
|
+
| TST reg_reg_shift { val[1].apply(@asm, val[0]) }
|
1058
|
+
| TST reg_reg { val[1].apply(@asm, val[0]) }
|
1059
|
+
;
|
1060
|
+
|
1061
|
+
ubfiz_body
|
1062
|
+
: Wd COMMA Wd COMMA imm COMMA imm {
|
1063
|
+
result = FourArg.new(*val.values_at(0, 2, 4, 6))
|
1064
|
+
}
|
1065
|
+
| Xd COMMA Xd COMMA imm COMMA imm {
|
1066
|
+
result = FourArg.new(*val.values_at(0, 2, 4, 6))
|
1067
|
+
}
|
1068
|
+
;
|
1069
|
+
|
1070
|
+
xd_wd_wd_xd
|
1071
|
+
: Xd COMMA Wd COMMA Wd COMMA Xd {
|
1072
|
+
result = FourArg.new(*val.values_at(0, 2, 4, 6))
|
1073
|
+
}
|
1074
|
+
;
|
1075
|
+
|
1076
|
+
wd_wd_read_reg
|
1077
|
+
: Wd COMMA Wd COMMA read_reg RSQ {
|
1078
|
+
result = ThreeArg.new(*val.values_at(0, 2, 4))
|
1079
|
+
}
|
1080
|
+
;
|
1081
|
+
|
1082
|
+
reg_reg_read_reg
|
1083
|
+
: Wd COMMA Wd COMMA read_reg {
|
1084
|
+
result = ThreeArg.new(*val.values_at(0, 2, 4))
|
1085
|
+
}
|
1086
|
+
| Xd COMMA Xd COMMA read_reg {
|
1087
|
+
result = ThreeArg.new(*val.values_at(0, 2, 4))
|
1088
|
+
}
|
1089
|
+
;
|
1090
|
+
|
1091
|
+
reg_reg_read_reg_imm
|
1092
|
+
: wd_wd_read_reg_imm
|
1093
|
+
| xd_xd_read_reg_imm
|
1094
|
+
;
|
1095
|
+
|
1096
|
+
wd_wd_read_reg_imm
|
1097
|
+
: Wd COMMA Wd COMMA read_reg_imm {
|
1098
|
+
result = ThreeArg.new(*val.values_at(0, 2, 4))
|
1099
|
+
}
|
1100
|
+
;
|
1101
|
+
|
1102
|
+
xd_xd_read_reg_imm
|
1103
|
+
: Xd COMMA Xd COMMA read_reg_imm {
|
1104
|
+
result = ThreeArg.new(*val.values_at(0, 2, 4))
|
1105
|
+
}
|
1106
|
+
;
|
1107
|
+
|
1108
|
+
xd_wd_wd
|
1109
|
+
: Xd COMMA Wd COMMA Wd {
|
1110
|
+
result = ThreeArg.new(*val.values_at(0, 2, 4))
|
1111
|
+
}
|
1112
|
+
;
|
1113
|
+
|
1114
|
+
xd_wd
|
1115
|
+
: Xd COMMA Wd {
|
1116
|
+
result = TwoArg.new(*val.values_at(0, 2))
|
1117
|
+
}
|
1118
|
+
;
|
1119
|
+
|
1120
|
+
reg_reg_imm_imm
|
1121
|
+
: Wd COMMA Wd COMMA imm COMMA imm {
|
1122
|
+
result = FourArg.new(*val.values_at(0, 2, 4, 6))
|
1123
|
+
}
|
1124
|
+
| Xd COMMA Xd COMMA imm COMMA imm {
|
1125
|
+
result = FourArg.new(*val.values_at(0, 2, 4, 6))
|
1126
|
+
}
|
1127
|
+
;
|
1128
|
+
|
1129
|
+
shift
|
1130
|
+
: LSL { result = val[0].to_sym }
|
1131
|
+
| LSR { result = val[0].to_sym }
|
1132
|
+
| ASR { result = val[0].to_sym }
|
1133
|
+
| ROR { result = val[0].to_sym }
|
1134
|
+
;
|
1135
|
+
|
1136
|
+
register
|
1137
|
+
: Xd
|
1138
|
+
| Wd
|
1139
|
+
;
|
1140
|
+
|
1141
|
+
xd_xd : Xd COMMA Xd { result = TwoArg.new(val[0], val[2]) };
|
1142
|
+
|
1143
|
+
reg_reg
|
1144
|
+
: Wd COMMA Wd { result = TwoArg.new(val[0], val[2]) }
|
1145
|
+
| xd_xd
|
1146
|
+
;
|
1147
|
+
|
1148
|
+
xd_xd_xd
|
1149
|
+
: Xd COMMA Xd COMMA Xd { result = ThreeArg.new(val[0], val[2], val[4]) }
|
1150
|
+
;
|
1151
|
+
|
1152
|
+
wd_wd_wd
|
1153
|
+
: Wd COMMA Wd COMMA Wd { result = ThreeArg.new(val[0], val[2], val[4]) }
|
1154
|
+
;
|
1155
|
+
|
1156
|
+
wd_wd_xd
|
1157
|
+
: Wd COMMA Wd COMMA Xd { result = ThreeArg.new(val[0], val[2], val[4]) }
|
1158
|
+
;
|
1159
|
+
|
1160
|
+
wd_wd
|
1161
|
+
: Wd COMMA Wd { result = TwoArg.new(val[0], val[2]) }
|
1162
|
+
;
|
1163
|
+
|
1164
|
+
wd_xd
|
1165
|
+
: Wd COMMA Xd { result = TwoArg.new(val[0], val[2]) }
|
1166
|
+
;
|
1167
|
+
|
1168
|
+
wd_xd_xd
|
1169
|
+
: Wd COMMA Xd COMMA Xd { result = ThreeArg.new(val[0], val[2], val[4]) }
|
1170
|
+
;
|
1171
|
+
|
1172
|
+
reg_reg_reg
|
1173
|
+
: wd_wd_wd
|
1174
|
+
| xd_xd_xd
|
1175
|
+
;
|
1176
|
+
|
1177
|
+
reg_reg_reg_reg
|
1178
|
+
: Wd COMMA Wd COMMA Wd COMMA Wd { result = FourArg.new(val[0], val[2], val[4], val[6]) }
|
1179
|
+
| Xd COMMA Xd COMMA Xd COMMA Xd { result = FourArg.new(val[0], val[2], val[4], val[6]) }
|
1180
|
+
;
|
1181
|
+
|
1182
|
+
reg_imm
|
1183
|
+
: Wd COMMA imm { result = TwoArg.new(val[0], val[2]) }
|
1184
|
+
| Xd COMMA imm { result = TwoArg.new(val[0], val[2]) }
|
1185
|
+
;
|
1186
|
+
|
1187
|
+
reg_reg_imm
|
1188
|
+
: Wd COMMA Wd COMMA imm {
|
1189
|
+
result = ThreeArg.new(val[0], val[2], val[4])
|
1190
|
+
}
|
1191
|
+
| Xd COMMA Xd COMMA imm {
|
1192
|
+
result = ThreeArg.new(val[0], val[2], val[4])
|
1193
|
+
}
|
1194
|
+
| Xd COMMA SP COMMA imm {
|
1195
|
+
result = ThreeArg.new(val[0], val[2], val[4])
|
1196
|
+
}
|
1197
|
+
| SP COMMA Xd COMMA imm {
|
1198
|
+
result = ThreeArg.new(val[0], val[2], val[4])
|
1199
|
+
}
|
1200
|
+
| WSP COMMA Wd COMMA imm {
|
1201
|
+
result = ThreeArg.new(val[0], val[2], val[4])
|
1202
|
+
}
|
1203
|
+
| Wd COMMA WSP COMMA imm {
|
1204
|
+
result = ThreeArg.new(val[0], val[2], val[4])
|
1205
|
+
}
|
1206
|
+
| WSP COMMA WSP COMMA imm {
|
1207
|
+
result = ThreeArg.new(val[0], val[2], val[4])
|
1208
|
+
}
|
1209
|
+
;
|
1210
|
+
|
1211
|
+
reg_reg_reg_imm
|
1212
|
+
: Wd COMMA Wd COMMA Wd COMMA imm {
|
1213
|
+
result = FourArg.new(val[0], val[2], val[4], val[6])
|
1214
|
+
}
|
1215
|
+
| Xd COMMA Xd COMMA Xd COMMA imm {
|
1216
|
+
result = FourArg.new(val[0], val[2], val[4], val[6])
|
1217
|
+
}
|
1218
|
+
;
|
1219
|
+
|
1220
|
+
imm
|
1221
|
+
: '#' NUMBER { result = val[1] }
|
1222
|
+
| NUMBER { result = val[0] }
|
1223
|
+
;
|
1224
|
+
|
1225
|
+
xt: Xd | XZR;
|
1226
|
+
|
1227
|
+
cond : EQ | LO | LT | HS | GT | LE | NE | MI | GE | PL | LS | HI | VC | VS;
|
1228
|
+
|
1229
|
+
extend
|
1230
|
+
: UXTB
|
1231
|
+
| UXTH
|
1232
|
+
| UXTW
|
1233
|
+
| UXTX
|
1234
|
+
| SXTB
|
1235
|
+
| SXTH
|
1236
|
+
| SXTW
|
1237
|
+
| SXTX
|
1238
|
+
;
|
1239
|
+
|
1240
|
+
ldr_extend
|
1241
|
+
: LSL
|
1242
|
+
| UXTW
|
1243
|
+
| SXTW
|
1244
|
+
| SXTX
|
1245
|
+
;
|
1246
|
+
|
1247
|
+
dc_op
|
1248
|
+
: IVAC
|
1249
|
+
| ISW
|
1250
|
+
| IGVAC
|
1251
|
+
| IGSW
|
1252
|
+
| IGDVAC
|
1253
|
+
| IGDSW
|
1254
|
+
| CSW
|
1255
|
+
| CGSW
|
1256
|
+
| CGDSW
|
1257
|
+
| CISW
|
1258
|
+
| CIGSW
|
1259
|
+
| CIGDSW
|
1260
|
+
| ZVA
|
1261
|
+
| GVA
|
1262
|
+
| GZVA
|
1263
|
+
| CVAC
|
1264
|
+
| CGVAC
|
1265
|
+
| CGDVAC
|
1266
|
+
| CVAU
|
1267
|
+
| CVAP
|
1268
|
+
| CGVAP
|
1269
|
+
| CGDVAP
|
1270
|
+
| CVADP
|
1271
|
+
| CGVADP
|
1272
|
+
| CGDVADP
|
1273
|
+
| CIVAC
|
1274
|
+
| CIGVAC
|
1275
|
+
| CIGDVAC
|
1276
|
+
;
|
1277
|
+
ic_op
|
1278
|
+
: IALLUIS
|
1279
|
+
| IALLU
|
1280
|
+
| IVAU
|
1281
|
+
;
|
1282
|
+
|
1283
|
+
at_op
|
1284
|
+
: S1E1R
|
1285
|
+
| S1E1W
|
1286
|
+
| S1E0R
|
1287
|
+
| S1E0W
|
1288
|
+
| S1E1RP
|
1289
|
+
| S1E1WP
|
1290
|
+
| S1E2R
|
1291
|
+
| S1E2W
|
1292
|
+
| S12E1R
|
1293
|
+
| S12E1W
|
1294
|
+
| S12E0R
|
1295
|
+
| S12E0W
|
1296
|
+
| S1E3R
|
1297
|
+
| S1E3W
|
1298
|
+
;
|
1299
|
+
|
1300
|
+
dmb_option
|
1301
|
+
: OSHLD
|
1302
|
+
| OSHST
|
1303
|
+
| OSH
|
1304
|
+
| NSHLD
|
1305
|
+
| NSHST
|
1306
|
+
| NSH
|
1307
|
+
| ISHLD
|
1308
|
+
| ISHST
|
1309
|
+
| ISH
|
1310
|
+
| LD
|
1311
|
+
| ST
|
1312
|
+
| SY
|
1313
|
+
;
|
1314
|
+
|
1315
|
+
tlbi_op
|
1316
|
+
: VMALLE1OS
|
1317
|
+
| VAE1OS
|
1318
|
+
| ASIDE1OS
|
1319
|
+
| VAAE1OS
|
1320
|
+
| VALE1OS
|
1321
|
+
| VAALE1OS
|
1322
|
+
| RVAE1IS
|
1323
|
+
| RVAAE1IS
|
1324
|
+
| RVALE1IS
|
1325
|
+
| RVAALE1IS
|
1326
|
+
| VMALLE1IS
|
1327
|
+
| VAE1IS
|
1328
|
+
| ASIDE1IS
|
1329
|
+
| VAAE1IS
|
1330
|
+
| VALE1IS
|
1331
|
+
| VAALE1IS
|
1332
|
+
| RVAE1OS
|
1333
|
+
| RVAAE1OS
|
1334
|
+
| RVALE1OS
|
1335
|
+
| RVAALE1OS
|
1336
|
+
| RVAE1
|
1337
|
+
| RVAAE1
|
1338
|
+
| RVALE1
|
1339
|
+
| RVAALE1
|
1340
|
+
| VMALLE1
|
1341
|
+
| VAE1
|
1342
|
+
| ASIDE1
|
1343
|
+
| VAAE1
|
1344
|
+
| VALE1
|
1345
|
+
| VAALE1
|
1346
|
+
| IPAS2E1IS
|
1347
|
+
| RIPAS2E1IS
|
1348
|
+
| IPAS2LE1IS
|
1349
|
+
| RIPAS2LE1IS
|
1350
|
+
| ALLE2OS
|
1351
|
+
| VAE2OS
|
1352
|
+
| ALLE1OS
|
1353
|
+
| VALE2OS
|
1354
|
+
| VMALLS12E1OS
|
1355
|
+
| RVAE2IS
|
1356
|
+
| RVALE2IS
|
1357
|
+
| ALLE2IS
|
1358
|
+
| VAE2IS
|
1359
|
+
| ALLE1IS
|
1360
|
+
| VALE2IS
|
1361
|
+
| VMALLS12E1IS
|
1362
|
+
| IPAS2E1OS
|
1363
|
+
| IPAS2E1
|
1364
|
+
| RIPAS2E1
|
1365
|
+
| RIPAS2E1OS
|
1366
|
+
| IPAS2LE1OS
|
1367
|
+
| IPAS2LE1
|
1368
|
+
| RIPAS2LE1
|
1369
|
+
| RIPAS2LE1OS
|
1370
|
+
| RVAE2OS
|
1371
|
+
| RVALE2OS
|
1372
|
+
| RVAE2
|
1373
|
+
| RVALE2
|
1374
|
+
| ALLE2
|
1375
|
+
| VAE2
|
1376
|
+
| ALLE1
|
1377
|
+
| VALE2
|
1378
|
+
| VMALLS12E1
|
1379
|
+
| ALLE3OS
|
1380
|
+
| VAE3OS
|
1381
|
+
| VALE3OS
|
1382
|
+
| RVAE3IS
|
1383
|
+
| RVALE3IS
|
1384
|
+
| ALLE3IS
|
1385
|
+
| VAE3IS
|
1386
|
+
| VALE3IS
|
1387
|
+
| RVAE3OS
|
1388
|
+
| RVALE3OS
|
1389
|
+
| RVAE3
|
1390
|
+
| RVALE3
|
1391
|
+
| ALLE3
|
1392
|
+
| VAE3
|
1393
|
+
| VALE3
|
1394
|
+
;
|