aarch64 1.0.1 → 2.0.0
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- checksums.yaml +4 -4
- data/README.md +1 -1
- data/Rakefile +37 -0
- data/aarch64.gemspec +1 -0
- data/lib/aarch64/instructions/adc.rb +10 -10
- data/lib/aarch64/instructions/adcs.rb +10 -10
- data/lib/aarch64/instructions/add_addsub_ext.rb +14 -14
- data/lib/aarch64/instructions/add_addsub_imm.rb +12 -12
- data/lib/aarch64/instructions/add_addsub_shift.rb +14 -14
- data/lib/aarch64/instructions/addg.rb +10 -10
- data/lib/aarch64/instructions/adds_addsub_ext.rb +14 -14
- data/lib/aarch64/instructions/adds_addsub_imm.rb +12 -12
- data/lib/aarch64/instructions/adds_addsub_shift.rb +14 -14
- data/lib/aarch64/instructions/adr.rb +7 -7
- data/lib/aarch64/instructions/adrp.rb +7 -7
- data/lib/aarch64/instructions/and_log_imm.rb +14 -14
- data/lib/aarch64/instructions/and_log_shift.rb +14 -14
- data/lib/aarch64/instructions/ands_log_imm.rb +14 -14
- data/lib/aarch64/instructions/ands_log_shift.rb +14 -14
- data/lib/aarch64/instructions/asrv.rb +10 -10
- data/lib/aarch64/instructions/autda.rb +9 -12
- data/lib/aarch64/instructions/autdb.rb +9 -12
- data/lib/aarch64/instructions/autia.rb +9 -12
- data/lib/aarch64/instructions/autib.rb +9 -12
- data/lib/aarch64/instructions/axflag.rb +1 -1
- data/lib/aarch64/instructions/b_cond.rb +5 -5
- data/lib/aarch64/instructions/b_uncond.rb +3 -3
- data/lib/aarch64/instructions/bc_cond.rb +5 -5
- data/lib/aarch64/instructions/bfm.rb +13 -13
- data/lib/aarch64/instructions/bic_log_shift.rb +14 -14
- data/lib/aarch64/instructions/bics.rb +14 -14
- data/lib/aarch64/instructions/bl.rb +3 -3
- data/lib/aarch64/instructions/blr.rb +4 -4
- data/lib/aarch64/instructions/blra.rb +10 -10
- data/lib/aarch64/instructions/br.rb +4 -4
- data/lib/aarch64/instructions/bra.rb +10 -10
- data/lib/aarch64/instructions/brk.rb +3 -3
- data/lib/aarch64/instructions/bti.rb +3 -3
- data/lib/aarch64/instructions/cas.rb +14 -14
- data/lib/aarch64/instructions/casb.rb +12 -12
- data/lib/aarch64/instructions/cash.rb +12 -12
- data/lib/aarch64/instructions/casp.rb +14 -14
- data/lib/aarch64/instructions/cbnz.rb +7 -7
- data/lib/aarch64/instructions/cbz.rb +7 -7
- data/lib/aarch64/instructions/ccmn_imm.rb +12 -12
- data/lib/aarch64/instructions/ccmn_reg.rb +12 -12
- data/lib/aarch64/instructions/ccmp_imm.rb +12 -12
- data/lib/aarch64/instructions/ccmp_reg.rb +12 -12
- data/lib/aarch64/instructions/cfinv.rb +2 -9
- data/lib/aarch64/instructions/clrex.rb +3 -3
- data/lib/aarch64/instructions/cls_int.rb +8 -8
- data/lib/aarch64/instructions/clz_int.rb +8 -8
- data/lib/aarch64/instructions/crc32.rb +12 -12
- data/lib/aarch64/instructions/crc32c.rb +12 -12
- data/lib/aarch64/instructions/csdb.rb +1 -1
- data/lib/aarch64/instructions/csel.rb +12 -12
- data/lib/aarch64/instructions/csinc.rb +12 -12
- data/lib/aarch64/instructions/csinv.rb +12 -12
- data/lib/aarch64/instructions/csneg.rb +12 -12
- data/lib/aarch64/instructions/dcps.rb +5 -5
- data/lib/aarch64/instructions/dgh.rb +1 -1
- data/lib/aarch64/instructions/dmb.rb +3 -3
- data/lib/aarch64/instructions/drps.rb +2 -9
- data/lib/aarch64/instructions/dsb.rb +3 -3
- data/lib/aarch64/instructions/eon.rb +14 -14
- data/lib/aarch64/instructions/eor_log_imm.rb +14 -14
- data/lib/aarch64/instructions/eor_log_shift.rb +14 -14
- data/lib/aarch64/instructions/eret.rb +2 -9
- data/lib/aarch64/instructions/ereta.rb +3 -3
- data/lib/aarch64/instructions/esb.rb +1 -1
- data/lib/aarch64/instructions/extr.rb +13 -13
- data/lib/aarch64/instructions/gmi.rb +8 -8
- data/lib/aarch64/instructions/hint.rb +5 -5
- data/lib/aarch64/instructions/hlt.rb +3 -3
- data/lib/aarch64/instructions/hvc.rb +3 -3
- data/lib/aarch64/instructions/irg.rb +8 -8
- data/lib/aarch64/instructions/isb.rb +3 -3
- data/lib/aarch64/instructions/ld64b.rb +6 -6
- data/lib/aarch64/instructions/ldadd.rb +14 -14
- data/lib/aarch64/instructions/ldaddb.rb +12 -12
- data/lib/aarch64/instructions/ldaddh.rb +12 -12
- data/lib/aarch64/instructions/ldapr.rb +8 -8
- data/lib/aarch64/instructions/ldaprb.rb +6 -6
- data/lib/aarch64/instructions/ldaprh.rb +6 -6
- data/lib/aarch64/instructions/ldapur_gen.rb +12 -12
- data/lib/aarch64/instructions/ldar.rb +8 -8
- data/lib/aarch64/instructions/ldaxp.rb +10 -10
- data/lib/aarch64/instructions/ldaxr.rb +8 -8
- data/lib/aarch64/instructions/ldclr.rb +14 -14
- data/lib/aarch64/instructions/ldclrb.rb +14 -14
- data/lib/aarch64/instructions/ldeor.rb +14 -14
- data/lib/aarch64/instructions/ldg.rb +8 -8
- data/lib/aarch64/instructions/ldgm.rb +6 -6
- data/lib/aarch64/instructions/ldlar.rb +8 -8
- data/lib/aarch64/instructions/ldnp_gen.rb +12 -12
- data/lib/aarch64/instructions/ldp_gen.rb +14 -14
- data/lib/aarch64/instructions/ldpsw.rb +12 -12
- data/lib/aarch64/instructions/ldr_imm_gen.rb +12 -12
- data/lib/aarch64/instructions/ldr_imm_unsigned.rb +10 -10
- data/lib/aarch64/instructions/ldr_lit_gen.rb +7 -7
- data/lib/aarch64/instructions/ldr_reg_gen.rb +14 -14
- data/lib/aarch64/instructions/ldra.rb +14 -14
- data/lib/aarch64/instructions/ldrb_imm.rb +10 -10
- data/lib/aarch64/instructions/ldrb_reg.rb +12 -12
- data/lib/aarch64/instructions/ldrb_unsigned.rb +8 -8
- data/lib/aarch64/instructions/ldrh_imm.rb +10 -10
- data/lib/aarch64/instructions/ldrh_reg.rb +12 -12
- data/lib/aarch64/instructions/ldrh_unsigned.rb +8 -8
- data/lib/aarch64/instructions/ldrsb_imm.rb +12 -12
- data/lib/aarch64/instructions/ldrsb_reg.rb +14 -14
- data/lib/aarch64/instructions/ldrsb_unsigned.rb +10 -10
- data/lib/aarch64/instructions/ldrsh_imm.rb +12 -12
- data/lib/aarch64/instructions/ldrsh_reg.rb +14 -14
- data/lib/aarch64/instructions/ldrsh_unsigned.rb +10 -10
- data/lib/aarch64/instructions/ldrsw_imm.rb +10 -10
- data/lib/aarch64/instructions/ldrsw_lit.rb +5 -5
- data/lib/aarch64/instructions/ldrsw_reg.rb +12 -12
- data/lib/aarch64/instructions/ldrsw_unsigned.rb +8 -8
- data/lib/aarch64/instructions/ldset.rb +14 -14
- data/lib/aarch64/instructions/ldsetb.rb +12 -12
- data/lib/aarch64/instructions/ldseth.rb +12 -12
- data/lib/aarch64/instructions/ldsmax.rb +14 -14
- data/lib/aarch64/instructions/ldsmaxb.rb +12 -12
- data/lib/aarch64/instructions/ldsmaxh.rb +12 -12
- data/lib/aarch64/instructions/ldsmin.rb +14 -14
- data/lib/aarch64/instructions/ldsminb.rb +12 -12
- data/lib/aarch64/instructions/ldsminh.rb +12 -12
- data/lib/aarch64/instructions/ldtr.rb +10 -10
- data/lib/aarch64/instructions/ldtrb.rb +8 -8
- data/lib/aarch64/instructions/ldtrh.rb +8 -8
- data/lib/aarch64/instructions/ldtrsb.rb +10 -10
- data/lib/aarch64/instructions/ldtrsh.rb +10 -10
- data/lib/aarch64/instructions/ldtrsw.rb +8 -8
- data/lib/aarch64/instructions/ldumax.rb +14 -14
- data/lib/aarch64/instructions/ldumaxb.rb +12 -12
- data/lib/aarch64/instructions/ldumaxh.rb +12 -12
- data/lib/aarch64/instructions/ldumin.rb +14 -14
- data/lib/aarch64/instructions/lduminb.rb +12 -12
- data/lib/aarch64/instructions/lduminh.rb +12 -12
- data/lib/aarch64/instructions/ldur_gen.rb +10 -10
- data/lib/aarch64/instructions/ldursb.rb +10 -10
- data/lib/aarch64/instructions/ldursh.rb +10 -10
- data/lib/aarch64/instructions/ldursw.rb +8 -8
- data/lib/aarch64/instructions/ldxp.rb +10 -10
- data/lib/aarch64/instructions/ldxr.rb +8 -8
- data/lib/aarch64/instructions/lslv.rb +10 -10
- data/lib/aarch64/instructions/lsrv.rb +10 -10
- data/lib/aarch64/instructions/madd.rb +12 -12
- data/lib/aarch64/instructions/movk.rb +10 -10
- data/lib/aarch64/instructions/movn.rb +10 -10
- data/lib/aarch64/instructions/movz.rb +10 -10
- data/lib/aarch64/instructions/mrs.rb +14 -14
- data/lib/aarch64/instructions/msr_imm.rb +7 -7
- data/lib/aarch64/instructions/msr_reg.rb +14 -14
- data/lib/aarch64/instructions/msub.rb +12 -12
- data/lib/aarch64/instructions/nop.rb +1 -1
- data/lib/aarch64/instructions/orn_log_shift.rb +14 -14
- data/lib/aarch64/instructions/orr_log_imm.rb +14 -14
- data/lib/aarch64/instructions/orr_log_shift.rb +14 -14
- data/lib/aarch64/instructions/pacda.rb +8 -8
- data/lib/aarch64/instructions/pacdb.rb +8 -8
- data/lib/aarch64/instructions/pacga.rb +8 -8
- data/lib/aarch64/instructions/pacia.rb +8 -8
- data/lib/aarch64/instructions/pacia2.rb +5 -5
- data/lib/aarch64/instructions/pacib.rb +8 -8
- data/lib/aarch64/instructions/prfm_imm.rb +8 -8
- data/lib/aarch64/instructions/prfm_lit.rb +8 -8
- data/lib/aarch64/instructions/prfm_reg.rb +12 -12
- data/lib/aarch64/instructions/prfum.rb +8 -8
- data/lib/aarch64/instructions/psb.rb +2 -9
- data/lib/aarch64/instructions/rbit_int.rb +8 -8
- data/lib/aarch64/instructions/ret.rb +4 -4
- data/lib/aarch64/instructions/reta.rb +3 -3
- data/lib/aarch64/instructions/rev.rb +10 -10
- data/lib/aarch64/instructions/rmif.rb +8 -8
- data/lib/aarch64/instructions/rorv.rb +10 -10
- data/lib/aarch64/instructions/sb.rb +1 -1
- data/lib/aarch64/instructions/sbc.rb +10 -10
- data/lib/aarch64/instructions/sbcs.rb +10 -10
- data/lib/aarch64/instructions/sbfm.rb +13 -13
- data/lib/aarch64/instructions/sdiv.rb +10 -10
- data/lib/aarch64/instructions/setf.rb +6 -6
- data/lib/aarch64/instructions/sev.rb +1 -7
- data/lib/aarch64/instructions/sevl.rb +1 -1
- data/lib/aarch64/instructions/smaddl.rb +10 -10
- data/lib/aarch64/instructions/smc.rb +3 -3
- data/lib/aarch64/instructions/smsubl.rb +10 -10
- data/lib/aarch64/instructions/smulh.rb +8 -8
- data/lib/aarch64/instructions/st2g.rb +10 -10
- data/lib/aarch64/instructions/st64b.rb +6 -6
- data/lib/aarch64/instructions/st64bv.rb +8 -8
- data/lib/aarch64/instructions/st64bv0.rb +8 -8
- data/lib/aarch64/instructions/stg.rb +10 -10
- data/lib/aarch64/instructions/stgm.rb +6 -6
- data/lib/aarch64/instructions/stgp.rb +12 -12
- data/lib/aarch64/instructions/stllr.rb +8 -8
- data/lib/aarch64/instructions/stllrb.rb +6 -6
- data/lib/aarch64/instructions/stllrh.rb +6 -6
- data/lib/aarch64/instructions/stlr.rb +8 -8
- data/lib/aarch64/instructions/stlrb.rb +6 -6
- data/lib/aarch64/instructions/stlrh.rb +6 -6
- data/lib/aarch64/instructions/stlur_gen.rb +10 -10
- data/lib/aarch64/instructions/stlxp.rb +12 -12
- data/lib/aarch64/instructions/stlxr.rb +10 -10
- data/lib/aarch64/instructions/stlxrb.rb +8 -8
- data/lib/aarch64/instructions/stlxrh.rb +8 -8
- data/lib/aarch64/instructions/stnp_gen.rb +12 -12
- data/lib/aarch64/instructions/stp_gen.rb +14 -14
- data/lib/aarch64/instructions/str_imm_gen.rb +12 -12
- data/lib/aarch64/instructions/str_imm_unsigned.rb +10 -10
- data/lib/aarch64/instructions/str_reg_gen.rb +14 -14
- data/lib/aarch64/instructions/strb_imm.rb +10 -10
- data/lib/aarch64/instructions/strb_imm_unsigned.rb +8 -8
- data/lib/aarch64/instructions/strb_reg.rb +12 -12
- data/lib/aarch64/instructions/strh_imm.rb +10 -10
- data/lib/aarch64/instructions/strh_imm_unsigned.rb +8 -8
- data/lib/aarch64/instructions/strh_reg.rb +12 -12
- data/lib/aarch64/instructions/sttr.rb +10 -10
- data/lib/aarch64/instructions/stur_gen.rb +10 -10
- data/lib/aarch64/instructions/stxp.rb +12 -12
- data/lib/aarch64/instructions/stxr.rb +10 -10
- data/lib/aarch64/instructions/stxrb.rb +8 -8
- data/lib/aarch64/instructions/stxrh.rb +8 -8
- data/lib/aarch64/instructions/stz2g.rb +10 -10
- data/lib/aarch64/instructions/stzg.rb +10 -10
- data/lib/aarch64/instructions/stzgm.rb +6 -6
- data/lib/aarch64/instructions/sub_addsub_ext.rb +14 -14
- data/lib/aarch64/instructions/sub_addsub_imm.rb +12 -12
- data/lib/aarch64/instructions/sub_addsub_shift.rb +14 -14
- data/lib/aarch64/instructions/subg.rb +10 -10
- data/lib/aarch64/instructions/subp.rb +8 -8
- data/lib/aarch64/instructions/subps.rb +8 -8
- data/lib/aarch64/instructions/subs_addsub_ext.rb +14 -14
- data/lib/aarch64/instructions/subs_addsub_imm.rb +12 -12
- data/lib/aarch64/instructions/subs_addsub_shift.rb +14 -14
- data/lib/aarch64/instructions/svc.rb +3 -3
- data/lib/aarch64/instructions/swp.rb +14 -14
- data/lib/aarch64/instructions/swpb.rb +12 -12
- data/lib/aarch64/instructions/swph.rb +12 -12
- data/lib/aarch64/instructions/sys.rb +12 -12
- data/lib/aarch64/instructions/sysl.rb +12 -12
- data/lib/aarch64/instructions/tbnz.rb +9 -9
- data/lib/aarch64/instructions/tbz.rb +9 -9
- data/lib/aarch64/instructions/tsb.rb +1 -7
- data/lib/aarch64/instructions/ubfm.rb +13 -13
- data/lib/aarch64/instructions/udf_perm_undef.rb +3 -3
- data/lib/aarch64/instructions/udiv.rb +10 -10
- data/lib/aarch64/instructions/umaddl.rb +10 -10
- data/lib/aarch64/instructions/umsubl.rb +10 -10
- data/lib/aarch64/instructions/umulh.rb +8 -8
- data/lib/aarch64/instructions/wfe.rb +2 -9
- data/lib/aarch64/instructions/wfet.rb +4 -4
- data/lib/aarch64/instructions/wfi.rb +1 -1
- data/lib/aarch64/instructions/wfit.rb +4 -4
- data/lib/aarch64/instructions/xaflag.rb +1 -1
- data/lib/aarch64/instructions/xpac.rb +6 -6
- data/lib/aarch64/instructions/xpaclri.rb +1 -1
- data/lib/aarch64/instructions/yield.rb +2 -9
- data/lib/aarch64/instructions.rb +26 -8
- data/lib/aarch64/parser.rb +227 -0
- data/lib/aarch64/parser.tab.rb +6534 -0
- data/lib/aarch64/parser.y +1394 -0
- data/lib/aarch64/utils.rb +34 -0
- data/lib/aarch64/version.rb +1 -1
- data/lib/aarch64.rb +128 -58
- data/test/base_instructions_test.rb +34 -4
- data/test/helper.rb +48 -8
- data/test/parser_test.rb +1820 -0
- metadata +25 -14
- data/lib/aarch64/instructions/setgp.rb +0 -25
- data/lib/aarch64/instructions/setgpn.rb +0 -25
- data/lib/aarch64/instructions/setgpt.rb +0 -25
- data/lib/aarch64/instructions/setgptn.rb +0 -25
- data/lib/aarch64/instructions/setp.rb +0 -25
- data/lib/aarch64/instructions/setpn.rb +0 -25
- data/lib/aarch64/instructions/setpt.rb +0 -25
- data/lib/aarch64/instructions/setptn.rb +0 -25
@@ -3,26 +3,26 @@ module AArch64
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# SMADDL -- A64
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# Signed Multiply-Add Long
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# SMADDL <Xd>, <Wn>, <Wm>, <Xa>
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class SMADDL
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class SMADDL < Instruction
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def initialize rd, rn, rm, ra
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@rd = rd
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@rn = rn
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@rm = rm
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@ra = ra
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@rd = check_mask(rd, 0x1f)
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@rn = check_mask(rn, 0x1f)
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@rm = check_mask(rm, 0x1f)
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@ra = check_mask(ra, 0x1f)
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end
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def encode
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SMADDL(@rm
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SMADDL(@rm, @ra, @rn, @rd)
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end
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private
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def SMADDL rm, ra, rn, rd
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insn = 0b1_00_11011_0_01_00000_0_00000_00000_00000
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insn |= ((rm
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insn |= ((ra
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insn |= ((rn
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insn |= (rd
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insn |= ((rm) << 16)
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insn |= ((ra) << 10)
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insn |= ((rn) << 5)
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insn |= (rd)
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insn
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end
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end
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@@ -3,9 +3,9 @@ module AArch64
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# SMC -- A64
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# Secure Monitor Call
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# SMC #<imm>
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class SMC
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class SMC < Instruction
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def initialize imm16
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@imm16 = imm16
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@imm16 = check_mask(imm16, 0xffff)
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end
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def encode
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@@ -16,7 +16,7 @@ module AArch64
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def SMC imm16
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insn = 0b11010100_000_0000000000000000_000_11
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insn |= ((imm16
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insn |= ((imm16) << 5)
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insn
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end
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end
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@@ -3,26 +3,26 @@ module AArch64
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# SMSUBL -- A64
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# Signed Multiply-Subtract Long
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# SMSUBL <Xd>, <Wn>, <Wm>, <Xa>
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class SMSUBL
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class SMSUBL < Instruction
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def initialize rd, rn, rm, ra
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@rd = rd
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@rn = rn
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@rm = rm
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@ra = ra
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@rd = check_mask(rd, 0x1f)
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@rn = check_mask(rn, 0x1f)
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@rm = check_mask(rm, 0x1f)
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@ra = check_mask(ra, 0x1f)
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end
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def encode
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SMSUBL(@rm
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SMSUBL(@rm, @ra, @rn, @rd)
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end
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private
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def SMSUBL rm, ra, rn, rd
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insn = 0b1_00_11011_0_01_00000_1_00000_00000_00000
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insn |= ((rm
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insn |= ((ra
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insn |= ((rn
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insn |= (rd
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insn |= ((rm) << 16)
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insn |= ((ra) << 10)
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+
insn |= ((rn) << 5)
|
25
|
+
insn |= (rd)
|
26
26
|
insn
|
27
27
|
end
|
28
28
|
end
|
@@ -3,24 +3,24 @@ module AArch64
|
|
3
3
|
# SMULH -- A64
|
4
4
|
# Signed Multiply High
|
5
5
|
# SMULH <Xd>, <Xn>, <Xm>
|
6
|
-
class SMULH
|
6
|
+
class SMULH < Instruction
|
7
7
|
def initialize rd, rn, rm
|
8
|
-
@rd = rd
|
9
|
-
@rn = rn
|
10
|
-
@rm = rm
|
8
|
+
@rd = check_mask(rd, 0x1f)
|
9
|
+
@rn = check_mask(rn, 0x1f)
|
10
|
+
@rm = check_mask(rm, 0x1f)
|
11
11
|
end
|
12
12
|
|
13
13
|
def encode
|
14
|
-
SMULH(@rm
|
14
|
+
SMULH(@rm, @rn, @rd)
|
15
15
|
end
|
16
16
|
|
17
17
|
private
|
18
18
|
|
19
19
|
def SMULH rm, rn, rd
|
20
20
|
insn = 0b1_00_11011_0_10_00000_0_11111_00000_00000
|
21
|
-
insn |= ((rm
|
22
|
-
insn |= ((rn
|
23
|
-
insn |= (rd
|
21
|
+
insn |= ((rm) << 16)
|
22
|
+
insn |= ((rn) << 5)
|
23
|
+
insn |= (rd)
|
24
24
|
insn
|
25
25
|
end
|
26
26
|
end
|
@@ -5,26 +5,26 @@ module AArch64
|
|
5
5
|
# ST2G <Xt|SP>, [<Xn|SP>], #<simm>
|
6
6
|
# ST2G <Xt|SP>, [<Xn|SP>, #<simm>]!
|
7
7
|
# ST2G <Xt|SP>, [<Xn|SP>{, #<simm>}]
|
8
|
-
class ST2G
|
8
|
+
class ST2G < Instruction
|
9
9
|
def initialize xt, xn, imm9, option
|
10
|
-
@xt = xt
|
11
|
-
@xn = xn
|
12
|
-
@imm9 = imm9
|
13
|
-
@option = option
|
10
|
+
@xt = check_mask(xt, 0x1f)
|
11
|
+
@xn = check_mask(xn, 0x1f)
|
12
|
+
@imm9 = check_mask(imm9, 0x1ff)
|
13
|
+
@option = check_mask(option, 0x03)
|
14
14
|
end
|
15
15
|
|
16
16
|
def encode
|
17
|
-
ST2G(@imm9, @option, @xn
|
17
|
+
ST2G(@imm9, @option, @xn, @xt)
|
18
18
|
end
|
19
19
|
|
20
20
|
private
|
21
21
|
|
22
22
|
def ST2G imm9, option, xn, xt
|
23
23
|
insn = 0b11011001_1_0_1_000000000_00_00000_00000
|
24
|
-
insn |= ((imm9
|
25
|
-
insn |= ((option
|
26
|
-
insn |= ((xn
|
27
|
-
insn |= (xt
|
24
|
+
insn |= ((imm9) << 12)
|
25
|
+
insn |= ((option) << 10)
|
26
|
+
insn |= ((xn) << 5)
|
27
|
+
insn |= (xt)
|
28
28
|
insn
|
29
29
|
end
|
30
30
|
end
|
@@ -3,22 +3,22 @@ module AArch64
|
|
3
3
|
# ST64B -- A64
|
4
4
|
# Single-copy Atomic 64-byte Store without Return
|
5
5
|
# ST64B <Xt>, [<Xn|SP> {,#0}]
|
6
|
-
class ST64B
|
6
|
+
class ST64B < Instruction
|
7
7
|
def initialize rt, rn
|
8
|
-
@rt = rt
|
9
|
-
@rn = rn
|
8
|
+
@rt = check_mask(rt, 0x1f)
|
9
|
+
@rn = check_mask(rn, 0x1f)
|
10
10
|
end
|
11
11
|
|
12
12
|
def encode
|
13
|
-
ST64B(@rn
|
13
|
+
ST64B(@rn, @rt)
|
14
14
|
end
|
15
15
|
|
16
16
|
private
|
17
17
|
|
18
18
|
def ST64B rn, rt
|
19
19
|
insn = 0b11_111_0_00_0_0_1_11111_1_001_00_00000_00000
|
20
|
-
insn |= ((rn
|
21
|
-
insn |= (rt
|
20
|
+
insn |= ((rn) << 5)
|
21
|
+
insn |= (rt)
|
22
22
|
insn
|
23
23
|
end
|
24
24
|
end
|
@@ -3,24 +3,24 @@ module AArch64
|
|
3
3
|
# ST64BV -- A64
|
4
4
|
# Single-copy Atomic 64-byte Store with Return
|
5
5
|
# ST64BV <Xs>, <Xt>, [<Xn|SP>]
|
6
|
-
class ST64BV
|
6
|
+
class ST64BV < Instruction
|
7
7
|
def initialize rs, rt, rn
|
8
|
-
@rs = rs
|
9
|
-
@rt = rt
|
10
|
-
@rn = rn
|
8
|
+
@rs = check_mask(rs, 0x1f)
|
9
|
+
@rt = check_mask(rt, 0x1f)
|
10
|
+
@rn = check_mask(rn, 0x1f)
|
11
11
|
end
|
12
12
|
|
13
13
|
def encode
|
14
|
-
ST64BV(@rs
|
14
|
+
ST64BV(@rs, @rn, @rt)
|
15
15
|
end
|
16
16
|
|
17
17
|
private
|
18
18
|
|
19
19
|
def ST64BV rs, rn, rt
|
20
20
|
insn = 0b11_111_0_00_0_0_1_00000_1_011_00_00000_00000
|
21
|
-
insn |= ((rs
|
22
|
-
insn |= ((rn
|
23
|
-
insn |= (rt
|
21
|
+
insn |= ((rs) << 16)
|
22
|
+
insn |= ((rn) << 5)
|
23
|
+
insn |= (rt)
|
24
24
|
insn
|
25
25
|
end
|
26
26
|
end
|
@@ -3,24 +3,24 @@ module AArch64
|
|
3
3
|
# ST64BV0 -- A64
|
4
4
|
# Single-copy Atomic 64-byte EL0 Store with Return
|
5
5
|
# ST64BV0 <Xs>, <Xt>, [<Xn|SP>]
|
6
|
-
class ST64BV0
|
6
|
+
class ST64BV0 < Instruction
|
7
7
|
def initialize rs, rt, rn
|
8
|
-
@rs = rs
|
9
|
-
@rt = rt
|
10
|
-
@rn = rn
|
8
|
+
@rs = check_mask(rs, 0x1f)
|
9
|
+
@rt = check_mask(rt, 0x1f)
|
10
|
+
@rn = check_mask(rn, 0x1f)
|
11
11
|
end
|
12
12
|
|
13
13
|
def encode
|
14
|
-
ST64BV0(@rs
|
14
|
+
ST64BV0(@rs, @rn, @rt)
|
15
15
|
end
|
16
16
|
|
17
17
|
private
|
18
18
|
|
19
19
|
def ST64BV0 rs, rn, rt
|
20
20
|
insn = 0b11_111_0_00_0_0_1_00000_1_010_00_00000_00000
|
21
|
-
insn |= ((rs
|
22
|
-
insn |= ((rn
|
23
|
-
insn |= (rt
|
21
|
+
insn |= ((rs) << 16)
|
22
|
+
insn |= ((rn) << 5)
|
23
|
+
insn |= (rt)
|
24
24
|
insn
|
25
25
|
end
|
26
26
|
end
|
@@ -5,26 +5,26 @@ module AArch64
|
|
5
5
|
# STG <Xt|SP>, [<Xn|SP>], #<simm>
|
6
6
|
# STG <Xt|SP>, [<Xn|SP>, #<simm>]!
|
7
7
|
# STG <Xt|SP>, [<Xn|SP>{, #<simm>}]
|
8
|
-
class STG
|
8
|
+
class STG < Instruction
|
9
9
|
def initialize xt, xn, imm9, option
|
10
|
-
@xt = xt
|
11
|
-
@xn = xn
|
12
|
-
@imm9 = imm9
|
13
|
-
@option = option
|
10
|
+
@xt = check_mask(xt, 0x1f)
|
11
|
+
@xn = check_mask(xn, 0x1f)
|
12
|
+
@imm9 = check_mask(imm9, 0x1ff)
|
13
|
+
@option = check_mask(option, 0x03)
|
14
14
|
end
|
15
15
|
|
16
16
|
def encode
|
17
|
-
STG(@imm9, @option, @xn
|
17
|
+
STG(@imm9, @option, @xn, @xt)
|
18
18
|
end
|
19
19
|
|
20
20
|
private
|
21
21
|
|
22
22
|
def STG imm9, option, xn, xt
|
23
23
|
insn = 0b11011001_0_0_1_000000000_00_00000_00000
|
24
|
-
insn |= ((imm9
|
25
|
-
insn |= ((option
|
26
|
-
insn |= ((xn
|
27
|
-
insn |= (xt
|
24
|
+
insn |= ((imm9) << 12)
|
25
|
+
insn |= ((option) << 10)
|
26
|
+
insn |= ((xn) << 5)
|
27
|
+
insn |= (xt)
|
28
28
|
insn
|
29
29
|
end
|
30
30
|
end
|
@@ -3,22 +3,22 @@ module AArch64
|
|
3
3
|
# STGM -- A64
|
4
4
|
# Store Tag Multiple
|
5
5
|
# STGM <Xt>, [<Xn|SP>]
|
6
|
-
class STGM
|
6
|
+
class STGM < Instruction
|
7
7
|
def initialize xt, xn
|
8
|
-
@xt = xt
|
9
|
-
@xn = xn
|
8
|
+
@xt = check_mask(xt, 0x1f)
|
9
|
+
@xn = check_mask(xn, 0x1f)
|
10
10
|
end
|
11
11
|
|
12
12
|
def encode
|
13
|
-
STGM(@xn
|
13
|
+
STGM(@xn, @xt)
|
14
14
|
end
|
15
15
|
|
16
16
|
private
|
17
17
|
|
18
18
|
def STGM xn, xt
|
19
19
|
insn = 0b11011001_1_0_1_0_0_0_0_0_0_0_0_0_0_0_00000_00000
|
20
|
-
insn |= ((xn
|
21
|
-
insn |= (xt
|
20
|
+
insn |= ((xn) << 5)
|
21
|
+
insn |= (xt)
|
22
22
|
insn
|
23
23
|
end
|
24
24
|
end
|
@@ -5,28 +5,28 @@ module AArch64
|
|
5
5
|
# STGP <Xt1>, <Xt2>, [<Xn|SP>], #<imm>
|
6
6
|
# STGP <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]!
|
7
7
|
# STGP <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]
|
8
|
-
class STGP
|
8
|
+
class STGP < Instruction
|
9
9
|
def initialize xt, xt2, xn, simm7, option
|
10
|
-
@xt = xt
|
11
|
-
@xt2 = xt2
|
12
|
-
@xn = xn
|
13
|
-
@simm7 = simm7
|
14
|
-
@option = option
|
10
|
+
@xt = check_mask(xt, 0x1f)
|
11
|
+
@xt2 = check_mask(xt2, 0x1f)
|
12
|
+
@xn = check_mask(xn, 0x1f)
|
13
|
+
@simm7 = check_mask(simm7, 0x7f)
|
14
|
+
@option = check_mask(option, 0x03)
|
15
15
|
end
|
16
16
|
|
17
17
|
def encode
|
18
|
-
STGP(@option, @simm7, @xt2
|
18
|
+
STGP(@option, @simm7, @xt2, @xn, @xt)
|
19
19
|
end
|
20
20
|
|
21
21
|
private
|
22
22
|
|
23
23
|
def STGP option, simm7, xt2, xn, xt
|
24
24
|
insn = 0b0_1_101_0_000_0_0000000_00000_00000_00000
|
25
|
-
insn |= ((option
|
26
|
-
insn |= ((simm7
|
27
|
-
insn |= ((xt2
|
28
|
-
insn |= ((xn
|
29
|
-
insn |= (xt
|
25
|
+
insn |= ((option) << 23)
|
26
|
+
insn |= ((simm7) << 15)
|
27
|
+
insn |= ((xt2) << 10)
|
28
|
+
insn |= ((xn) << 5)
|
29
|
+
insn |= (xt)
|
30
30
|
insn
|
31
31
|
end
|
32
32
|
end
|
@@ -4,24 +4,24 @@ module AArch64
|
|
4
4
|
# Store LORelease Register
|
5
5
|
# STLLR <Wt>, [<Xn|SP>{,#0}]
|
6
6
|
# STLLR <Xt>, [<Xn|SP>{,#0}]
|
7
|
-
class STLLR
|
7
|
+
class STLLR < Instruction
|
8
8
|
def initialize rt, rn, size
|
9
|
-
@rt = rt
|
10
|
-
@rn = rn
|
11
|
-
@size = size
|
9
|
+
@rt = check_mask(rt, 0x1f)
|
10
|
+
@rn = check_mask(rn, 0x1f)
|
11
|
+
@size = check_mask(size, 0x03)
|
12
12
|
end
|
13
13
|
|
14
14
|
def encode
|
15
|
-
STLLR(@size, @rn
|
15
|
+
STLLR(@size, @rn, @rt)
|
16
16
|
end
|
17
17
|
|
18
18
|
private
|
19
19
|
|
20
20
|
def STLLR size, rn, rt
|
21
21
|
insn = 0b00_001000_1_0_0_11111_0_11111_00000_00000
|
22
|
-
insn |= ((size
|
23
|
-
insn |= ((rn
|
24
|
-
insn |= (rt
|
22
|
+
insn |= ((size) << 30)
|
23
|
+
insn |= ((rn) << 5)
|
24
|
+
insn |= (rt)
|
25
25
|
insn
|
26
26
|
end
|
27
27
|
end
|
@@ -3,22 +3,22 @@ module AArch64
|
|
3
3
|
# STLLRB -- A64
|
4
4
|
# Store LORelease Register Byte
|
5
5
|
# STLLRB <Wt>, [<Xn|SP>{,#0}]
|
6
|
-
class STLLRB
|
6
|
+
class STLLRB < Instruction
|
7
7
|
def initialize rt, rn
|
8
|
-
@rt = rt
|
9
|
-
@rn = rn
|
8
|
+
@rt = check_mask(rt, 0x1f)
|
9
|
+
@rn = check_mask(rn, 0x1f)
|
10
10
|
end
|
11
11
|
|
12
12
|
def encode
|
13
|
-
STLLRB(@rn
|
13
|
+
STLLRB(@rn, @rt)
|
14
14
|
end
|
15
15
|
|
16
16
|
private
|
17
17
|
|
18
18
|
def STLLRB rn, rt
|
19
19
|
insn = 0b00_001000_1_0_0_11111_0_11111_00000_00000
|
20
|
-
insn |= ((rn
|
21
|
-
insn |= (rt
|
20
|
+
insn |= ((rn) << 5)
|
21
|
+
insn |= (rt)
|
22
22
|
insn
|
23
23
|
end
|
24
24
|
end
|
@@ -3,22 +3,22 @@ module AArch64
|
|
3
3
|
# STLLRH -- A64
|
4
4
|
# Store LORelease Register Halfword
|
5
5
|
# STLLRH <Wt>, [<Xn|SP>{,#0}]
|
6
|
-
class STLLRH
|
6
|
+
class STLLRH < Instruction
|
7
7
|
def initialize rt, rn
|
8
|
-
@rt = rt
|
9
|
-
@rn = rn
|
8
|
+
@rt = check_mask(rt, 0x1f)
|
9
|
+
@rn = check_mask(rn, 0x1f)
|
10
10
|
end
|
11
11
|
|
12
12
|
def encode
|
13
|
-
STLLRH(@rn
|
13
|
+
STLLRH(@rn, @rt)
|
14
14
|
end
|
15
15
|
|
16
16
|
private
|
17
17
|
|
18
18
|
def STLLRH rn, rt
|
19
19
|
insn = 0b01_001000_1_0_0_11111_0_11111_00000_00000
|
20
|
-
insn |= ((rn
|
21
|
-
insn |= (rt
|
20
|
+
insn |= ((rn) << 5)
|
21
|
+
insn |= (rt)
|
22
22
|
insn
|
23
23
|
end
|
24
24
|
end
|
@@ -4,24 +4,24 @@ module AArch64
|
|
4
4
|
# Store-Release Register
|
5
5
|
# STLR <Wt>, [<Xn|SP>{,#0}]
|
6
6
|
# STLR <Xt>, [<Xn|SP>{,#0}]
|
7
|
-
class STLR
|
7
|
+
class STLR < Instruction
|
8
8
|
def initialize rt, rn, size
|
9
|
-
@rt = rt
|
10
|
-
@rn = rn
|
11
|
-
@size = size
|
9
|
+
@rt = check_mask(rt, 0x1f)
|
10
|
+
@rn = check_mask(rn, 0x1f)
|
11
|
+
@size = check_mask(size, 0x03)
|
12
12
|
end
|
13
13
|
|
14
14
|
def encode
|
15
|
-
STLR(@size, @rn
|
15
|
+
STLR(@size, @rn, @rt)
|
16
16
|
end
|
17
17
|
|
18
18
|
private
|
19
19
|
|
20
20
|
def STLR size, rn, rt
|
21
21
|
insn = 0b00_001000_1_0_0_11111_1_11111_00000_00000
|
22
|
-
insn |= ((size
|
23
|
-
insn |= ((rn
|
24
|
-
insn |= (rt
|
22
|
+
insn |= ((size) << 30)
|
23
|
+
insn |= ((rn) << 5)
|
24
|
+
insn |= (rt)
|
25
25
|
insn
|
26
26
|
end
|
27
27
|
end
|
@@ -3,22 +3,22 @@ module AArch64
|
|
3
3
|
# STLRB -- A64
|
4
4
|
# Store-Release Register Byte
|
5
5
|
# STLRB <Wt>, [<Xn|SP>{,#0}]
|
6
|
-
class STLRB
|
6
|
+
class STLRB < Instruction
|
7
7
|
def initialize rt, rn
|
8
|
-
@rt = rt
|
9
|
-
@rn = rn
|
8
|
+
@rt = check_mask(rt, 0x1f)
|
9
|
+
@rn = check_mask(rn, 0x1f)
|
10
10
|
end
|
11
11
|
|
12
12
|
def encode
|
13
|
-
STLRB(@rn
|
13
|
+
STLRB(@rn, @rt)
|
14
14
|
end
|
15
15
|
|
16
16
|
private
|
17
17
|
|
18
18
|
def STLRB rn, rt
|
19
19
|
insn = 0b00_001000_1_0_0_11111_1_11111_00000_00000
|
20
|
-
insn |= ((rn
|
21
|
-
insn |= (rt
|
20
|
+
insn |= ((rn) << 5)
|
21
|
+
insn |= (rt)
|
22
22
|
insn
|
23
23
|
end
|
24
24
|
end
|
@@ -3,22 +3,22 @@ module AArch64
|
|
3
3
|
# STLRH -- A64
|
4
4
|
# Store-Release Register Halfword
|
5
5
|
# STLRH <Wt>, [<Xn|SP>{,#0}]
|
6
|
-
class STLRH
|
6
|
+
class STLRH < Instruction
|
7
7
|
def initialize rt, rn
|
8
|
-
@rt = rt
|
9
|
-
@rn = rn
|
8
|
+
@rt = check_mask(rt, 0x1f)
|
9
|
+
@rn = check_mask(rn, 0x1f)
|
10
10
|
end
|
11
11
|
|
12
12
|
def encode
|
13
|
-
STLRH(@rn
|
13
|
+
STLRH(@rn, @rt)
|
14
14
|
end
|
15
15
|
|
16
16
|
private
|
17
17
|
|
18
18
|
def STLRH rn, rt
|
19
19
|
insn = 0b01_001000_1_0_0_11111_1_11111_00000_00000
|
20
|
-
insn |= ((rn
|
21
|
-
insn |= (rt
|
20
|
+
insn |= ((rn) << 5)
|
21
|
+
insn |= (rt)
|
22
22
|
insn
|
23
23
|
end
|
24
24
|
end
|
@@ -4,26 +4,26 @@ module AArch64
|
|
4
4
|
# Store-Release Register (unscaled)
|
5
5
|
# STLUR <Wt>, [<Xn|SP>{, #<simm>}]
|
6
6
|
# STLUR <Xt>, [<Xn|SP>{, #<simm>}]
|
7
|
-
class STLUR_gen
|
7
|
+
class STLUR_gen < Instruction
|
8
8
|
def initialize rt, rn, imm9, size
|
9
|
-
@rt = rt
|
10
|
-
@rn = rn
|
11
|
-
@imm9 = imm9
|
12
|
-
@size = size
|
9
|
+
@rt = check_mask(rt, 0x1f)
|
10
|
+
@rn = check_mask(rn, 0x1f)
|
11
|
+
@imm9 = check_mask(imm9, 0x1ff)
|
12
|
+
@size = check_mask(size, 0x03)
|
13
13
|
end
|
14
14
|
|
15
15
|
def encode
|
16
|
-
STLUR_gen(@size, @imm9, @rn
|
16
|
+
STLUR_gen(@size, @imm9, @rn, @rt)
|
17
17
|
end
|
18
18
|
|
19
19
|
private
|
20
20
|
|
21
21
|
def STLUR_gen size, imm9, rn, rt
|
22
22
|
insn = 0b00_011001_00_0_000000000_00_00000_00000
|
23
|
-
insn |= ((size
|
24
|
-
insn |= ((imm9
|
25
|
-
insn |= ((rn
|
26
|
-
insn |= (rt
|
23
|
+
insn |= ((size) << 30)
|
24
|
+
insn |= ((imm9) << 12)
|
25
|
+
insn |= ((rn) << 5)
|
26
|
+
insn |= (rt)
|
27
27
|
insn
|
28
28
|
end
|
29
29
|
end
|
@@ -4,28 +4,28 @@ module AArch64
|
|
4
4
|
# Store-Release Exclusive Pair of registers
|
5
5
|
# STLXP <Ws>, <Wt1>, <Wt2>, [<Xn|SP>{,#0}]
|
6
6
|
# STLXP <Ws>, <Xt1>, <Xt2>, [<Xn|SP>{,#0}]
|
7
|
-
class STLXP
|
7
|
+
class STLXP < Instruction
|
8
8
|
def initialize rs, rt, rt2, rn, sz
|
9
|
-
@rs = rs
|
10
|
-
@rt = rt
|
11
|
-
@rt2 = rt2
|
12
|
-
@rn = rn
|
13
|
-
@sz = sz
|
9
|
+
@rs = check_mask(rs, 0x1f)
|
10
|
+
@rt = check_mask(rt, 0x1f)
|
11
|
+
@rt2 = check_mask(rt2, 0x1f)
|
12
|
+
@rn = check_mask(rn, 0x1f)
|
13
|
+
@sz = check_mask(sz, 0x01)
|
14
14
|
end
|
15
15
|
|
16
16
|
def encode
|
17
|
-
STLXP(@sz, @rs
|
17
|
+
STLXP(@sz, @rs, @rt2, @rn, @rt)
|
18
18
|
end
|
19
19
|
|
20
20
|
private
|
21
21
|
|
22
22
|
def STLXP sz, rs, rt2, rn, rt
|
23
23
|
insn = 0b1_0_001000_0_0_1_00000_1_00000_00000_00000
|
24
|
-
insn |= ((sz
|
25
|
-
insn |= ((rs
|
26
|
-
insn |= ((rt2
|
27
|
-
insn |= ((rn
|
28
|
-
insn |= (rt
|
24
|
+
insn |= ((sz) << 30)
|
25
|
+
insn |= ((rs) << 16)
|
26
|
+
insn |= ((rt2) << 10)
|
27
|
+
insn |= ((rn) << 5)
|
28
|
+
insn |= (rt)
|
29
29
|
insn
|
30
30
|
end
|
31
31
|
end
|