aarch64 1.0.1 → 2.0.0

Sign up to get free protection for your applications and to get access to all the features.
Files changed (277) hide show
  1. checksums.yaml +4 -4
  2. data/README.md +1 -1
  3. data/Rakefile +37 -0
  4. data/aarch64.gemspec +1 -0
  5. data/lib/aarch64/instructions/adc.rb +10 -10
  6. data/lib/aarch64/instructions/adcs.rb +10 -10
  7. data/lib/aarch64/instructions/add_addsub_ext.rb +14 -14
  8. data/lib/aarch64/instructions/add_addsub_imm.rb +12 -12
  9. data/lib/aarch64/instructions/add_addsub_shift.rb +14 -14
  10. data/lib/aarch64/instructions/addg.rb +10 -10
  11. data/lib/aarch64/instructions/adds_addsub_ext.rb +14 -14
  12. data/lib/aarch64/instructions/adds_addsub_imm.rb +12 -12
  13. data/lib/aarch64/instructions/adds_addsub_shift.rb +14 -14
  14. data/lib/aarch64/instructions/adr.rb +7 -7
  15. data/lib/aarch64/instructions/adrp.rb +7 -7
  16. data/lib/aarch64/instructions/and_log_imm.rb +14 -14
  17. data/lib/aarch64/instructions/and_log_shift.rb +14 -14
  18. data/lib/aarch64/instructions/ands_log_imm.rb +14 -14
  19. data/lib/aarch64/instructions/ands_log_shift.rb +14 -14
  20. data/lib/aarch64/instructions/asrv.rb +10 -10
  21. data/lib/aarch64/instructions/autda.rb +9 -12
  22. data/lib/aarch64/instructions/autdb.rb +9 -12
  23. data/lib/aarch64/instructions/autia.rb +9 -12
  24. data/lib/aarch64/instructions/autib.rb +9 -12
  25. data/lib/aarch64/instructions/axflag.rb +1 -1
  26. data/lib/aarch64/instructions/b_cond.rb +5 -5
  27. data/lib/aarch64/instructions/b_uncond.rb +3 -3
  28. data/lib/aarch64/instructions/bc_cond.rb +5 -5
  29. data/lib/aarch64/instructions/bfm.rb +13 -13
  30. data/lib/aarch64/instructions/bic_log_shift.rb +14 -14
  31. data/lib/aarch64/instructions/bics.rb +14 -14
  32. data/lib/aarch64/instructions/bl.rb +3 -3
  33. data/lib/aarch64/instructions/blr.rb +4 -4
  34. data/lib/aarch64/instructions/blra.rb +10 -10
  35. data/lib/aarch64/instructions/br.rb +4 -4
  36. data/lib/aarch64/instructions/bra.rb +10 -10
  37. data/lib/aarch64/instructions/brk.rb +3 -3
  38. data/lib/aarch64/instructions/bti.rb +3 -3
  39. data/lib/aarch64/instructions/cas.rb +14 -14
  40. data/lib/aarch64/instructions/casb.rb +12 -12
  41. data/lib/aarch64/instructions/cash.rb +12 -12
  42. data/lib/aarch64/instructions/casp.rb +14 -14
  43. data/lib/aarch64/instructions/cbnz.rb +7 -7
  44. data/lib/aarch64/instructions/cbz.rb +7 -7
  45. data/lib/aarch64/instructions/ccmn_imm.rb +12 -12
  46. data/lib/aarch64/instructions/ccmn_reg.rb +12 -12
  47. data/lib/aarch64/instructions/ccmp_imm.rb +12 -12
  48. data/lib/aarch64/instructions/ccmp_reg.rb +12 -12
  49. data/lib/aarch64/instructions/cfinv.rb +2 -9
  50. data/lib/aarch64/instructions/clrex.rb +3 -3
  51. data/lib/aarch64/instructions/cls_int.rb +8 -8
  52. data/lib/aarch64/instructions/clz_int.rb +8 -8
  53. data/lib/aarch64/instructions/crc32.rb +12 -12
  54. data/lib/aarch64/instructions/crc32c.rb +12 -12
  55. data/lib/aarch64/instructions/csdb.rb +1 -1
  56. data/lib/aarch64/instructions/csel.rb +12 -12
  57. data/lib/aarch64/instructions/csinc.rb +12 -12
  58. data/lib/aarch64/instructions/csinv.rb +12 -12
  59. data/lib/aarch64/instructions/csneg.rb +12 -12
  60. data/lib/aarch64/instructions/dcps.rb +5 -5
  61. data/lib/aarch64/instructions/dgh.rb +1 -1
  62. data/lib/aarch64/instructions/dmb.rb +3 -3
  63. data/lib/aarch64/instructions/drps.rb +2 -9
  64. data/lib/aarch64/instructions/dsb.rb +3 -3
  65. data/lib/aarch64/instructions/eon.rb +14 -14
  66. data/lib/aarch64/instructions/eor_log_imm.rb +14 -14
  67. data/lib/aarch64/instructions/eor_log_shift.rb +14 -14
  68. data/lib/aarch64/instructions/eret.rb +2 -9
  69. data/lib/aarch64/instructions/ereta.rb +3 -3
  70. data/lib/aarch64/instructions/esb.rb +1 -1
  71. data/lib/aarch64/instructions/extr.rb +13 -13
  72. data/lib/aarch64/instructions/gmi.rb +8 -8
  73. data/lib/aarch64/instructions/hint.rb +5 -5
  74. data/lib/aarch64/instructions/hlt.rb +3 -3
  75. data/lib/aarch64/instructions/hvc.rb +3 -3
  76. data/lib/aarch64/instructions/irg.rb +8 -8
  77. data/lib/aarch64/instructions/isb.rb +3 -3
  78. data/lib/aarch64/instructions/ld64b.rb +6 -6
  79. data/lib/aarch64/instructions/ldadd.rb +14 -14
  80. data/lib/aarch64/instructions/ldaddb.rb +12 -12
  81. data/lib/aarch64/instructions/ldaddh.rb +12 -12
  82. data/lib/aarch64/instructions/ldapr.rb +8 -8
  83. data/lib/aarch64/instructions/ldaprb.rb +6 -6
  84. data/lib/aarch64/instructions/ldaprh.rb +6 -6
  85. data/lib/aarch64/instructions/ldapur_gen.rb +12 -12
  86. data/lib/aarch64/instructions/ldar.rb +8 -8
  87. data/lib/aarch64/instructions/ldaxp.rb +10 -10
  88. data/lib/aarch64/instructions/ldaxr.rb +8 -8
  89. data/lib/aarch64/instructions/ldclr.rb +14 -14
  90. data/lib/aarch64/instructions/ldclrb.rb +14 -14
  91. data/lib/aarch64/instructions/ldeor.rb +14 -14
  92. data/lib/aarch64/instructions/ldg.rb +8 -8
  93. data/lib/aarch64/instructions/ldgm.rb +6 -6
  94. data/lib/aarch64/instructions/ldlar.rb +8 -8
  95. data/lib/aarch64/instructions/ldnp_gen.rb +12 -12
  96. data/lib/aarch64/instructions/ldp_gen.rb +14 -14
  97. data/lib/aarch64/instructions/ldpsw.rb +12 -12
  98. data/lib/aarch64/instructions/ldr_imm_gen.rb +12 -12
  99. data/lib/aarch64/instructions/ldr_imm_unsigned.rb +10 -10
  100. data/lib/aarch64/instructions/ldr_lit_gen.rb +7 -7
  101. data/lib/aarch64/instructions/ldr_reg_gen.rb +14 -14
  102. data/lib/aarch64/instructions/ldra.rb +14 -14
  103. data/lib/aarch64/instructions/ldrb_imm.rb +10 -10
  104. data/lib/aarch64/instructions/ldrb_reg.rb +12 -12
  105. data/lib/aarch64/instructions/ldrb_unsigned.rb +8 -8
  106. data/lib/aarch64/instructions/ldrh_imm.rb +10 -10
  107. data/lib/aarch64/instructions/ldrh_reg.rb +12 -12
  108. data/lib/aarch64/instructions/ldrh_unsigned.rb +8 -8
  109. data/lib/aarch64/instructions/ldrsb_imm.rb +12 -12
  110. data/lib/aarch64/instructions/ldrsb_reg.rb +14 -14
  111. data/lib/aarch64/instructions/ldrsb_unsigned.rb +10 -10
  112. data/lib/aarch64/instructions/ldrsh_imm.rb +12 -12
  113. data/lib/aarch64/instructions/ldrsh_reg.rb +14 -14
  114. data/lib/aarch64/instructions/ldrsh_unsigned.rb +10 -10
  115. data/lib/aarch64/instructions/ldrsw_imm.rb +10 -10
  116. data/lib/aarch64/instructions/ldrsw_lit.rb +5 -5
  117. data/lib/aarch64/instructions/ldrsw_reg.rb +12 -12
  118. data/lib/aarch64/instructions/ldrsw_unsigned.rb +8 -8
  119. data/lib/aarch64/instructions/ldset.rb +14 -14
  120. data/lib/aarch64/instructions/ldsetb.rb +12 -12
  121. data/lib/aarch64/instructions/ldseth.rb +12 -12
  122. data/lib/aarch64/instructions/ldsmax.rb +14 -14
  123. data/lib/aarch64/instructions/ldsmaxb.rb +12 -12
  124. data/lib/aarch64/instructions/ldsmaxh.rb +12 -12
  125. data/lib/aarch64/instructions/ldsmin.rb +14 -14
  126. data/lib/aarch64/instructions/ldsminb.rb +12 -12
  127. data/lib/aarch64/instructions/ldsminh.rb +12 -12
  128. data/lib/aarch64/instructions/ldtr.rb +10 -10
  129. data/lib/aarch64/instructions/ldtrb.rb +8 -8
  130. data/lib/aarch64/instructions/ldtrh.rb +8 -8
  131. data/lib/aarch64/instructions/ldtrsb.rb +10 -10
  132. data/lib/aarch64/instructions/ldtrsh.rb +10 -10
  133. data/lib/aarch64/instructions/ldtrsw.rb +8 -8
  134. data/lib/aarch64/instructions/ldumax.rb +14 -14
  135. data/lib/aarch64/instructions/ldumaxb.rb +12 -12
  136. data/lib/aarch64/instructions/ldumaxh.rb +12 -12
  137. data/lib/aarch64/instructions/ldumin.rb +14 -14
  138. data/lib/aarch64/instructions/lduminb.rb +12 -12
  139. data/lib/aarch64/instructions/lduminh.rb +12 -12
  140. data/lib/aarch64/instructions/ldur_gen.rb +10 -10
  141. data/lib/aarch64/instructions/ldursb.rb +10 -10
  142. data/lib/aarch64/instructions/ldursh.rb +10 -10
  143. data/lib/aarch64/instructions/ldursw.rb +8 -8
  144. data/lib/aarch64/instructions/ldxp.rb +10 -10
  145. data/lib/aarch64/instructions/ldxr.rb +8 -8
  146. data/lib/aarch64/instructions/lslv.rb +10 -10
  147. data/lib/aarch64/instructions/lsrv.rb +10 -10
  148. data/lib/aarch64/instructions/madd.rb +12 -12
  149. data/lib/aarch64/instructions/movk.rb +10 -10
  150. data/lib/aarch64/instructions/movn.rb +10 -10
  151. data/lib/aarch64/instructions/movz.rb +10 -10
  152. data/lib/aarch64/instructions/mrs.rb +14 -14
  153. data/lib/aarch64/instructions/msr_imm.rb +7 -7
  154. data/lib/aarch64/instructions/msr_reg.rb +14 -14
  155. data/lib/aarch64/instructions/msub.rb +12 -12
  156. data/lib/aarch64/instructions/nop.rb +1 -1
  157. data/lib/aarch64/instructions/orn_log_shift.rb +14 -14
  158. data/lib/aarch64/instructions/orr_log_imm.rb +14 -14
  159. data/lib/aarch64/instructions/orr_log_shift.rb +14 -14
  160. data/lib/aarch64/instructions/pacda.rb +8 -8
  161. data/lib/aarch64/instructions/pacdb.rb +8 -8
  162. data/lib/aarch64/instructions/pacga.rb +8 -8
  163. data/lib/aarch64/instructions/pacia.rb +8 -8
  164. data/lib/aarch64/instructions/pacia2.rb +5 -5
  165. data/lib/aarch64/instructions/pacib.rb +8 -8
  166. data/lib/aarch64/instructions/prfm_imm.rb +8 -8
  167. data/lib/aarch64/instructions/prfm_lit.rb +8 -8
  168. data/lib/aarch64/instructions/prfm_reg.rb +12 -12
  169. data/lib/aarch64/instructions/prfum.rb +8 -8
  170. data/lib/aarch64/instructions/psb.rb +2 -9
  171. data/lib/aarch64/instructions/rbit_int.rb +8 -8
  172. data/lib/aarch64/instructions/ret.rb +4 -4
  173. data/lib/aarch64/instructions/reta.rb +3 -3
  174. data/lib/aarch64/instructions/rev.rb +10 -10
  175. data/lib/aarch64/instructions/rmif.rb +8 -8
  176. data/lib/aarch64/instructions/rorv.rb +10 -10
  177. data/lib/aarch64/instructions/sb.rb +1 -1
  178. data/lib/aarch64/instructions/sbc.rb +10 -10
  179. data/lib/aarch64/instructions/sbcs.rb +10 -10
  180. data/lib/aarch64/instructions/sbfm.rb +13 -13
  181. data/lib/aarch64/instructions/sdiv.rb +10 -10
  182. data/lib/aarch64/instructions/setf.rb +6 -6
  183. data/lib/aarch64/instructions/sev.rb +1 -7
  184. data/lib/aarch64/instructions/sevl.rb +1 -1
  185. data/lib/aarch64/instructions/smaddl.rb +10 -10
  186. data/lib/aarch64/instructions/smc.rb +3 -3
  187. data/lib/aarch64/instructions/smsubl.rb +10 -10
  188. data/lib/aarch64/instructions/smulh.rb +8 -8
  189. data/lib/aarch64/instructions/st2g.rb +10 -10
  190. data/lib/aarch64/instructions/st64b.rb +6 -6
  191. data/lib/aarch64/instructions/st64bv.rb +8 -8
  192. data/lib/aarch64/instructions/st64bv0.rb +8 -8
  193. data/lib/aarch64/instructions/stg.rb +10 -10
  194. data/lib/aarch64/instructions/stgm.rb +6 -6
  195. data/lib/aarch64/instructions/stgp.rb +12 -12
  196. data/lib/aarch64/instructions/stllr.rb +8 -8
  197. data/lib/aarch64/instructions/stllrb.rb +6 -6
  198. data/lib/aarch64/instructions/stllrh.rb +6 -6
  199. data/lib/aarch64/instructions/stlr.rb +8 -8
  200. data/lib/aarch64/instructions/stlrb.rb +6 -6
  201. data/lib/aarch64/instructions/stlrh.rb +6 -6
  202. data/lib/aarch64/instructions/stlur_gen.rb +10 -10
  203. data/lib/aarch64/instructions/stlxp.rb +12 -12
  204. data/lib/aarch64/instructions/stlxr.rb +10 -10
  205. data/lib/aarch64/instructions/stlxrb.rb +8 -8
  206. data/lib/aarch64/instructions/stlxrh.rb +8 -8
  207. data/lib/aarch64/instructions/stnp_gen.rb +12 -12
  208. data/lib/aarch64/instructions/stp_gen.rb +14 -14
  209. data/lib/aarch64/instructions/str_imm_gen.rb +12 -12
  210. data/lib/aarch64/instructions/str_imm_unsigned.rb +10 -10
  211. data/lib/aarch64/instructions/str_reg_gen.rb +14 -14
  212. data/lib/aarch64/instructions/strb_imm.rb +10 -10
  213. data/lib/aarch64/instructions/strb_imm_unsigned.rb +8 -8
  214. data/lib/aarch64/instructions/strb_reg.rb +12 -12
  215. data/lib/aarch64/instructions/strh_imm.rb +10 -10
  216. data/lib/aarch64/instructions/strh_imm_unsigned.rb +8 -8
  217. data/lib/aarch64/instructions/strh_reg.rb +12 -12
  218. data/lib/aarch64/instructions/sttr.rb +10 -10
  219. data/lib/aarch64/instructions/stur_gen.rb +10 -10
  220. data/lib/aarch64/instructions/stxp.rb +12 -12
  221. data/lib/aarch64/instructions/stxr.rb +10 -10
  222. data/lib/aarch64/instructions/stxrb.rb +8 -8
  223. data/lib/aarch64/instructions/stxrh.rb +8 -8
  224. data/lib/aarch64/instructions/stz2g.rb +10 -10
  225. data/lib/aarch64/instructions/stzg.rb +10 -10
  226. data/lib/aarch64/instructions/stzgm.rb +6 -6
  227. data/lib/aarch64/instructions/sub_addsub_ext.rb +14 -14
  228. data/lib/aarch64/instructions/sub_addsub_imm.rb +12 -12
  229. data/lib/aarch64/instructions/sub_addsub_shift.rb +14 -14
  230. data/lib/aarch64/instructions/subg.rb +10 -10
  231. data/lib/aarch64/instructions/subp.rb +8 -8
  232. data/lib/aarch64/instructions/subps.rb +8 -8
  233. data/lib/aarch64/instructions/subs_addsub_ext.rb +14 -14
  234. data/lib/aarch64/instructions/subs_addsub_imm.rb +12 -12
  235. data/lib/aarch64/instructions/subs_addsub_shift.rb +14 -14
  236. data/lib/aarch64/instructions/svc.rb +3 -3
  237. data/lib/aarch64/instructions/swp.rb +14 -14
  238. data/lib/aarch64/instructions/swpb.rb +12 -12
  239. data/lib/aarch64/instructions/swph.rb +12 -12
  240. data/lib/aarch64/instructions/sys.rb +12 -12
  241. data/lib/aarch64/instructions/sysl.rb +12 -12
  242. data/lib/aarch64/instructions/tbnz.rb +9 -9
  243. data/lib/aarch64/instructions/tbz.rb +9 -9
  244. data/lib/aarch64/instructions/tsb.rb +1 -7
  245. data/lib/aarch64/instructions/ubfm.rb +13 -13
  246. data/lib/aarch64/instructions/udf_perm_undef.rb +3 -3
  247. data/lib/aarch64/instructions/udiv.rb +10 -10
  248. data/lib/aarch64/instructions/umaddl.rb +10 -10
  249. data/lib/aarch64/instructions/umsubl.rb +10 -10
  250. data/lib/aarch64/instructions/umulh.rb +8 -8
  251. data/lib/aarch64/instructions/wfe.rb +2 -9
  252. data/lib/aarch64/instructions/wfet.rb +4 -4
  253. data/lib/aarch64/instructions/wfi.rb +1 -1
  254. data/lib/aarch64/instructions/wfit.rb +4 -4
  255. data/lib/aarch64/instructions/xaflag.rb +1 -1
  256. data/lib/aarch64/instructions/xpac.rb +6 -6
  257. data/lib/aarch64/instructions/xpaclri.rb +1 -1
  258. data/lib/aarch64/instructions/yield.rb +2 -9
  259. data/lib/aarch64/instructions.rb +26 -8
  260. data/lib/aarch64/parser.rb +227 -0
  261. data/lib/aarch64/parser.tab.rb +6534 -0
  262. data/lib/aarch64/parser.y +1394 -0
  263. data/lib/aarch64/utils.rb +34 -0
  264. data/lib/aarch64/version.rb +1 -1
  265. data/lib/aarch64.rb +128 -58
  266. data/test/base_instructions_test.rb +34 -4
  267. data/test/helper.rb +48 -8
  268. data/test/parser_test.rb +1820 -0
  269. metadata +25 -14
  270. data/lib/aarch64/instructions/setgp.rb +0 -25
  271. data/lib/aarch64/instructions/setgpn.rb +0 -25
  272. data/lib/aarch64/instructions/setgpt.rb +0 -25
  273. data/lib/aarch64/instructions/setgptn.rb +0 -25
  274. data/lib/aarch64/instructions/setp.rb +0 -25
  275. data/lib/aarch64/instructions/setpn.rb +0 -25
  276. data/lib/aarch64/instructions/setpt.rb +0 -25
  277. data/lib/aarch64/instructions/setptn.rb +0 -25
@@ -3,14 +3,8 @@ module AArch64
3
3
  # SEV -- A64
4
4
  # Send Event
5
5
  # SEV
6
- class SEV
6
+ class SEV < Instruction
7
7
  def encode
8
- SEV()
9
- end
10
-
11
- private
12
-
13
- def SEV
14
8
  0b1101010100_0_00_011_0010_0000_100_11111
15
9
  end
16
10
  end
@@ -3,7 +3,7 @@ module AArch64
3
3
  # SEVL -- A64
4
4
  # Send Event Local
5
5
  # SEVL
6
- class SEVL
6
+ class SEVL < Instruction
7
7
  def encode
8
8
  0b1101010100_0_00_011_0010_0000_101_11111
9
9
  end
@@ -3,26 +3,26 @@ module AArch64
3
3
  # SMADDL -- A64
4
4
  # Signed Multiply-Add Long
5
5
  # SMADDL <Xd>, <Wn>, <Wm>, <Xa>
6
- class SMADDL
6
+ class SMADDL < Instruction
7
7
  def initialize rd, rn, rm, ra
8
- @rd = rd
9
- @rn = rn
10
- @rm = rm
11
- @ra = ra
8
+ @rd = check_mask(rd, 0x1f)
9
+ @rn = check_mask(rn, 0x1f)
10
+ @rm = check_mask(rm, 0x1f)
11
+ @ra = check_mask(ra, 0x1f)
12
12
  end
13
13
 
14
14
  def encode
15
- SMADDL(@rm.to_i, @ra.to_i, @rn.to_i, @rd.to_i)
15
+ SMADDL(@rm, @ra, @rn, @rd)
16
16
  end
17
17
 
18
18
  private
19
19
 
20
20
  def SMADDL rm, ra, rn, rd
21
21
  insn = 0b1_00_11011_0_01_00000_0_00000_00000_00000
22
- insn |= ((rm & 0x1f) << 16)
23
- insn |= ((ra & 0x1f) << 10)
24
- insn |= ((rn & 0x1f) << 5)
25
- insn |= (rd & 0x1f)
22
+ insn |= ((rm) << 16)
23
+ insn |= ((ra) << 10)
24
+ insn |= ((rn) << 5)
25
+ insn |= (rd)
26
26
  insn
27
27
  end
28
28
  end
@@ -3,9 +3,9 @@ module AArch64
3
3
  # SMC -- A64
4
4
  # Secure Monitor Call
5
5
  # SMC #<imm>
6
- class SMC
6
+ class SMC < Instruction
7
7
  def initialize imm16
8
- @imm16 = imm16
8
+ @imm16 = check_mask(imm16, 0xffff)
9
9
  end
10
10
 
11
11
  def encode
@@ -16,7 +16,7 @@ module AArch64
16
16
 
17
17
  def SMC imm16
18
18
  insn = 0b11010100_000_0000000000000000_000_11
19
- insn |= ((imm16 & 0xffff) << 5)
19
+ insn |= ((imm16) << 5)
20
20
  insn
21
21
  end
22
22
  end
@@ -3,26 +3,26 @@ module AArch64
3
3
  # SMSUBL -- A64
4
4
  # Signed Multiply-Subtract Long
5
5
  # SMSUBL <Xd>, <Wn>, <Wm>, <Xa>
6
- class SMSUBL
6
+ class SMSUBL < Instruction
7
7
  def initialize rd, rn, rm, ra
8
- @rd = rd
9
- @rn = rn
10
- @rm = rm
11
- @ra = ra
8
+ @rd = check_mask(rd, 0x1f)
9
+ @rn = check_mask(rn, 0x1f)
10
+ @rm = check_mask(rm, 0x1f)
11
+ @ra = check_mask(ra, 0x1f)
12
12
  end
13
13
 
14
14
  def encode
15
- SMSUBL(@rm.to_i, @ra.to_i, @rn.to_i, @rd.to_i)
15
+ SMSUBL(@rm, @ra, @rn, @rd)
16
16
  end
17
17
 
18
18
  private
19
19
 
20
20
  def SMSUBL rm, ra, rn, rd
21
21
  insn = 0b1_00_11011_0_01_00000_1_00000_00000_00000
22
- insn |= ((rm & 0x1f) << 16)
23
- insn |= ((ra & 0x1f) << 10)
24
- insn |= ((rn & 0x1f) << 5)
25
- insn |= (rd & 0x1f)
22
+ insn |= ((rm) << 16)
23
+ insn |= ((ra) << 10)
24
+ insn |= ((rn) << 5)
25
+ insn |= (rd)
26
26
  insn
27
27
  end
28
28
  end
@@ -3,24 +3,24 @@ module AArch64
3
3
  # SMULH -- A64
4
4
  # Signed Multiply High
5
5
  # SMULH <Xd>, <Xn>, <Xm>
6
- class SMULH
6
+ class SMULH < Instruction
7
7
  def initialize rd, rn, rm
8
- @rd = rd
9
- @rn = rn
10
- @rm = rm
8
+ @rd = check_mask(rd, 0x1f)
9
+ @rn = check_mask(rn, 0x1f)
10
+ @rm = check_mask(rm, 0x1f)
11
11
  end
12
12
 
13
13
  def encode
14
- SMULH(@rm.to_i, @rn.to_i, @rd.to_i)
14
+ SMULH(@rm, @rn, @rd)
15
15
  end
16
16
 
17
17
  private
18
18
 
19
19
  def SMULH rm, rn, rd
20
20
  insn = 0b1_00_11011_0_10_00000_0_11111_00000_00000
21
- insn |= ((rm & 0x1f) << 16)
22
- insn |= ((rn & 0x1f) << 5)
23
- insn |= (rd & 0x1f)
21
+ insn |= ((rm) << 16)
22
+ insn |= ((rn) << 5)
23
+ insn |= (rd)
24
24
  insn
25
25
  end
26
26
  end
@@ -5,26 +5,26 @@ module AArch64
5
5
  # ST2G <Xt|SP>, [<Xn|SP>], #<simm>
6
6
  # ST2G <Xt|SP>, [<Xn|SP>, #<simm>]!
7
7
  # ST2G <Xt|SP>, [<Xn|SP>{, #<simm>}]
8
- class ST2G
8
+ class ST2G < Instruction
9
9
  def initialize xt, xn, imm9, option
10
- @xt = xt
11
- @xn = xn
12
- @imm9 = imm9
13
- @option = option
10
+ @xt = check_mask(xt, 0x1f)
11
+ @xn = check_mask(xn, 0x1f)
12
+ @imm9 = check_mask(imm9, 0x1ff)
13
+ @option = check_mask(option, 0x03)
14
14
  end
15
15
 
16
16
  def encode
17
- ST2G(@imm9, @option, @xn.to_i, @xt.to_i)
17
+ ST2G(@imm9, @option, @xn, @xt)
18
18
  end
19
19
 
20
20
  private
21
21
 
22
22
  def ST2G imm9, option, xn, xt
23
23
  insn = 0b11011001_1_0_1_000000000_00_00000_00000
24
- insn |= ((imm9 & 0x1ff) << 12)
25
- insn |= ((option & 0x3) << 10)
26
- insn |= ((xn & 0x1f) << 5)
27
- insn |= (xt & 0x1f)
24
+ insn |= ((imm9) << 12)
25
+ insn |= ((option) << 10)
26
+ insn |= ((xn) << 5)
27
+ insn |= (xt)
28
28
  insn
29
29
  end
30
30
  end
@@ -3,22 +3,22 @@ module AArch64
3
3
  # ST64B -- A64
4
4
  # Single-copy Atomic 64-byte Store without Return
5
5
  # ST64B <Xt>, [<Xn|SP> {,#0}]
6
- class ST64B
6
+ class ST64B < Instruction
7
7
  def initialize rt, rn
8
- @rt = rt
9
- @rn = rn
8
+ @rt = check_mask(rt, 0x1f)
9
+ @rn = check_mask(rn, 0x1f)
10
10
  end
11
11
 
12
12
  def encode
13
- ST64B(@rn.to_i, @rt.to_i)
13
+ ST64B(@rn, @rt)
14
14
  end
15
15
 
16
16
  private
17
17
 
18
18
  def ST64B rn, rt
19
19
  insn = 0b11_111_0_00_0_0_1_11111_1_001_00_00000_00000
20
- insn |= ((rn & 0x1f) << 5)
21
- insn |= (rt & 0x1f)
20
+ insn |= ((rn) << 5)
21
+ insn |= (rt)
22
22
  insn
23
23
  end
24
24
  end
@@ -3,24 +3,24 @@ module AArch64
3
3
  # ST64BV -- A64
4
4
  # Single-copy Atomic 64-byte Store with Return
5
5
  # ST64BV <Xs>, <Xt>, [<Xn|SP>]
6
- class ST64BV
6
+ class ST64BV < Instruction
7
7
  def initialize rs, rt, rn
8
- @rs = rs
9
- @rt = rt
10
- @rn = rn
8
+ @rs = check_mask(rs, 0x1f)
9
+ @rt = check_mask(rt, 0x1f)
10
+ @rn = check_mask(rn, 0x1f)
11
11
  end
12
12
 
13
13
  def encode
14
- ST64BV(@rs.to_i, @rn.to_i, @rt.to_i)
14
+ ST64BV(@rs, @rn, @rt)
15
15
  end
16
16
 
17
17
  private
18
18
 
19
19
  def ST64BV rs, rn, rt
20
20
  insn = 0b11_111_0_00_0_0_1_00000_1_011_00_00000_00000
21
- insn |= ((rs & 0x1f) << 16)
22
- insn |= ((rn & 0x1f) << 5)
23
- insn |= (rt & 0x1f)
21
+ insn |= ((rs) << 16)
22
+ insn |= ((rn) << 5)
23
+ insn |= (rt)
24
24
  insn
25
25
  end
26
26
  end
@@ -3,24 +3,24 @@ module AArch64
3
3
  # ST64BV0 -- A64
4
4
  # Single-copy Atomic 64-byte EL0 Store with Return
5
5
  # ST64BV0 <Xs>, <Xt>, [<Xn|SP>]
6
- class ST64BV0
6
+ class ST64BV0 < Instruction
7
7
  def initialize rs, rt, rn
8
- @rs = rs
9
- @rt = rt
10
- @rn = rn
8
+ @rs = check_mask(rs, 0x1f)
9
+ @rt = check_mask(rt, 0x1f)
10
+ @rn = check_mask(rn, 0x1f)
11
11
  end
12
12
 
13
13
  def encode
14
- ST64BV0(@rs.to_i, @rn.to_i, @rt.to_i)
14
+ ST64BV0(@rs, @rn, @rt)
15
15
  end
16
16
 
17
17
  private
18
18
 
19
19
  def ST64BV0 rs, rn, rt
20
20
  insn = 0b11_111_0_00_0_0_1_00000_1_010_00_00000_00000
21
- insn |= ((rs & 0x1f) << 16)
22
- insn |= ((rn & 0x1f) << 5)
23
- insn |= (rt & 0x1f)
21
+ insn |= ((rs) << 16)
22
+ insn |= ((rn) << 5)
23
+ insn |= (rt)
24
24
  insn
25
25
  end
26
26
  end
@@ -5,26 +5,26 @@ module AArch64
5
5
  # STG <Xt|SP>, [<Xn|SP>], #<simm>
6
6
  # STG <Xt|SP>, [<Xn|SP>, #<simm>]!
7
7
  # STG <Xt|SP>, [<Xn|SP>{, #<simm>}]
8
- class STG
8
+ class STG < Instruction
9
9
  def initialize xt, xn, imm9, option
10
- @xt = xt
11
- @xn = xn
12
- @imm9 = imm9
13
- @option = option
10
+ @xt = check_mask(xt, 0x1f)
11
+ @xn = check_mask(xn, 0x1f)
12
+ @imm9 = check_mask(imm9, 0x1ff)
13
+ @option = check_mask(option, 0x03)
14
14
  end
15
15
 
16
16
  def encode
17
- STG(@imm9, @option, @xn.to_i, @xt.to_i)
17
+ STG(@imm9, @option, @xn, @xt)
18
18
  end
19
19
 
20
20
  private
21
21
 
22
22
  def STG imm9, option, xn, xt
23
23
  insn = 0b11011001_0_0_1_000000000_00_00000_00000
24
- insn |= ((imm9 & 0x1ff) << 12)
25
- insn |= ((option & 0x3) << 10)
26
- insn |= ((xn & 0x1f) << 5)
27
- insn |= (xt & 0x1f)
24
+ insn |= ((imm9) << 12)
25
+ insn |= ((option) << 10)
26
+ insn |= ((xn) << 5)
27
+ insn |= (xt)
28
28
  insn
29
29
  end
30
30
  end
@@ -3,22 +3,22 @@ module AArch64
3
3
  # STGM -- A64
4
4
  # Store Tag Multiple
5
5
  # STGM <Xt>, [<Xn|SP>]
6
- class STGM
6
+ class STGM < Instruction
7
7
  def initialize xt, xn
8
- @xt = xt
9
- @xn = xn
8
+ @xt = check_mask(xt, 0x1f)
9
+ @xn = check_mask(xn, 0x1f)
10
10
  end
11
11
 
12
12
  def encode
13
- STGM(@xn.to_i, @xt.to_i)
13
+ STGM(@xn, @xt)
14
14
  end
15
15
 
16
16
  private
17
17
 
18
18
  def STGM xn, xt
19
19
  insn = 0b11011001_1_0_1_0_0_0_0_0_0_0_0_0_0_0_00000_00000
20
- insn |= ((xn & 0x1f) << 5)
21
- insn |= (xt & 0x1f)
20
+ insn |= ((xn) << 5)
21
+ insn |= (xt)
22
22
  insn
23
23
  end
24
24
  end
@@ -5,28 +5,28 @@ module AArch64
5
5
  # STGP <Xt1>, <Xt2>, [<Xn|SP>], #<imm>
6
6
  # STGP <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]!
7
7
  # STGP <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]
8
- class STGP
8
+ class STGP < Instruction
9
9
  def initialize xt, xt2, xn, simm7, option
10
- @xt = xt
11
- @xt2 = xt2
12
- @xn = xn
13
- @simm7 = simm7
14
- @option = option
10
+ @xt = check_mask(xt, 0x1f)
11
+ @xt2 = check_mask(xt2, 0x1f)
12
+ @xn = check_mask(xn, 0x1f)
13
+ @simm7 = check_mask(simm7, 0x7f)
14
+ @option = check_mask(option, 0x03)
15
15
  end
16
16
 
17
17
  def encode
18
- STGP(@option, @simm7, @xt2.to_i, @xn.to_i, @xt.to_i)
18
+ STGP(@option, @simm7, @xt2, @xn, @xt)
19
19
  end
20
20
 
21
21
  private
22
22
 
23
23
  def STGP option, simm7, xt2, xn, xt
24
24
  insn = 0b0_1_101_0_000_0_0000000_00000_00000_00000
25
- insn |= ((option & 0x3) << 23)
26
- insn |= ((simm7 & 0x7f) << 15)
27
- insn |= ((xt2 & 0x1f) << 10)
28
- insn |= ((xn & 0x1f) << 5)
29
- insn |= (xt & 0x1f)
25
+ insn |= ((option) << 23)
26
+ insn |= ((simm7) << 15)
27
+ insn |= ((xt2) << 10)
28
+ insn |= ((xn) << 5)
29
+ insn |= (xt)
30
30
  insn
31
31
  end
32
32
  end
@@ -4,24 +4,24 @@ module AArch64
4
4
  # Store LORelease Register
5
5
  # STLLR <Wt>, [<Xn|SP>{,#0}]
6
6
  # STLLR <Xt>, [<Xn|SP>{,#0}]
7
- class STLLR
7
+ class STLLR < Instruction
8
8
  def initialize rt, rn, size
9
- @rt = rt
10
- @rn = rn
11
- @size = size
9
+ @rt = check_mask(rt, 0x1f)
10
+ @rn = check_mask(rn, 0x1f)
11
+ @size = check_mask(size, 0x03)
12
12
  end
13
13
 
14
14
  def encode
15
- STLLR(@size, @rn.to_i, @rt.to_i)
15
+ STLLR(@size, @rn, @rt)
16
16
  end
17
17
 
18
18
  private
19
19
 
20
20
  def STLLR size, rn, rt
21
21
  insn = 0b00_001000_1_0_0_11111_0_11111_00000_00000
22
- insn |= ((size & 0x3) << 30)
23
- insn |= ((rn & 0x1f) << 5)
24
- insn |= (rt & 0x1f)
22
+ insn |= ((size) << 30)
23
+ insn |= ((rn) << 5)
24
+ insn |= (rt)
25
25
  insn
26
26
  end
27
27
  end
@@ -3,22 +3,22 @@ module AArch64
3
3
  # STLLRB -- A64
4
4
  # Store LORelease Register Byte
5
5
  # STLLRB <Wt>, [<Xn|SP>{,#0}]
6
- class STLLRB
6
+ class STLLRB < Instruction
7
7
  def initialize rt, rn
8
- @rt = rt
9
- @rn = rn
8
+ @rt = check_mask(rt, 0x1f)
9
+ @rn = check_mask(rn, 0x1f)
10
10
  end
11
11
 
12
12
  def encode
13
- STLLRB(@rn.to_i, @rt.to_i)
13
+ STLLRB(@rn, @rt)
14
14
  end
15
15
 
16
16
  private
17
17
 
18
18
  def STLLRB rn, rt
19
19
  insn = 0b00_001000_1_0_0_11111_0_11111_00000_00000
20
- insn |= ((rn & 0x1f) << 5)
21
- insn |= (rt & 0x1f)
20
+ insn |= ((rn) << 5)
21
+ insn |= (rt)
22
22
  insn
23
23
  end
24
24
  end
@@ -3,22 +3,22 @@ module AArch64
3
3
  # STLLRH -- A64
4
4
  # Store LORelease Register Halfword
5
5
  # STLLRH <Wt>, [<Xn|SP>{,#0}]
6
- class STLLRH
6
+ class STLLRH < Instruction
7
7
  def initialize rt, rn
8
- @rt = rt
9
- @rn = rn
8
+ @rt = check_mask(rt, 0x1f)
9
+ @rn = check_mask(rn, 0x1f)
10
10
  end
11
11
 
12
12
  def encode
13
- STLLRH(@rn.to_i, @rt.to_i)
13
+ STLLRH(@rn, @rt)
14
14
  end
15
15
 
16
16
  private
17
17
 
18
18
  def STLLRH rn, rt
19
19
  insn = 0b01_001000_1_0_0_11111_0_11111_00000_00000
20
- insn |= ((rn & 0x1f) << 5)
21
- insn |= (rt & 0x1f)
20
+ insn |= ((rn) << 5)
21
+ insn |= (rt)
22
22
  insn
23
23
  end
24
24
  end
@@ -4,24 +4,24 @@ module AArch64
4
4
  # Store-Release Register
5
5
  # STLR <Wt>, [<Xn|SP>{,#0}]
6
6
  # STLR <Xt>, [<Xn|SP>{,#0}]
7
- class STLR
7
+ class STLR < Instruction
8
8
  def initialize rt, rn, size
9
- @rt = rt
10
- @rn = rn
11
- @size = size
9
+ @rt = check_mask(rt, 0x1f)
10
+ @rn = check_mask(rn, 0x1f)
11
+ @size = check_mask(size, 0x03)
12
12
  end
13
13
 
14
14
  def encode
15
- STLR(@size, @rn.to_i, @rt.to_i)
15
+ STLR(@size, @rn, @rt)
16
16
  end
17
17
 
18
18
  private
19
19
 
20
20
  def STLR size, rn, rt
21
21
  insn = 0b00_001000_1_0_0_11111_1_11111_00000_00000
22
- insn |= ((size & 0x3) << 30)
23
- insn |= ((rn & 0x1f) << 5)
24
- insn |= (rt & 0x1f)
22
+ insn |= ((size) << 30)
23
+ insn |= ((rn) << 5)
24
+ insn |= (rt)
25
25
  insn
26
26
  end
27
27
  end
@@ -3,22 +3,22 @@ module AArch64
3
3
  # STLRB -- A64
4
4
  # Store-Release Register Byte
5
5
  # STLRB <Wt>, [<Xn|SP>{,#0}]
6
- class STLRB
6
+ class STLRB < Instruction
7
7
  def initialize rt, rn
8
- @rt = rt
9
- @rn = rn
8
+ @rt = check_mask(rt, 0x1f)
9
+ @rn = check_mask(rn, 0x1f)
10
10
  end
11
11
 
12
12
  def encode
13
- STLRB(@rn.to_i, @rt.to_i)
13
+ STLRB(@rn, @rt)
14
14
  end
15
15
 
16
16
  private
17
17
 
18
18
  def STLRB rn, rt
19
19
  insn = 0b00_001000_1_0_0_11111_1_11111_00000_00000
20
- insn |= ((rn & 0x1f) << 5)
21
- insn |= (rt & 0x1f)
20
+ insn |= ((rn) << 5)
21
+ insn |= (rt)
22
22
  insn
23
23
  end
24
24
  end
@@ -3,22 +3,22 @@ module AArch64
3
3
  # STLRH -- A64
4
4
  # Store-Release Register Halfword
5
5
  # STLRH <Wt>, [<Xn|SP>{,#0}]
6
- class STLRH
6
+ class STLRH < Instruction
7
7
  def initialize rt, rn
8
- @rt = rt
9
- @rn = rn
8
+ @rt = check_mask(rt, 0x1f)
9
+ @rn = check_mask(rn, 0x1f)
10
10
  end
11
11
 
12
12
  def encode
13
- STLRH(@rn.to_i, @rt.to_i)
13
+ STLRH(@rn, @rt)
14
14
  end
15
15
 
16
16
  private
17
17
 
18
18
  def STLRH rn, rt
19
19
  insn = 0b01_001000_1_0_0_11111_1_11111_00000_00000
20
- insn |= ((rn & 0x1f) << 5)
21
- insn |= (rt & 0x1f)
20
+ insn |= ((rn) << 5)
21
+ insn |= (rt)
22
22
  insn
23
23
  end
24
24
  end
@@ -4,26 +4,26 @@ module AArch64
4
4
  # Store-Release Register (unscaled)
5
5
  # STLUR <Wt>, [<Xn|SP>{, #<simm>}]
6
6
  # STLUR <Xt>, [<Xn|SP>{, #<simm>}]
7
- class STLUR_gen
7
+ class STLUR_gen < Instruction
8
8
  def initialize rt, rn, imm9, size
9
- @rt = rt
10
- @rn = rn
11
- @imm9 = imm9
12
- @size = size
9
+ @rt = check_mask(rt, 0x1f)
10
+ @rn = check_mask(rn, 0x1f)
11
+ @imm9 = check_mask(imm9, 0x1ff)
12
+ @size = check_mask(size, 0x03)
13
13
  end
14
14
 
15
15
  def encode
16
- STLUR_gen(@size, @imm9, @rn.to_i, @rt.to_i)
16
+ STLUR_gen(@size, @imm9, @rn, @rt)
17
17
  end
18
18
 
19
19
  private
20
20
 
21
21
  def STLUR_gen size, imm9, rn, rt
22
22
  insn = 0b00_011001_00_0_000000000_00_00000_00000
23
- insn |= ((size & 0x3) << 30)
24
- insn |= ((imm9 & 0x1ff) << 12)
25
- insn |= ((rn & 0x1f) << 5)
26
- insn |= (rt & 0x1f)
23
+ insn |= ((size) << 30)
24
+ insn |= ((imm9) << 12)
25
+ insn |= ((rn) << 5)
26
+ insn |= (rt)
27
27
  insn
28
28
  end
29
29
  end
@@ -4,28 +4,28 @@ module AArch64
4
4
  # Store-Release Exclusive Pair of registers
5
5
  # STLXP <Ws>, <Wt1>, <Wt2>, [<Xn|SP>{,#0}]
6
6
  # STLXP <Ws>, <Xt1>, <Xt2>, [<Xn|SP>{,#0}]
7
- class STLXP
7
+ class STLXP < Instruction
8
8
  def initialize rs, rt, rt2, rn, sz
9
- @rs = rs
10
- @rt = rt
11
- @rt2 = rt2
12
- @rn = rn
13
- @sz = sz
9
+ @rs = check_mask(rs, 0x1f)
10
+ @rt = check_mask(rt, 0x1f)
11
+ @rt2 = check_mask(rt2, 0x1f)
12
+ @rn = check_mask(rn, 0x1f)
13
+ @sz = check_mask(sz, 0x01)
14
14
  end
15
15
 
16
16
  def encode
17
- STLXP(@sz, @rs.to_i, @rt2.to_i, @rn.to_i, @rt.to_i)
17
+ STLXP(@sz, @rs, @rt2, @rn, @rt)
18
18
  end
19
19
 
20
20
  private
21
21
 
22
22
  def STLXP sz, rs, rt2, rn, rt
23
23
  insn = 0b1_0_001000_0_0_1_00000_1_00000_00000_00000
24
- insn |= ((sz & 0x1) << 30)
25
- insn |= ((rs & 0x1f) << 16)
26
- insn |= ((rt2 & 0x1f) << 10)
27
- insn |= ((rn & 0x1f) << 5)
28
- insn |= (rt & 0x1f)
24
+ insn |= ((sz) << 30)
25
+ insn |= ((rs) << 16)
26
+ insn |= ((rt2) << 10)
27
+ insn |= ((rn) << 5)
28
+ insn |= (rt)
29
29
  insn
30
30
  end
31
31
  end