aarch64 1.0.1 → 2.0.0

data/lib/aarch64/instructions/sev.rb

@@ -3,14 +3,8 @@ module AArch64
     # SEV -- A64
     # Send Event
     # SEV
-    class SEV
+    class SEV < Instruction
       def encode
-        SEV()
-      end
-
-      private
-
-      def SEV
         0b1101010100_0_00_011_0010_0000_100_11111
       end
     end

data/lib/aarch64/instructions/sevl.rb

@@ -3,7 +3,7 @@ module AArch64
     # SEVL -- A64
     # Send Event Local
     # SEVL
-    class SEVL
+    class SEVL < Instruction
       def encode
         0b1101010100_0_00_011_0010_0000_101_11111
       end

data/lib/aarch64/instructions/smaddl.rb

@@ -3,26 +3,26 @@ module AArch64
     # SMADDL -- A64
     # Signed Multiply-Add Long
     # SMADDL  <Xd>, <Wn>, <Wm>, <Xa>
-    class SMADDL
+    class SMADDL < Instruction
       def initialize rd, rn, rm, ra
-        @rd = rd
-        @rn = rn
-        @rm = rm
-        @ra = ra
+        @rd = check_mask(rd, 0x1f)
+        @rn = check_mask(rn, 0x1f)
+        @rm = check_mask(rm, 0x1f)
+        @ra = check_mask(ra, 0x1f)
       end
 
       def encode
-        SMADDL(@rm.to_i, @ra.to_i, @rn.to_i, @rd.to_i)
+        SMADDL(@rm, @ra, @rn, @rd)
       end
 
       private
 
       def SMADDL rm, ra, rn, rd
         insn = 0b1_00_11011_0_01_00000_0_00000_00000_00000
-        insn |= ((rm & 0x1f) << 16)
-        insn |= ((ra & 0x1f) << 10)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rd & 0x1f)
+        insn |= ((rm) << 16)
+        insn |= ((ra) << 10)
+        insn |= ((rn) << 5)
+        insn |= (rd)
         insn
       end
     end

data/lib/aarch64/instructions/smc.rb

@@ -3,9 +3,9 @@ module AArch64
     # SMC -- A64
     # Secure Monitor Call
     # SMC  #<imm>
-    class SMC
+    class SMC < Instruction
       def initialize imm16
-        @imm16 = imm16
+        @imm16 = check_mask(imm16, 0xffff)
       end
 
       def encode
@@ -16,7 +16,7 @@ module AArch64
 
       def SMC imm16
         insn = 0b11010100_000_0000000000000000_000_11
-        insn |= ((imm16 & 0xffff) << 5)
+        insn |= ((imm16) << 5)
         insn
       end
     end

data/lib/aarch64/instructions/smsubl.rb

@@ -3,26 +3,26 @@ module AArch64
     # SMSUBL -- A64
     # Signed Multiply-Subtract Long
     # SMSUBL  <Xd>, <Wn>, <Wm>, <Xa>
-    class SMSUBL
+    class SMSUBL < Instruction
       def initialize rd, rn, rm, ra
-        @rd = rd
-        @rn = rn
-        @rm = rm
-        @ra = ra
+        @rd = check_mask(rd, 0x1f)
+        @rn = check_mask(rn, 0x1f)
+        @rm = check_mask(rm, 0x1f)
+        @ra = check_mask(ra, 0x1f)
       end
 
       def encode
-        SMSUBL(@rm.to_i, @ra.to_i, @rn.to_i, @rd.to_i)
+        SMSUBL(@rm, @ra, @rn, @rd)
       end
 
       private
 
       def SMSUBL rm, ra, rn, rd
         insn = 0b1_00_11011_0_01_00000_1_00000_00000_00000
-        insn |= ((rm & 0x1f) << 16)
-        insn |= ((ra & 0x1f) << 10)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rd & 0x1f)
+        insn |= ((rm) << 16)
+        insn |= ((ra) << 10)
+        insn |= ((rn) << 5)
+        insn |= (rd)
         insn
       end
     end

data/lib/aarch64/instructions/smulh.rb

@@ -3,24 +3,24 @@ module AArch64
     # SMULH -- A64
     # Signed Multiply High
     # SMULH  <Xd>, <Xn>, <Xm>
-    class SMULH
+    class SMULH < Instruction
       def initialize rd, rn, rm
-        @rd = rd
-        @rn = rn
-        @rm = rm
+        @rd = check_mask(rd, 0x1f)
+        @rn = check_mask(rn, 0x1f)
+        @rm = check_mask(rm, 0x1f)
       end
 
       def encode
-        SMULH(@rm.to_i, @rn.to_i, @rd.to_i)
+        SMULH(@rm, @rn, @rd)
       end
 
       private
 
       def SMULH rm, rn, rd
         insn = 0b1_00_11011_0_10_00000_0_11111_00000_00000
-        insn |= ((rm & 0x1f) << 16)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rd & 0x1f)
+        insn |= ((rm) << 16)
+        insn |= ((rn) << 5)
+        insn |= (rd)
         insn
       end
     end

data/lib/aarch64/instructions/st2g.rb

@@ -5,26 +5,26 @@ module AArch64
     # ST2G  <Xt|SP>, [<Xn|SP>], #<simm>
     # ST2G  <Xt|SP>, [<Xn|SP>, #<simm>]!
     # ST2G  <Xt|SP>, [<Xn|SP>{, #<simm>}]
-    class ST2G
+    class ST2G < Instruction
       def initialize xt, xn, imm9, option
-        @xt     = xt
-        @xn     = xn
-        @imm9   = imm9
-        @option = option
+        @xt     = check_mask(xt, 0x1f)
+        @xn     = check_mask(xn, 0x1f)
+        @imm9   = check_mask(imm9, 0x1ff)
+        @option = check_mask(option, 0x03)
       end
 
       def encode
-        ST2G(@imm9, @option, @xn.to_i, @xt.to_i)
+        ST2G(@imm9, @option, @xn, @xt)
       end
 
       private
 
       def ST2G imm9, option, xn, xt
         insn = 0b11011001_1_0_1_000000000_00_00000_00000
-        insn |= ((imm9 & 0x1ff) << 12)
-        insn |= ((option & 0x3) << 10)
-        insn |= ((xn & 0x1f) << 5)
-        insn |= (xt & 0x1f)
+        insn |= ((imm9) << 12)
+        insn |= ((option) << 10)
+        insn |= ((xn) << 5)
+        insn |= (xt)
         insn
       end
     end

data/lib/aarch64/instructions/st64b.rb

@@ -3,22 +3,22 @@ module AArch64
     # ST64B -- A64
     # Single-copy Atomic 64-byte Store without Return
     # ST64B  <Xt>, [<Xn|SP> {,#0}]
-    class ST64B
+    class ST64B < Instruction
       def initialize rt, rn
-        @rt = rt
-        @rn = rn
+        @rt = check_mask(rt, 0x1f)
+        @rn = check_mask(rn, 0x1f)
       end
 
       def encode
-        ST64B(@rn.to_i, @rt.to_i)
+        ST64B(@rn, @rt)
       end
 
       private
 
       def ST64B rn, rt
         insn = 0b11_111_0_00_0_0_1_11111_1_001_00_00000_00000
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/st64bv.rb

@@ -3,24 +3,24 @@ module AArch64
     # ST64BV -- A64
     # Single-copy Atomic 64-byte Store with Return
     # ST64BV  <Xs>, <Xt>, [<Xn|SP>]
-    class ST64BV
+    class ST64BV < Instruction
       def initialize rs, rt, rn
-        @rs = rs
-        @rt = rt
-        @rn = rn
+        @rs = check_mask(rs, 0x1f)
+        @rt = check_mask(rt, 0x1f)
+        @rn = check_mask(rn, 0x1f)
       end
 
       def encode
-        ST64BV(@rs.to_i, @rn.to_i, @rt.to_i)
+        ST64BV(@rs, @rn, @rt)
       end
 
       private
 
       def ST64BV rs, rn, rt
         insn = 0b11_111_0_00_0_0_1_00000_1_011_00_00000_00000
-        insn |= ((rs & 0x1f) << 16)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((rs) << 16)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/st64bv0.rb

@@ -3,24 +3,24 @@ module AArch64
     # ST64BV0 -- A64
     # Single-copy Atomic 64-byte EL0 Store with Return
     # ST64BV0  <Xs>, <Xt>, [<Xn|SP>]
-    class ST64BV0
+    class ST64BV0 < Instruction
       def initialize rs, rt, rn
-        @rs = rs
-        @rt = rt
-        @rn = rn
+        @rs = check_mask(rs, 0x1f)
+        @rt = check_mask(rt, 0x1f)
+        @rn = check_mask(rn, 0x1f)
       end
 
       def encode
-        ST64BV0(@rs.to_i, @rn.to_i, @rt.to_i)
+        ST64BV0(@rs, @rn, @rt)
       end
 
       private
 
       def ST64BV0 rs, rn, rt
         insn = 0b11_111_0_00_0_0_1_00000_1_010_00_00000_00000
-        insn |= ((rs & 0x1f) << 16)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((rs) << 16)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/stg.rb

@@ -5,26 +5,26 @@ module AArch64
     # STG  <Xt|SP>, [<Xn|SP>], #<simm>
     # STG  <Xt|SP>, [<Xn|SP>, #<simm>]!
     # STG  <Xt|SP>, [<Xn|SP>{, #<simm>}]
-    class STG
+    class STG < Instruction
       def initialize xt, xn, imm9, option
-        @xt     = xt
-        @xn     = xn
-        @imm9   = imm9
-        @option = option
+        @xt     = check_mask(xt, 0x1f)
+        @xn     = check_mask(xn, 0x1f)
+        @imm9   = check_mask(imm9, 0x1ff)
+        @option = check_mask(option, 0x03)
       end
 
       def encode
-        STG(@imm9, @option, @xn.to_i, @xt.to_i)
+        STG(@imm9, @option, @xn, @xt)
       end
 
       private
 
       def STG imm9, option, xn, xt
         insn = 0b11011001_0_0_1_000000000_00_00000_00000
-        insn |= ((imm9 & 0x1ff) << 12)
-        insn |= ((option & 0x3) << 10)
-        insn |= ((xn & 0x1f) << 5)
-        insn |= (xt & 0x1f)
+        insn |= ((imm9) << 12)
+        insn |= ((option) << 10)
+        insn |= ((xn) << 5)
+        insn |= (xt)
         insn
       end
     end

data/lib/aarch64/instructions/stgm.rb

@@ -3,22 +3,22 @@ module AArch64
     # STGM -- A64
     # Store Tag Multiple
     # STGM  <Xt>, [<Xn|SP>]
-    class STGM
+    class STGM < Instruction
       def initialize xt, xn
-        @xt = xt
-        @xn = xn
+        @xt = check_mask(xt, 0x1f)
+        @xn = check_mask(xn, 0x1f)
       end
 
       def encode
-        STGM(@xn.to_i, @xt.to_i)
+        STGM(@xn, @xt)
       end
 
       private
 
       def STGM xn, xt
         insn = 0b11011001_1_0_1_0_0_0_0_0_0_0_0_0_0_0_00000_00000
-        insn |= ((xn & 0x1f) << 5)
-        insn |= (xt & 0x1f)
+        insn |= ((xn) << 5)
+        insn |= (xt)
         insn
       end
     end

data/lib/aarch64/instructions/stgp.rb

@@ -5,28 +5,28 @@ module AArch64
     # STGP  <Xt1>, <Xt2>, [<Xn|SP>], #<imm>
     # STGP  <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]!
     # STGP  <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]
-    class STGP
+    class STGP < Instruction
       def initialize xt, xt2, xn, simm7, option
-        @xt     = xt
-        @xt2    = xt2
-        @xn     = xn
-        @simm7  = simm7
-        @option = option
+        @xt     = check_mask(xt, 0x1f)
+        @xt2    = check_mask(xt2, 0x1f)
+        @xn     = check_mask(xn, 0x1f)
+        @simm7  = check_mask(simm7, 0x7f)
+        @option = check_mask(option, 0x03)
       end
 
       def encode
-        STGP(@option, @simm7, @xt2.to_i, @xn.to_i, @xt.to_i)
+        STGP(@option, @simm7, @xt2, @xn, @xt)
       end
 
       private
 
       def STGP option, simm7, xt2, xn, xt
         insn = 0b0_1_101_0_000_0_0000000_00000_00000_00000
-        insn |= ((option & 0x3) << 23)
-        insn |= ((simm7 & 0x7f) << 15)
-        insn |= ((xt2 & 0x1f) << 10)
-        insn |= ((xn & 0x1f) << 5)
-        insn |= (xt & 0x1f)
+        insn |= ((option) << 23)
+        insn |= ((simm7) << 15)
+        insn |= ((xt2) << 10)
+        insn |= ((xn) << 5)
+        insn |= (xt)
         insn
       end
     end

data/lib/aarch64/instructions/stllr.rb

@@ -4,24 +4,24 @@ module AArch64
     # Store LORelease Register
     # STLLR  <Wt>, [<Xn|SP>{,#0}]
     # STLLR  <Xt>, [<Xn|SP>{,#0}]
-    class STLLR
+    class STLLR < Instruction
       def initialize rt, rn, size
-        @rt   = rt
-        @rn   = rn
-        @size = size
+        @rt   = check_mask(rt, 0x1f)
+        @rn   = check_mask(rn, 0x1f)
+        @size = check_mask(size, 0x03)
       end
 
       def encode
-        STLLR(@size, @rn.to_i, @rt.to_i)
+        STLLR(@size, @rn, @rt)
       end
 
       private
 
       def STLLR size, rn, rt
         insn = 0b00_001000_1_0_0_11111_0_11111_00000_00000
-        insn |= ((size & 0x3) << 30)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((size) << 30)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/stllrb.rb

@@ -3,22 +3,22 @@ module AArch64
     # STLLRB -- A64
     # Store LORelease Register Byte
     # STLLRB  <Wt>, [<Xn|SP>{,#0}]
-    class STLLRB
+    class STLLRB < Instruction
       def initialize rt, rn
-        @rt = rt
-        @rn = rn
+        @rt = check_mask(rt, 0x1f)
+        @rn = check_mask(rn, 0x1f)
       end
 
       def encode
-        STLLRB(@rn.to_i, @rt.to_i)
+        STLLRB(@rn, @rt)
       end
 
       private
 
       def STLLRB rn, rt
         insn = 0b00_001000_1_0_0_11111_0_11111_00000_00000
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/stllrh.rb

@@ -3,22 +3,22 @@ module AArch64
     # STLLRH -- A64
     # Store LORelease Register Halfword
     # STLLRH  <Wt>, [<Xn|SP>{,#0}]
-    class STLLRH
+    class STLLRH < Instruction
       def initialize rt, rn
-        @rt = rt
-        @rn = rn
+        @rt = check_mask(rt, 0x1f)
+        @rn = check_mask(rn, 0x1f)
       end
 
       def encode
-        STLLRH(@rn.to_i, @rt.to_i)
+        STLLRH(@rn, @rt)
       end
 
       private
 
       def STLLRH rn, rt
         insn = 0b01_001000_1_0_0_11111_0_11111_00000_00000
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/stlr.rb

@@ -4,24 +4,24 @@ module AArch64
     # Store-Release Register
     # STLR  <Wt>, [<Xn|SP>{,#0}]
     # STLR  <Xt>, [<Xn|SP>{,#0}]
-    class STLR
+    class STLR < Instruction
       def initialize rt, rn, size
-        @rt   = rt
-        @rn   = rn
-        @size = size
+        @rt   = check_mask(rt, 0x1f)
+        @rn   = check_mask(rn, 0x1f)
+        @size = check_mask(size, 0x03)
       end
 
       def encode
-        STLR(@size, @rn.to_i, @rt.to_i)
+        STLR(@size, @rn, @rt)
       end
 
       private
 
       def STLR size, rn, rt
         insn = 0b00_001000_1_0_0_11111_1_11111_00000_00000
-        insn |= ((size & 0x3) << 30)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((size) << 30)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/stlrb.rb

@@ -3,22 +3,22 @@ module AArch64
     # STLRB -- A64
     # Store-Release Register Byte
     # STLRB  <Wt>, [<Xn|SP>{,#0}]
-    class STLRB
+    class STLRB < Instruction
       def initialize rt, rn
-        @rt = rt
-        @rn = rn
+        @rt = check_mask(rt, 0x1f)
+        @rn = check_mask(rn, 0x1f)
       end
 
       def encode
-        STLRB(@rn.to_i, @rt.to_i)
+        STLRB(@rn, @rt)
       end
 
       private
 
       def STLRB rn, rt
         insn = 0b00_001000_1_0_0_11111_1_11111_00000_00000
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/stlrh.rb

@@ -3,22 +3,22 @@ module AArch64
     # STLRH -- A64
     # Store-Release Register Halfword
     # STLRH  <Wt>, [<Xn|SP>{,#0}]
-    class STLRH
+    class STLRH < Instruction
       def initialize rt, rn
-        @rt = rt
-        @rn = rn
+        @rt = check_mask(rt, 0x1f)
+        @rn = check_mask(rn, 0x1f)
       end
 
       def encode
-        STLRH(@rn.to_i, @rt.to_i)
+        STLRH(@rn, @rt)
       end
 
       private
 
       def STLRH rn, rt
         insn = 0b01_001000_1_0_0_11111_1_11111_00000_00000
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/stlur_gen.rb

@@ -4,26 +4,26 @@ module AArch64
     # Store-Release Register (unscaled)
     # STLUR  <Wt>, [<Xn|SP>{, #<simm>}]
     # STLUR  <Xt>, [<Xn|SP>{, #<simm>}]
-    class STLUR_gen
+    class STLUR_gen < Instruction
       def initialize rt, rn, imm9, size
-        @rt   = rt
-        @rn   = rn
-        @imm9 = imm9
-        @size = size
+        @rt   = check_mask(rt, 0x1f)
+        @rn   = check_mask(rn, 0x1f)
+        @imm9 = check_mask(imm9, 0x1ff)
+        @size = check_mask(size, 0x03)
       end
 
       def encode
-        STLUR_gen(@size, @imm9, @rn.to_i, @rt.to_i)
+        STLUR_gen(@size, @imm9, @rn, @rt)
       end
 
       private
 
       def STLUR_gen size, imm9, rn, rt
         insn = 0b00_011001_00_0_000000000_00_00000_00000
-        insn |= ((size & 0x3) << 30)
-        insn |= ((imm9 & 0x1ff) << 12)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((size) << 30)
+        insn |= ((imm9) << 12)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/stlxp.rb

@@ -4,28 +4,28 @@ module AArch64
     # Store-Release Exclusive Pair of registers
     # STLXP  <Ws>, <Wt1>, <Wt2>, [<Xn|SP>{,#0}]
     # STLXP  <Ws>, <Xt1>, <Xt2>, [<Xn|SP>{,#0}]
-    class STLXP
+    class STLXP < Instruction
       def initialize rs, rt, rt2, rn, sz
-        @rs  = rs
-        @rt  = rt
-        @rt2 = rt2
-        @rn  = rn
-        @sz  = sz
+        @rs  = check_mask(rs, 0x1f)
+        @rt  = check_mask(rt, 0x1f)
+        @rt2 = check_mask(rt2, 0x1f)
+        @rn  = check_mask(rn, 0x1f)
+        @sz  = check_mask(sz, 0x01)
       end
 
       def encode
-        STLXP(@sz, @rs.to_i, @rt2.to_i, @rn.to_i, @rt.to_i)
+        STLXP(@sz, @rs, @rt2, @rn, @rt)
       end
 
       private
 
       def STLXP sz, rs, rt2, rn, rt
         insn = 0b1_0_001000_0_0_1_00000_1_00000_00000_00000
-        insn |= ((sz & 0x1) << 30)
-        insn |= ((rs & 0x1f) << 16)
-        insn |= ((rt2 & 0x1f) << 10)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((sz) << 30)
+        insn |= ((rs) << 16)
+        insn |= ((rt2) << 10)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end