aarch64 1.0.1 → 2.0.0

data/lib/aarch64/instructions/csinc.rb

@@ -4,28 +4,28 @@ module AArch64
     # Conditional Select Increment
     # CSINC  <Wd>, <Wn>, <Wm>, <cond>
     # CSINC  <Xd>, <Xn>, <Xm>, <cond>
-    class CSINC
+    class CSINC < Instruction
       def initialize rd, rn, rm, cond, sf
-        @rd   = rd
-        @rn   = rn
-        @rm   = rm
-        @cond = cond
-        @sf   = sf
+        @rd   = check_mask(rd, 0x1f)
+        @rn   = check_mask(rn, 0x1f)
+        @rm   = check_mask(rm, 0x1f)
+        @cond = check_mask(cond, 0x0f)
+        @sf   = check_mask(sf, 0x01)
       end
 
       def encode
-        CSINC(@sf, @rm.to_i, @cond, @rn.to_i, @rd.to_i)
+        CSINC(@sf, @rm, @cond, @rn, @rd)
       end
 
       private
 
       def CSINC sf, rm, cond, rn, rd
         insn = 0b0_0_0_11010100_00000_0000_0_1_00000_00000
-        insn |= ((sf & 0x1) << 31)
-        insn |= ((rm & 0x1f) << 16)
-        insn |= ((cond & 0xf) << 12)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rd & 0x1f)
+        insn |= ((sf) << 31)
+        insn |= ((rm) << 16)
+        insn |= ((cond) << 12)
+        insn |= ((rn) << 5)
+        insn |= (rd)
         insn
       end
     end

data/lib/aarch64/instructions/csinv.rb

@@ -4,28 +4,28 @@ module AArch64
     # Conditional Select Invert
     # CSINV  <Wd>, <Wn>, <Wm>, <cond>
     # CSINV  <Xd>, <Xn>, <Xm>, <cond>
-    class CSINV
+    class CSINV < Instruction
       def initialize rd, rn, rm, cond, sf
-        @rd   = rd
-        @rn   = rn
-        @rm   = rm
-        @cond = cond
-        @sf   = sf
+        @rd   = check_mask(rd, 0x1f)
+        @rn   = check_mask(rn, 0x1f)
+        @rm   = check_mask(rm, 0x1f)
+        @cond = check_mask(cond, 0x0f)
+        @sf   = check_mask(sf, 0x01)
       end
 
       def encode
-        CSINV(@sf, @rm.to_i, @cond, @rn.to_i, @rd.to_i)
+        CSINV(@sf, @rm, @cond, @rn, @rd)
       end
 
       private
 
       def CSINV sf, rm, cond, rn, rd
         insn = 0b0_1_0_11010100_00000_0000_0_0_00000_00000
-        insn |= ((sf & 0x1) << 31)
-        insn |= ((rm & 0x1f) << 16)
-        insn |= ((cond & 0xf) << 12)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rd & 0x1f)
+        insn |= ((sf) << 31)
+        insn |= ((rm) << 16)
+        insn |= ((cond) << 12)
+        insn |= ((rn) << 5)
+        insn |= (rd)
         insn
       end
     end

data/lib/aarch64/instructions/csneg.rb

@@ -4,28 +4,28 @@ module AArch64
     # Conditional Select Negation
     # CSNEG  <Wd>, <Wn>, <Wm>, <cond>
     # CSNEG  <Xd>, <Xn>, <Xm>, <cond>
-    class CSNEG
+    class CSNEG < Instruction
       def initialize rd, rn, rm, cond, sf
-        @rd   = rd
-        @rn   = rn
-        @rm   = rm
-        @cond = cond
-        @sf   = sf
+        @rd   = check_mask(rd, 0x1f)
+        @rn   = check_mask(rn, 0x1f)
+        @rm   = check_mask(rm, 0x1f)
+        @cond = check_mask(cond, 0x0f)
+        @sf   = check_mask(sf, 0x01)
       end
 
       def encode
-        CSNEG(@sf, @rm.to_i, @cond, @rn.to_i, @rd.to_i)
+        CSNEG(@sf, @rm, @cond, @rn, @rd)
       end
 
       private
 
       def CSNEG sf, rm, cond, rn, rd
         insn = 0b0_1_0_11010100_00000_0000_0_1_00000_00000
-        insn |= ((sf & 0x1) << 31)
-        insn |= ((rm & 0x1f) << 16)
-        insn |= ((cond & 0xf) << 12)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rd & 0x1f)
+        insn |= ((sf) << 31)
+        insn |= ((rm) << 16)
+        insn |= ((cond) << 12)
+        insn |= ((rn) << 5)
+        insn |= (rd)
         insn
       end
     end

data/lib/aarch64/instructions/dcps.rb

@@ -3,10 +3,10 @@ module AArch64
     # DCPS1 -- A64
     # Debug Change PE State to EL1.
     # DCPS1  {#<imm>}
-    class DCPS
+    class DCPS < Instruction
       def initialize imm, ll
-        @imm = imm
-        @ll  = ll
+        @imm = check_mask(imm, 0xffff)
+        @ll  = check_mask(ll, 0x03)
       end
 
       def encode
@@ -17,8 +17,8 @@ module AArch64
 
       def DCPS imm16, ll
         insn = 0b11010100_101_0000000000000000_000_00
-        insn |= ((imm16 & 0xffff) << 5)
-        insn |= (ll & 0x3)
+        insn |= ((imm16) << 5)
+        insn |= (ll)
         insn
       end
     end

data/lib/aarch64/instructions/dgh.rb

@@ -3,7 +3,7 @@ module AArch64
     # DGH -- A64
     # Data Gathering Hint
     # DGH
-    class DGH
+    class DGH < Instruction
       def encode
         0b1101010100_0_00_011_0010_0000_110_11111
       end

data/lib/aarch64/instructions/dmb.rb

@@ -3,9 +3,9 @@ module AArch64
     # DMB -- A64
     # Data Memory Barrier
     # DMB  <option>|#<imm>
-    class DMB
+    class DMB < Instruction
       def initialize imm
-        @imm = imm
+        @imm = check_mask(imm, 0x0f)
       end
 
       def encode
@@ -16,7 +16,7 @@ module AArch64
 
       def DMB crm
         insn = 0b1101010100_0_00_011_0011_0000_1_01_11111
-        insn |= ((crm & 0xf) << 8)
+        insn |= ((crm) << 8)
         insn
       end
     end

data/lib/aarch64/instructions/drps.rb

@@ -3,16 +3,9 @@ module AArch64
     # DRPS -- A64
     # Debug restore process state
     # DRPS
-    class DRPS
+    class DRPS < Instruction
       def encode
-        DRPS()
-      end
-
-      private
-
-      def DRPS
-        insn = 0b1101011_0101_11111_000000_11111_00000
-        insn
+        0b1101011_0101_11111_000000_11111_00000
       end
     end
   end

data/lib/aarch64/instructions/dsb.rb

@@ -4,9 +4,9 @@ module AArch64
     # Data Synchronization Barrier
     # DSB  <option>|#<imm>
     # DSB  <option>nXS|#<imm>
-    class DSB
+    class DSB < Instruction
       def initialize imm
-        @imm = imm
+        @imm = check_mask(imm, 0x0f)
       end
 
       def encode
@@ -17,7 +17,7 @@ module AArch64
 
       def DSB crm
         insn = 0b1101010100_0_00_011_0011_0000_1_00_11111
-        insn |= ((crm & 0xf) << 8)
+        insn |= ((crm) << 8)
         insn
       end
     end

data/lib/aarch64/instructions/eon.rb

@@ -4,30 +4,30 @@ module AArch64
     # Bitwise Exclusive OR NOT (shifted register)
     # EON  <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
     # EON  <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
-    class EON
+    class EON < Instruction
       def initialize rd, rn, rm, shift, imm, sf
-        @rd    = rd
-        @rn    = rn
-        @rm    = rm
-        @shift = shift
-        @imm   = imm
-        @sf    = sf
+        @rd    = check_mask(rd, 0x1f)
+        @rn    = check_mask(rn, 0x1f)
+        @rm    = check_mask(rm, 0x1f)
+        @shift = check_mask(shift, 0x03)
+        @imm   = check_mask(imm, 0x3f)
+        @sf    = check_mask(sf, 0x01)
       end
 
       def encode
-        EON(@sf, @shift, @rm.to_i, @imm, @rn.to_i, @rd.to_i)
+        EON(@sf, @shift, @rm, @imm, @rn, @rd)
       end
 
       private
 
       def EON sf, shift, rm, imm6, rn, rd
         insn = 0b0_10_01010_00_1_00000_000000_00000_00000
-        insn |= ((sf & 0x1) << 31)
-        insn |= ((shift & 0x3) << 22)
-        insn |= ((rm & 0x1f) << 16)
-        insn |= ((imm6 & 0x3f) << 10)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rd & 0x1f)
+        insn |= ((sf) << 31)
+        insn |= ((shift) << 22)
+        insn |= ((rm) << 16)
+        insn |= ((imm6) << 10)
+        insn |= ((rn) << 5)
+        insn |= (rd)
         insn
       end
     end

data/lib/aarch64/instructions/eor_log_imm.rb

@@ -4,30 +4,30 @@ module AArch64
     # Bitwise Exclusive OR (immediate)
     # EOR  <Wd|WSP>, <Wn>, #<imm>
     # EOR  <Xd|SP>, <Xn>, #<imm>
-    class EOR_log_imm
+    class EOR_log_imm < Instruction
       def initialize rd, rn, n, immr, imms, sf
-        @rd   = rd
-        @rn   = rn
-        @n    = n
-        @immr = immr
-        @imms = imms
-        @sf   = sf
+        @rd   = check_mask(rd, 0x1f)
+        @rn   = check_mask(rn, 0x1f)
+        @n    = check_mask(n, 0x01)
+        @immr = check_mask(immr, 0x3f)
+        @imms = check_mask(imms, 0x3f)
+        @sf   = check_mask(sf, 0x01)
       end
 
       def encode
-        EOR_log_imm(@sf, @n, @immr, @imms, @rn.to_i, @rd.to_i)
+        EOR_log_imm(@sf, @n, @immr, @imms, @rn, @rd)
       end
 
       private
 
       def EOR_log_imm sf, n, immr, imms, rn, rd
         insn = 0b0_10_100100_0_000000_000000_00000_00000
-        insn |= ((sf & 0x1) << 31)
-        insn |= ((n & 0x1) << 22)
-        insn |= ((immr & 0x3f) << 16)
-        insn |= ((imms & 0x3f) << 10)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rd & 0x1f)
+        insn |= ((sf) << 31)
+        insn |= ((n) << 22)
+        insn |= ((immr) << 16)
+        insn |= ((imms) << 10)
+        insn |= ((rn) << 5)
+        insn |= (rd)
         insn
       end
     end

data/lib/aarch64/instructions/eor_log_shift.rb

@@ -4,30 +4,30 @@ module AArch64
     # Bitwise Exclusive OR (shifted register)
     # EOR  <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
     # EOR  <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
-    class EOR_log_shift
+    class EOR_log_shift < Instruction
       def initialize rd, rn, rm, shift, imm6, sf
-        @rd    = rd
-        @rn    = rn
-        @rm    = rm
-        @shift = shift
-        @imm6  = imm6
-        @sf    = sf
+        @rd    = check_mask(rd, 0x1f)
+        @rn    = check_mask(rn, 0x1f)
+        @rm    = check_mask(rm, 0x1f)
+        @shift = check_mask(shift, 0x03)
+        @imm6  = check_mask(imm6, 0x3f)
+        @sf    = check_mask(sf, 0x01)
       end
 
       def encode
-        EOR_log_shift(@sf, @shift, @rm.to_i, @imm6, @rn.to_i, @rd.to_i)
+        EOR_log_shift(@sf, @shift, @rm, @imm6, @rn, @rd)
       end
 
       private
 
       def EOR_log_shift sf, shift, rm, imm6, rn, rd
         insn = 0b0_10_01010_00_0_00000_000000_00000_00000
-        insn |= ((sf & 0x1) << 31)
-        insn |= ((shift & 0x3) << 22)
-        insn |= ((rm & 0x1f) << 16)
-        insn |= ((imm6 & 0x3f) << 10)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rd & 0x1f)
+        insn |= ((sf) << 31)
+        insn |= ((shift) << 22)
+        insn |= ((rm) << 16)
+        insn |= ((imm6) << 10)
+        insn |= ((rn) << 5)
+        insn |= (rd)
         insn
       end
     end

data/lib/aarch64/instructions/eret.rb

@@ -3,16 +3,9 @@ module AArch64
     # ERET -- A64
     # Exception Return
     # ERET
-    class ERET
+    class ERET < Instruction
       def encode
-        ERET()
-      end
-
-      private
-
-      def ERET
-        insn = 0b1101011_0_100_11111_0000_0_0_11111_00000
-        insn
+        0b1101011_0_100_11111_0000_0_0_11111_00000
       end
     end
   end

data/lib/aarch64/instructions/ereta.rb

@@ -4,9 +4,9 @@ module AArch64
     # Exception Return, with pointer authentication
     # ERETAA
     # ERETAB
-    class ERETA
+    class ERETA < Instruction
       def initialize m
-        @m = m
+        @m = check_mask(m, 0x01)
       end
 
       def encode
@@ -17,7 +17,7 @@ module AArch64
 
       def ERETA m
         insn = 0b1101011_0_100_11111_0000_1_0_11111_11111
-        insn |= ((m & 0x1) << 10)
+        insn |= ((m) << 10)
         insn
       end
     end

data/lib/aarch64/instructions/esb.rb

@@ -3,7 +3,7 @@ module AArch64
     # ESB -- A64
     # Error Synchronization Barrier
     # ESB
-    class ESB
+    class ESB < Instruction
       def encode
         0b1101010100_0_00_011_0010_0010_000_11111
       end

data/lib/aarch64/instructions/extr.rb

@@ -4,29 +4,29 @@ module AArch64
     # Extract register
     # EXTR  <Wd>, <Wn>, <Wm>, #<lsb>
     # EXTR  <Xd>, <Xn>, <Xm>, #<lsb>
-    class EXTR
+    class EXTR < Instruction
       def initialize rd, rn, rm, lsb, sf
-        @rd  = rd
-        @rn  = rn
-        @rm  = rm
-        @lsb = lsb
-        @sf  = sf
+        @rd  = check_mask(rd, 0x1f)
+        @rn  = check_mask(rn, 0x1f)
+        @rm  = check_mask(rm, 0x1f)
+        @lsb = check_mask(lsb, 0x3f)
+        @sf  = check_mask(sf, 0x01)
       end
 
       def encode
-        EXTR(@sf, @sf, @rm.to_i, @lsb, @rn.to_i, @rd.to_i)
+        EXTR(@sf, @sf, @rm, @lsb, @rn, @rd)
       end
 
       private
 
       def EXTR sf, n, rm, imms, rn, rd
         insn = 0b0_00_100111_0_0_00000_000000_00000_00000
-        insn |= ((sf & 0x1) << 31)
-        insn |= ((n & 0x1) << 22)
-        insn |= ((rm & 0x1f) << 16)
-        insn |= ((imms & 0x3f) << 10)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rd & 0x1f)
+        insn |= ((sf) << 31)
+        insn |= ((n) << 22)
+        insn |= ((rm) << 16)
+        insn |= ((imms) << 10)
+        insn |= ((rn) << 5)
+        insn |= (rd)
         insn
       end
     end

data/lib/aarch64/instructions/gmi.rb

@@ -3,24 +3,24 @@ module AArch64
     # GMI -- A64
     # Tag Mask Insert
     # GMI  <Xd>, <Xn|SP>, <Xm>
-    class GMI
+    class GMI < Instruction
       def initialize rd, rn, rm
-        @rd = rd
-        @rn = rn
-        @rm = rm
+        @rd = check_mask(rd, 0x1f)
+        @rn = check_mask(rn, 0x1f)
+        @rm = check_mask(rm, 0x1f)
       end
 
       def encode
-        GMI(@rm.to_i, @rn.to_i, @rd.to_i)
+        GMI(@rm, @rn, @rd)
       end
 
       private
 
       def GMI xm, xn, xd
         insn = 0b1_0_0_11010110_00000_0_0_0_1_0_1_00000_00000
-        insn |= ((xm & 0x1f) << 16)
-        insn |= ((xn & 0x1f) << 5)
-        insn |= (xd & 0x1f)
+        insn |= ((xm) << 16)
+        insn |= ((xn) << 5)
+        insn |= (xd)
         insn
       end
     end

data/lib/aarch64/instructions/hint.rb

@@ -3,10 +3,10 @@ module AArch64
     # HINT -- A64
     # Hint instruction
     # HINT  #<imm>
-    class HINT
+    class HINT < Instruction
       def initialize crm, op2
-        @crm = crm
-        @op2 = op2
+        @crm = check_mask(crm, 0x0f)
+        @op2 = check_mask(op2, 0x07)
       end
 
       def encode
@@ -17,8 +17,8 @@ module AArch64
 
       def HINT crm, op2
         insn = 0b1101010100_0_00_011_0010_0000_000_11111
-        insn |= ((crm & 0xf) << 8)
-        insn |= ((op2 & 0x7) << 5)
+        insn |= ((crm) << 8)
+        insn |= ((op2) << 5)
         insn
       end
     end

data/lib/aarch64/instructions/hlt.rb

@@ -3,9 +3,9 @@ module AArch64
     # HLT -- A64
     # Halt instruction
     # HLT  #<imm>
-    class HLT
+    class HLT < Instruction
       def initialize imm
-        @imm = imm
+        @imm = check_mask(imm, 0xffff)
       end
 
       def encode
@@ -16,7 +16,7 @@ module AArch64
 
       def HLT imm16
         insn = 0b11010100_010_0000000000000000_000_00
-        insn |= ((imm16 & 0xffff) << 5)
+        insn |= ((imm16) << 5)
         insn
       end
     end

data/lib/aarch64/instructions/hvc.rb

@@ -3,9 +3,9 @@ module AArch64
     # HVC -- A64
     # Hypervisor Call
     # HVC  #<imm>
-    class HVC
+    class HVC < Instruction
       def initialize imm
-        @imm = imm
+        @imm = check_mask(imm, 0xffff)
       end
 
       def encode
@@ -16,7 +16,7 @@ module AArch64
 
       def HVC imm16
         insn = 0b11010100_000_0000000000000000_000_10
-        insn |= ((imm16 & 0xffff) << 5)
+        insn |= ((imm16) << 5)
         insn
       end
     end

data/lib/aarch64/instructions/irg.rb

@@ -3,24 +3,24 @@ module AArch64
     # IRG -- A64
     # Insert Random Tag
     # IRG  <Xd|SP>, <Xn|SP>{, <Xm>}
-    class IRG
+    class IRG < Instruction
       def initialize rd, rn, rm
-        @rd = rd
-        @rn = rn
-        @rm = rm
+        @rd = check_mask(rd, 0x1f)
+        @rn = check_mask(rn, 0x1f)
+        @rm = check_mask(rm, 0x1f)
       end
 
       def encode
-        IRG(@rm.to_i, @rn.to_i, @rd.to_i)
+        IRG(@rm, @rn, @rd)
       end
 
       private
 
       def IRG xm, xn, xd
         insn = 0b1_0_0_11010110_00000_0_0_0_1_0_0_00000_00000
-        insn |= ((xm & 0x1f) << 16)
-        insn |= ((xn & 0x1f) << 5)
-        insn |= (xd & 0x1f)
+        insn |= ((xm) << 16)
+        insn |= ((xn) << 5)
+        insn |= (xd)
         insn
       end
     end

data/lib/aarch64/instructions/isb.rb

@@ -3,9 +3,9 @@ module AArch64
     # ISB -- A64
     # Instruction Synchronization Barrier
     # ISB  {<option>|#<imm>}
-    class ISB
+    class ISB < Instruction
       def initialize imm
-        @imm = imm
+        @imm = check_mask(imm, 0x0f)
       end
 
       def encode
@@ -16,7 +16,7 @@ module AArch64
 
       def ISB crm
         insn = 0b1101010100_0_00_011_0011_0000_1_10_11111
-        insn |= ((crm & 0xf) << 8)
+        insn |= ((crm) << 8)
         insn
       end
     end

data/lib/aarch64/instructions/ld64b.rb

@@ -3,22 +3,22 @@ module AArch64
     # LD64B -- A64
     # Single-copy Atomic 64-byte Load
     # LD64B  <Xt>, [<Xn|SP> {,#0}]
-    class LD64B
+    class LD64B < Instruction
       def initialize rt, rn
-        @rt = rt
-        @rn = rn
+        @rt = check_mask(rt, 0x1f)
+        @rn = check_mask(rn, 0x1f)
       end
 
       def encode
-        LD64B(@rn.to_i, @rt.to_i)
+        LD64B(@rn, @rt)
       end
 
       private
 
       def LD64B rn, rt
         insn = 0b11_111_0_00_0_0_1_11111_1_101_00_00000_00000
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end