aarch64 1.0.1 → 2.0.0

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (277) hide show
  1. checksums.yaml +4 -4
  2. data/README.md +1 -1
  3. data/Rakefile +37 -0
  4. data/aarch64.gemspec +1 -0
  5. data/lib/aarch64/instructions/adc.rb +10 -10
  6. data/lib/aarch64/instructions/adcs.rb +10 -10
  7. data/lib/aarch64/instructions/add_addsub_ext.rb +14 -14
  8. data/lib/aarch64/instructions/add_addsub_imm.rb +12 -12
  9. data/lib/aarch64/instructions/add_addsub_shift.rb +14 -14
  10. data/lib/aarch64/instructions/addg.rb +10 -10
  11. data/lib/aarch64/instructions/adds_addsub_ext.rb +14 -14
  12. data/lib/aarch64/instructions/adds_addsub_imm.rb +12 -12
  13. data/lib/aarch64/instructions/adds_addsub_shift.rb +14 -14
  14. data/lib/aarch64/instructions/adr.rb +7 -7
  15. data/lib/aarch64/instructions/adrp.rb +7 -7
  16. data/lib/aarch64/instructions/and_log_imm.rb +14 -14
  17. data/lib/aarch64/instructions/and_log_shift.rb +14 -14
  18. data/lib/aarch64/instructions/ands_log_imm.rb +14 -14
  19. data/lib/aarch64/instructions/ands_log_shift.rb +14 -14
  20. data/lib/aarch64/instructions/asrv.rb +10 -10
  21. data/lib/aarch64/instructions/autda.rb +9 -12
  22. data/lib/aarch64/instructions/autdb.rb +9 -12
  23. data/lib/aarch64/instructions/autia.rb +9 -12
  24. data/lib/aarch64/instructions/autib.rb +9 -12
  25. data/lib/aarch64/instructions/axflag.rb +1 -1
  26. data/lib/aarch64/instructions/b_cond.rb +5 -5
  27. data/lib/aarch64/instructions/b_uncond.rb +3 -3
  28. data/lib/aarch64/instructions/bc_cond.rb +5 -5
  29. data/lib/aarch64/instructions/bfm.rb +13 -13
  30. data/lib/aarch64/instructions/bic_log_shift.rb +14 -14
  31. data/lib/aarch64/instructions/bics.rb +14 -14
  32. data/lib/aarch64/instructions/bl.rb +3 -3
  33. data/lib/aarch64/instructions/blr.rb +4 -4
  34. data/lib/aarch64/instructions/blra.rb +10 -10
  35. data/lib/aarch64/instructions/br.rb +4 -4
  36. data/lib/aarch64/instructions/bra.rb +10 -10
  37. data/lib/aarch64/instructions/brk.rb +3 -3
  38. data/lib/aarch64/instructions/bti.rb +3 -3
  39. data/lib/aarch64/instructions/cas.rb +14 -14
  40. data/lib/aarch64/instructions/casb.rb +12 -12
  41. data/lib/aarch64/instructions/cash.rb +12 -12
  42. data/lib/aarch64/instructions/casp.rb +14 -14
  43. data/lib/aarch64/instructions/cbnz.rb +7 -7
  44. data/lib/aarch64/instructions/cbz.rb +7 -7
  45. data/lib/aarch64/instructions/ccmn_imm.rb +12 -12
  46. data/lib/aarch64/instructions/ccmn_reg.rb +12 -12
  47. data/lib/aarch64/instructions/ccmp_imm.rb +12 -12
  48. data/lib/aarch64/instructions/ccmp_reg.rb +12 -12
  49. data/lib/aarch64/instructions/cfinv.rb +2 -9
  50. data/lib/aarch64/instructions/clrex.rb +3 -3
  51. data/lib/aarch64/instructions/cls_int.rb +8 -8
  52. data/lib/aarch64/instructions/clz_int.rb +8 -8
  53. data/lib/aarch64/instructions/crc32.rb +12 -12
  54. data/lib/aarch64/instructions/crc32c.rb +12 -12
  55. data/lib/aarch64/instructions/csdb.rb +1 -1
  56. data/lib/aarch64/instructions/csel.rb +12 -12
  57. data/lib/aarch64/instructions/csinc.rb +12 -12
  58. data/lib/aarch64/instructions/csinv.rb +12 -12
  59. data/lib/aarch64/instructions/csneg.rb +12 -12
  60. data/lib/aarch64/instructions/dcps.rb +5 -5
  61. data/lib/aarch64/instructions/dgh.rb +1 -1
  62. data/lib/aarch64/instructions/dmb.rb +3 -3
  63. data/lib/aarch64/instructions/drps.rb +2 -9
  64. data/lib/aarch64/instructions/dsb.rb +3 -3
  65. data/lib/aarch64/instructions/eon.rb +14 -14
  66. data/lib/aarch64/instructions/eor_log_imm.rb +14 -14
  67. data/lib/aarch64/instructions/eor_log_shift.rb +14 -14
  68. data/lib/aarch64/instructions/eret.rb +2 -9
  69. data/lib/aarch64/instructions/ereta.rb +3 -3
  70. data/lib/aarch64/instructions/esb.rb +1 -1
  71. data/lib/aarch64/instructions/extr.rb +13 -13
  72. data/lib/aarch64/instructions/gmi.rb +8 -8
  73. data/lib/aarch64/instructions/hint.rb +5 -5
  74. data/lib/aarch64/instructions/hlt.rb +3 -3
  75. data/lib/aarch64/instructions/hvc.rb +3 -3
  76. data/lib/aarch64/instructions/irg.rb +8 -8
  77. data/lib/aarch64/instructions/isb.rb +3 -3
  78. data/lib/aarch64/instructions/ld64b.rb +6 -6
  79. data/lib/aarch64/instructions/ldadd.rb +14 -14
  80. data/lib/aarch64/instructions/ldaddb.rb +12 -12
  81. data/lib/aarch64/instructions/ldaddh.rb +12 -12
  82. data/lib/aarch64/instructions/ldapr.rb +8 -8
  83. data/lib/aarch64/instructions/ldaprb.rb +6 -6
  84. data/lib/aarch64/instructions/ldaprh.rb +6 -6
  85. data/lib/aarch64/instructions/ldapur_gen.rb +12 -12
  86. data/lib/aarch64/instructions/ldar.rb +8 -8
  87. data/lib/aarch64/instructions/ldaxp.rb +10 -10
  88. data/lib/aarch64/instructions/ldaxr.rb +8 -8
  89. data/lib/aarch64/instructions/ldclr.rb +14 -14
  90. data/lib/aarch64/instructions/ldclrb.rb +14 -14
  91. data/lib/aarch64/instructions/ldeor.rb +14 -14
  92. data/lib/aarch64/instructions/ldg.rb +8 -8
  93. data/lib/aarch64/instructions/ldgm.rb +6 -6
  94. data/lib/aarch64/instructions/ldlar.rb +8 -8
  95. data/lib/aarch64/instructions/ldnp_gen.rb +12 -12
  96. data/lib/aarch64/instructions/ldp_gen.rb +14 -14
  97. data/lib/aarch64/instructions/ldpsw.rb +12 -12
  98. data/lib/aarch64/instructions/ldr_imm_gen.rb +12 -12
  99. data/lib/aarch64/instructions/ldr_imm_unsigned.rb +10 -10
  100. data/lib/aarch64/instructions/ldr_lit_gen.rb +7 -7
  101. data/lib/aarch64/instructions/ldr_reg_gen.rb +14 -14
  102. data/lib/aarch64/instructions/ldra.rb +14 -14
  103. data/lib/aarch64/instructions/ldrb_imm.rb +10 -10
  104. data/lib/aarch64/instructions/ldrb_reg.rb +12 -12
  105. data/lib/aarch64/instructions/ldrb_unsigned.rb +8 -8
  106. data/lib/aarch64/instructions/ldrh_imm.rb +10 -10
  107. data/lib/aarch64/instructions/ldrh_reg.rb +12 -12
  108. data/lib/aarch64/instructions/ldrh_unsigned.rb +8 -8
  109. data/lib/aarch64/instructions/ldrsb_imm.rb +12 -12
  110. data/lib/aarch64/instructions/ldrsb_reg.rb +14 -14
  111. data/lib/aarch64/instructions/ldrsb_unsigned.rb +10 -10
  112. data/lib/aarch64/instructions/ldrsh_imm.rb +12 -12
  113. data/lib/aarch64/instructions/ldrsh_reg.rb +14 -14
  114. data/lib/aarch64/instructions/ldrsh_unsigned.rb +10 -10
  115. data/lib/aarch64/instructions/ldrsw_imm.rb +10 -10
  116. data/lib/aarch64/instructions/ldrsw_lit.rb +5 -5
  117. data/lib/aarch64/instructions/ldrsw_reg.rb +12 -12
  118. data/lib/aarch64/instructions/ldrsw_unsigned.rb +8 -8
  119. data/lib/aarch64/instructions/ldset.rb +14 -14
  120. data/lib/aarch64/instructions/ldsetb.rb +12 -12
  121. data/lib/aarch64/instructions/ldseth.rb +12 -12
  122. data/lib/aarch64/instructions/ldsmax.rb +14 -14
  123. data/lib/aarch64/instructions/ldsmaxb.rb +12 -12
  124. data/lib/aarch64/instructions/ldsmaxh.rb +12 -12
  125. data/lib/aarch64/instructions/ldsmin.rb +14 -14
  126. data/lib/aarch64/instructions/ldsminb.rb +12 -12
  127. data/lib/aarch64/instructions/ldsminh.rb +12 -12
  128. data/lib/aarch64/instructions/ldtr.rb +10 -10
  129. data/lib/aarch64/instructions/ldtrb.rb +8 -8
  130. data/lib/aarch64/instructions/ldtrh.rb +8 -8
  131. data/lib/aarch64/instructions/ldtrsb.rb +10 -10
  132. data/lib/aarch64/instructions/ldtrsh.rb +10 -10
  133. data/lib/aarch64/instructions/ldtrsw.rb +8 -8
  134. data/lib/aarch64/instructions/ldumax.rb +14 -14
  135. data/lib/aarch64/instructions/ldumaxb.rb +12 -12
  136. data/lib/aarch64/instructions/ldumaxh.rb +12 -12
  137. data/lib/aarch64/instructions/ldumin.rb +14 -14
  138. data/lib/aarch64/instructions/lduminb.rb +12 -12
  139. data/lib/aarch64/instructions/lduminh.rb +12 -12
  140. data/lib/aarch64/instructions/ldur_gen.rb +10 -10
  141. data/lib/aarch64/instructions/ldursb.rb +10 -10
  142. data/lib/aarch64/instructions/ldursh.rb +10 -10
  143. data/lib/aarch64/instructions/ldursw.rb +8 -8
  144. data/lib/aarch64/instructions/ldxp.rb +10 -10
  145. data/lib/aarch64/instructions/ldxr.rb +8 -8
  146. data/lib/aarch64/instructions/lslv.rb +10 -10
  147. data/lib/aarch64/instructions/lsrv.rb +10 -10
  148. data/lib/aarch64/instructions/madd.rb +12 -12
  149. data/lib/aarch64/instructions/movk.rb +10 -10
  150. data/lib/aarch64/instructions/movn.rb +10 -10
  151. data/lib/aarch64/instructions/movz.rb +10 -10
  152. data/lib/aarch64/instructions/mrs.rb +14 -14
  153. data/lib/aarch64/instructions/msr_imm.rb +7 -7
  154. data/lib/aarch64/instructions/msr_reg.rb +14 -14
  155. data/lib/aarch64/instructions/msub.rb +12 -12
  156. data/lib/aarch64/instructions/nop.rb +1 -1
  157. data/lib/aarch64/instructions/orn_log_shift.rb +14 -14
  158. data/lib/aarch64/instructions/orr_log_imm.rb +14 -14
  159. data/lib/aarch64/instructions/orr_log_shift.rb +14 -14
  160. data/lib/aarch64/instructions/pacda.rb +8 -8
  161. data/lib/aarch64/instructions/pacdb.rb +8 -8
  162. data/lib/aarch64/instructions/pacga.rb +8 -8
  163. data/lib/aarch64/instructions/pacia.rb +8 -8
  164. data/lib/aarch64/instructions/pacia2.rb +5 -5
  165. data/lib/aarch64/instructions/pacib.rb +8 -8
  166. data/lib/aarch64/instructions/prfm_imm.rb +8 -8
  167. data/lib/aarch64/instructions/prfm_lit.rb +8 -8
  168. data/lib/aarch64/instructions/prfm_reg.rb +12 -12
  169. data/lib/aarch64/instructions/prfum.rb +8 -8
  170. data/lib/aarch64/instructions/psb.rb +2 -9
  171. data/lib/aarch64/instructions/rbit_int.rb +8 -8
  172. data/lib/aarch64/instructions/ret.rb +4 -4
  173. data/lib/aarch64/instructions/reta.rb +3 -3
  174. data/lib/aarch64/instructions/rev.rb +10 -10
  175. data/lib/aarch64/instructions/rmif.rb +8 -8
  176. data/lib/aarch64/instructions/rorv.rb +10 -10
  177. data/lib/aarch64/instructions/sb.rb +1 -1
  178. data/lib/aarch64/instructions/sbc.rb +10 -10
  179. data/lib/aarch64/instructions/sbcs.rb +10 -10
  180. data/lib/aarch64/instructions/sbfm.rb +13 -13
  181. data/lib/aarch64/instructions/sdiv.rb +10 -10
  182. data/lib/aarch64/instructions/setf.rb +6 -6
  183. data/lib/aarch64/instructions/sev.rb +1 -7
  184. data/lib/aarch64/instructions/sevl.rb +1 -1
  185. data/lib/aarch64/instructions/smaddl.rb +10 -10
  186. data/lib/aarch64/instructions/smc.rb +3 -3
  187. data/lib/aarch64/instructions/smsubl.rb +10 -10
  188. data/lib/aarch64/instructions/smulh.rb +8 -8
  189. data/lib/aarch64/instructions/st2g.rb +10 -10
  190. data/lib/aarch64/instructions/st64b.rb +6 -6
  191. data/lib/aarch64/instructions/st64bv.rb +8 -8
  192. data/lib/aarch64/instructions/st64bv0.rb +8 -8
  193. data/lib/aarch64/instructions/stg.rb +10 -10
  194. data/lib/aarch64/instructions/stgm.rb +6 -6
  195. data/lib/aarch64/instructions/stgp.rb +12 -12
  196. data/lib/aarch64/instructions/stllr.rb +8 -8
  197. data/lib/aarch64/instructions/stllrb.rb +6 -6
  198. data/lib/aarch64/instructions/stllrh.rb +6 -6
  199. data/lib/aarch64/instructions/stlr.rb +8 -8
  200. data/lib/aarch64/instructions/stlrb.rb +6 -6
  201. data/lib/aarch64/instructions/stlrh.rb +6 -6
  202. data/lib/aarch64/instructions/stlur_gen.rb +10 -10
  203. data/lib/aarch64/instructions/stlxp.rb +12 -12
  204. data/lib/aarch64/instructions/stlxr.rb +10 -10
  205. data/lib/aarch64/instructions/stlxrb.rb +8 -8
  206. data/lib/aarch64/instructions/stlxrh.rb +8 -8
  207. data/lib/aarch64/instructions/stnp_gen.rb +12 -12
  208. data/lib/aarch64/instructions/stp_gen.rb +14 -14
  209. data/lib/aarch64/instructions/str_imm_gen.rb +12 -12
  210. data/lib/aarch64/instructions/str_imm_unsigned.rb +10 -10
  211. data/lib/aarch64/instructions/str_reg_gen.rb +14 -14
  212. data/lib/aarch64/instructions/strb_imm.rb +10 -10
  213. data/lib/aarch64/instructions/strb_imm_unsigned.rb +8 -8
  214. data/lib/aarch64/instructions/strb_reg.rb +12 -12
  215. data/lib/aarch64/instructions/strh_imm.rb +10 -10
  216. data/lib/aarch64/instructions/strh_imm_unsigned.rb +8 -8
  217. data/lib/aarch64/instructions/strh_reg.rb +12 -12
  218. data/lib/aarch64/instructions/sttr.rb +10 -10
  219. data/lib/aarch64/instructions/stur_gen.rb +10 -10
  220. data/lib/aarch64/instructions/stxp.rb +12 -12
  221. data/lib/aarch64/instructions/stxr.rb +10 -10
  222. data/lib/aarch64/instructions/stxrb.rb +8 -8
  223. data/lib/aarch64/instructions/stxrh.rb +8 -8
  224. data/lib/aarch64/instructions/stz2g.rb +10 -10
  225. data/lib/aarch64/instructions/stzg.rb +10 -10
  226. data/lib/aarch64/instructions/stzgm.rb +6 -6
  227. data/lib/aarch64/instructions/sub_addsub_ext.rb +14 -14
  228. data/lib/aarch64/instructions/sub_addsub_imm.rb +12 -12
  229. data/lib/aarch64/instructions/sub_addsub_shift.rb +14 -14
  230. data/lib/aarch64/instructions/subg.rb +10 -10
  231. data/lib/aarch64/instructions/subp.rb +8 -8
  232. data/lib/aarch64/instructions/subps.rb +8 -8
  233. data/lib/aarch64/instructions/subs_addsub_ext.rb +14 -14
  234. data/lib/aarch64/instructions/subs_addsub_imm.rb +12 -12
  235. data/lib/aarch64/instructions/subs_addsub_shift.rb +14 -14
  236. data/lib/aarch64/instructions/svc.rb +3 -3
  237. data/lib/aarch64/instructions/swp.rb +14 -14
  238. data/lib/aarch64/instructions/swpb.rb +12 -12
  239. data/lib/aarch64/instructions/swph.rb +12 -12
  240. data/lib/aarch64/instructions/sys.rb +12 -12
  241. data/lib/aarch64/instructions/sysl.rb +12 -12
  242. data/lib/aarch64/instructions/tbnz.rb +9 -9
  243. data/lib/aarch64/instructions/tbz.rb +9 -9
  244. data/lib/aarch64/instructions/tsb.rb +1 -7
  245. data/lib/aarch64/instructions/ubfm.rb +13 -13
  246. data/lib/aarch64/instructions/udf_perm_undef.rb +3 -3
  247. data/lib/aarch64/instructions/udiv.rb +10 -10
  248. data/lib/aarch64/instructions/umaddl.rb +10 -10
  249. data/lib/aarch64/instructions/umsubl.rb +10 -10
  250. data/lib/aarch64/instructions/umulh.rb +8 -8
  251. data/lib/aarch64/instructions/wfe.rb +2 -9
  252. data/lib/aarch64/instructions/wfet.rb +4 -4
  253. data/lib/aarch64/instructions/wfi.rb +1 -1
  254. data/lib/aarch64/instructions/wfit.rb +4 -4
  255. data/lib/aarch64/instructions/xaflag.rb +1 -1
  256. data/lib/aarch64/instructions/xpac.rb +6 -6
  257. data/lib/aarch64/instructions/xpaclri.rb +1 -1
  258. data/lib/aarch64/instructions/yield.rb +2 -9
  259. data/lib/aarch64/instructions.rb +26 -8
  260. data/lib/aarch64/parser.rb +227 -0
  261. data/lib/aarch64/parser.tab.rb +6534 -0
  262. data/lib/aarch64/parser.y +1394 -0
  263. data/lib/aarch64/utils.rb +34 -0
  264. data/lib/aarch64/version.rb +1 -1
  265. data/lib/aarch64.rb +128 -58
  266. data/test/base_instructions_test.rb +34 -4
  267. data/test/helper.rb +48 -8
  268. data/test/parser_test.rb +1820 -0
  269. metadata +25 -14
  270. data/lib/aarch64/instructions/setgp.rb +0 -25
  271. data/lib/aarch64/instructions/setgpn.rb +0 -25
  272. data/lib/aarch64/instructions/setgpt.rb +0 -25
  273. data/lib/aarch64/instructions/setgptn.rb +0 -25
  274. data/lib/aarch64/instructions/setp.rb +0 -25
  275. data/lib/aarch64/instructions/setpn.rb +0 -25
  276. data/lib/aarch64/instructions/setpt.rb +0 -25
  277. data/lib/aarch64/instructions/setptn.rb +0 -25
@@ -4,26 +4,26 @@ module AArch64
4
4
  # Store Exclusive Register
5
5
  # STXR <Ws>, <Wt>, [<Xn|SP>{,#0}]
6
6
  # STXR <Ws>, <Xt>, [<Xn|SP>{,#0}]
7
- class STXR
7
+ class STXR < Instruction
8
8
  def initialize rs, rt, rn, size
9
- @rs = rs
10
- @rt = rt
11
- @rn = rn
12
- @size = size
9
+ @rs = check_mask(rs, 0x1f)
10
+ @rt = check_mask(rt, 0x1f)
11
+ @rn = check_mask(rn, 0x1f)
12
+ @size = check_mask(size, 0x03)
13
13
  end
14
14
 
15
15
  def encode
16
- STXR(@size, @rs.to_i, @rn.to_i, @rt.to_i)
16
+ STXR(@size, @rs, @rn, @rt)
17
17
  end
18
18
 
19
19
  private
20
20
 
21
21
  def STXR size, rs, rn, rt
22
22
  insn = 0b00_001000_0_0_0_00000_0_11111_00000_00000
23
- insn |= ((size & 0x3) << 30)
24
- insn |= ((rs & 0x1f) << 16)
25
- insn |= ((rn & 0x1f) << 5)
26
- insn |= (rt & 0x1f)
23
+ insn |= ((size) << 30)
24
+ insn |= ((rs) << 16)
25
+ insn |= ((rn) << 5)
26
+ insn |= (rt)
27
27
  insn
28
28
  end
29
29
  end
@@ -3,24 +3,24 @@ module AArch64
3
3
  # STXRB -- A64
4
4
  # Store Exclusive Register Byte
5
5
  # STXRB <Ws>, <Wt>, [<Xn|SP>{,#0}]
6
- class STXRB
6
+ class STXRB < Instruction
7
7
  def initialize rs, rt, rn
8
- @rs = rs
9
- @rt = rt
10
- @rn = rn
8
+ @rs = check_mask(rs, 0x1f)
9
+ @rt = check_mask(rt, 0x1f)
10
+ @rn = check_mask(rn, 0x1f)
11
11
  end
12
12
 
13
13
  def encode
14
- STXRB(@rs.to_i, @rn.to_i, @rt.to_i)
14
+ STXRB(@rs, @rn, @rt)
15
15
  end
16
16
 
17
17
  private
18
18
 
19
19
  def STXRB rs, rn, rt
20
20
  insn = 0b00_001000_0_0_0_00000_0_11111_00000_00000
21
- insn |= ((rs & 0x1f) << 16)
22
- insn |= ((rn & 0x1f) << 5)
23
- insn |= (rt & 0x1f)
21
+ insn |= ((rs) << 16)
22
+ insn |= ((rn) << 5)
23
+ insn |= (rt)
24
24
  insn
25
25
  end
26
26
  end
@@ -3,24 +3,24 @@ module AArch64
3
3
  # STXRH -- A64
4
4
  # Store Exclusive Register Halfword
5
5
  # STXRH <Ws>, <Wt>, [<Xn|SP>{,#0}]
6
- class STXRH
6
+ class STXRH < Instruction
7
7
  def initialize rs, rt, rn
8
- @rs = rs
9
- @rt = rt
10
- @rn = rn
8
+ @rs = check_mask(rs, 0x1f)
9
+ @rt = check_mask(rt, 0x1f)
10
+ @rn = check_mask(rn, 0x1f)
11
11
  end
12
12
 
13
13
  def encode
14
- STXRH(@rs.to_i, @rn.to_i, @rt.to_i)
14
+ STXRH(@rs, @rn, @rt)
15
15
  end
16
16
 
17
17
  private
18
18
 
19
19
  def STXRH rs, rn, rt
20
20
  insn = 0b01_001000_0_0_0_00000_0_11111_00000_00000
21
- insn |= ((rs & 0x1f) << 16)
22
- insn |= ((rn & 0x1f) << 5)
23
- insn |= (rt & 0x1f)
21
+ insn |= ((rs) << 16)
22
+ insn |= ((rn) << 5)
23
+ insn |= (rt)
24
24
  insn
25
25
  end
26
26
  end
@@ -5,26 +5,26 @@ module AArch64
5
5
  # STZ2G <Xt|SP>, [<Xn|SP>], #<simm>
6
6
  # STZ2G <Xt|SP>, [<Xn|SP>, #<simm>]!
7
7
  # STZ2G <Xt|SP>, [<Xn|SP>{, #<simm>}]
8
- class STZ2G
8
+ class STZ2G < Instruction
9
9
  def initialize xt, xn, imm9, opt
10
- @xt = xt
11
- @xn = xn
12
- @imm9 = imm9
13
- @opt = opt
10
+ @xt = check_mask(xt, 0x1f)
11
+ @xn = check_mask(xn, 0x1f)
12
+ @imm9 = check_mask(imm9, 0x1ff)
13
+ @opt = check_mask(opt, 0x03)
14
14
  end
15
15
 
16
16
  def encode
17
- STZ2G(@imm9, @opt, @xn.to_i, @xt.to_i)
17
+ STZ2G(@imm9, @opt, @xn, @xt)
18
18
  end
19
19
 
20
20
  private
21
21
 
22
22
  def STZ2G imm9, opt, xn, xt
23
23
  insn = 0b11011001_1_1_1_000000000_00_00000_00000
24
- insn |= ((imm9 & 0x1ff) << 12)
25
- insn |= ((opt & 0x3) << 10)
26
- insn |= ((xn & 0x1f) << 5)
27
- insn |= (xt & 0x1f)
24
+ insn |= ((imm9) << 12)
25
+ insn |= ((opt) << 10)
26
+ insn |= ((xn) << 5)
27
+ insn |= (xt)
28
28
  insn
29
29
  end
30
30
  end
@@ -5,26 +5,26 @@ module AArch64
5
5
  # STZG <Xt|SP>, [<Xn|SP>], #<simm>
6
6
  # STZG <Xt|SP>, [<Xn|SP>, #<simm>]!
7
7
  # STZG <Xt|SP>, [<Xn|SP>{, #<simm>}]
8
- class STZG
8
+ class STZG < Instruction
9
9
  def initialize xt, xn, imm9, opt
10
- @xt = xt
11
- @xn = xn
12
- @imm9 = imm9
13
- @opt = opt
10
+ @xt = check_mask(xt, 0x1f)
11
+ @xn = check_mask(xn, 0x1f)
12
+ @imm9 = check_mask(imm9, 0x1ff)
13
+ @opt = check_mask(opt, 0x03)
14
14
  end
15
15
 
16
16
  def encode
17
- STZG(@imm9, @opt, @xn.to_i, @xt.to_i)
17
+ STZG(@imm9, @opt, @xn, @xt)
18
18
  end
19
19
 
20
20
  private
21
21
 
22
22
  def STZG imm9, opt, xn, xt
23
23
  insn = 0b11011001_0_1_1_000000000_00_00000_00000
24
- insn |= ((imm9 & 0x1ff) << 12)
25
- insn |= ((opt & 0x3) << 10)
26
- insn |= ((xn & 0x1f) << 5)
27
- insn |= (xt & 0x1f)
24
+ insn |= ((imm9) << 12)
25
+ insn |= ((opt) << 10)
26
+ insn |= ((xn) << 5)
27
+ insn |= (xt)
28
28
  insn
29
29
  end
30
30
  end
@@ -3,22 +3,22 @@ module AArch64
3
3
  # STZGM -- A64
4
4
  # Store Tag and Zero Multiple
5
5
  # STZGM <Xt>, [<Xn|SP>]
6
- class STZGM
6
+ class STZGM < Instruction
7
7
  def initialize rt, rn
8
- @rt = rt
9
- @rn = rn
8
+ @rt = check_mask(rt, 0x1f)
9
+ @rn = check_mask(rn, 0x1f)
10
10
  end
11
11
 
12
12
  def encode
13
- STZGM(@rn.to_i, @rt.to_i)
13
+ STZGM(@rn, @rt)
14
14
  end
15
15
 
16
16
  private
17
17
 
18
18
  def STZGM xn, xt
19
19
  insn = 0b11011001_0_0_1_0_0_0_0_0_0_0_0_0_0_0_00000_00000
20
- insn |= ((xn & 0x1f) << 5)
21
- insn |= (xt & 0x1f)
20
+ insn |= ((xn) << 5)
21
+ insn |= (xt)
22
22
  insn
23
23
  end
24
24
  end
@@ -4,30 +4,30 @@ module AArch64
4
4
  # Subtract (extended register)
5
5
  # SUB <Wd|WSP>, <Wn|WSP>, <Wm>{, <extend> {#<amount>}}
6
6
  # SUB <Xd|SP>, <Xn|SP>, <R><m>{, <extend> {#<amount>}}
7
- class SUB_addsub_ext
7
+ class SUB_addsub_ext < Instruction
8
8
  def initialize rd, rn, rm, extend, amount, sf
9
- @rd = rd
10
- @rn = rn
11
- @rm = rm
12
- @extend = extend
13
- @amount = amount
14
- @sf = sf
9
+ @rd = check_mask(rd, 0x1f)
10
+ @rn = check_mask(rn, 0x1f)
11
+ @rm = check_mask(rm, 0x1f)
12
+ @extend = check_mask(extend, 0x07)
13
+ @amount = check_mask(amount, 0x07)
14
+ @sf = check_mask(sf, 0x01)
15
15
  end
16
16
 
17
17
  def encode
18
- SUB_addsub_ext(@sf, @rm.to_i, @extend, @amount, @rn.to_i, @rd.to_i)
18
+ SUB_addsub_ext(@sf, @rm, @extend, @amount, @rn, @rd)
19
19
  end
20
20
 
21
21
  private
22
22
 
23
23
  def SUB_addsub_ext sf, rm, option, imm3, rn, rd
24
24
  insn = 0b0_1_0_01011_00_1_00000_000_000_00000_00000
25
- insn |= ((sf & 0x1) << 31)
26
- insn |= ((rm & 0x1f) << 16)
27
- insn |= ((option & 0x7) << 13)
28
- insn |= ((imm3 & 0x7) << 10)
29
- insn |= ((rn & 0x1f) << 5)
30
- insn |= (rd & 0x1f)
25
+ insn |= ((sf) << 31)
26
+ insn |= ((rm) << 16)
27
+ insn |= ((option) << 13)
28
+ insn |= ((imm3) << 10)
29
+ insn |= ((rn) << 5)
30
+ insn |= (rd)
31
31
  insn
32
32
  end
33
33
  end
@@ -4,28 +4,28 @@ module AArch64
4
4
  # Subtract (immediate)
5
5
  # SUB <Wd|WSP>, <Wn|WSP>, #<imm>{, <shift>}
6
6
  # SUB <Xd|SP>, <Xn|SP>, #<imm>{, <shift>}
7
- class SUB_addsub_imm
7
+ class SUB_addsub_imm < Instruction
8
8
  def initialize rd, rn, imm, shift, sf
9
- @rd = rd
10
- @rn = rn
11
- @imm = imm
12
- @shift = shift
13
- @sf = sf
9
+ @rd = check_mask(rd, 0x1f)
10
+ @rn = check_mask(rn, 0x1f)
11
+ @imm = check_mask(imm, 0xfff)
12
+ @shift = check_mask(shift, 0x01)
13
+ @sf = check_mask(sf, 0x01)
14
14
  end
15
15
 
16
16
  def encode
17
- SUB_addsub_imm(@sf, @shift, @imm, @rn.to_i, @rd.to_i)
17
+ SUB_addsub_imm(@sf, @shift, @imm, @rn, @rd)
18
18
  end
19
19
 
20
20
  private
21
21
 
22
22
  def SUB_addsub_imm sf, sh, imm12, rn, rd
23
23
  insn = 0b0_1_0_100010_0_000000000000_00000_00000
24
- insn |= ((sf & 0x1) << 31)
25
- insn |= ((sh & 0x1) << 22)
26
- insn |= ((imm12 & 0xfff) << 10)
27
- insn |= ((rn & 0x1f) << 5)
28
- insn |= (rd & 0x1f)
24
+ insn |= ((sf) << 31)
25
+ insn |= ((sh) << 22)
26
+ insn |= ((imm12) << 10)
27
+ insn |= ((rn) << 5)
28
+ insn |= (rd)
29
29
  insn
30
30
  end
31
31
  end
@@ -4,30 +4,30 @@ module AArch64
4
4
  # Subtract (shifted register)
5
5
  # SUB <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
6
6
  # SUB <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
7
- class SUB_addsub_shift
7
+ class SUB_addsub_shift < Instruction
8
8
  def initialize rd, rn, rm, shift, amount, sf
9
- @rd = rd
10
- @rn = rn
11
- @rm = rm
12
- @shift = shift
13
- @amount = amount
14
- @sf = sf
9
+ @rd = check_mask(rd, 0x1f)
10
+ @rn = check_mask(rn, 0x1f)
11
+ @rm = check_mask(rm, 0x1f)
12
+ @shift = check_mask(shift, 0x03)
13
+ @amount = check_mask(amount, 0x3f)
14
+ @sf = check_mask(sf, 0x01)
15
15
  end
16
16
 
17
17
  def encode
18
- SUB_addsub_shift(@sf, @shift, @rm.to_i, @amount, @rn.to_i, @rd.to_i)
18
+ SUB_addsub_shift(@sf, @shift, @rm, @amount, @rn, @rd)
19
19
  end
20
20
 
21
21
  private
22
22
 
23
23
  def SUB_addsub_shift sf, shift, rm, imm6, rn, rd
24
24
  insn = 0b0_1_0_01011_00_0_00000_000000_00000_00000
25
- insn |= ((sf & 0x1) << 31)
26
- insn |= ((shift & 0x3) << 22)
27
- insn |= ((rm & 0x1f) << 16)
28
- insn |= ((imm6 & 0x3f) << 10)
29
- insn |= ((rn & 0x1f) << 5)
30
- insn |= (rd & 0x1f)
25
+ insn |= ((sf) << 31)
26
+ insn |= ((shift) << 22)
27
+ insn |= ((rm) << 16)
28
+ insn |= ((imm6) << 10)
29
+ insn |= ((rn) << 5)
30
+ insn |= (rd)
31
31
  insn
32
32
  end
33
33
  end
@@ -3,26 +3,26 @@ module AArch64
3
3
  # SUBG -- A64
4
4
  # Subtract with Tag
5
5
  # SUBG <Xd|SP>, <Xn|SP>, #<uimm6>, #<uimm4>
6
- class SUBG
6
+ class SUBG < Instruction
7
7
  def initialize xd, xn, uimm6, uimm4
8
- @xd = xd
9
- @xn = xn
10
- @uimm6 = uimm6
11
- @uimm4 = uimm4
8
+ @xd = check_mask(xd, 0x1f)
9
+ @xn = check_mask(xn, 0x1f)
10
+ @uimm6 = check_mask(uimm6, 0x3f)
11
+ @uimm4 = check_mask(uimm4, 0x0f)
12
12
  end
13
13
 
14
14
  def encode
15
- SUBG(@uimm6, @uimm4, @xn.to_i, @xd.to_i)
15
+ SUBG(@uimm6, @uimm4, @xn, @xd)
16
16
  end
17
17
 
18
18
  private
19
19
 
20
20
  def SUBG uimm6, uimm4, xn, xd
21
21
  insn = 0b1_1_0_100011_0_000000_00_0000_00000_00000
22
- insn |= ((uimm6 & 0x3f) << 16)
23
- insn |= ((uimm4 & 0xf) << 10)
24
- insn |= ((xn & 0x1f) << 5)
25
- insn |= (xd & 0x1f)
22
+ insn |= ((uimm6) << 16)
23
+ insn |= ((uimm4) << 10)
24
+ insn |= ((xn) << 5)
25
+ insn |= (xd)
26
26
  insn
27
27
  end
28
28
  end
@@ -3,24 +3,24 @@ module AArch64
3
3
  # SUBP -- A64
4
4
  # Subtract Pointer
5
5
  # SUBP <Xd>, <Xn|SP>, <Xm|SP>
6
- class SUBP
6
+ class SUBP < Instruction
7
7
  def initialize xd, xn, xm
8
- @xd = xd
9
- @xn = xn
10
- @xm = xm
8
+ @xd = check_mask(xd, 0x1f)
9
+ @xn = check_mask(xn, 0x1f)
10
+ @xm = check_mask(xm, 0x1f)
11
11
  end
12
12
 
13
13
  def encode
14
- SUBP(@xm.to_i, @xn.to_i, @xm.to_i)
14
+ SUBP(@xm, @xn, @xd)
15
15
  end
16
16
 
17
17
  private
18
18
 
19
19
  def SUBP xm, xn, xd
20
20
  insn = 0b1_0_0_11010110_00000_0_0_0_0_0_0_00000_00000
21
- insn |= ((xm & 0x1f) << 16)
22
- insn |= ((xn & 0x1f) << 5)
23
- insn |= (xd & 0x1f)
21
+ insn |= ((xm) << 16)
22
+ insn |= ((xn) << 5)
23
+ insn |= (xd)
24
24
  insn
25
25
  end
26
26
  end
@@ -3,24 +3,24 @@ module AArch64
3
3
  # SUBPS -- A64
4
4
  # Subtract Pointer, setting Flags
5
5
  # SUBPS <Xd>, <Xn|SP>, <Xm|SP>
6
- class SUBPS
6
+ class SUBPS < Instruction
7
7
  def initialize xd, xn, xm
8
- @xd = xd
9
- @xn = xn
10
- @xm = xm
8
+ @xd = check_mask(xd, 0x1f)
9
+ @xn = check_mask(xn, 0x1f)
10
+ @xm = check_mask(xm, 0x1f)
11
11
  end
12
12
 
13
13
  def encode
14
- SUBPS(@xm.to_i, @xn.to_i, @xd.to_i)
14
+ SUBPS(@xm, @xn, @xd)
15
15
  end
16
16
 
17
17
  private
18
18
 
19
19
  def SUBPS xm, xn, xd
20
20
  insn = 0b1_0_1_11010110_00000_0_0_0_0_0_0_00000_00000
21
- insn |= ((xm & 0x1f) << 16)
22
- insn |= ((xn & 0x1f) << 5)
23
- insn |= (xd & 0x1f)
21
+ insn |= ((xm) << 16)
22
+ insn |= ((xn) << 5)
23
+ insn |= (xd)
24
24
  insn
25
25
  end
26
26
  end
@@ -4,30 +4,30 @@ module AArch64
4
4
  # Subtract (extended register), setting flags
5
5
  # SUBS <Wd>, <Wn|WSP>, <Wm>{, <extend> {#<amount>}}
6
6
  # SUBS <Xd>, <Xn|SP>, <R><m>{, <extend> {#<amount>}}
7
- class SUBS_addsub_ext
7
+ class SUBS_addsub_ext < Instruction
8
8
  def initialize rd, rn, rm, extend, amount, sf
9
- @rd = rd
10
- @rn = rn
11
- @rm = rm
12
- @extend = extend
13
- @amount = amount
14
- @sf = sf
9
+ @rd = check_mask(rd, 0x1f)
10
+ @rn = check_mask(rn, 0x1f)
11
+ @rm = check_mask(rm, 0x1f)
12
+ @extend = check_mask(extend, 0x07)
13
+ @amount = check_mask(amount, 0x07)
14
+ @sf = check_mask(sf, 0x01)
15
15
  end
16
16
 
17
17
  def encode
18
- SUBS_addsub_ext(@sf, @rm.to_i, @extend, @amount, @rn.to_i, @rd.to_i)
18
+ SUBS_addsub_ext(@sf, @rm, @extend, @amount, @rn, @rd)
19
19
  end
20
20
 
21
21
  private
22
22
 
23
23
  def SUBS_addsub_ext sf, rm, option, imm3, rn, rd
24
24
  insn = 0b0_1_1_01011_00_1_00000_000_000_00000_00000
25
- insn |= ((sf & 0x1) << 31)
26
- insn |= ((rm & 0x1f) << 16)
27
- insn |= ((option & 0x7) << 13)
28
- insn |= ((imm3 & 0x7) << 10)
29
- insn |= ((rn & 0x1f) << 5)
30
- insn |= (rd & 0x1f)
25
+ insn |= ((sf) << 31)
26
+ insn |= ((rm) << 16)
27
+ insn |= ((option) << 13)
28
+ insn |= ((imm3) << 10)
29
+ insn |= ((rn) << 5)
30
+ insn |= (rd)
31
31
  insn
32
32
  end
33
33
  end
@@ -4,28 +4,28 @@ module AArch64
4
4
  # Subtract (immediate), setting flags
5
5
  # SUBS <Wd>, <Wn|WSP>, #<imm>{, <shift>}
6
6
  # SUBS <Xd>, <Xn|SP>, #<imm>{, <shift>}
7
- class SUBS_addsub_imm
7
+ class SUBS_addsub_imm < Instruction
8
8
  def initialize rd, rn, imm, shift, sf
9
- @rd = rd
10
- @rn = rn
11
- @imm = imm
12
- @shift = shift
13
- @sf = sf
9
+ @rd = check_mask(rd, 0x1f)
10
+ @rn = check_mask(rn, 0x1f)
11
+ @imm = check_mask(imm, 0xfff)
12
+ @shift = check_mask(shift, 0x01)
13
+ @sf = check_mask(sf, 0x01)
14
14
  end
15
15
 
16
16
  def encode
17
- SUBS_addsub_imm(@sf, @shift, @imm, @rn.to_i, @rd.to_i)
17
+ SUBS_addsub_imm(@sf, @shift, @imm, @rn, @rd)
18
18
  end
19
19
 
20
20
  private
21
21
 
22
22
  def SUBS_addsub_imm sf, sh, imm12, rn, rd
23
23
  insn = 0b0_1_1_100010_0_000000000000_00000_00000
24
- insn |= ((sf & 0x1) << 31)
25
- insn |= ((sh & 0x1) << 22)
26
- insn |= ((imm12 & 0xfff) << 10)
27
- insn |= ((rn & 0x1f) << 5)
28
- insn |= (rd & 0x1f)
24
+ insn |= ((sf) << 31)
25
+ insn |= ((sh) << 22)
26
+ insn |= ((imm12) << 10)
27
+ insn |= ((rn) << 5)
28
+ insn |= (rd)
29
29
  insn
30
30
  end
31
31
  end
@@ -4,30 +4,30 @@ module AArch64
4
4
  # Subtract (shifted register), setting flags
5
5
  # SUBS <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
6
6
  # SUBS <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
7
- class SUBS_addsub_shift
7
+ class SUBS_addsub_shift < Instruction
8
8
  def initialize rd, rn, rm, shift, amount, sf
9
- @rd = rd
10
- @rn = rn
11
- @rm = rm
12
- @shift = shift
13
- @amount = amount
14
- @sf = sf
9
+ @rd = check_mask(rd, 0x1f)
10
+ @rn = check_mask(rn, 0x1f)
11
+ @rm = check_mask(rm, 0x1f)
12
+ @shift = check_mask(shift, 0x03)
13
+ @amount = check_mask(amount, 0x3f)
14
+ @sf = check_mask(sf, 0x01)
15
15
  end
16
16
 
17
17
  def encode
18
- SUBS_addsub_shift(@sf, @shift, @rm.to_i, @amount, @rn.to_i, @rd.to_i)
18
+ SUBS_addsub_shift(@sf, @shift, @rm, @amount, @rn, @rd)
19
19
  end
20
20
 
21
21
  private
22
22
 
23
23
  def SUBS_addsub_shift sf, shift, rm, imm6, rn, rd
24
24
  insn = 0b0_1_1_01011_00_0_00000_000000_00000_00000
25
- insn |= ((sf & 0x1) << 31)
26
- insn |= ((shift & 0x3) << 22)
27
- insn |= ((rm & 0x1f) << 16)
28
- insn |= ((imm6 & 0x3f) << 10)
29
- insn |= ((rn & 0x1f) << 5)
30
- insn |= (rd & 0x1f)
25
+ insn |= ((sf) << 31)
26
+ insn |= ((shift) << 22)
27
+ insn |= ((rm) << 16)
28
+ insn |= ((imm6) << 10)
29
+ insn |= ((rn) << 5)
30
+ insn |= (rd)
31
31
  insn
32
32
  end
33
33
  end
@@ -3,9 +3,9 @@ module AArch64
3
3
  # SVC -- A64
4
4
  # Supervisor Call
5
5
  # SVC #<imm>
6
- class SVC
6
+ class SVC < Instruction
7
7
  def initialize imm
8
- @imm = imm
8
+ @imm = check_mask(imm, 0xffff)
9
9
  end
10
10
 
11
11
  def encode
@@ -16,7 +16,7 @@ module AArch64
16
16
 
17
17
  def SVC imm16
18
18
  insn = 0b11010100_000_0000000000000000_000_01
19
- insn |= ((imm16 & 0xffff) << 5)
19
+ insn |= ((imm16) << 5)
20
20
  insn
21
21
  end
22
22
  end
@@ -10,30 +10,30 @@ module AArch64
10
10
  # SWPA <Xs>, <Xt>, [<Xn|SP>]
11
11
  # SWPAL <Xs>, <Xt>, [<Xn|SP>]
12
12
  # SWPL <Xs>, <Xt>, [<Xn|SP>]
13
- class SWP
13
+ class SWP < Instruction
14
14
  def initialize rs, rt, rn, size, a, r
15
- @rs = rs
16
- @rt = rt
17
- @rn = rn
18
- @size = size
19
- @a = a
20
- @r = r
15
+ @rs = check_mask(rs, 0x1f)
16
+ @rt = check_mask(rt, 0x1f)
17
+ @rn = check_mask(rn, 0x1f)
18
+ @size = check_mask(size, 0x03)
19
+ @a = check_mask(a, 0x01)
20
+ @r = check_mask(r, 0x01)
21
21
  end
22
22
 
23
23
  def encode
24
- SWP(@size, @a, @r, @rs.to_i, @rn.to_i, @rt.to_i)
24
+ SWP(@size, @a, @r, @rs, @rn, @rt)
25
25
  end
26
26
 
27
27
  private
28
28
 
29
29
  def SWP size, a, r, rs, rn, rt
30
30
  insn = 0b00_111_0_00_0_0_1_00000_1_000_00_00000_00000
31
- insn |= ((size & 0x3) << 30)
32
- insn |= ((a & 0x1) << 23)
33
- insn |= ((r & 0x1) << 22)
34
- insn |= ((rs & 0x1f) << 16)
35
- insn |= ((rn & 0x1f) << 5)
36
- insn |= (rt & 0x1f)
31
+ insn |= ((size) << 30)
32
+ insn |= ((a) << 23)
33
+ insn |= ((r) << 22)
34
+ insn |= ((rs) << 16)
35
+ insn |= ((rn) << 5)
36
+ insn |= (rt)
37
37
  insn
38
38
  end
39
39
  end