aarch64 1.0.1 → 2.0.0

data/lib/aarch64/instructions/stxr.rb

@@ -4,26 +4,26 @@ module AArch64
     # Store Exclusive Register
     # STXR  <Ws>, <Wt>, [<Xn|SP>{,#0}]
     # STXR  <Ws>, <Xt>, [<Xn|SP>{,#0}]
-    class STXR
+    class STXR < Instruction
       def initialize rs, rt, rn, size
-        @rs   = rs
-        @rt   = rt
-        @rn   = rn
-        @size = size
+        @rs   = check_mask(rs, 0x1f)
+        @rt   = check_mask(rt, 0x1f)
+        @rn   = check_mask(rn, 0x1f)
+        @size = check_mask(size, 0x03)
       end
 
       def encode
-        STXR(@size, @rs.to_i, @rn.to_i, @rt.to_i)
+        STXR(@size, @rs, @rn, @rt)
       end
 
       private
 
       def STXR size, rs, rn, rt
         insn = 0b00_001000_0_0_0_00000_0_11111_00000_00000
-        insn |= ((size & 0x3) << 30)
-        insn |= ((rs & 0x1f) << 16)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((size) << 30)
+        insn |= ((rs) << 16)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/stxrb.rb

@@ -3,24 +3,24 @@ module AArch64
     # STXRB -- A64
     # Store Exclusive Register Byte
     # STXRB  <Ws>, <Wt>, [<Xn|SP>{,#0}]
-    class STXRB
+    class STXRB < Instruction
       def initialize rs, rt, rn
-        @rs = rs
-        @rt = rt
-        @rn = rn
+        @rs = check_mask(rs, 0x1f)
+        @rt = check_mask(rt, 0x1f)
+        @rn = check_mask(rn, 0x1f)
       end
 
       def encode
-        STXRB(@rs.to_i, @rn.to_i, @rt.to_i)
+        STXRB(@rs, @rn, @rt)
       end
 
       private
 
       def STXRB rs, rn, rt
         insn = 0b00_001000_0_0_0_00000_0_11111_00000_00000
-        insn |= ((rs & 0x1f) << 16)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((rs) << 16)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/stxrh.rb

@@ -3,24 +3,24 @@ module AArch64
     # STXRH -- A64
     # Store Exclusive Register Halfword
     # STXRH  <Ws>, <Wt>, [<Xn|SP>{,#0}]
-    class STXRH
+    class STXRH < Instruction
       def initialize rs, rt, rn
-        @rs = rs
-        @rt = rt
-        @rn = rn
+        @rs = check_mask(rs, 0x1f)
+        @rt = check_mask(rt, 0x1f)
+        @rn = check_mask(rn, 0x1f)
       end
 
       def encode
-        STXRH(@rs.to_i, @rn.to_i, @rt.to_i)
+        STXRH(@rs, @rn, @rt)
       end
 
       private
 
       def STXRH rs, rn, rt
         insn = 0b01_001000_0_0_0_00000_0_11111_00000_00000
-        insn |= ((rs & 0x1f) << 16)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((rs) << 16)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end

data/lib/aarch64/instructions/stz2g.rb

@@ -5,26 +5,26 @@ module AArch64
     # STZ2G  <Xt|SP>, [<Xn|SP>], #<simm>
     # STZ2G  <Xt|SP>, [<Xn|SP>, #<simm>]!
     # STZ2G  <Xt|SP>, [<Xn|SP>{, #<simm>}]
-    class STZ2G
+    class STZ2G < Instruction
       def initialize xt, xn, imm9, opt
-        @xt   = xt
-        @xn   = xn
-        @imm9 = imm9
-        @opt  = opt
+        @xt   = check_mask(xt, 0x1f)
+        @xn   = check_mask(xn, 0x1f)
+        @imm9 = check_mask(imm9, 0x1ff)
+        @opt  = check_mask(opt, 0x03)
       end
 
       def encode
-        STZ2G(@imm9, @opt, @xn.to_i, @xt.to_i)
+        STZ2G(@imm9, @opt, @xn, @xt)
       end
 
       private
 
       def STZ2G imm9, opt, xn, xt
         insn = 0b11011001_1_1_1_000000000_00_00000_00000
-        insn |= ((imm9 & 0x1ff) << 12)
-        insn |= ((opt & 0x3) << 10)
-        insn |= ((xn & 0x1f) << 5)
-        insn |= (xt & 0x1f)
+        insn |= ((imm9) << 12)
+        insn |= ((opt) << 10)
+        insn |= ((xn) << 5)
+        insn |= (xt)
         insn
       end
     end

data/lib/aarch64/instructions/stzg.rb

@@ -5,26 +5,26 @@ module AArch64
     # STZG  <Xt|SP>, [<Xn|SP>], #<simm>
     # STZG  <Xt|SP>, [<Xn|SP>, #<simm>]!
     # STZG  <Xt|SP>, [<Xn|SP>{, #<simm>}]
-    class STZG
+    class STZG < Instruction
       def initialize xt, xn, imm9, opt
-        @xt   = xt
-        @xn   = xn
-        @imm9 = imm9
-        @opt  = opt
+        @xt   = check_mask(xt, 0x1f)
+        @xn   = check_mask(xn, 0x1f)
+        @imm9 = check_mask(imm9, 0x1ff)
+        @opt  = check_mask(opt, 0x03)
       end
 
       def encode
-        STZG(@imm9, @opt, @xn.to_i, @xt.to_i)
+        STZG(@imm9, @opt, @xn, @xt)
       end
 
       private
 
       def STZG imm9, opt, xn, xt
         insn = 0b11011001_0_1_1_000000000_00_00000_00000
-        insn |= ((imm9 & 0x1ff) << 12)
-        insn |= ((opt & 0x3) << 10)
-        insn |= ((xn & 0x1f) << 5)
-        insn |= (xt & 0x1f)
+        insn |= ((imm9) << 12)
+        insn |= ((opt) << 10)
+        insn |= ((xn) << 5)
+        insn |= (xt)
         insn
       end
     end

data/lib/aarch64/instructions/stzgm.rb

@@ -3,22 +3,22 @@ module AArch64
     # STZGM -- A64
     # Store Tag and Zero Multiple
     # STZGM  <Xt>, [<Xn|SP>]
-    class STZGM
+    class STZGM < Instruction
       def initialize rt, rn
-        @rt = rt
-        @rn = rn
+        @rt = check_mask(rt, 0x1f)
+        @rn = check_mask(rn, 0x1f)
       end
 
       def encode
-        STZGM(@rn.to_i, @rt.to_i)
+        STZGM(@rn, @rt)
       end
 
       private
 
       def STZGM xn, xt
         insn = 0b11011001_0_0_1_0_0_0_0_0_0_0_0_0_0_0_00000_00000
-        insn |= ((xn & 0x1f) << 5)
-        insn |= (xt & 0x1f)
+        insn |= ((xn) << 5)
+        insn |= (xt)
         insn
       end
     end

data/lib/aarch64/instructions/sub_addsub_ext.rb

@@ -4,30 +4,30 @@ module AArch64
     # Subtract (extended register)
     # SUB  <Wd|WSP>, <Wn|WSP>, <Wm>{, <extend> {#<amount>}}
     # SUB  <Xd|SP>, <Xn|SP>, <R><m>{, <extend> {#<amount>}}
-    class SUB_addsub_ext
+    class SUB_addsub_ext < Instruction
       def initialize rd, rn, rm, extend, amount, sf
-        @rd     = rd
-        @rn     = rn
-        @rm     = rm
-        @extend = extend
-        @amount = amount
-        @sf     = sf
+        @rd     = check_mask(rd, 0x1f)
+        @rn     = check_mask(rn, 0x1f)
+        @rm     = check_mask(rm, 0x1f)
+        @extend = check_mask(extend, 0x07)
+        @amount = check_mask(amount, 0x07)
+        @sf     = check_mask(sf, 0x01)
       end
 
       def encode
-        SUB_addsub_ext(@sf, @rm.to_i, @extend, @amount, @rn.to_i, @rd.to_i)
+        SUB_addsub_ext(@sf, @rm, @extend, @amount, @rn, @rd)
       end
 
       private
 
       def SUB_addsub_ext sf, rm, option, imm3, rn, rd
         insn = 0b0_1_0_01011_00_1_00000_000_000_00000_00000
-        insn |= ((sf & 0x1) << 31)
-        insn |= ((rm & 0x1f) << 16)
-        insn |= ((option & 0x7) << 13)
-        insn |= ((imm3 & 0x7) << 10)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rd & 0x1f)
+        insn |= ((sf) << 31)
+        insn |= ((rm) << 16)
+        insn |= ((option) << 13)
+        insn |= ((imm3) << 10)
+        insn |= ((rn) << 5)
+        insn |= (rd)
         insn
       end
     end

data/lib/aarch64/instructions/sub_addsub_imm.rb

@@ -4,28 +4,28 @@ module AArch64
     # Subtract (immediate)
     # SUB  <Wd|WSP>, <Wn|WSP>, #<imm>{, <shift>}
     # SUB  <Xd|SP>, <Xn|SP>, #<imm>{, <shift>}
-    class SUB_addsub_imm
+    class SUB_addsub_imm < Instruction
       def initialize rd, rn, imm, shift, sf
-        @rd    = rd
-        @rn    = rn
-        @imm   = imm
-        @shift = shift
-        @sf    = sf
+        @rd    = check_mask(rd, 0x1f)
+        @rn    = check_mask(rn, 0x1f)
+        @imm   = check_mask(imm, 0xfff)
+        @shift = check_mask(shift, 0x01)
+        @sf    = check_mask(sf, 0x01)
       end
 
       def encode
-        SUB_addsub_imm(@sf, @shift, @imm, @rn.to_i, @rd.to_i)
+        SUB_addsub_imm(@sf, @shift, @imm, @rn, @rd)
       end
 
       private
 
       def SUB_addsub_imm sf, sh, imm12, rn, rd
         insn = 0b0_1_0_100010_0_000000000000_00000_00000
-        insn |= ((sf & 0x1) << 31)
-        insn |= ((sh & 0x1) << 22)
-        insn |= ((imm12 & 0xfff) << 10)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rd & 0x1f)
+        insn |= ((sf) << 31)
+        insn |= ((sh) << 22)
+        insn |= ((imm12) << 10)
+        insn |= ((rn) << 5)
+        insn |= (rd)
         insn
       end
     end

data/lib/aarch64/instructions/sub_addsub_shift.rb

@@ -4,30 +4,30 @@ module AArch64
     # Subtract (shifted register)
     # SUB  <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
     # SUB  <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
-    class SUB_addsub_shift
+    class SUB_addsub_shift < Instruction
       def initialize rd, rn, rm, shift, amount, sf
-        @rd     = rd
-        @rn     = rn
-        @rm     = rm
-        @shift  = shift
-        @amount = amount
-        @sf     = sf
+        @rd     = check_mask(rd, 0x1f)
+        @rn     = check_mask(rn, 0x1f)
+        @rm     = check_mask(rm, 0x1f)
+        @shift  = check_mask(shift, 0x03)
+        @amount = check_mask(amount, 0x3f)
+        @sf     = check_mask(sf, 0x01)
       end
 
       def encode
-        SUB_addsub_shift(@sf, @shift, @rm.to_i, @amount, @rn.to_i, @rd.to_i)
+        SUB_addsub_shift(@sf, @shift, @rm, @amount, @rn, @rd)
       end
 
       private
 
       def SUB_addsub_shift sf, shift, rm, imm6, rn, rd
         insn = 0b0_1_0_01011_00_0_00000_000000_00000_00000
-        insn |= ((sf & 0x1) << 31)
-        insn |= ((shift & 0x3) << 22)
-        insn |= ((rm & 0x1f) << 16)
-        insn |= ((imm6 & 0x3f) << 10)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rd & 0x1f)
+        insn |= ((sf) << 31)
+        insn |= ((shift) << 22)
+        insn |= ((rm) << 16)
+        insn |= ((imm6) << 10)
+        insn |= ((rn) << 5)
+        insn |= (rd)
         insn
       end
     end

data/lib/aarch64/instructions/subg.rb

@@ -3,26 +3,26 @@ module AArch64
     # SUBG -- A64
     # Subtract with Tag
     # SUBG  <Xd|SP>, <Xn|SP>, #<uimm6>, #<uimm4>
-    class SUBG
+    class SUBG < Instruction
       def initialize xd, xn, uimm6, uimm4
-        @xd    = xd
-        @xn    = xn
-        @uimm6 = uimm6
-        @uimm4 = uimm4
+        @xd    = check_mask(xd, 0x1f)
+        @xn    = check_mask(xn, 0x1f)
+        @uimm6 = check_mask(uimm6, 0x3f)
+        @uimm4 = check_mask(uimm4, 0x0f)
       end
 
       def encode
-        SUBG(@uimm6, @uimm4, @xn.to_i, @xd.to_i)
+        SUBG(@uimm6, @uimm4, @xn, @xd)
       end
 
       private
 
       def SUBG uimm6, uimm4, xn, xd
         insn = 0b1_1_0_100011_0_000000_00_0000_00000_00000
-        insn |= ((uimm6 & 0x3f) << 16)
-        insn |= ((uimm4 & 0xf) << 10)
-        insn |= ((xn & 0x1f) << 5)
-        insn |= (xd & 0x1f)
+        insn |= ((uimm6) << 16)
+        insn |= ((uimm4) << 10)
+        insn |= ((xn) << 5)
+        insn |= (xd)
         insn
       end
     end

data/lib/aarch64/instructions/subp.rb

@@ -3,24 +3,24 @@ module AArch64
     # SUBP -- A64
     # Subtract Pointer
     # SUBP  <Xd>, <Xn|SP>, <Xm|SP>
-    class SUBP
+    class SUBP < Instruction
       def initialize xd, xn, xm
-        @xd = xd
-        @xn = xn
-        @xm = xm
+        @xd = check_mask(xd, 0x1f)
+        @xn = check_mask(xn, 0x1f)
+        @xm = check_mask(xm, 0x1f)
       end
 
       def encode
-        SUBP(@xm.to_i, @xn.to_i, @xm.to_i)
+        SUBP(@xm, @xn, @xd)
       end
 
       private
 
       def SUBP xm, xn, xd
         insn = 0b1_0_0_11010110_00000_0_0_0_0_0_0_00000_00000
-        insn |= ((xm & 0x1f) << 16)
-        insn |= ((xn & 0x1f) << 5)
-        insn |= (xd & 0x1f)
+        insn |= ((xm) << 16)
+        insn |= ((xn) << 5)
+        insn |= (xd)
         insn
       end
     end

data/lib/aarch64/instructions/subps.rb

@@ -3,24 +3,24 @@ module AArch64
     # SUBPS -- A64
     # Subtract Pointer, setting Flags
     # SUBPS  <Xd>, <Xn|SP>, <Xm|SP>
-    class SUBPS
+    class SUBPS < Instruction
       def initialize xd, xn, xm
-        @xd = xd
-        @xn = xn
-        @xm = xm
+        @xd = check_mask(xd, 0x1f)
+        @xn = check_mask(xn, 0x1f)
+        @xm = check_mask(xm, 0x1f)
       end
 
       def encode
-        SUBPS(@xm.to_i, @xn.to_i, @xd.to_i)
+        SUBPS(@xm, @xn, @xd)
       end
 
       private
 
       def SUBPS xm, xn, xd
         insn = 0b1_0_1_11010110_00000_0_0_0_0_0_0_00000_00000
-        insn |= ((xm & 0x1f) << 16)
-        insn |= ((xn & 0x1f) << 5)
-        insn |= (xd & 0x1f)
+        insn |= ((xm) << 16)
+        insn |= ((xn) << 5)
+        insn |= (xd)
         insn
       end
     end

data/lib/aarch64/instructions/subs_addsub_ext.rb

@@ -4,30 +4,30 @@ module AArch64
     # Subtract (extended register), setting flags
     # SUBS  <Wd>, <Wn|WSP>, <Wm>{, <extend> {#<amount>}}
     # SUBS  <Xd>, <Xn|SP>, <R><m>{, <extend> {#<amount>}}
-    class SUBS_addsub_ext
+    class SUBS_addsub_ext < Instruction
       def initialize rd, rn, rm, extend, amount, sf
-        @rd     = rd
-        @rn     = rn
-        @rm     = rm
-        @extend = extend
-        @amount = amount
-        @sf     = sf
+        @rd     = check_mask(rd, 0x1f)
+        @rn     = check_mask(rn, 0x1f)
+        @rm     = check_mask(rm, 0x1f)
+        @extend = check_mask(extend, 0x07)
+        @amount = check_mask(amount, 0x07)
+        @sf     = check_mask(sf, 0x01)
       end
 
       def encode
-        SUBS_addsub_ext(@sf, @rm.to_i, @extend, @amount, @rn.to_i, @rd.to_i)
+        SUBS_addsub_ext(@sf, @rm, @extend, @amount, @rn, @rd)
       end
 
       private
 
       def SUBS_addsub_ext sf, rm, option, imm3, rn, rd
         insn = 0b0_1_1_01011_00_1_00000_000_000_00000_00000
-        insn |= ((sf & 0x1) << 31)
-        insn |= ((rm & 0x1f) << 16)
-        insn |= ((option & 0x7) << 13)
-        insn |= ((imm3 & 0x7) << 10)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rd & 0x1f)
+        insn |= ((sf) << 31)
+        insn |= ((rm) << 16)
+        insn |= ((option) << 13)
+        insn |= ((imm3) << 10)
+        insn |= ((rn) << 5)
+        insn |= (rd)
         insn
       end
     end

data/lib/aarch64/instructions/subs_addsub_imm.rb

@@ -4,28 +4,28 @@ module AArch64
     # Subtract (immediate), setting flags
     # SUBS  <Wd>, <Wn|WSP>, #<imm>{, <shift>}
     # SUBS  <Xd>, <Xn|SP>, #<imm>{, <shift>}
-    class SUBS_addsub_imm
+    class SUBS_addsub_imm < Instruction
       def initialize rd, rn, imm, shift, sf
-        @rd    = rd
-        @rn    = rn
-        @imm   = imm
-        @shift = shift
-        @sf    = sf
+        @rd    = check_mask(rd, 0x1f)
+        @rn    = check_mask(rn, 0x1f)
+        @imm   = check_mask(imm, 0xfff)
+        @shift = check_mask(shift, 0x01)
+        @sf    = check_mask(sf, 0x01)
       end
 
       def encode
-        SUBS_addsub_imm(@sf, @shift, @imm, @rn.to_i, @rd.to_i)
+        SUBS_addsub_imm(@sf, @shift, @imm, @rn, @rd)
       end
 
       private
 
       def SUBS_addsub_imm sf, sh, imm12, rn, rd
         insn = 0b0_1_1_100010_0_000000000000_00000_00000
-        insn |= ((sf & 0x1) << 31)
-        insn |= ((sh & 0x1) << 22)
-        insn |= ((imm12 & 0xfff) << 10)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rd & 0x1f)
+        insn |= ((sf) << 31)
+        insn |= ((sh) << 22)
+        insn |= ((imm12) << 10)
+        insn |= ((rn) << 5)
+        insn |= (rd)
         insn
       end
     end

data/lib/aarch64/instructions/subs_addsub_shift.rb

@@ -4,30 +4,30 @@ module AArch64
     # Subtract (shifted register), setting flags
     # SUBS  <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
     # SUBS  <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
-    class SUBS_addsub_shift
+    class SUBS_addsub_shift < Instruction
       def initialize rd, rn, rm, shift, amount, sf
-        @rd     = rd
-        @rn     = rn
-        @rm     = rm
-        @shift  = shift
-        @amount = amount
-        @sf     = sf
+        @rd     = check_mask(rd, 0x1f)
+        @rn     = check_mask(rn, 0x1f)
+        @rm     = check_mask(rm, 0x1f)
+        @shift  = check_mask(shift, 0x03)
+        @amount = check_mask(amount, 0x3f)
+        @sf     = check_mask(sf, 0x01)
       end
 
       def encode
-        SUBS_addsub_shift(@sf, @shift, @rm.to_i, @amount, @rn.to_i, @rd.to_i)
+        SUBS_addsub_shift(@sf, @shift, @rm, @amount, @rn, @rd)
       end
 
       private
 
       def SUBS_addsub_shift sf, shift, rm, imm6, rn, rd
         insn = 0b0_1_1_01011_00_0_00000_000000_00000_00000
-        insn |= ((sf & 0x1) << 31)
-        insn |= ((shift & 0x3) << 22)
-        insn |= ((rm & 0x1f) << 16)
-        insn |= ((imm6 & 0x3f) << 10)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rd & 0x1f)
+        insn |= ((sf) << 31)
+        insn |= ((shift) << 22)
+        insn |= ((rm) << 16)
+        insn |= ((imm6) << 10)
+        insn |= ((rn) << 5)
+        insn |= (rd)
         insn
       end
     end

data/lib/aarch64/instructions/svc.rb

@@ -3,9 +3,9 @@ module AArch64
     # SVC -- A64
     # Supervisor Call
     # SVC  #<imm>
-    class SVC
+    class SVC < Instruction
       def initialize imm
-        @imm = imm
+        @imm = check_mask(imm, 0xffff)
       end
 
       def encode
@@ -16,7 +16,7 @@ module AArch64
 
       def SVC imm16
         insn = 0b11010100_000_0000000000000000_000_01
-        insn |= ((imm16 & 0xffff) << 5)
+        insn |= ((imm16) << 5)
         insn
       end
     end

data/lib/aarch64/instructions/swp.rb

@@ -10,30 +10,30 @@ module AArch64
     # SWPA  <Xs>, <Xt>, [<Xn|SP>]
     # SWPAL  <Xs>, <Xt>, [<Xn|SP>]
     # SWPL  <Xs>, <Xt>, [<Xn|SP>]
-    class SWP
+    class SWP < Instruction
       def initialize rs, rt, rn, size, a, r
-        @rs   = rs
-        @rt   = rt
-        @rn   = rn
-        @size = size
-        @a    = a
-        @r    = r
+        @rs   = check_mask(rs, 0x1f)
+        @rt   = check_mask(rt, 0x1f)
+        @rn   = check_mask(rn, 0x1f)
+        @size = check_mask(size, 0x03)
+        @a    = check_mask(a, 0x01)
+        @r    = check_mask(r, 0x01)
       end
 
       def encode
-        SWP(@size, @a, @r, @rs.to_i, @rn.to_i, @rt.to_i)
+        SWP(@size, @a, @r, @rs, @rn, @rt)
       end
 
       private
 
       def SWP size, a, r, rs, rn, rt
         insn = 0b00_111_0_00_0_0_1_00000_1_000_00_00000_00000
-        insn |= ((size & 0x3) << 30)
-        insn |= ((a & 0x1) << 23)
-        insn |= ((r & 0x1) << 22)
-        insn |= ((rs & 0x1f) << 16)
-        insn |= ((rn & 0x1f) << 5)
-        insn |= (rt & 0x1f)
+        insn |= ((size) << 30)
+        insn |= ((a) << 23)
+        insn |= ((r) << 22)
+        insn |= ((rs) << 16)
+        insn |= ((rn) << 5)
+        insn |= (rt)
         insn
       end
     end