aarch64 1.0.1 → 2.0.0
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- checksums.yaml +4 -4
- data/README.md +1 -1
- data/Rakefile +37 -0
- data/aarch64.gemspec +1 -0
- data/lib/aarch64/instructions/adc.rb +10 -10
- data/lib/aarch64/instructions/adcs.rb +10 -10
- data/lib/aarch64/instructions/add_addsub_ext.rb +14 -14
- data/lib/aarch64/instructions/add_addsub_imm.rb +12 -12
- data/lib/aarch64/instructions/add_addsub_shift.rb +14 -14
- data/lib/aarch64/instructions/addg.rb +10 -10
- data/lib/aarch64/instructions/adds_addsub_ext.rb +14 -14
- data/lib/aarch64/instructions/adds_addsub_imm.rb +12 -12
- data/lib/aarch64/instructions/adds_addsub_shift.rb +14 -14
- data/lib/aarch64/instructions/adr.rb +7 -7
- data/lib/aarch64/instructions/adrp.rb +7 -7
- data/lib/aarch64/instructions/and_log_imm.rb +14 -14
- data/lib/aarch64/instructions/and_log_shift.rb +14 -14
- data/lib/aarch64/instructions/ands_log_imm.rb +14 -14
- data/lib/aarch64/instructions/ands_log_shift.rb +14 -14
- data/lib/aarch64/instructions/asrv.rb +10 -10
- data/lib/aarch64/instructions/autda.rb +9 -12
- data/lib/aarch64/instructions/autdb.rb +9 -12
- data/lib/aarch64/instructions/autia.rb +9 -12
- data/lib/aarch64/instructions/autib.rb +9 -12
- data/lib/aarch64/instructions/axflag.rb +1 -1
- data/lib/aarch64/instructions/b_cond.rb +5 -5
- data/lib/aarch64/instructions/b_uncond.rb +3 -3
- data/lib/aarch64/instructions/bc_cond.rb +5 -5
- data/lib/aarch64/instructions/bfm.rb +13 -13
- data/lib/aarch64/instructions/bic_log_shift.rb +14 -14
- data/lib/aarch64/instructions/bics.rb +14 -14
- data/lib/aarch64/instructions/bl.rb +3 -3
- data/lib/aarch64/instructions/blr.rb +4 -4
- data/lib/aarch64/instructions/blra.rb +10 -10
- data/lib/aarch64/instructions/br.rb +4 -4
- data/lib/aarch64/instructions/bra.rb +10 -10
- data/lib/aarch64/instructions/brk.rb +3 -3
- data/lib/aarch64/instructions/bti.rb +3 -3
- data/lib/aarch64/instructions/cas.rb +14 -14
- data/lib/aarch64/instructions/casb.rb +12 -12
- data/lib/aarch64/instructions/cash.rb +12 -12
- data/lib/aarch64/instructions/casp.rb +14 -14
- data/lib/aarch64/instructions/cbnz.rb +7 -7
- data/lib/aarch64/instructions/cbz.rb +7 -7
- data/lib/aarch64/instructions/ccmn_imm.rb +12 -12
- data/lib/aarch64/instructions/ccmn_reg.rb +12 -12
- data/lib/aarch64/instructions/ccmp_imm.rb +12 -12
- data/lib/aarch64/instructions/ccmp_reg.rb +12 -12
- data/lib/aarch64/instructions/cfinv.rb +2 -9
- data/lib/aarch64/instructions/clrex.rb +3 -3
- data/lib/aarch64/instructions/cls_int.rb +8 -8
- data/lib/aarch64/instructions/clz_int.rb +8 -8
- data/lib/aarch64/instructions/crc32.rb +12 -12
- data/lib/aarch64/instructions/crc32c.rb +12 -12
- data/lib/aarch64/instructions/csdb.rb +1 -1
- data/lib/aarch64/instructions/csel.rb +12 -12
- data/lib/aarch64/instructions/csinc.rb +12 -12
- data/lib/aarch64/instructions/csinv.rb +12 -12
- data/lib/aarch64/instructions/csneg.rb +12 -12
- data/lib/aarch64/instructions/dcps.rb +5 -5
- data/lib/aarch64/instructions/dgh.rb +1 -1
- data/lib/aarch64/instructions/dmb.rb +3 -3
- data/lib/aarch64/instructions/drps.rb +2 -9
- data/lib/aarch64/instructions/dsb.rb +3 -3
- data/lib/aarch64/instructions/eon.rb +14 -14
- data/lib/aarch64/instructions/eor_log_imm.rb +14 -14
- data/lib/aarch64/instructions/eor_log_shift.rb +14 -14
- data/lib/aarch64/instructions/eret.rb +2 -9
- data/lib/aarch64/instructions/ereta.rb +3 -3
- data/lib/aarch64/instructions/esb.rb +1 -1
- data/lib/aarch64/instructions/extr.rb +13 -13
- data/lib/aarch64/instructions/gmi.rb +8 -8
- data/lib/aarch64/instructions/hint.rb +5 -5
- data/lib/aarch64/instructions/hlt.rb +3 -3
- data/lib/aarch64/instructions/hvc.rb +3 -3
- data/lib/aarch64/instructions/irg.rb +8 -8
- data/lib/aarch64/instructions/isb.rb +3 -3
- data/lib/aarch64/instructions/ld64b.rb +6 -6
- data/lib/aarch64/instructions/ldadd.rb +14 -14
- data/lib/aarch64/instructions/ldaddb.rb +12 -12
- data/lib/aarch64/instructions/ldaddh.rb +12 -12
- data/lib/aarch64/instructions/ldapr.rb +8 -8
- data/lib/aarch64/instructions/ldaprb.rb +6 -6
- data/lib/aarch64/instructions/ldaprh.rb +6 -6
- data/lib/aarch64/instructions/ldapur_gen.rb +12 -12
- data/lib/aarch64/instructions/ldar.rb +8 -8
- data/lib/aarch64/instructions/ldaxp.rb +10 -10
- data/lib/aarch64/instructions/ldaxr.rb +8 -8
- data/lib/aarch64/instructions/ldclr.rb +14 -14
- data/lib/aarch64/instructions/ldclrb.rb +14 -14
- data/lib/aarch64/instructions/ldeor.rb +14 -14
- data/lib/aarch64/instructions/ldg.rb +8 -8
- data/lib/aarch64/instructions/ldgm.rb +6 -6
- data/lib/aarch64/instructions/ldlar.rb +8 -8
- data/lib/aarch64/instructions/ldnp_gen.rb +12 -12
- data/lib/aarch64/instructions/ldp_gen.rb +14 -14
- data/lib/aarch64/instructions/ldpsw.rb +12 -12
- data/lib/aarch64/instructions/ldr_imm_gen.rb +12 -12
- data/lib/aarch64/instructions/ldr_imm_unsigned.rb +10 -10
- data/lib/aarch64/instructions/ldr_lit_gen.rb +7 -7
- data/lib/aarch64/instructions/ldr_reg_gen.rb +14 -14
- data/lib/aarch64/instructions/ldra.rb +14 -14
- data/lib/aarch64/instructions/ldrb_imm.rb +10 -10
- data/lib/aarch64/instructions/ldrb_reg.rb +12 -12
- data/lib/aarch64/instructions/ldrb_unsigned.rb +8 -8
- data/lib/aarch64/instructions/ldrh_imm.rb +10 -10
- data/lib/aarch64/instructions/ldrh_reg.rb +12 -12
- data/lib/aarch64/instructions/ldrh_unsigned.rb +8 -8
- data/lib/aarch64/instructions/ldrsb_imm.rb +12 -12
- data/lib/aarch64/instructions/ldrsb_reg.rb +14 -14
- data/lib/aarch64/instructions/ldrsb_unsigned.rb +10 -10
- data/lib/aarch64/instructions/ldrsh_imm.rb +12 -12
- data/lib/aarch64/instructions/ldrsh_reg.rb +14 -14
- data/lib/aarch64/instructions/ldrsh_unsigned.rb +10 -10
- data/lib/aarch64/instructions/ldrsw_imm.rb +10 -10
- data/lib/aarch64/instructions/ldrsw_lit.rb +5 -5
- data/lib/aarch64/instructions/ldrsw_reg.rb +12 -12
- data/lib/aarch64/instructions/ldrsw_unsigned.rb +8 -8
- data/lib/aarch64/instructions/ldset.rb +14 -14
- data/lib/aarch64/instructions/ldsetb.rb +12 -12
- data/lib/aarch64/instructions/ldseth.rb +12 -12
- data/lib/aarch64/instructions/ldsmax.rb +14 -14
- data/lib/aarch64/instructions/ldsmaxb.rb +12 -12
- data/lib/aarch64/instructions/ldsmaxh.rb +12 -12
- data/lib/aarch64/instructions/ldsmin.rb +14 -14
- data/lib/aarch64/instructions/ldsminb.rb +12 -12
- data/lib/aarch64/instructions/ldsminh.rb +12 -12
- data/lib/aarch64/instructions/ldtr.rb +10 -10
- data/lib/aarch64/instructions/ldtrb.rb +8 -8
- data/lib/aarch64/instructions/ldtrh.rb +8 -8
- data/lib/aarch64/instructions/ldtrsb.rb +10 -10
- data/lib/aarch64/instructions/ldtrsh.rb +10 -10
- data/lib/aarch64/instructions/ldtrsw.rb +8 -8
- data/lib/aarch64/instructions/ldumax.rb +14 -14
- data/lib/aarch64/instructions/ldumaxb.rb +12 -12
- data/lib/aarch64/instructions/ldumaxh.rb +12 -12
- data/lib/aarch64/instructions/ldumin.rb +14 -14
- data/lib/aarch64/instructions/lduminb.rb +12 -12
- data/lib/aarch64/instructions/lduminh.rb +12 -12
- data/lib/aarch64/instructions/ldur_gen.rb +10 -10
- data/lib/aarch64/instructions/ldursb.rb +10 -10
- data/lib/aarch64/instructions/ldursh.rb +10 -10
- data/lib/aarch64/instructions/ldursw.rb +8 -8
- data/lib/aarch64/instructions/ldxp.rb +10 -10
- data/lib/aarch64/instructions/ldxr.rb +8 -8
- data/lib/aarch64/instructions/lslv.rb +10 -10
- data/lib/aarch64/instructions/lsrv.rb +10 -10
- data/lib/aarch64/instructions/madd.rb +12 -12
- data/lib/aarch64/instructions/movk.rb +10 -10
- data/lib/aarch64/instructions/movn.rb +10 -10
- data/lib/aarch64/instructions/movz.rb +10 -10
- data/lib/aarch64/instructions/mrs.rb +14 -14
- data/lib/aarch64/instructions/msr_imm.rb +7 -7
- data/lib/aarch64/instructions/msr_reg.rb +14 -14
- data/lib/aarch64/instructions/msub.rb +12 -12
- data/lib/aarch64/instructions/nop.rb +1 -1
- data/lib/aarch64/instructions/orn_log_shift.rb +14 -14
- data/lib/aarch64/instructions/orr_log_imm.rb +14 -14
- data/lib/aarch64/instructions/orr_log_shift.rb +14 -14
- data/lib/aarch64/instructions/pacda.rb +8 -8
- data/lib/aarch64/instructions/pacdb.rb +8 -8
- data/lib/aarch64/instructions/pacga.rb +8 -8
- data/lib/aarch64/instructions/pacia.rb +8 -8
- data/lib/aarch64/instructions/pacia2.rb +5 -5
- data/lib/aarch64/instructions/pacib.rb +8 -8
- data/lib/aarch64/instructions/prfm_imm.rb +8 -8
- data/lib/aarch64/instructions/prfm_lit.rb +8 -8
- data/lib/aarch64/instructions/prfm_reg.rb +12 -12
- data/lib/aarch64/instructions/prfum.rb +8 -8
- data/lib/aarch64/instructions/psb.rb +2 -9
- data/lib/aarch64/instructions/rbit_int.rb +8 -8
- data/lib/aarch64/instructions/ret.rb +4 -4
- data/lib/aarch64/instructions/reta.rb +3 -3
- data/lib/aarch64/instructions/rev.rb +10 -10
- data/lib/aarch64/instructions/rmif.rb +8 -8
- data/lib/aarch64/instructions/rorv.rb +10 -10
- data/lib/aarch64/instructions/sb.rb +1 -1
- data/lib/aarch64/instructions/sbc.rb +10 -10
- data/lib/aarch64/instructions/sbcs.rb +10 -10
- data/lib/aarch64/instructions/sbfm.rb +13 -13
- data/lib/aarch64/instructions/sdiv.rb +10 -10
- data/lib/aarch64/instructions/setf.rb +6 -6
- data/lib/aarch64/instructions/sev.rb +1 -7
- data/lib/aarch64/instructions/sevl.rb +1 -1
- data/lib/aarch64/instructions/smaddl.rb +10 -10
- data/lib/aarch64/instructions/smc.rb +3 -3
- data/lib/aarch64/instructions/smsubl.rb +10 -10
- data/lib/aarch64/instructions/smulh.rb +8 -8
- data/lib/aarch64/instructions/st2g.rb +10 -10
- data/lib/aarch64/instructions/st64b.rb +6 -6
- data/lib/aarch64/instructions/st64bv.rb +8 -8
- data/lib/aarch64/instructions/st64bv0.rb +8 -8
- data/lib/aarch64/instructions/stg.rb +10 -10
- data/lib/aarch64/instructions/stgm.rb +6 -6
- data/lib/aarch64/instructions/stgp.rb +12 -12
- data/lib/aarch64/instructions/stllr.rb +8 -8
- data/lib/aarch64/instructions/stllrb.rb +6 -6
- data/lib/aarch64/instructions/stllrh.rb +6 -6
- data/lib/aarch64/instructions/stlr.rb +8 -8
- data/lib/aarch64/instructions/stlrb.rb +6 -6
- data/lib/aarch64/instructions/stlrh.rb +6 -6
- data/lib/aarch64/instructions/stlur_gen.rb +10 -10
- data/lib/aarch64/instructions/stlxp.rb +12 -12
- data/lib/aarch64/instructions/stlxr.rb +10 -10
- data/lib/aarch64/instructions/stlxrb.rb +8 -8
- data/lib/aarch64/instructions/stlxrh.rb +8 -8
- data/lib/aarch64/instructions/stnp_gen.rb +12 -12
- data/lib/aarch64/instructions/stp_gen.rb +14 -14
- data/lib/aarch64/instructions/str_imm_gen.rb +12 -12
- data/lib/aarch64/instructions/str_imm_unsigned.rb +10 -10
- data/lib/aarch64/instructions/str_reg_gen.rb +14 -14
- data/lib/aarch64/instructions/strb_imm.rb +10 -10
- data/lib/aarch64/instructions/strb_imm_unsigned.rb +8 -8
- data/lib/aarch64/instructions/strb_reg.rb +12 -12
- data/lib/aarch64/instructions/strh_imm.rb +10 -10
- data/lib/aarch64/instructions/strh_imm_unsigned.rb +8 -8
- data/lib/aarch64/instructions/strh_reg.rb +12 -12
- data/lib/aarch64/instructions/sttr.rb +10 -10
- data/lib/aarch64/instructions/stur_gen.rb +10 -10
- data/lib/aarch64/instructions/stxp.rb +12 -12
- data/lib/aarch64/instructions/stxr.rb +10 -10
- data/lib/aarch64/instructions/stxrb.rb +8 -8
- data/lib/aarch64/instructions/stxrh.rb +8 -8
- data/lib/aarch64/instructions/stz2g.rb +10 -10
- data/lib/aarch64/instructions/stzg.rb +10 -10
- data/lib/aarch64/instructions/stzgm.rb +6 -6
- data/lib/aarch64/instructions/sub_addsub_ext.rb +14 -14
- data/lib/aarch64/instructions/sub_addsub_imm.rb +12 -12
- data/lib/aarch64/instructions/sub_addsub_shift.rb +14 -14
- data/lib/aarch64/instructions/subg.rb +10 -10
- data/lib/aarch64/instructions/subp.rb +8 -8
- data/lib/aarch64/instructions/subps.rb +8 -8
- data/lib/aarch64/instructions/subs_addsub_ext.rb +14 -14
- data/lib/aarch64/instructions/subs_addsub_imm.rb +12 -12
- data/lib/aarch64/instructions/subs_addsub_shift.rb +14 -14
- data/lib/aarch64/instructions/svc.rb +3 -3
- data/lib/aarch64/instructions/swp.rb +14 -14
- data/lib/aarch64/instructions/swpb.rb +12 -12
- data/lib/aarch64/instructions/swph.rb +12 -12
- data/lib/aarch64/instructions/sys.rb +12 -12
- data/lib/aarch64/instructions/sysl.rb +12 -12
- data/lib/aarch64/instructions/tbnz.rb +9 -9
- data/lib/aarch64/instructions/tbz.rb +9 -9
- data/lib/aarch64/instructions/tsb.rb +1 -7
- data/lib/aarch64/instructions/ubfm.rb +13 -13
- data/lib/aarch64/instructions/udf_perm_undef.rb +3 -3
- data/lib/aarch64/instructions/udiv.rb +10 -10
- data/lib/aarch64/instructions/umaddl.rb +10 -10
- data/lib/aarch64/instructions/umsubl.rb +10 -10
- data/lib/aarch64/instructions/umulh.rb +8 -8
- data/lib/aarch64/instructions/wfe.rb +2 -9
- data/lib/aarch64/instructions/wfet.rb +4 -4
- data/lib/aarch64/instructions/wfi.rb +1 -1
- data/lib/aarch64/instructions/wfit.rb +4 -4
- data/lib/aarch64/instructions/xaflag.rb +1 -1
- data/lib/aarch64/instructions/xpac.rb +6 -6
- data/lib/aarch64/instructions/xpaclri.rb +1 -1
- data/lib/aarch64/instructions/yield.rb +2 -9
- data/lib/aarch64/instructions.rb +26 -8
- data/lib/aarch64/parser.rb +227 -0
- data/lib/aarch64/parser.tab.rb +6534 -0
- data/lib/aarch64/parser.y +1394 -0
- data/lib/aarch64/utils.rb +34 -0
- data/lib/aarch64/version.rb +1 -1
- data/lib/aarch64.rb +128 -58
- data/test/base_instructions_test.rb +34 -4
- data/test/helper.rb +48 -8
- data/test/parser_test.rb +1820 -0
- metadata +25 -14
- data/lib/aarch64/instructions/setgp.rb +0 -25
- data/lib/aarch64/instructions/setgpn.rb +0 -25
- data/lib/aarch64/instructions/setgpt.rb +0 -25
- data/lib/aarch64/instructions/setgptn.rb +0 -25
- data/lib/aarch64/instructions/setp.rb +0 -25
- data/lib/aarch64/instructions/setpn.rb +0 -25
- data/lib/aarch64/instructions/setpt.rb +0 -25
- data/lib/aarch64/instructions/setptn.rb +0 -25
@@ -3,24 +3,24 @@ module AArch64
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# PACGA -- A64
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# Pointer Authentication Code, using Generic key
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# PACGA <Xd>, <Xn>, <Xm|SP>
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class PACGA
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class PACGA < Instruction
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def initialize rd, rn, rm
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@rd = rd
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@rn = rn
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@rm = rm
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@rd = check_mask(rd, 0x1f)
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@rn = check_mask(rn, 0x1f)
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@rm = check_mask(rm, 0x1f)
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end
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def encode
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PACGA(@rm
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PACGA(@rm, @rn, @rd)
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end
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private
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def PACGA rm, rn, rd
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insn = 0b1_0_0_11010110_00000_001100_00000_00000
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insn |= ((rm
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insn |= ((rn
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insn |= (rd
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insn |= ((rm) << 16)
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insn |= ((rn) << 5)
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insn |= (rd)
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insn
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end
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end
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@@ -7,24 +7,24 @@ module AArch64
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# PACIA1716
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# PACIASP
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# PACIAZ
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class PACIA
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class PACIA < Instruction
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def initialize rd, rn, z
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@rd = rd
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@rn = rn
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@z = z
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@rd = check_mask(rd, 0x1f)
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@rn = check_mask(rn, 0x1f)
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@z = check_mask(z, 0x01)
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end
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def encode
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PACIA(@z, @rn
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PACIA(@z, @rn, @rd)
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end
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private
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def PACIA z, rn, rd
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insn = 0b1_1_0_11010110_00001_0_0_0_000_00000_00000
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insn |= ((z
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insn |= ((rn
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insn |= (rd
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insn |= ((z) << 13)
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insn |= ((rn) << 5)
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insn |= (rd)
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insn
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end
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end
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# PACIA1716
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# PACIASP
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# PACIAZ
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class PACIA2
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class PACIA2 < Instruction
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def initialize crm, op2
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@crm = crm
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@op2 = op2
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@crm = check_mask(crm, 0x0f)
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@op2 = check_mask(op2, 0x07)
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end
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def encode
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def PACIA2 crm, op2
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insn = 0b11010101000000110010_0000_000_11111
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insn |= ((crm
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insn |= ((op2
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insn |= ((crm) << 8)
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insn |= ((op2) << 5)
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insn
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end
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end
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@@ -7,24 +7,24 @@ module AArch64
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# PACIB1716
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8
8
|
# PACIBSP
|
9
9
|
# PACIBZ
|
10
|
-
class PACIB
|
10
|
+
class PACIB < Instruction
|
11
11
|
def initialize rd, rn, z
|
12
|
-
@rd = rd
|
13
|
-
@rn = rn
|
14
|
-
@z = z
|
12
|
+
@rd = check_mask(rd, 0x1f)
|
13
|
+
@rn = check_mask(rn, 0x1f)
|
14
|
+
@z = check_mask(z, 0x01)
|
15
15
|
end
|
16
16
|
|
17
17
|
def encode
|
18
|
-
PACIB(@z, @rn
|
18
|
+
PACIB(@z, @rn, @rd)
|
19
19
|
end
|
20
20
|
|
21
21
|
private
|
22
22
|
|
23
23
|
def PACIB z, rn, rd
|
24
24
|
insn = 0b1_1_0_11010110_00001_0_0_0_001_00000_00000
|
25
|
-
insn |= ((z
|
26
|
-
insn |= ((rn
|
27
|
-
insn |= (rd
|
25
|
+
insn |= ((z) << 13)
|
26
|
+
insn |= ((rn) << 5)
|
27
|
+
insn |= (rd)
|
28
28
|
insn
|
29
29
|
end
|
30
30
|
end
|
@@ -3,24 +3,24 @@ module AArch64
|
|
3
3
|
# PRFM (immediate) -- A64
|
4
4
|
# Prefetch Memory (immediate)
|
5
5
|
# PRFM (<prfop>|#<imm5>), [<Xn|SP>{, #<pimm>}]
|
6
|
-
class PRFM_imm
|
6
|
+
class PRFM_imm < Instruction
|
7
7
|
def initialize rt, rn, imm12
|
8
|
-
@rt = rt
|
9
|
-
@rn = rn
|
10
|
-
@imm12 = imm12
|
8
|
+
@rt = check_mask(rt, 0x1f)
|
9
|
+
@rn = check_mask(rn, 0x1f)
|
10
|
+
@imm12 = check_mask(imm12, 0xfff)
|
11
11
|
end
|
12
12
|
|
13
13
|
def encode
|
14
|
-
PRFM_imm(@imm12, @rn
|
14
|
+
PRFM_imm(@imm12, @rn, @rt)
|
15
15
|
end
|
16
16
|
|
17
17
|
private
|
18
18
|
|
19
19
|
def PRFM_imm imm12, rn, rt
|
20
20
|
insn = 0b11_111_0_01_10_000000000000_00000_00000
|
21
|
-
insn |= ((imm12
|
22
|
-
insn |= ((rn
|
23
|
-
insn |= (rt
|
21
|
+
insn |= ((imm12) << 10)
|
22
|
+
insn |= ((rn) << 5)
|
23
|
+
insn |= (rt)
|
24
24
|
insn
|
25
25
|
end
|
26
26
|
end
|
@@ -3,22 +3,22 @@ module AArch64
|
|
3
3
|
# PRFM (literal) -- A64
|
4
4
|
# Prefetch Memory (literal)
|
5
5
|
# PRFM (<prfop>|#<imm5>), <label>
|
6
|
-
class PRFM_lit
|
7
|
-
def initialize rt,
|
8
|
-
@
|
9
|
-
@rt = rt
|
6
|
+
class PRFM_lit < Instruction
|
7
|
+
def initialize rt, label
|
8
|
+
@label = label
|
9
|
+
@rt = check_mask(rt, 0x1f)
|
10
10
|
end
|
11
11
|
|
12
12
|
def encode
|
13
|
-
PRFM_lit(@
|
13
|
+
PRFM_lit(check_mask(unwrap_label(@label), 0x7ffff), @rt)
|
14
14
|
end
|
15
15
|
|
16
16
|
private
|
17
17
|
|
18
|
-
def PRFM_lit
|
18
|
+
def PRFM_lit label, rt
|
19
19
|
insn = 0b11_011_0_00_0000000000000000000_00000
|
20
|
-
insn |= (
|
21
|
-
insn |=
|
20
|
+
insn |= (label << 5)
|
21
|
+
insn |= rt
|
22
22
|
insn
|
23
23
|
end
|
24
24
|
end
|
@@ -3,28 +3,28 @@ module AArch64
|
|
3
3
|
# PRFM (register) -- A64
|
4
4
|
# Prefetch Memory (register)
|
5
5
|
# PRFM (<prfop>|#<imm5>), [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
|
6
|
-
class PRFM_reg
|
6
|
+
class PRFM_reg < Instruction
|
7
7
|
def initialize rt, rn, rm, option, s
|
8
|
-
@rt = rt
|
9
|
-
@rn = rn
|
10
|
-
@rm = rm
|
11
|
-
@option = option
|
12
|
-
@s = s
|
8
|
+
@rt = check_mask(rt, 0x1f)
|
9
|
+
@rn = check_mask(rn, 0x1f)
|
10
|
+
@rm = check_mask(rm, 0x1f)
|
11
|
+
@option = check_mask(option, 0x07)
|
12
|
+
@s = check_mask(s, 0x01)
|
13
13
|
end
|
14
14
|
|
15
15
|
def encode
|
16
|
-
PRFM_reg(@rm
|
16
|
+
PRFM_reg(@rm, @option, @s, @rn, @rt)
|
17
17
|
end
|
18
18
|
|
19
19
|
private
|
20
20
|
|
21
21
|
def PRFM_reg rm, option, s, rn, rt
|
22
22
|
insn = 0b11_111_0_00_10_1_00000_000_0_10_00000_00000
|
23
|
-
insn |= ((rm
|
24
|
-
insn |= ((option
|
25
|
-
insn |= ((s
|
26
|
-
insn |= ((rn
|
27
|
-
insn |= (rt
|
23
|
+
insn |= ((rm) << 16)
|
24
|
+
insn |= ((option) << 13)
|
25
|
+
insn |= ((s) << 12)
|
26
|
+
insn |= ((rn) << 5)
|
27
|
+
insn |= (rt)
|
28
28
|
insn
|
29
29
|
end
|
30
30
|
end
|
@@ -3,24 +3,24 @@ module AArch64
|
|
3
3
|
# PRFUM -- A64
|
4
4
|
# Prefetch Memory (unscaled offset)
|
5
5
|
# PRFUM (<prfop>|#<imm5>), [<Xn|SP>{, #<simm>}]
|
6
|
-
class PRFUM
|
6
|
+
class PRFUM < Instruction
|
7
7
|
def initialize rt, rn, imm9
|
8
|
-
@rt = rt
|
9
|
-
@rn = rn
|
10
|
-
@imm9 = imm9
|
8
|
+
@rt = check_mask(rt, 0x1f)
|
9
|
+
@rn = check_mask(rn, 0x1f)
|
10
|
+
@imm9 = check_mask(imm9, 0x1ff)
|
11
11
|
end
|
12
12
|
|
13
13
|
def encode
|
14
|
-
PRFUM(@imm9, @rn
|
14
|
+
PRFUM(@imm9, @rn, @rt)
|
15
15
|
end
|
16
16
|
|
17
17
|
private
|
18
18
|
|
19
19
|
def PRFUM imm9, rn, rt
|
20
20
|
insn = 0b11_111_0_00_10_0_000000000_00_00000_00000
|
21
|
-
insn |= ((imm9
|
22
|
-
insn |= ((rn
|
23
|
-
insn |= (rt
|
21
|
+
insn |= ((imm9) << 12)
|
22
|
+
insn |= ((rn) << 5)
|
23
|
+
insn |= (rt)
|
24
24
|
insn
|
25
25
|
end
|
26
26
|
end
|
@@ -3,16 +3,9 @@ module AArch64
|
|
3
3
|
# PSB CSYNC -- A64
|
4
4
|
# Profiling Synchronization Barrier
|
5
5
|
# PSB CSYNC
|
6
|
-
class PSB
|
6
|
+
class PSB < Instruction
|
7
7
|
def encode
|
8
|
-
|
9
|
-
end
|
10
|
-
|
11
|
-
private
|
12
|
-
|
13
|
-
def PSB
|
14
|
-
insn = 0b1101010100_0_00_011_0010_0010_001_11111
|
15
|
-
insn
|
8
|
+
0b1101010100_0_00_011_0010_0010_001_11111
|
16
9
|
end
|
17
10
|
end
|
18
11
|
end
|
@@ -4,24 +4,24 @@ module AArch64
|
|
4
4
|
# Reverse Bits
|
5
5
|
# RBIT <Wd>, <Wn>
|
6
6
|
# RBIT <Xd>, <Xn>
|
7
|
-
class RBIT_int
|
7
|
+
class RBIT_int < Instruction
|
8
8
|
def initialize rd, rn, sf
|
9
|
-
@rd = rd
|
10
|
-
@rn = rn
|
11
|
-
@sf = sf
|
9
|
+
@rd = check_mask(rd, 0x1f)
|
10
|
+
@rn = check_mask(rn, 0x1f)
|
11
|
+
@sf = check_mask(sf, 0x01)
|
12
12
|
end
|
13
13
|
|
14
14
|
def encode
|
15
|
-
RBIT_int(@sf, @rn
|
15
|
+
RBIT_int(@sf, @rn, @rd)
|
16
16
|
end
|
17
17
|
|
18
18
|
private
|
19
19
|
|
20
20
|
def RBIT_int sf, rn, rd
|
21
21
|
insn = 0b0_1_0_11010110_00000_0000_00_00000_00000
|
22
|
-
insn |= ((sf
|
23
|
-
insn |= ((rn
|
24
|
-
insn |= (rd
|
22
|
+
insn |= ((sf) << 31)
|
23
|
+
insn |= ((rn) << 5)
|
24
|
+
insn |= (rd)
|
25
25
|
insn
|
26
26
|
end
|
27
27
|
end
|
@@ -3,20 +3,20 @@ module AArch64
|
|
3
3
|
# RET -- A64
|
4
4
|
# Return from subroutine
|
5
5
|
# RET {<Xn>}
|
6
|
-
class RET
|
6
|
+
class RET < Instruction
|
7
7
|
def initialize reg
|
8
|
-
@reg = reg
|
8
|
+
@reg = check_mask(reg, 0x1f)
|
9
9
|
end
|
10
10
|
|
11
11
|
def encode
|
12
|
-
RET(@reg
|
12
|
+
RET(@reg)
|
13
13
|
end
|
14
14
|
|
15
15
|
private
|
16
16
|
|
17
17
|
def RET rn
|
18
18
|
insn = 0b1101011_0_0_10_11111_0000_0_0_00000_00000
|
19
|
-
insn |= ((rn
|
19
|
+
insn |= ((rn) << 5)
|
20
20
|
insn
|
21
21
|
end
|
22
22
|
end
|
@@ -4,9 +4,9 @@ module AArch64
|
|
4
4
|
# Return from subroutine, with pointer authentication
|
5
5
|
# RETAA
|
6
6
|
# RETAB
|
7
|
-
class RETA
|
7
|
+
class RETA < Instruction
|
8
8
|
def initialize m
|
9
|
-
@m = m
|
9
|
+
@m = check_mask(m, 0x01)
|
10
10
|
end
|
11
11
|
|
12
12
|
def encode
|
@@ -17,7 +17,7 @@ module AArch64
|
|
17
17
|
|
18
18
|
def RETA m
|
19
19
|
insn = 0b1101011_0_0_10_11111_0000_1_0_11111_11111
|
20
|
-
insn |= ((m
|
20
|
+
insn |= ((m) << 10)
|
21
21
|
insn
|
22
22
|
end
|
23
23
|
end
|
@@ -4,26 +4,26 @@ module AArch64
|
|
4
4
|
# Reverse Bytes
|
5
5
|
# REV <Wd>, <Wn>
|
6
6
|
# REV <Xd>, <Xn>
|
7
|
-
class REV
|
7
|
+
class REV < Instruction
|
8
8
|
def initialize rd, rn, sf, opc
|
9
|
-
@rd = rd
|
10
|
-
@rn = rn
|
11
|
-
@sf = sf
|
12
|
-
@opc = opc
|
9
|
+
@rd = check_mask(rd, 0x1f)
|
10
|
+
@rn = check_mask(rn, 0x1f)
|
11
|
+
@sf = check_mask(sf, 0x01)
|
12
|
+
@opc = check_mask(opc, 0x03)
|
13
13
|
end
|
14
14
|
|
15
15
|
def encode
|
16
|
-
REV(@sf, @rn
|
16
|
+
REV(@sf, @rn, @rd, @opc)
|
17
17
|
end
|
18
18
|
|
19
19
|
private
|
20
20
|
|
21
21
|
def REV sf, rn, rd, opc
|
22
22
|
insn = 0b0_1_0_11010110_00000_0000_00_00000_00000
|
23
|
-
insn |= ((sf
|
24
|
-
insn |= ((opc
|
25
|
-
insn |= ((rn
|
26
|
-
insn |= (rd
|
23
|
+
insn |= ((sf) << 31)
|
24
|
+
insn |= ((opc) << 10)
|
25
|
+
insn |= ((rn) << 5)
|
26
|
+
insn |= (rd)
|
27
27
|
insn
|
28
28
|
end
|
29
29
|
end
|
@@ -3,24 +3,24 @@ module AArch64
|
|
3
3
|
# RMIF -- A64
|
4
4
|
# Rotate, Mask Insert Flags
|
5
5
|
# RMIF <Xn>, #<shift>, #<mask>
|
6
|
-
class RMIF
|
6
|
+
class RMIF < Instruction
|
7
7
|
def initialize rn, imm6, mask
|
8
|
-
@rn = rn
|
9
|
-
@imm6 = imm6
|
10
|
-
@mask = mask
|
8
|
+
@rn = check_mask(rn, 0x1f)
|
9
|
+
@imm6 = check_mask(imm6, 0x3f)
|
10
|
+
@mask = check_mask(mask, 0x0f)
|
11
11
|
end
|
12
12
|
|
13
13
|
def encode
|
14
|
-
RMIF(@imm6, @rn
|
14
|
+
RMIF(@imm6, @rn, @mask)
|
15
15
|
end
|
16
16
|
|
17
17
|
private
|
18
18
|
|
19
19
|
def RMIF imm6, rn, mask
|
20
20
|
insn = 0b1_0_1_11010000_000000_00001_00000_0_0000
|
21
|
-
insn |= ((imm6
|
22
|
-
insn |= ((rn
|
23
|
-
insn |= (mask
|
21
|
+
insn |= ((imm6) << 15)
|
22
|
+
insn |= ((rn) << 5)
|
23
|
+
insn |= (mask)
|
24
24
|
insn
|
25
25
|
end
|
26
26
|
end
|
@@ -4,26 +4,26 @@ module AArch64
|
|
4
4
|
# Rotate Right Variable
|
5
5
|
# RORV <Wd>, <Wn>, <Wm>
|
6
6
|
# RORV <Xd>, <Xn>, <Xm>
|
7
|
-
class RORV
|
7
|
+
class RORV < Instruction
|
8
8
|
def initialize rd, rn, rm, sf
|
9
|
-
@rd = rd
|
10
|
-
@rn = rn
|
11
|
-
@rm = rm
|
12
|
-
@sf = sf
|
9
|
+
@rd = check_mask(rd, 0x1f)
|
10
|
+
@rn = check_mask(rn, 0x1f)
|
11
|
+
@rm = check_mask(rm, 0x1f)
|
12
|
+
@sf = check_mask(sf, 0x01)
|
13
13
|
end
|
14
14
|
|
15
15
|
def encode
|
16
|
-
RORV(@sf, @rm
|
16
|
+
RORV(@sf, @rm, @rn, @rd)
|
17
17
|
end
|
18
18
|
|
19
19
|
private
|
20
20
|
|
21
21
|
def RORV sf, rm, rn, rd
|
22
22
|
insn = 0b0_0_0_11010110_00000_0010_11_00000_00000
|
23
|
-
insn |= ((sf
|
24
|
-
insn |= ((rm
|
25
|
-
insn |= ((rn
|
26
|
-
insn |= (rd
|
23
|
+
insn |= ((sf) << 31)
|
24
|
+
insn |= ((rm) << 16)
|
25
|
+
insn |= ((rn) << 5)
|
26
|
+
insn |= (rd)
|
27
27
|
insn
|
28
28
|
end
|
29
29
|
end
|
@@ -4,26 +4,26 @@ module AArch64
|
|
4
4
|
# Subtract with Carry
|
5
5
|
# SBC <Wd>, <Wn>, <Wm>
|
6
6
|
# SBC <Xd>, <Xn>, <Xm>
|
7
|
-
class SBC
|
7
|
+
class SBC < Instruction
|
8
8
|
def initialize rd, rn, rm, sf
|
9
|
-
@rd = rd
|
10
|
-
@rn = rn
|
11
|
-
@rm = rm
|
12
|
-
@sf = sf
|
9
|
+
@rd = check_mask(rd, 0x1f)
|
10
|
+
@rn = check_mask(rn, 0x1f)
|
11
|
+
@rm = check_mask(rm, 0x1f)
|
12
|
+
@sf = check_mask(sf, 0x01)
|
13
13
|
end
|
14
14
|
|
15
15
|
def encode
|
16
|
-
SBC(@sf, @rm
|
16
|
+
SBC(@sf, @rm, @rn, @rd)
|
17
17
|
end
|
18
18
|
|
19
19
|
private
|
20
20
|
|
21
21
|
def SBC sf, rm, rn, rd
|
22
22
|
insn = 0b0_1_0_11010000_00000_000000_00000_00000
|
23
|
-
insn |= ((sf
|
24
|
-
insn |= ((rm
|
25
|
-
insn |= ((rn
|
26
|
-
insn |= (rd
|
23
|
+
insn |= ((sf) << 31)
|
24
|
+
insn |= ((rm) << 16)
|
25
|
+
insn |= ((rn) << 5)
|
26
|
+
insn |= (rd)
|
27
27
|
insn
|
28
28
|
end
|
29
29
|
end
|
@@ -4,26 +4,26 @@ module AArch64
|
|
4
4
|
# Subtract with Carry, setting flags
|
5
5
|
# SBCS <Wd>, <Wn>, <Wm>
|
6
6
|
# SBCS <Xd>, <Xn>, <Xm>
|
7
|
-
class SBCS
|
7
|
+
class SBCS < Instruction
|
8
8
|
def initialize rd, rn, rm, sf
|
9
|
-
@rd = rd
|
10
|
-
@rn = rn
|
11
|
-
@rm = rm
|
12
|
-
@sf = sf
|
9
|
+
@rd = check_mask(rd, 0x1f)
|
10
|
+
@rn = check_mask(rn, 0x1f)
|
11
|
+
@rm = check_mask(rm, 0x1f)
|
12
|
+
@sf = check_mask(sf, 0x01)
|
13
13
|
end
|
14
14
|
|
15
15
|
def encode
|
16
|
-
SBCS(@sf, @rm
|
16
|
+
SBCS(@sf, @rm, @rn, @rd)
|
17
17
|
end
|
18
18
|
|
19
19
|
private
|
20
20
|
|
21
21
|
def SBCS sf, rm, rn, rd
|
22
22
|
insn = 0b0_1_1_11010000_00000_000000_00000_00000
|
23
|
-
insn |= ((sf
|
24
|
-
insn |= ((rm
|
25
|
-
insn |= ((rn
|
26
|
-
insn |= (rd
|
23
|
+
insn |= ((sf) << 31)
|
24
|
+
insn |= ((rm) << 16)
|
25
|
+
insn |= ((rn) << 5)
|
26
|
+
insn |= (rd)
|
27
27
|
insn
|
28
28
|
end
|
29
29
|
end
|
@@ -4,29 +4,29 @@ module AArch64
|
|
4
4
|
# Signed Bitfield Move
|
5
5
|
# SBFM <Wd>, <Wn>, #<immr>, #<imms>
|
6
6
|
# SBFM <Xd>, <Xn>, #<immr>, #<imms>
|
7
|
-
class SBFM
|
7
|
+
class SBFM < Instruction
|
8
8
|
def initialize d, n, immr, imms, sf
|
9
|
-
@
|
10
|
-
@
|
11
|
-
@immr = immr
|
12
|
-
@imms = imms
|
13
|
-
@sf = sf
|
9
|
+
@rd = check_mask(d, 0x1f)
|
10
|
+
@rn = check_mask(n, 0x1f)
|
11
|
+
@immr = check_mask(immr, 0x3f)
|
12
|
+
@imms = check_mask(imms, 0x3f)
|
13
|
+
@sf = check_mask(sf, 0x01)
|
14
14
|
end
|
15
15
|
|
16
16
|
def encode
|
17
|
-
SBFM(@sf, @sf, @immr, @imms, @
|
17
|
+
SBFM(@sf, @sf, @immr, @imms, @rn, @rd)
|
18
18
|
end
|
19
19
|
|
20
20
|
private
|
21
21
|
|
22
22
|
def SBFM sf, n, immr, imms, rn, rd
|
23
23
|
insn = 0b0_00_100110_0_000000_000000_00000_00000
|
24
|
-
insn |= ((sf
|
25
|
-
insn |= ((n
|
26
|
-
insn |= ((immr
|
27
|
-
insn |= ((imms
|
28
|
-
insn |= ((rn
|
29
|
-
insn |= (rd
|
24
|
+
insn |= ((sf) << 31)
|
25
|
+
insn |= ((n) << 22)
|
26
|
+
insn |= ((immr) << 16)
|
27
|
+
insn |= ((imms) << 10)
|
28
|
+
insn |= ((rn) << 5)
|
29
|
+
insn |= (rd)
|
30
30
|
insn
|
31
31
|
end
|
32
32
|
end
|
@@ -4,26 +4,26 @@ module AArch64
|
|
4
4
|
# Signed Divide
|
5
5
|
# SDIV <Wd>, <Wn>, <Wm>
|
6
6
|
# SDIV <Xd>, <Xn>, <Xm>
|
7
|
-
class SDIV
|
7
|
+
class SDIV < Instruction
|
8
8
|
def initialize rd, rn, rm, sf
|
9
|
-
@rd = rd
|
10
|
-
@rn = rn
|
11
|
-
@rm = rm
|
12
|
-
@sf = sf
|
9
|
+
@rd = check_mask(rd, 0x1f)
|
10
|
+
@rn = check_mask(rn, 0x1f)
|
11
|
+
@rm = check_mask(rm, 0x1f)
|
12
|
+
@sf = check_mask(sf, 0x01)
|
13
13
|
end
|
14
14
|
|
15
15
|
def encode
|
16
|
-
SDIV(@sf, @rm
|
16
|
+
SDIV(@sf, @rm, @rn, @rd)
|
17
17
|
end
|
18
18
|
|
19
19
|
private
|
20
20
|
|
21
21
|
def SDIV sf, rm, rn, rd
|
22
22
|
insn = 0b0_0_0_11010110_00000_00001_1_00000_00000
|
23
|
-
insn |= ((sf
|
24
|
-
insn |= ((rm
|
25
|
-
insn |= ((rn
|
26
|
-
insn |= (rd
|
23
|
+
insn |= ((sf) << 31)
|
24
|
+
insn |= ((rm) << 16)
|
25
|
+
insn |= ((rn) << 5)
|
26
|
+
insn |= (rd)
|
27
27
|
insn
|
28
28
|
end
|
29
29
|
end
|
@@ -4,22 +4,22 @@ module AArch64
|
|
4
4
|
# Evaluation of 8 or 16 bit flag values
|
5
5
|
# SETF8 <Wn>
|
6
6
|
# SETF16 <Wn>
|
7
|
-
class SETF
|
7
|
+
class SETF < Instruction
|
8
8
|
def initialize rn, sz
|
9
|
-
@rn = rn
|
10
|
-
@sz = sz
|
9
|
+
@rn = check_mask(rn, 0x1f)
|
10
|
+
@sz = check_mask(sz, 0x01)
|
11
11
|
end
|
12
12
|
|
13
13
|
def encode
|
14
|
-
SETF(@sz, @rn
|
14
|
+
SETF(@sz, @rn)
|
15
15
|
end
|
16
16
|
|
17
17
|
private
|
18
18
|
|
19
19
|
def SETF sz, rn
|
20
20
|
insn = 0b0_0_1_11010000_000000_0_0010_00000_0_1101
|
21
|
-
insn |= ((sz
|
22
|
-
insn |= ((rn
|
21
|
+
insn |= ((sz) << 14)
|
22
|
+
insn |= ((rn) << 5)
|
23
23
|
insn
|
24
24
|
end
|
25
25
|
end
|