aarch64 1.0.0

data/lib/aarch64/instructions/msr_reg.rb

@@ -0,0 +1,34 @@
+module AArch64
+  module Instructions
+    # MSR (register) -- A64
+    # Move general-purpose register to System Register
+    # MSR  (<systemreg>|S<op0>_<op1>_<Cn>_<Cm>_<op2>), <Xt>
+    class MSR_reg
+      def initialize o0, op1, crn, crm, op2, rt
+        @o0  = o0
+        @op1 = op1
+        @crn = crn
+        @crm = crm
+        @op2 = op2
+        @rt  = rt
+      end
+
+      def encode
+        self.MSR_reg(@o0, @op1, @crn, @crm, @op2, @rt.to_i)
+      end
+
+      private
+
+      def MSR_reg o0, op1, crn, crm, op2, rt
+        insn = 0b1101010100_0_1_0_000_0000_0000_000_00000
+        insn |= ((o0 & 0x1) << 19)
+        insn |= ((op1 & 0x7) << 16)
+        insn |= ((crn & 0xf) << 12)
+        insn |= ((crm & 0xf) << 8)
+        insn |= ((op2 & 0x7) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/msub.rb

@@ -0,0 +1,33 @@
+module AArch64
+  module Instructions
+    # MSUB -- A64
+    # Multiply-Subtract
+    # MSUB  <Wd>, <Wn>, <Wm>, <Wa>
+    # MSUB  <Xd>, <Xn>, <Xm>, <Xa>
+    class MSUB
+      def initialize rd, rn, rm, ra, sf
+        @rd = rd
+        @rn = rn
+        @rm = rm
+        @ra = ra
+        @sf = sf
+      end
+
+      def encode
+        self.MSUB(@sf, @rm.to_i, @ra.to_i, @rn.to_i, @rd.to_i)
+      end
+
+      private
+
+      def MSUB sf, rm, ra, rn, rd
+        insn = 0b0_00_11011_000_00000_1_00000_00000_00000
+        insn |= ((sf & 0x1) << 31)
+        insn |= ((rm & 0x1f) << 16)
+        insn |= ((ra & 0x1f) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/nop.rb

@@ -0,0 +1,19 @@
+module AArch64
+  module Instructions
+    # NOP -- A64
+    # No Operation
+    # NOP
+    class NOP
+      def encode
+        self.NOP
+      end
+
+      private
+
+      def NOP
+        insn = 0b1101010100_0_00_011_0010_0000_000_11111
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/orn_log_shift.rb

@@ -0,0 +1,35 @@
+module AArch64
+  module Instructions
+    # ORN (shifted register) -- A64
+    # Bitwise OR NOT (shifted register)
+    # ORN  <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
+    # ORN  <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
+    class ORN_log_shift
+      def initialize rd, rn, rm, shift, imm6, sf
+        @rd    = rd
+        @rn    = rn
+        @rm    = rm
+        @shift = shift
+        @imm6  = imm6
+        @sf    = sf
+      end
+
+      def encode
+        self.ORN_log_shift(@sf, @shift, @rm.to_i, @imm6, @rn.to_i, @rd.to_i)
+      end
+
+      private
+
+      def ORN_log_shift sf, shift, rm, imm6, rn, rd
+        insn = 0b0_01_01010_00_1_00000_000000_00000_00000
+        insn |= ((sf & 0x1) << 31)
+        insn |= ((shift & 0x3) << 22)
+        insn |= ((rm & 0x1f) << 16)
+        insn |= ((imm6 & 0x3f) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/orr_log_imm.rb

@@ -0,0 +1,35 @@
+module AArch64
+  module Instructions
+    # ORR (immediate) -- A64
+    # Bitwise OR (immediate)
+    # ORR  <Wd|WSP>, <Wn>, #<imm>
+    # ORR  <Xd|SP>, <Xn>, #<imm>
+    class ORR_log_imm
+      def initialize rd, rn, n, immr, imms, sf
+        @rd   = rd
+        @rn   = rn
+        @n    = n
+        @immr = immr
+        @imms = imms
+        @sf   = sf
+      end
+
+      def encode
+        self.ORR_log_imm(@sf, @n, @immr, @imms, @rn.to_i, @rd.to_i)
+      end
+
+      private
+
+      def ORR_log_imm sf, n, immr, imms, rn, rd
+        insn = 0b0_01_100100_0_000000_000000_00000_00000
+        insn |= ((sf & 0x1) << 31)
+        insn |= ((n & 0x1) << 22)
+        insn |= ((immr & 0x3f) << 16)
+        insn |= ((imms & 0x3f) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/orr_log_shift.rb

@@ -0,0 +1,35 @@
+module AArch64
+  module Instructions
+    # ORR (shifted register) -- A64
+    # Bitwise OR (shifted register)
+    # ORR  <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
+    # ORR  <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
+    class ORR_log_shift
+      def initialize rd, rn, rm, shift, imm6, sf
+        @rd    = rd
+        @rn    = rn
+        @rm    = rm
+        @shift = shift
+        @imm6  = imm6
+        @sf    = sf
+      end
+
+      def encode
+        self.ORR_log_shift(@sf, @shift, @rm.to_i, @imm6, @rn.to_i, @rd.to_i)
+      end
+
+      private
+
+      def ORR_log_shift sf, shift, rm, imm6, rn, rd
+        insn = 0b0_01_01010_00_0_00000_000000_00000_00000
+        insn |= ((sf & 0x1) << 31)
+        insn |= ((shift & 0x3) << 22)
+        insn |= ((rm & 0x1f) << 16)
+        insn |= ((imm6 & 0x3f) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/pacda.rb

@@ -0,0 +1,29 @@
+module AArch64
+  module Instructions
+    # PACDA, PACDZA -- A64
+    # Pointer Authentication Code for Data address, using key A
+    # PACDA  <Xd>, <Xn|SP>
+    # PACDZA  <Xd>
+    class PACDA
+      def initialize rd, rn, z
+        @rd = rd
+        @rn = rn
+        @z  = z
+      end
+
+      def encode
+        self.PACDA(@z, @rn.to_i, @rd.to_i)
+      end
+
+      private
+
+      def PACDA z, rn, rd
+        insn = 0b1_1_0_11010110_00001_0_0_0_010_00000_00000
+        insn |= ((z & 0x1) << 13)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/pacdb.rb

@@ -0,0 +1,29 @@
+module AArch64
+  module Instructions
+    # PACDB, PACDZB -- A64
+    # Pointer Authentication Code for Data address, using key B
+    # PACDB  <Xd>, <Xn|SP>
+    # PACDZB  <Xd>
+    class PACDB
+      def initialize rd, rn, z
+        @rd = rd
+        @rn = rn
+        @z  = z
+      end
+
+      def encode
+        self.PACDB(@z, @rn.to_i, @rd.to_i)
+      end
+
+      private
+
+      def PACDB z, rn, rd
+        insn = 0b1_1_0_11010110_00001_0_0_0_011_00000_00000
+        insn |= ((z & 0x1) << 13)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/pacga.rb

@@ -0,0 +1,28 @@
+module AArch64
+  module Instructions
+    # PACGA -- A64
+    # Pointer Authentication Code, using Generic key
+    # PACGA  <Xd>, <Xn>, <Xm|SP>
+    class PACGA
+      def initialize rd, rn, rm
+        @rd = rd
+        @rn = rn
+        @rm = rm
+      end
+
+      def encode
+        self.PACGA(@rm.to_i, @rn.to_i, @rd.to_i)
+      end
+
+      private
+
+      def PACGA rm, rn, rd
+        insn = 0b1_0_0_11010110_00000_001100_00000_00000
+        insn |= ((rm & 0x1f) << 16)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/pacia.rb

@@ -0,0 +1,32 @@
+module AArch64
+  module Instructions
+    # PACIA, PACIA1716, PACIASP, PACIAZ, PACIZA -- A64
+    # Pointer Authentication Code for Instruction address, using key A
+    # PACIA  <Xd>, <Xn|SP>
+    # PACIZA  <Xd>
+    # PACIA1716
+    # PACIASP
+    # PACIAZ
+    class PACIA
+      def initialize rd, rn, z
+        @rd = rd
+        @rn = rn
+        @z  = z
+      end
+
+      def encode
+        self.PACIA(@z, @rn.to_i, @rd.to_i)
+      end
+
+      private
+
+      def PACIA z, rn, rd
+        insn = 0b1_1_0_11010110_00001_0_0_0_000_00000_00000
+        insn |= ((z & 0x1) << 13)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/pacia2.rb

@@ -0,0 +1,28 @@
+module AArch64
+  module Instructions
+    # PACIA, PACIA1716, PACIASP, PACIAZ, PACIZA -- A64
+    # Pointer Authentication Code for Instruction address, using key A
+    # PACIA1716
+    # PACIASP
+    # PACIAZ
+    class PACIA2
+      def initialize crm, op2
+        @crm = crm
+        @op2 = op2
+      end
+
+      def encode
+        self.PACIA2(@crm, @op2)
+      end
+
+      private
+
+      def PACIA2 crm, op2
+        insn = 0b11010101000000110010_0000_000_11111
+        insn |= ((crm & 0xf) << 8)
+        insn |= ((op2 & 0x7) << 5)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/pacib.rb

@@ -0,0 +1,32 @@
+module AArch64
+  module Instructions
+    # PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZB -- A64
+    # Pointer Authentication Code for Instruction address, using key B
+    # PACIB  <Xd>, <Xn|SP>
+    # PACIZB  <Xd>
+    # PACIB1716
+    # PACIBSP
+    # PACIBZ
+    class PACIB
+      def initialize rd, rn, z
+        @rd = rd
+        @rn = rn
+        @z  = z
+      end
+
+      def encode
+        self.PACIB(@z, @rn.to_i, @rd.to_i)
+      end
+
+      private
+
+      def PACIB z, rn, rd
+        insn = 0b1_1_0_11010110_00001_0_0_0_001_00000_00000
+        insn |= ((z & 0x1) << 13)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/prfm_imm.rb

@@ -0,0 +1,28 @@
+module AArch64
+  module Instructions
+    # PRFM (immediate) -- A64
+    # Prefetch Memory (immediate)
+    # PRFM  (<prfop>|#<imm5>), [<Xn|SP>{, #<pimm>}]
+    class PRFM_imm
+      def initialize rt, rn, imm12
+        @rt    = rt
+        @rn    = rn
+        @imm12 = imm12
+      end
+
+      def encode
+        self.PRFM_imm(@imm12, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def PRFM_imm imm12, rn, rt
+        insn = 0b11_111_0_01_10_000000000000_00000_00000
+        insn |= ((imm12 & 0xfff) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/prfm_lit.rb

@@ -0,0 +1,26 @@
+module AArch64
+  module Instructions
+    # PRFM (literal) -- A64
+    # Prefetch Memory (literal)
+    # PRFM  (<prfop>|#<imm5>), <label>
+    class PRFM_lit
+      def initialize rt, imm19
+        @imm19 = imm19
+        @rt    = rt
+      end
+
+      def encode
+        self.PRFM_lit(@imm19.to_i / 4, @rt.to_i)
+      end
+
+      private
+
+      def PRFM_lit imm19, rt
+        insn = 0b11_011_0_00_0000000000000000000_00000
+        insn |= ((imm19 & 0x7ffff) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/prfm_reg.rb

@@ -0,0 +1,32 @@
+module AArch64
+  module Instructions
+    # PRFM (register) -- A64
+    # Prefetch Memory (register)
+    # PRFM  (<prfop>|#<imm5>), [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
+    class PRFM_reg
+      def initialize rt, rn, rm, option, s
+        @rt     = rt
+        @rn     = rn
+        @rm     = rm
+        @option = option
+        @s      = s
+      end
+
+      def encode
+        self.PRFM_reg(@rm.to_i, @option, @s, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def PRFM_reg rm, option, s, rn, rt
+        insn = 0b11_111_0_00_10_1_00000_000_0_10_00000_00000
+        insn |= ((rm & 0x1f) << 16)
+        insn |= ((option & 0x7) << 13)
+        insn |= ((s & 0x1) << 12)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/prfum.rb

@@ -0,0 +1,28 @@
+module AArch64
+  module Instructions
+    # PRFUM -- A64
+    # Prefetch Memory (unscaled offset)
+    # PRFUM (<prfop>|#<imm5>), [<Xn|SP>{, #<simm>}]
+    class PRFUM
+      def initialize rt, rn, imm9
+        @rt   = rt
+        @rn   = rn
+        @imm9 = imm9
+      end
+
+      def encode
+        self.PRFUM(@imm9, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def PRFUM imm9, rn, rt
+        insn = 0b11_111_0_00_10_0_000000000_00_00000_00000
+        insn |= ((imm9 & 0x1ff) << 12)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/psb.rb

@@ -0,0 +1,19 @@
+module AArch64
+  module Instructions
+    # PSB CSYNC -- A64
+    # Profiling Synchronization Barrier
+    # PSB CSYNC
+    class PSB
+      def encode
+        self.PSB
+      end
+
+      private
+
+      def PSB
+        insn = 0b1101010100_0_00_011_0010_0010_001_11111
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/rbit_int.rb

@@ -0,0 +1,29 @@
+module AArch64
+  module Instructions
+    # RBIT -- A64
+    # Reverse Bits
+    # RBIT  <Wd>, <Wn>
+    # RBIT  <Xd>, <Xn>
+    class RBIT_int
+      def initialize rd, rn, sf
+        @rd = rd
+        @rn = rn
+        @sf = sf
+      end
+
+      def encode
+        self.RBIT_int(@sf, @rn.to_i, @rd.to_i)
+      end
+
+      private
+
+      def RBIT_int sf, rn, rd
+        insn = 0b0_1_0_11010110_00000_0000_00_00000_00000
+        insn |= ((sf & 0x1) << 31)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/ret.rb

@@ -0,0 +1,24 @@
+module AArch64
+  module Instructions
+    # RET -- A64
+    # Return from subroutine
+    # RET  {<Xn>}
+    class RET
+      def initialize reg
+        @reg = reg
+      end
+
+      def encode
+        RET(@reg.to_i)
+      end
+
+      private
+
+      def RET rn
+        insn = 0b1101011_0_0_10_11111_0000_0_0_00000_00000
+        insn |= ((rn & 0x1f) << 5)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/reta.rb

@@ -0,0 +1,25 @@
+module AArch64
+  module Instructions
+    # RETAA, RETAB -- A64
+    # Return from subroutine, with pointer authentication
+    # RETAA
+    # RETAB
+    class RETA
+      def initialize m
+        @m = m
+      end
+
+      def encode
+        self.RETA(@m)
+      end
+
+      private
+
+      def RETA m
+        insn = 0b1101011_0_0_10_11111_0000_1_0_11111_11111
+        insn |= ((m & 0x1) << 10)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/rev.rb

@@ -0,0 +1,31 @@
+module AArch64
+  module Instructions
+    # REV -- A64
+    # Reverse Bytes
+    # REV  <Wd>, <Wn>
+    # REV  <Xd>, <Xn>
+    class REV
+      def initialize rd, rn, sf, opc
+        @rd  = rd
+        @rn  = rn
+        @sf  = sf
+        @opc = opc
+      end
+
+      def encode
+        self.REV(@sf, @rn.to_i, @rd.to_i, @opc)
+      end
+
+      private
+
+      def REV sf, rn, rd, opc
+        insn = 0b0_1_0_11010110_00000_0000_00_00000_00000
+        insn |= ((sf & 0x1) << 31)
+        insn |= ((opc & 0x3) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/rmif.rb

@@ -0,0 +1,28 @@
+module AArch64
+  module Instructions
+    # RMIF -- A64
+    # Rotate, Mask Insert Flags
+    # RMIF  <Xn>, #<shift>, #<mask>
+    class RMIF
+      def initialize rn, imm6, mask
+        @rn   = rn
+        @imm6 = imm6
+        @mask = mask
+      end
+
+      def encode
+        self.RMIF(@imm6, @rn.to_i, @mask)
+      end
+
+      private
+
+      def RMIF imm6, rn, mask
+        insn = 0b1_0_1_11010000_000000_00001_00000_0_0000
+        insn |= ((imm6 & 0x3f) << 15)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (mask & 0xf)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/rorv.rb

@@ -0,0 +1,31 @@
+module AArch64
+  module Instructions
+    # RORV -- A64
+    # Rotate Right Variable
+    # RORV  <Wd>, <Wn>, <Wm>
+    # RORV  <Xd>, <Xn>, <Xm>
+    class RORV
+      def initialize rd, rn, rm, sf
+        @rd = rd
+        @rn = rn
+        @rm = rm
+        @sf = sf
+      end
+
+      def encode
+        self.RORV(@sf, @rm.to_i, @rn.to_i, @rd.to_i)
+      end
+
+      private
+
+      def RORV sf, rm, rn, rd
+        insn = 0b0_0_0_11010110_00000_0010_11_00000_00000
+        insn |= ((sf & 0x1) << 31)
+        insn |= ((rm & 0x1f) << 16)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end