aarch64 1.0.0

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Files changed (281) hide show
  1. checksums.yaml +7 -0
  2. data/CODE_OF_CONDUCT.md +77 -0
  3. data/Gemfile +3 -0
  4. data/LICENSE +201 -0
  5. data/README.md +77 -0
  6. data/Rakefile +168 -0
  7. data/aarch64.gemspec +21 -0
  8. data/bin/build_instructions.rb +102 -0
  9. data/lib/aarch64/instructions/adc.rb +31 -0
  10. data/lib/aarch64/instructions/adcs.rb +30 -0
  11. data/lib/aarch64/instructions/add_addsub_ext.rb +35 -0
  12. data/lib/aarch64/instructions/add_addsub_imm.rb +32 -0
  13. data/lib/aarch64/instructions/add_addsub_shift.rb +35 -0
  14. data/lib/aarch64/instructions/addg.rb +30 -0
  15. data/lib/aarch64/instructions/adds_addsub_ext.rb +35 -0
  16. data/lib/aarch64/instructions/adds_addsub_imm.rb +33 -0
  17. data/lib/aarch64/instructions/adds_addsub_shift.rb +35 -0
  18. data/lib/aarch64/instructions/adr.rb +28 -0
  19. data/lib/aarch64/instructions/adrp.rb +28 -0
  20. data/lib/aarch64/instructions/and_log_imm.rb +35 -0
  21. data/lib/aarch64/instructions/and_log_shift.rb +35 -0
  22. data/lib/aarch64/instructions/ands_log_imm.rb +35 -0
  23. data/lib/aarch64/instructions/ands_log_shift.rb +35 -0
  24. data/lib/aarch64/instructions/asrv.rb +31 -0
  25. data/lib/aarch64/instructions/autda.rb +32 -0
  26. data/lib/aarch64/instructions/autdb.rb +32 -0
  27. data/lib/aarch64/instructions/autia.rb +35 -0
  28. data/lib/aarch64/instructions/autib.rb +35 -0
  29. data/lib/aarch64/instructions/axflag.rb +18 -0
  30. data/lib/aarch64/instructions/b_cond.rb +26 -0
  31. data/lib/aarch64/instructions/b_uncond.rb +24 -0
  32. data/lib/aarch64/instructions/bc_cond.rb +26 -0
  33. data/lib/aarch64/instructions/bfm.rb +34 -0
  34. data/lib/aarch64/instructions/bic_log_shift.rb +35 -0
  35. data/lib/aarch64/instructions/bics.rb +35 -0
  36. data/lib/aarch64/instructions/bl.rb +24 -0
  37. data/lib/aarch64/instructions/blr.rb +24 -0
  38. data/lib/aarch64/instructions/blra.rb +33 -0
  39. data/lib/aarch64/instructions/br.rb +24 -0
  40. data/lib/aarch64/instructions/bra.rb +33 -0
  41. data/lib/aarch64/instructions/brk.rb +24 -0
  42. data/lib/aarch64/instructions/bti.rb +24 -0
  43. data/lib/aarch64/instructions/cas.rb +41 -0
  44. data/lib/aarch64/instructions/casb.rb +35 -0
  45. data/lib/aarch64/instructions/cash.rb +35 -0
  46. data/lib/aarch64/instructions/casp.rb +41 -0
  47. data/lib/aarch64/instructions/cbnz.rb +29 -0
  48. data/lib/aarch64/instructions/cbz.rb +29 -0
  49. data/lib/aarch64/instructions/ccmn_imm.rb +33 -0
  50. data/lib/aarch64/instructions/ccmn_reg.rb +33 -0
  51. data/lib/aarch64/instructions/ccmp_imm.rb +33 -0
  52. data/lib/aarch64/instructions/ccmp_reg.rb +33 -0
  53. data/lib/aarch64/instructions/cfinv.rb +19 -0
  54. data/lib/aarch64/instructions/clrex.rb +24 -0
  55. data/lib/aarch64/instructions/cls_int.rb +29 -0
  56. data/lib/aarch64/instructions/clz_int.rb +29 -0
  57. data/lib/aarch64/instructions/crc32.rb +35 -0
  58. data/lib/aarch64/instructions/crc32c.rb +35 -0
  59. data/lib/aarch64/instructions/csdb.rb +19 -0
  60. data/lib/aarch64/instructions/csel.rb +33 -0
  61. data/lib/aarch64/instructions/csinc.rb +33 -0
  62. data/lib/aarch64/instructions/csinv.rb +33 -0
  63. data/lib/aarch64/instructions/csneg.rb +33 -0
  64. data/lib/aarch64/instructions/dcps.rb +26 -0
  65. data/lib/aarch64/instructions/dgh.rb +19 -0
  66. data/lib/aarch64/instructions/dmb.rb +24 -0
  67. data/lib/aarch64/instructions/drps.rb +19 -0
  68. data/lib/aarch64/instructions/dsb.rb +25 -0
  69. data/lib/aarch64/instructions/eon.rb +35 -0
  70. data/lib/aarch64/instructions/eor_log_imm.rb +35 -0
  71. data/lib/aarch64/instructions/eor_log_shift.rb +35 -0
  72. data/lib/aarch64/instructions/eret.rb +19 -0
  73. data/lib/aarch64/instructions/ereta.rb +25 -0
  74. data/lib/aarch64/instructions/esb.rb +19 -0
  75. data/lib/aarch64/instructions/extr.rb +34 -0
  76. data/lib/aarch64/instructions/gmi.rb +28 -0
  77. data/lib/aarch64/instructions/hint.rb +26 -0
  78. data/lib/aarch64/instructions/hlt.rb +24 -0
  79. data/lib/aarch64/instructions/hvc.rb +24 -0
  80. data/lib/aarch64/instructions/irg.rb +28 -0
  81. data/lib/aarch64/instructions/isb.rb +24 -0
  82. data/lib/aarch64/instructions/ld64b.rb +26 -0
  83. data/lib/aarch64/instructions/ldadd.rb +41 -0
  84. data/lib/aarch64/instructions/ldaddb.rb +35 -0
  85. data/lib/aarch64/instructions/ldaddh.rb +35 -0
  86. data/lib/aarch64/instructions/ldapr.rb +29 -0
  87. data/lib/aarch64/instructions/ldaprb.rb +26 -0
  88. data/lib/aarch64/instructions/ldaprh.rb +26 -0
  89. data/lib/aarch64/instructions/ldapur_gen.rb +33 -0
  90. data/lib/aarch64/instructions/ldar.rb +29 -0
  91. data/lib/aarch64/instructions/ldaxp.rb +31 -0
  92. data/lib/aarch64/instructions/ldaxr.rb +29 -0
  93. data/lib/aarch64/instructions/ldclr.rb +41 -0
  94. data/lib/aarch64/instructions/ldclrb.rb +37 -0
  95. data/lib/aarch64/instructions/ldeor.rb +41 -0
  96. data/lib/aarch64/instructions/ldg.rb +28 -0
  97. data/lib/aarch64/instructions/ldgm.rb +26 -0
  98. data/lib/aarch64/instructions/ldlar.rb +29 -0
  99. data/lib/aarch64/instructions/ldnp_gen.rb +33 -0
  100. data/lib/aarch64/instructions/ldp_gen.rb +39 -0
  101. data/lib/aarch64/instructions/ldpsw.rb +34 -0
  102. data/lib/aarch64/instructions/ldr_imm_gen.rb +35 -0
  103. data/lib/aarch64/instructions/ldr_imm_unsigned.rb +31 -0
  104. data/lib/aarch64/instructions/ldr_lit_gen.rb +29 -0
  105. data/lib/aarch64/instructions/ldr_reg_gen.rb +35 -0
  106. data/lib/aarch64/instructions/ldra.rb +37 -0
  107. data/lib/aarch64/instructions/ldrb_imm.rb +32 -0
  108. data/lib/aarch64/instructions/ldrb_reg.rb +33 -0
  109. data/lib/aarch64/instructions/ldrb_unsigned.rb +28 -0
  110. data/lib/aarch64/instructions/ldrh_imm.rb +32 -0
  111. data/lib/aarch64/instructions/ldrh_reg.rb +32 -0
  112. data/lib/aarch64/instructions/ldrh_unsigned.rb +28 -0
  113. data/lib/aarch64/instructions/ldrsb_imm.rb +37 -0
  114. data/lib/aarch64/instructions/ldrsb_reg.rb +37 -0
  115. data/lib/aarch64/instructions/ldrsb_unsigned.rb +35 -0
  116. data/lib/aarch64/instructions/ldrsh_imm.rb +37 -0
  117. data/lib/aarch64/instructions/ldrsh_reg.rb +35 -0
  118. data/lib/aarch64/instructions/ldrsh_unsigned.rb +31 -0
  119. data/lib/aarch64/instructions/ldrsw_imm.rb +32 -0
  120. data/lib/aarch64/instructions/ldrsw_lit.rb +26 -0
  121. data/lib/aarch64/instructions/ldrsw_reg.rb +32 -0
  122. data/lib/aarch64/instructions/ldrsw_unsigned.rb +30 -0
  123. data/lib/aarch64/instructions/ldset.rb +41 -0
  124. data/lib/aarch64/instructions/ldsetb.rb +35 -0
  125. data/lib/aarch64/instructions/ldseth.rb +35 -0
  126. data/lib/aarch64/instructions/ldsmax.rb +41 -0
  127. data/lib/aarch64/instructions/ldsmaxb.rb +35 -0
  128. data/lib/aarch64/instructions/ldsmaxh.rb +35 -0
  129. data/lib/aarch64/instructions/ldsmin.rb +41 -0
  130. data/lib/aarch64/instructions/ldsminb.rb +35 -0
  131. data/lib/aarch64/instructions/ldsminh.rb +35 -0
  132. data/lib/aarch64/instructions/ldtr.rb +31 -0
  133. data/lib/aarch64/instructions/ldtrb.rb +28 -0
  134. data/lib/aarch64/instructions/ldtrh.rb +28 -0
  135. data/lib/aarch64/instructions/ldtrsb.rb +31 -0
  136. data/lib/aarch64/instructions/ldtrsh.rb +31 -0
  137. data/lib/aarch64/instructions/ldtrsw.rb +28 -0
  138. data/lib/aarch64/instructions/ldumax.rb +41 -0
  139. data/lib/aarch64/instructions/ldumaxb.rb +35 -0
  140. data/lib/aarch64/instructions/ldumaxh.rb +35 -0
  141. data/lib/aarch64/instructions/ldumin.rb +41 -0
  142. data/lib/aarch64/instructions/lduminb.rb +35 -0
  143. data/lib/aarch64/instructions/lduminh.rb +35 -0
  144. data/lib/aarch64/instructions/ldur_gen.rb +31 -0
  145. data/lib/aarch64/instructions/ldursb.rb +31 -0
  146. data/lib/aarch64/instructions/ldursh.rb +31 -0
  147. data/lib/aarch64/instructions/ldursw.rb +28 -0
  148. data/lib/aarch64/instructions/ldxp.rb +31 -0
  149. data/lib/aarch64/instructions/ldxr.rb +29 -0
  150. data/lib/aarch64/instructions/lslv.rb +31 -0
  151. data/lib/aarch64/instructions/lsrv.rb +31 -0
  152. data/lib/aarch64/instructions/madd.rb +33 -0
  153. data/lib/aarch64/instructions/movk.rb +31 -0
  154. data/lib/aarch64/instructions/movn.rb +31 -0
  155. data/lib/aarch64/instructions/movz.rb +31 -0
  156. data/lib/aarch64/instructions/mrs.rb +34 -0
  157. data/lib/aarch64/instructions/msr_imm.rb +28 -0
  158. data/lib/aarch64/instructions/msr_reg.rb +34 -0
  159. data/lib/aarch64/instructions/msub.rb +33 -0
  160. data/lib/aarch64/instructions/nop.rb +19 -0
  161. data/lib/aarch64/instructions/orn_log_shift.rb +35 -0
  162. data/lib/aarch64/instructions/orr_log_imm.rb +35 -0
  163. data/lib/aarch64/instructions/orr_log_shift.rb +35 -0
  164. data/lib/aarch64/instructions/pacda.rb +29 -0
  165. data/lib/aarch64/instructions/pacdb.rb +29 -0
  166. data/lib/aarch64/instructions/pacga.rb +28 -0
  167. data/lib/aarch64/instructions/pacia.rb +32 -0
  168. data/lib/aarch64/instructions/pacia2.rb +28 -0
  169. data/lib/aarch64/instructions/pacib.rb +32 -0
  170. data/lib/aarch64/instructions/prfm_imm.rb +28 -0
  171. data/lib/aarch64/instructions/prfm_lit.rb +26 -0
  172. data/lib/aarch64/instructions/prfm_reg.rb +32 -0
  173. data/lib/aarch64/instructions/prfum.rb +28 -0
  174. data/lib/aarch64/instructions/psb.rb +19 -0
  175. data/lib/aarch64/instructions/rbit_int.rb +29 -0
  176. data/lib/aarch64/instructions/ret.rb +24 -0
  177. data/lib/aarch64/instructions/reta.rb +25 -0
  178. data/lib/aarch64/instructions/rev.rb +31 -0
  179. data/lib/aarch64/instructions/rmif.rb +28 -0
  180. data/lib/aarch64/instructions/rorv.rb +31 -0
  181. data/lib/aarch64/instructions/sb.rb +19 -0
  182. data/lib/aarch64/instructions/sbc.rb +31 -0
  183. data/lib/aarch64/instructions/sbcs.rb +31 -0
  184. data/lib/aarch64/instructions/sbfm.rb +34 -0
  185. data/lib/aarch64/instructions/sdiv.rb +31 -0
  186. data/lib/aarch64/instructions/setf.rb +27 -0
  187. data/lib/aarch64/instructions/setgp.rb +25 -0
  188. data/lib/aarch64/instructions/setgpn.rb +25 -0
  189. data/lib/aarch64/instructions/setgpt.rb +25 -0
  190. data/lib/aarch64/instructions/setgptn.rb +25 -0
  191. data/lib/aarch64/instructions/setp.rb +25 -0
  192. data/lib/aarch64/instructions/setpn.rb +25 -0
  193. data/lib/aarch64/instructions/setpt.rb +25 -0
  194. data/lib/aarch64/instructions/setptn.rb +25 -0
  195. data/lib/aarch64/instructions/sev.rb +18 -0
  196. data/lib/aarch64/instructions/sevl.rb +18 -0
  197. data/lib/aarch64/instructions/smaddl.rb +30 -0
  198. data/lib/aarch64/instructions/smc.rb +24 -0
  199. data/lib/aarch64/instructions/smsubl.rb +30 -0
  200. data/lib/aarch64/instructions/smulh.rb +28 -0
  201. data/lib/aarch64/instructions/st2g.rb +32 -0
  202. data/lib/aarch64/instructions/st64b.rb +26 -0
  203. data/lib/aarch64/instructions/st64bv.rb +28 -0
  204. data/lib/aarch64/instructions/st64bv0.rb +28 -0
  205. data/lib/aarch64/instructions/stg.rb +32 -0
  206. data/lib/aarch64/instructions/stgm.rb +26 -0
  207. data/lib/aarch64/instructions/stgp.rb +34 -0
  208. data/lib/aarch64/instructions/stllr.rb +29 -0
  209. data/lib/aarch64/instructions/stllrb.rb +26 -0
  210. data/lib/aarch64/instructions/stllrh.rb +26 -0
  211. data/lib/aarch64/instructions/stlr.rb +29 -0
  212. data/lib/aarch64/instructions/stlrb.rb +26 -0
  213. data/lib/aarch64/instructions/stlrh.rb +26 -0
  214. data/lib/aarch64/instructions/stlur_gen.rb +31 -0
  215. data/lib/aarch64/instructions/stlxp.rb +33 -0
  216. data/lib/aarch64/instructions/stlxr.rb +31 -0
  217. data/lib/aarch64/instructions/stlxrb.rb +28 -0
  218. data/lib/aarch64/instructions/stlxrh.rb +28 -0
  219. data/lib/aarch64/instructions/stnp_gen.rb +33 -0
  220. data/lib/aarch64/instructions/stp_gen.rb +39 -0
  221. data/lib/aarch64/instructions/str_imm_gen.rb +37 -0
  222. data/lib/aarch64/instructions/str_imm_unsigned.rb +31 -0
  223. data/lib/aarch64/instructions/str_reg_gen.rb +35 -0
  224. data/lib/aarch64/instructions/strb_imm.rb +32 -0
  225. data/lib/aarch64/instructions/strb_imm_unsigned.rb +28 -0
  226. data/lib/aarch64/instructions/strb_reg.rb +33 -0
  227. data/lib/aarch64/instructions/strh_imm.rb +32 -0
  228. data/lib/aarch64/instructions/strh_imm_unsigned.rb +28 -0
  229. data/lib/aarch64/instructions/strh_reg.rb +32 -0
  230. data/lib/aarch64/instructions/sttr.rb +31 -0
  231. data/lib/aarch64/instructions/stur_gen.rb +31 -0
  232. data/lib/aarch64/instructions/stxp.rb +33 -0
  233. data/lib/aarch64/instructions/stxr.rb +31 -0
  234. data/lib/aarch64/instructions/stxrb.rb +28 -0
  235. data/lib/aarch64/instructions/stxrh.rb +28 -0
  236. data/lib/aarch64/instructions/stz2g.rb +32 -0
  237. data/lib/aarch64/instructions/stzg.rb +32 -0
  238. data/lib/aarch64/instructions/stzgm.rb +26 -0
  239. data/lib/aarch64/instructions/sub_addsub_ext.rb +35 -0
  240. data/lib/aarch64/instructions/sub_addsub_imm.rb +33 -0
  241. data/lib/aarch64/instructions/sub_addsub_shift.rb +35 -0
  242. data/lib/aarch64/instructions/subg.rb +30 -0
  243. data/lib/aarch64/instructions/subp.rb +28 -0
  244. data/lib/aarch64/instructions/subps.rb +28 -0
  245. data/lib/aarch64/instructions/subs_addsub_ext.rb +35 -0
  246. data/lib/aarch64/instructions/subs_addsub_imm.rb +33 -0
  247. data/lib/aarch64/instructions/subs_addsub_shift.rb +35 -0
  248. data/lib/aarch64/instructions/svc.rb +24 -0
  249. data/lib/aarch64/instructions/swp.rb +41 -0
  250. data/lib/aarch64/instructions/swpb.rb +35 -0
  251. data/lib/aarch64/instructions/swph.rb +35 -0
  252. data/lib/aarch64/instructions/sys.rb +32 -0
  253. data/lib/aarch64/instructions/sysl.rb +32 -0
  254. data/lib/aarch64/instructions/tbnz.rb +30 -0
  255. data/lib/aarch64/instructions/tbz.rb +30 -0
  256. data/lib/aarch64/instructions/tsb.rb +18 -0
  257. data/lib/aarch64/instructions/ubfm.rb +34 -0
  258. data/lib/aarch64/instructions/udf_perm_undef.rb +24 -0
  259. data/lib/aarch64/instructions/udiv.rb +31 -0
  260. data/lib/aarch64/instructions/umaddl.rb +30 -0
  261. data/lib/aarch64/instructions/umsubl.rb +30 -0
  262. data/lib/aarch64/instructions/umulh.rb +28 -0
  263. data/lib/aarch64/instructions/wfe.rb +19 -0
  264. data/lib/aarch64/instructions/wfet.rb +24 -0
  265. data/lib/aarch64/instructions/wfi.rb +19 -0
  266. data/lib/aarch64/instructions/wfit.rb +24 -0
  267. data/lib/aarch64/instructions/xaflag.rb +19 -0
  268. data/lib/aarch64/instructions/xpac.rb +28 -0
  269. data/lib/aarch64/instructions/xpaclri.rb +18 -0
  270. data/lib/aarch64/instructions/yield.rb +19 -0
  271. data/lib/aarch64/instructions.rb +266 -0
  272. data/lib/aarch64/system_registers/mrs_msr_64.rb +395 -0
  273. data/lib/aarch64/utils.rb +325 -0
  274. data/lib/aarch64/version.rb +3 -0
  275. data/lib/aarch64.rb +2857 -0
  276. data/test/all_adds_test.rb +129 -0
  277. data/test/base_instructions_test.rb +9263 -0
  278. data/test/dsl_test.rb +11 -0
  279. data/test/helper.rb +51 -0
  280. data/test/not_supported_yet_test.rb +55 -0
  281. metadata +382 -0
@@ -0,0 +1,29 @@
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+ module AArch64
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+ module Instructions
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+ # LDLAR -- A64
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+ # Load LOAcquire Register
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+ # LDLAR <Wt>, [<Xn|SP>{,#0}]
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+ # LDLAR <Xt>, [<Xn|SP>{,#0}]
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+ class LDLAR
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+ def initialize rt, rn, size
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+ @rt = rt
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+ @rn = rn
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+ @size = size
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+ end
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+
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+ def encode
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+ self.LDLAR(@size, @rn.to_i, @rt.to_i)
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+ end
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+
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+ private
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+
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+ def LDLAR size, rn, rt
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+ insn = 0b00_001000_1_1_0_11111_0_11111_00000_00000
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+ insn |= ((size & 0x3) << 30)
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+ insn |= ((rn & 0x1f) << 5)
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+ insn |= (rt & 0x1f)
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+ insn
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+ end
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+ end
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+ end
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+ end
@@ -0,0 +1,33 @@
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+ module AArch64
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+ module Instructions
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+ # LDNP -- A64
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+ # Load Pair of Registers, with non-temporal hint
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+ # LDNP <Wt1>, <Wt2>, [<Xn|SP>{, #<imm>}]
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+ # LDNP <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]
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+ class LDNP_gen
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+ def initialize rt1, rt2, rn, imm, opc
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+ @rt1 = rt1
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+ @rt2 = rt2
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+ @rn = rn
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+ @imm = imm
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+ @opc = opc
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+ end
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+
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+ def encode
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+ self.LDNP_gen(@opc, @imm, @rt2.to_i, @rn.to_i, @rt1.to_i)
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+ end
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+
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+ private
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+
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+ def LDNP_gen opc, imm7, rt2, rn, rt
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+ insn = 0b00_101_0_000_1_0000000_00000_00000_00000
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+ insn |= ((opc & 0x3) << 30)
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+ insn |= ((imm7 & 0x7f) << 15)
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+ insn |= ((rt2 & 0x1f) << 10)
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+ insn |= ((rn & 0x1f) << 5)
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+ insn |= (rt & 0x1f)
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+ insn
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+ end
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+ end
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+ end
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+ end
@@ -0,0 +1,39 @@
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+ module AArch64
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+ module Instructions
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+ # LDP -- A64
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+ # Load Pair of Registers
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+ # LDP <Wt1>, <Wt2>, [<Xn|SP>], #<imm>
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+ # LDP <Xt1>, <Xt2>, [<Xn|SP>], #<imm>
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+ # LDP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]!
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+ # LDP <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]!
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+ # LDP <Wt1>, <Wt2>, [<Xn|SP>{, #<imm>}]
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+ # LDP <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]
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+ class LDP_gen
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+ def initialize rt, rt2, rn, imm7, mode, opc
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+ @rt = rt
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+ @rt2 = rt2
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+ @rn = rn
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+ @imm7 = imm7
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+ @mode = mode
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+ @opc = opc
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+ end
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+
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+ def encode
22
+ self.LDP_gen(@opc, @mode, @imm7, @rt2.to_i, @rn.to_i, @rt.to_i)
23
+ end
24
+
25
+ private
26
+
27
+ def LDP_gen opc, mode, imm7, rt2, rn, rt
28
+ insn = 0b00_101_0_000_1_0000000_00000_00000_00000
29
+ insn |= ((opc & 0x3) << 30)
30
+ insn |= ((mode & 0x7) << 23)
31
+ insn |= ((imm7 & 0x7f) << 15)
32
+ insn |= ((rt2 & 0x1f) << 10)
33
+ insn |= ((rn & 0x1f) << 5)
34
+ insn |= (rt & 0x1f)
35
+ insn
36
+ end
37
+ end
38
+ end
39
+ end
@@ -0,0 +1,34 @@
1
+ module AArch64
2
+ module Instructions
3
+ # LDPSW -- A64
4
+ # Load Pair of Registers Signed Word
5
+ # LDPSW <Xt1>, <Xt2>, [<Xn|SP>], #<imm>
6
+ # LDPSW <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]!
7
+ # LDPSW <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]
8
+ class LDPSW
9
+ def initialize rt, rt2, rn, imm7, mode
10
+ @rt = rt
11
+ @rt2 = rt2
12
+ @rn = rn
13
+ @imm7 = imm7
14
+ @mode = mode
15
+ end
16
+
17
+ def encode
18
+ self.LDPSW(@mode, @imm7, @rt2.to_i, @rn.to_i, @rt.to_i)
19
+ end
20
+
21
+ private
22
+
23
+ def LDPSW mode, imm7, rt2, rn, rt
24
+ insn = 0b01_101_0_000_1_0000000_00000_00000_00000
25
+ insn |= ((mode & 0x7) << 23)
26
+ insn |= ((imm7 & 0x7f) << 15)
27
+ insn |= ((rt2 & 0x1f) << 10)
28
+ insn |= ((rn & 0x1f) << 5)
29
+ insn |= (rt & 0x1f)
30
+ insn
31
+ end
32
+ end
33
+ end
34
+ end
@@ -0,0 +1,35 @@
1
+ module AArch64
2
+ module Instructions
3
+ # LDR (immediate) -- A64
4
+ # Load Register (immediate)
5
+ # LDR <Wt>, [<Xn|SP>], #<simm>
6
+ # LDR <Xt>, [<Xn|SP>], #<simm>
7
+ # LDR <Wt>, [<Xn|SP>, #<simm>]!
8
+ # LDR <Xt>, [<Xn|SP>, #<simm>]!
9
+ class LDR_imm_gen
10
+ def initialize rt, rn, imm9, size, mode
11
+ @rt = rt
12
+ @rn = rn
13
+ @imm9 = imm9
14
+ @size = size
15
+ @mode = mode
16
+ end
17
+
18
+ def encode
19
+ self.LDR_imm_gen(@size, @imm9, @mode, @rn.to_i, @rt.to_i)
20
+ end
21
+
22
+ private
23
+
24
+ def LDR_imm_gen size, imm9, mode, rn, rt
25
+ insn = 0b00_111_0_00_01_0_000000000_00_00000_00000
26
+ insn |= ((size & 0x3) << 30)
27
+ insn |= ((imm9 & 0x1ff) << 12)
28
+ insn |= ((mode & 0x3) << 10)
29
+ insn |= ((rn & 0x1f) << 5)
30
+ insn |= (rt & 0x1f)
31
+ insn
32
+ end
33
+ end
34
+ end
35
+ end
@@ -0,0 +1,31 @@
1
+ module AArch64
2
+ module Instructions
3
+ # LDR (immediate) -- A64
4
+ # Load Register (immediate)
5
+ # LDR <Wt>, [<Xn|SP>{, #<pimm>}]
6
+ # LDR <Xt>, [<Xn|SP>{, #<pimm>}]
7
+ class LDR_imm_unsigned
8
+ def initialize rt, rn, imm12, size
9
+ @rt = rt
10
+ @rn = rn
11
+ @imm12 = imm12
12
+ @size = size
13
+ end
14
+
15
+ def encode
16
+ self.LDR_imm_gen(@size, @imm12, @rn.to_i, @rt.to_i)
17
+ end
18
+
19
+ private
20
+
21
+ def LDR_imm_gen size, imm12, rn, rt
22
+ insn = 0b00_111_0_01_01_000000000000_00000_00000
23
+ insn |= ((size & 0x3) << 30)
24
+ insn |= ((imm12 & 0xfff) << 10)
25
+ insn |= ((rn & 0x1f) << 5)
26
+ insn |= (rt & 0x1f)
27
+ insn
28
+ end
29
+ end
30
+ end
31
+ end
@@ -0,0 +1,29 @@
1
+ module AArch64
2
+ module Instructions
3
+ # LDR (literal) -- A64
4
+ # Load Register (literal)
5
+ # LDR <Wt>, <label>
6
+ # LDR <Xt>, <label>
7
+ class LDR_lit_gen
8
+ def initialize rt, imm19, size
9
+ @rt = rt
10
+ @imm19 = imm19
11
+ @size = size
12
+ end
13
+
14
+ def encode
15
+ self.LDR_lit_gen(@size, @imm19.to_i / 4, @rt.to_i)
16
+ end
17
+
18
+ private
19
+
20
+ def LDR_lit_gen size, imm19, rt
21
+ insn = 0b00_011_0_00_0000000000000000000_00000
22
+ insn |= ((size & 0x3) << 30)
23
+ insn |= ((imm19 & 0x7ffff) << 5)
24
+ insn |= (rt & 0x1f)
25
+ insn
26
+ end
27
+ end
28
+ end
29
+ end
@@ -0,0 +1,35 @@
1
+ module AArch64
2
+ module Instructions
3
+ # LDR (register) -- A64
4
+ # Load Register (register)
5
+ # LDR <Wt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
6
+ # LDR <Xt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
7
+ class LDR_reg_gen
8
+ def initialize rt, rn, rm, size, option, s
9
+ @rt = rt
10
+ @rn = rn
11
+ @rm = rm
12
+ @size = size
13
+ @option = option
14
+ @s = s
15
+ end
16
+
17
+ def encode
18
+ self.LDR_reg_gen(@size, @rm.to_i, @option, @s, @rn.to_i, @rt.to_i)
19
+ end
20
+
21
+ private
22
+
23
+ def LDR_reg_gen size, rm, option, s, rn, rt
24
+ insn = 0b00_111_0_00_01_1_00000_000_0_10_00000_00000
25
+ insn |= ((size & 0x3) << 30)
26
+ insn |= ((rm & 0x1f) << 16)
27
+ insn |= ((option & 0x7) << 13)
28
+ insn |= ((s & 0x1) << 12)
29
+ insn |= ((rn & 0x1f) << 5)
30
+ insn |= (rt & 0x1f)
31
+ insn
32
+ end
33
+ end
34
+ end
35
+ end
@@ -0,0 +1,37 @@
1
+ module AArch64
2
+ module Instructions
3
+ # LDRAA, LDRAB -- A64
4
+ # Load Register, with pointer authentication
5
+ # LDRAA <Xt>, [<Xn|SP>{, #<simm>}]
6
+ # LDRAA <Xt>, [<Xn|SP>{, #<simm>}]!
7
+ # LDRAB <Xt>, [<Xn|SP>{, #<simm>}]
8
+ # LDRAB <Xt>, [<Xn|SP>{, #<simm>}]!
9
+ class LDRA
10
+ def initialize rt, rn, imm9, m, w, s
11
+ @rt = rt
12
+ @rn = rn
13
+ @imm9 = imm9
14
+ @m = m
15
+ @w = w
16
+ @s = s
17
+ end
18
+
19
+ def encode
20
+ self.LDRA(@m, @s, @imm9, @w, @rn.to_i, @rt.to_i)
21
+ end
22
+
23
+ private
24
+
25
+ def LDRA m, s, imm9, w, rn, rt
26
+ insn = 0b11_111_0_00_0_0_1_000000000_0_1_00000_00000
27
+ insn |= ((m & 0x1) << 23)
28
+ insn |= ((s & 0x1) << 22)
29
+ insn |= ((imm9 & 0x1ff) << 12)
30
+ insn |= ((w & 0x1) << 11)
31
+ insn |= ((rn & 0x1f) << 5)
32
+ insn |= (rt & 0x1f)
33
+ insn
34
+ end
35
+ end
36
+ end
37
+ end
@@ -0,0 +1,32 @@
1
+ module AArch64
2
+ module Instructions
3
+ # LDRB (immediate) -- A64
4
+ # Load Register Byte (immediate)
5
+ # LDRB <Wt>, [<Xn|SP>], #<simm>
6
+ # LDRB <Wt>, [<Xn|SP>, #<simm>]!
7
+ # LDRB <Wt>, [<Xn|SP>{, #<pimm>}]
8
+ class LDRB_imm
9
+ def initialize rt, rn, imm9, option
10
+ @rt = rt
11
+ @rn = rn
12
+ @imm9 = imm9
13
+ @option = option
14
+ end
15
+
16
+ def encode
17
+ self.LDRB_imm(@imm9, @option, @rn.to_i, @rt.to_i)
18
+ end
19
+
20
+ private
21
+
22
+ def LDRB_imm imm9, option, rn, rt
23
+ insn = 0b00_111_0_00_01_0_000000000_01_00000_00000
24
+ insn |= ((imm9 & 0x1ff) << 12)
25
+ insn |= ((option & 0x3) << 10)
26
+ insn |= ((rn & 0x1f) << 5)
27
+ insn |= (rt & 0x1f)
28
+ insn
29
+ end
30
+ end
31
+ end
32
+ end
@@ -0,0 +1,33 @@
1
+ module AArch64
2
+ module Instructions
3
+ # LDRB (register) -- A64
4
+ # Load Register Byte (register)
5
+ # LDRB <Wt>, [<Xn|SP>, (<Wm>|<Xm>), <extend> {<amount>}]
6
+ # LDRB <Wt>, [<Xn|SP>, <Xm>{, LSL <amount>}]
7
+ class LDRB_reg
8
+ def initialize rt, rn, rm, s, option
9
+ @rt = rt
10
+ @rn = rn
11
+ @rm = rm
12
+ @s = s
13
+ @option = option
14
+ end
15
+
16
+ def encode
17
+ self.LDRB_reg(@rm.to_i, @option, @s, @rn.to_i, @rt.to_i)
18
+ end
19
+
20
+ private
21
+
22
+ def LDRB_reg rm, option, s, rn, rt
23
+ insn = 0b00_111_0_00_01_1_00000_000_0_10_00000_00000
24
+ insn |= ((rm & 0x1f) << 16)
25
+ insn |= ((option & 0x7) << 13)
26
+ insn |= ((s & 0x1) << 12)
27
+ insn |= ((rn & 0x1f) << 5)
28
+ insn |= (rt & 0x1f)
29
+ insn
30
+ end
31
+ end
32
+ end
33
+ end
@@ -0,0 +1,28 @@
1
+ module AArch64
2
+ module Instructions
3
+ # LDRB (immediate) -- A64
4
+ # Load Register Byte (immediate)
5
+ # LDRB <Wt>, [<Xn|SP>{, #<pimm>}]
6
+ class LDRB_unsigned
7
+ def initialize rt, rn, imm12
8
+ @rt = rt
9
+ @rn = rn
10
+ @imm12 = imm12
11
+ end
12
+
13
+ def encode
14
+ self.LDRB_imm(@imm12, @rn.to_i, @rt.to_i)
15
+ end
16
+
17
+ private
18
+
19
+ def LDRB_imm imm12, rn, rt
20
+ insn = 0b00_111_0_01_01_0_00000000000_00000_00000
21
+ insn |= ((imm12 & 0xfff) << 10)
22
+ insn |= ((rn & 0x1f) << 5)
23
+ insn |= (rt & 0x1f)
24
+ insn
25
+ end
26
+ end
27
+ end
28
+ end
@@ -0,0 +1,32 @@
1
+ module AArch64
2
+ module Instructions
3
+ # LDRH (immediate) -- A64
4
+ # Load Register Halfword (immediate)
5
+ # LDRH <Wt>, [<Xn|SP>], #<simm>
6
+ # LDRH <Wt>, [<Xn|SP>, #<simm>]!
7
+ # LDRH <Wt>, [<Xn|SP>{, #<pimm>}]
8
+ class LDRH_imm
9
+ def initialize rt, rn, imm9, option
10
+ @rt = rt
11
+ @rn = rn
12
+ @imm9 = imm9
13
+ @option = option
14
+ end
15
+
16
+ def encode
17
+ self.LDRH_imm(@imm9, @option, @rn.to_i, @rt.to_i)
18
+ end
19
+
20
+ private
21
+
22
+ def LDRH_imm imm9, option, rn, rt
23
+ insn = 0b01_111_0_00_01_0_000000000_01_00000_00000
24
+ insn |= ((imm9 & 0x1ff) << 12)
25
+ insn |= ((option & 0x3) << 10)
26
+ insn |= ((rn & 0x1f) << 5)
27
+ insn |= (rt & 0x1f)
28
+ insn
29
+ end
30
+ end
31
+ end
32
+ end
@@ -0,0 +1,32 @@
1
+ module AArch64
2
+ module Instructions
3
+ # LDRH (register) -- A64
4
+ # Load Register Halfword (register)
5
+ # LDRH <Wt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
6
+ class LDRH_reg
7
+ def initialize rt, rn, rm, s, option
8
+ @rt = rt
9
+ @rn = rn
10
+ @rm = rm
11
+ @s = s
12
+ @option = option
13
+ end
14
+
15
+ def encode
16
+ self.LDRH_reg(@rm.to_i, @option, @s, @rn.to_i, @rt.to_i)
17
+ end
18
+
19
+ private
20
+
21
+ def LDRH_reg rm, option, s, rn, rt
22
+ insn = 0b01_111_0_00_01_1_00000_000_0_10_00000_00000
23
+ insn |= ((rm & 0x1f) << 16)
24
+ insn |= ((option & 0x7) << 13)
25
+ insn |= ((s & 0x1) << 12)
26
+ insn |= ((rn & 0x1f) << 5)
27
+ insn |= (rt & 0x1f)
28
+ insn
29
+ end
30
+ end
31
+ end
32
+ end
@@ -0,0 +1,28 @@
1
+ module AArch64
2
+ module Instructions
3
+ # LDRH (immediate) -- A64
4
+ # Load Register Halfword (immediate)
5
+ # LDRH <Wt>, [<Xn|SP>{, #<pimm>}]
6
+ class LDRH_unsigned
7
+ def initialize rt, rn, imm12
8
+ @rt = rt
9
+ @rn = rn
10
+ @imm12 = imm12
11
+ end
12
+
13
+ def encode
14
+ self.LDRH_unsigned(@imm12, @rn.to_i, @rt.to_i)
15
+ end
16
+
17
+ private
18
+
19
+ def LDRH_unsigned imm12, rn, rt
20
+ insn = 0b01_111_0_01_01_0_00000000000_00000_00000
21
+ insn |= ((imm12 & 0xfff) << 9)
22
+ insn |= ((rn & 0x1f) << 5)
23
+ insn |= (rt & 0x1f)
24
+ insn
25
+ end
26
+ end
27
+ end
28
+ end
@@ -0,0 +1,37 @@
1
+ module AArch64
2
+ module Instructions
3
+ # LDRSB (immediate) -- A64
4
+ # Load Register Signed Byte (immediate)
5
+ # LDRSB <Wt>, [<Xn|SP>], #<simm>
6
+ # LDRSB <Xt>, [<Xn|SP>], #<simm>
7
+ # LDRSB <Wt>, [<Xn|SP>, #<simm>]!
8
+ # LDRSB <Xt>, [<Xn|SP>, #<simm>]!
9
+ # LDRSB <Wt>, [<Xn|SP>{, #<pimm>}]
10
+ # LDRSB <Xt>, [<Xn|SP>{, #<pimm>}]
11
+ class LDRSB_imm
12
+ def initialize rt, rn, imm9, option, opc
13
+ @rt = rt
14
+ @rn = rn
15
+ @imm9 = imm9
16
+ @option = option
17
+ @opc = opc
18
+ end
19
+
20
+ def encode
21
+ self.LDRSB_imm(@opc, @imm9, @option, @rn.to_i, @rt.to_i)
22
+ end
23
+
24
+ private
25
+
26
+ def LDRSB_imm opc, imm9, option, rn, rt
27
+ insn = 0b00_111_0_00_00_0_000000000_01_00000_00000
28
+ insn |= ((opc & 0x3) << 22)
29
+ insn |= ((imm9 & 0x1ff) << 12)
30
+ insn |= ((option & 0x3) << 10)
31
+ insn |= ((rn & 0x1f) << 5)
32
+ insn |= (rt & 0x1f)
33
+ insn
34
+ end
35
+ end
36
+ end
37
+ end
@@ -0,0 +1,37 @@
1
+ module AArch64
2
+ module Instructions
3
+ # LDRSB (register) -- A64
4
+ # Load Register Signed Byte (register)
5
+ # LDRSB <Wt>, [<Xn|SP>, (<Wm>|<Xm>), <extend> {<amount>}]
6
+ # LDRSB <Wt>, [<Xn|SP>, <Xm>{, LSL <amount>}]
7
+ # LDRSB <Xt>, [<Xn|SP>, (<Wm>|<Xm>), <extend> {<amount>}]
8
+ # LDRSB <Xt>, [<Xn|SP>, <Xm>{, LSL <amount>}]
9
+ class LDRSB_reg
10
+ def initialize rt, rn, rm, s, option, opc
11
+ @rt = rt
12
+ @rn = rn
13
+ @rm = rm
14
+ @s = s
15
+ @option = option
16
+ @opc = opc
17
+ end
18
+
19
+ def encode
20
+ self.LDRSB_reg(@opc, @rm.to_i, @option, @s, @rn.to_i, @rt.to_i)
21
+ end
22
+
23
+ private
24
+
25
+ def LDRSB_reg opc, rm, option, s, rn, rt
26
+ insn = 0b00_111_0_00_00_1_00000_000_0_10_00000_00000
27
+ insn |= ((opc & 0x3) << 22)
28
+ insn |= ((rm & 0x1f) << 16)
29
+ insn |= ((option & 0x7) << 13)
30
+ insn |= ((s & 0x1) << 12)
31
+ insn |= ((rn & 0x1f) << 5)
32
+ insn |= (rt & 0x1f)
33
+ insn
34
+ end
35
+ end
36
+ end
37
+ end
@@ -0,0 +1,35 @@
1
+ module AArch64
2
+ module Instructions
3
+ # LDRSB (immediate) -- A64
4
+ # Load Register Signed Byte (immediate)
5
+ # LDRSB <Wt>, [<Xn|SP>], #<simm>
6
+ # LDRSB <Xt>, [<Xn|SP>], #<simm>
7
+ # LDRSB <Wt>, [<Xn|SP>, #<simm>]!
8
+ # LDRSB <Xt>, [<Xn|SP>, #<simm>]!
9
+ # LDRSB <Wt>, [<Xn|SP>{, #<pimm>}]
10
+ # LDRSB <Xt>, [<Xn|SP>{, #<pimm>}]
11
+ class LDRSB_unsigned
12
+ def initialize rt, rn, imm12, opc
13
+ @rt = rt
14
+ @rn = rn
15
+ @imm12 = imm12
16
+ @opc = opc
17
+ end
18
+
19
+ def encode
20
+ self.LDRSB_unsigned(@opc, @imm12, @rn.to_i, @rt.to_i)
21
+ end
22
+
23
+ private
24
+
25
+ def LDRSB_unsigned opc, imm12, rn, rt
26
+ insn = 0b00_111_0_01_00_0_00000000000_00000_00000
27
+ insn |= ((opc & 0x3) << 22)
28
+ insn |= ((imm12 & 0xfff) << 10)
29
+ insn |= ((rn & 0x1f) << 5)
30
+ insn |= (rt & 0x1f)
31
+ insn
32
+ end
33
+ end
34
+ end
35
+ end
@@ -0,0 +1,37 @@
1
+ module AArch64
2
+ module Instructions
3
+ # LDRSH (immediate) -- A64
4
+ # Load Register Signed Halfword (immediate)
5
+ # LDRSH <Wt>, [<Xn|SP>], #<simm>
6
+ # LDRSH <Xt>, [<Xn|SP>], #<simm>
7
+ # LDRSH <Wt>, [<Xn|SP>, #<simm>]!
8
+ # LDRSH <Xt>, [<Xn|SP>, #<simm>]!
9
+ # LDRSH <Wt>, [<Xn|SP>{, #<pimm>}]
10
+ # LDRSH <Xt>, [<Xn|SP>{, #<pimm>}]
11
+ class LDRSH_imm
12
+ def initialize rt, rn, imm9, option, opc
13
+ @rt = rt
14
+ @rn = rn
15
+ @imm9 = imm9
16
+ @option = option
17
+ @opc = opc
18
+ end
19
+
20
+ def encode
21
+ self.LDRSH_imm(@opc, @imm9, @option, @rn.to_i, @rt.to_i)
22
+ end
23
+
24
+ private
25
+
26
+ def LDRSH_imm opc, imm9, option, rn, rt
27
+ insn = 0b01_111_0_00_00_0_000000000_00_00000_00000
28
+ insn |= ((opc & 0x3) << 22)
29
+ insn |= ((imm9 & 0x1ff) << 12)
30
+ insn |= ((option & 0x3) << 10)
31
+ insn |= ((rn & 0x1f) << 5)
32
+ insn |= (rt & 0x1f)
33
+ insn
34
+ end
35
+ end
36
+ end
37
+ end
@@ -0,0 +1,35 @@
1
+ module AArch64
2
+ module Instructions
3
+ # LDRSH (register) -- A64
4
+ # Load Register Signed Halfword (register)
5
+ # LDRSH <Wt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
6
+ # LDRSH <Xt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
7
+ class LDRSH_reg
8
+ def initialize rt, rn, rm, s, option, opc
9
+ @rt = rt
10
+ @rn = rn
11
+ @rm = rm
12
+ @s = s
13
+ @option = option
14
+ @opc = opc
15
+ end
16
+
17
+ def encode
18
+ self.LDRSH_reg(@opc, @rm.to_i, @option, @s, @rn.to_i, @rt.to_i)
19
+ end
20
+
21
+ private
22
+
23
+ def LDRSH_reg opc, rm, option, s, rn, rt
24
+ insn = 0b01_111_0_00_00_1_00000_000_0_10_00000_00000
25
+ insn |= ((opc & 0x3) << 22)
26
+ insn |= ((rm & 0x1f) << 16)
27
+ insn |= ((option & 0x7) << 13)
28
+ insn |= ((s & 0x1) << 12)
29
+ insn |= ((rn & 0x1f) << 5)
30
+ insn |= (rt & 0x1f)
31
+ insn
32
+ end
33
+ end
34
+ end
35
+ end