aarch64 1.0.0

data/lib/aarch64/instructions/ldlar.rb

@@ -0,0 +1,29 @@
+module AArch64
+  module Instructions
+    # LDLAR -- A64
+    # Load LOAcquire Register
+    # LDLAR  <Wt>, [<Xn|SP>{,#0}]
+    # LDLAR  <Xt>, [<Xn|SP>{,#0}]
+    class LDLAR
+      def initialize rt, rn, size
+        @rt   = rt
+        @rn   = rn
+        @size = size
+      end
+
+      def encode
+        self.LDLAR(@size, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def LDLAR size, rn, rt
+        insn = 0b00_001000_1_1_0_11111_0_11111_00000_00000
+        insn |= ((size & 0x3) << 30)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/ldnp_gen.rb

@@ -0,0 +1,33 @@
+module AArch64
+  module Instructions
+    # LDNP -- A64
+    # Load Pair of Registers, with non-temporal hint
+    # LDNP  <Wt1>, <Wt2>, [<Xn|SP>{, #<imm>}]
+    # LDNP  <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]
+    class LDNP_gen
+      def initialize rt1, rt2, rn, imm, opc
+        @rt1 = rt1
+        @rt2 = rt2
+        @rn  = rn
+        @imm = imm
+        @opc = opc
+      end
+
+      def encode
+        self.LDNP_gen(@opc, @imm, @rt2.to_i, @rn.to_i, @rt1.to_i)
+      end
+
+      private
+
+      def LDNP_gen opc, imm7, rt2, rn, rt
+        insn = 0b00_101_0_000_1_0000000_00000_00000_00000
+        insn |= ((opc & 0x3) << 30)
+        insn |= ((imm7 & 0x7f) << 15)
+        insn |= ((rt2 & 0x1f) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/ldp_gen.rb

@@ -0,0 +1,39 @@
+module AArch64
+  module Instructions
+    # LDP -- A64
+    # Load Pair of Registers
+    # LDP  <Wt1>, <Wt2>, [<Xn|SP>], #<imm>
+    # LDP  <Xt1>, <Xt2>, [<Xn|SP>], #<imm>
+    # LDP  <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]!
+    # LDP  <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]!
+    # LDP  <Wt1>, <Wt2>, [<Xn|SP>{, #<imm>}]
+    # LDP  <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]
+    class LDP_gen
+      def initialize rt, rt2, rn, imm7, mode, opc
+        @rt   = rt
+        @rt2  = rt2
+        @rn   = rn
+        @imm7 = imm7
+        @mode = mode
+        @opc  = opc
+      end
+
+      def encode
+        self.LDP_gen(@opc, @mode, @imm7, @rt2.to_i, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def LDP_gen opc, mode, imm7, rt2, rn, rt
+        insn = 0b00_101_0_000_1_0000000_00000_00000_00000
+        insn |= ((opc & 0x3) << 30)
+        insn |= ((mode & 0x7) << 23)
+        insn |= ((imm7 & 0x7f) << 15)
+        insn |= ((rt2 & 0x1f) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/ldpsw.rb

@@ -0,0 +1,34 @@
+module AArch64
+  module Instructions
+    # LDPSW -- A64
+    # Load Pair of Registers Signed Word
+    # LDPSW  <Xt1>, <Xt2>, [<Xn|SP>], #<imm>
+    # LDPSW  <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]!
+    # LDPSW  <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]
+    class LDPSW
+      def initialize rt, rt2, rn, imm7, mode
+        @rt   = rt
+        @rt2  = rt2
+        @rn   = rn
+        @imm7 = imm7
+        @mode = mode
+      end
+
+      def encode
+        self.LDPSW(@mode, @imm7, @rt2.to_i, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def LDPSW mode, imm7, rt2, rn, rt
+        insn = 0b01_101_0_000_1_0000000_00000_00000_00000
+        insn |= ((mode & 0x7) << 23)
+        insn |= ((imm7 & 0x7f) << 15)
+        insn |= ((rt2 & 0x1f) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/ldr_imm_gen.rb

@@ -0,0 +1,35 @@
+module AArch64
+  module Instructions
+    # LDR (immediate) -- A64
+    # Load Register (immediate)
+    # LDR  <Wt>, [<Xn|SP>], #<simm>
+    # LDR  <Xt>, [<Xn|SP>], #<simm>
+    # LDR  <Wt>, [<Xn|SP>, #<simm>]!
+    # LDR  <Xt>, [<Xn|SP>, #<simm>]!
+    class LDR_imm_gen
+      def initialize rt, rn, imm9, size, mode
+        @rt   = rt
+        @rn   = rn
+        @imm9 = imm9
+        @size = size
+        @mode = mode
+      end
+
+      def encode
+        self.LDR_imm_gen(@size, @imm9, @mode, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def LDR_imm_gen size, imm9, mode, rn, rt
+        insn = 0b00_111_0_00_01_0_000000000_00_00000_00000
+        insn |= ((size & 0x3) << 30)
+        insn |= ((imm9 & 0x1ff) << 12)
+        insn |= ((mode & 0x3) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/ldr_imm_unsigned.rb

@@ -0,0 +1,31 @@
+module AArch64
+  module Instructions
+    # LDR (immediate) -- A64
+    # Load Register (immediate)
+    # LDR  <Wt>, [<Xn|SP>{, #<pimm>}]
+    # LDR  <Xt>, [<Xn|SP>{, #<pimm>}]
+    class LDR_imm_unsigned
+      def initialize rt, rn, imm12, size
+        @rt    = rt
+        @rn    = rn
+        @imm12 = imm12
+        @size  = size
+      end
+
+      def encode
+        self.LDR_imm_gen(@size, @imm12, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def LDR_imm_gen size, imm12, rn, rt
+        insn = 0b00_111_0_01_01_000000000000_00000_00000
+        insn |= ((size & 0x3) << 30)
+        insn |= ((imm12 & 0xfff) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/ldr_lit_gen.rb

@@ -0,0 +1,29 @@
+module AArch64
+  module Instructions
+    # LDR (literal) -- A64
+    # Load Register (literal)
+    # LDR  <Wt>, <label>
+    # LDR  <Xt>, <label>
+    class LDR_lit_gen
+      def initialize rt, imm19, size
+        @rt    = rt
+        @imm19 = imm19
+        @size  = size
+      end
+
+      def encode
+        self.LDR_lit_gen(@size, @imm19.to_i / 4, @rt.to_i)
+      end
+
+      private
+
+      def LDR_lit_gen size, imm19, rt
+        insn = 0b00_011_0_00_0000000000000000000_00000
+        insn |= ((size & 0x3) << 30)
+        insn |= ((imm19 & 0x7ffff) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/ldr_reg_gen.rb

@@ -0,0 +1,35 @@
+module AArch64
+  module Instructions
+    # LDR (register) -- A64
+    # Load Register (register)
+    # LDR  <Wt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
+    # LDR  <Xt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
+    class LDR_reg_gen
+      def initialize rt, rn, rm, size, option, s
+        @rt     = rt
+        @rn     = rn
+        @rm     = rm
+        @size   = size
+        @option = option
+        @s      = s
+      end
+
+      def encode
+        self.LDR_reg_gen(@size, @rm.to_i, @option, @s, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def LDR_reg_gen size, rm, option, s, rn, rt
+        insn = 0b00_111_0_00_01_1_00000_000_0_10_00000_00000
+        insn |= ((size & 0x3) << 30)
+        insn |= ((rm & 0x1f) << 16)
+        insn |= ((option & 0x7) << 13)
+        insn |= ((s & 0x1) << 12)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/ldra.rb

@@ -0,0 +1,37 @@
+module AArch64
+  module Instructions
+    # LDRAA, LDRAB -- A64
+    # Load Register, with pointer authentication
+    # LDRAA  <Xt>, [<Xn|SP>{, #<simm>}]
+    # LDRAA  <Xt>, [<Xn|SP>{, #<simm>}]!
+    # LDRAB  <Xt>, [<Xn|SP>{, #<simm>}]
+    # LDRAB  <Xt>, [<Xn|SP>{, #<simm>}]!
+    class LDRA
+      def initialize rt, rn, imm9, m, w, s
+        @rt   = rt
+        @rn   = rn
+        @imm9 = imm9
+        @m    = m
+        @w    = w
+        @s    = s
+      end
+
+      def encode
+        self.LDRA(@m, @s, @imm9, @w, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def LDRA m, s, imm9, w, rn, rt
+        insn = 0b11_111_0_00_0_0_1_000000000_0_1_00000_00000
+        insn |= ((m & 0x1) << 23)
+        insn |= ((s & 0x1) << 22)
+        insn |= ((imm9 & 0x1ff) << 12)
+        insn |= ((w & 0x1) << 11)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/ldrb_imm.rb

@@ -0,0 +1,32 @@
+module AArch64
+  module Instructions
+    # LDRB (immediate) -- A64
+    # Load Register Byte (immediate)
+    # LDRB  <Wt>, [<Xn|SP>], #<simm>
+    # LDRB  <Wt>, [<Xn|SP>, #<simm>]!
+    # LDRB  <Wt>, [<Xn|SP>{, #<pimm>}]
+    class LDRB_imm
+      def initialize rt, rn, imm9, option
+        @rt     = rt
+        @rn     = rn
+        @imm9   = imm9
+        @option = option
+      end
+
+      def encode
+        self.LDRB_imm(@imm9, @option, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def LDRB_imm imm9, option, rn, rt
+        insn = 0b00_111_0_00_01_0_000000000_01_00000_00000
+        insn |= ((imm9 & 0x1ff) << 12)
+        insn |= ((option & 0x3) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/ldrb_reg.rb

@@ -0,0 +1,33 @@
+module AArch64
+  module Instructions
+    # LDRB (register) -- A64
+    # Load Register Byte (register)
+    # LDRB  <Wt>, [<Xn|SP>, (<Wm>|<Xm>), <extend> {<amount>}]
+    # LDRB  <Wt>, [<Xn|SP>, <Xm>{, LSL <amount>}]
+    class LDRB_reg
+      def initialize rt, rn, rm, s, option
+        @rt     = rt
+        @rn     = rn
+        @rm     = rm
+        @s      = s
+        @option = option
+      end
+
+      def encode
+        self.LDRB_reg(@rm.to_i, @option, @s, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def LDRB_reg rm, option, s, rn, rt
+        insn = 0b00_111_0_00_01_1_00000_000_0_10_00000_00000
+        insn |= ((rm & 0x1f) << 16)
+        insn |= ((option & 0x7) << 13)
+        insn |= ((s & 0x1) << 12)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/ldrb_unsigned.rb

@@ -0,0 +1,28 @@
+module AArch64
+  module Instructions
+    # LDRB (immediate) -- A64
+    # Load Register Byte (immediate)
+    # LDRB  <Wt>, [<Xn|SP>{, #<pimm>}]
+    class LDRB_unsigned
+      def initialize rt, rn, imm12
+        @rt    = rt
+        @rn    = rn
+        @imm12 = imm12
+      end
+
+      def encode
+        self.LDRB_imm(@imm12, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def LDRB_imm imm12, rn, rt
+        insn = 0b00_111_0_01_01_0_00000000000_00000_00000
+        insn |= ((imm12 & 0xfff) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/ldrh_imm.rb

@@ -0,0 +1,32 @@
+module AArch64
+  module Instructions
+    # LDRH (immediate) -- A64
+    # Load Register Halfword (immediate)
+    # LDRH  <Wt>, [<Xn|SP>], #<simm>
+    # LDRH  <Wt>, [<Xn|SP>, #<simm>]!
+    # LDRH  <Wt>, [<Xn|SP>{, #<pimm>}]
+    class LDRH_imm
+      def initialize rt, rn, imm9, option
+        @rt     = rt
+        @rn     = rn
+        @imm9   = imm9
+        @option = option
+      end
+
+      def encode
+        self.LDRH_imm(@imm9, @option, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def LDRH_imm imm9, option, rn, rt
+        insn = 0b01_111_0_00_01_0_000000000_01_00000_00000
+        insn |= ((imm9 & 0x1ff) << 12)
+        insn |= ((option & 0x3) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/ldrh_reg.rb

@@ -0,0 +1,32 @@
+module AArch64
+  module Instructions
+    # LDRH (register) -- A64
+    # Load Register Halfword (register)
+    # LDRH  <Wt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
+    class LDRH_reg
+      def initialize rt, rn, rm, s, option
+        @rt     = rt
+        @rn     = rn
+        @rm     = rm
+        @s      = s
+        @option = option
+      end
+
+      def encode
+        self.LDRH_reg(@rm.to_i, @option, @s, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def LDRH_reg rm, option, s, rn, rt
+        insn = 0b01_111_0_00_01_1_00000_000_0_10_00000_00000
+        insn |= ((rm & 0x1f) << 16)
+        insn |= ((option & 0x7) << 13)
+        insn |= ((s & 0x1) << 12)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/ldrh_unsigned.rb

@@ -0,0 +1,28 @@
+module AArch64
+  module Instructions
+    # LDRH (immediate) -- A64
+    # Load Register Halfword (immediate)
+    # LDRH  <Wt>, [<Xn|SP>{, #<pimm>}]
+    class LDRH_unsigned
+      def initialize rt, rn, imm12
+        @rt    = rt
+        @rn    = rn
+        @imm12 = imm12
+      end
+
+      def encode
+        self.LDRH_unsigned(@imm12, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def LDRH_unsigned imm12, rn, rt
+        insn = 0b01_111_0_01_01_0_00000000000_00000_00000
+        insn |= ((imm12 & 0xfff) << 9)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/ldrsb_imm.rb

@@ -0,0 +1,37 @@
+module AArch64
+  module Instructions
+    # LDRSB (immediate) -- A64
+    # Load Register Signed Byte (immediate)
+    # LDRSB  <Wt>, [<Xn|SP>], #<simm>
+    # LDRSB  <Xt>, [<Xn|SP>], #<simm>
+    # LDRSB  <Wt>, [<Xn|SP>, #<simm>]!
+    # LDRSB  <Xt>, [<Xn|SP>, #<simm>]!
+    # LDRSB  <Wt>, [<Xn|SP>{, #<pimm>}]
+    # LDRSB  <Xt>, [<Xn|SP>{, #<pimm>}]
+    class LDRSB_imm
+      def initialize rt, rn, imm9, option, opc
+        @rt     = rt
+        @rn     = rn
+        @imm9   = imm9
+        @option = option
+        @opc    = opc
+      end
+
+      def encode
+        self.LDRSB_imm(@opc, @imm9, @option, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def LDRSB_imm opc, imm9, option, rn, rt
+        insn = 0b00_111_0_00_00_0_000000000_01_00000_00000
+        insn |= ((opc & 0x3) << 22)
+        insn |= ((imm9 & 0x1ff) << 12)
+        insn |= ((option & 0x3) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/ldrsb_reg.rb

@@ -0,0 +1,37 @@
+module AArch64
+  module Instructions
+    # LDRSB (register) -- A64
+    # Load Register Signed Byte (register)
+    # LDRSB  <Wt>, [<Xn|SP>, (<Wm>|<Xm>), <extend> {<amount>}]
+    # LDRSB  <Wt>, [<Xn|SP>, <Xm>{, LSL <amount>}]
+    # LDRSB  <Xt>, [<Xn|SP>, (<Wm>|<Xm>), <extend> {<amount>}]
+    # LDRSB  <Xt>, [<Xn|SP>, <Xm>{, LSL <amount>}]
+    class LDRSB_reg
+      def initialize rt, rn, rm, s, option, opc
+        @rt     = rt
+        @rn     = rn
+        @rm     = rm
+        @s      = s
+        @option = option
+        @opc    = opc
+      end
+
+      def encode
+        self.LDRSB_reg(@opc, @rm.to_i, @option, @s, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def LDRSB_reg opc, rm, option, s, rn, rt
+        insn = 0b00_111_0_00_00_1_00000_000_0_10_00000_00000
+        insn |= ((opc & 0x3) << 22)
+        insn |= ((rm & 0x1f) << 16)
+        insn |= ((option & 0x7) << 13)
+        insn |= ((s & 0x1) << 12)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/ldrsb_unsigned.rb

@@ -0,0 +1,35 @@
+module AArch64
+  module Instructions
+    # LDRSB (immediate) -- A64
+    # Load Register Signed Byte (immediate)
+    # LDRSB  <Wt>, [<Xn|SP>], #<simm>
+    # LDRSB  <Xt>, [<Xn|SP>], #<simm>
+    # LDRSB  <Wt>, [<Xn|SP>, #<simm>]!
+    # LDRSB  <Xt>, [<Xn|SP>, #<simm>]!
+    # LDRSB  <Wt>, [<Xn|SP>{, #<pimm>}]
+    # LDRSB  <Xt>, [<Xn|SP>{, #<pimm>}]
+    class LDRSB_unsigned
+      def initialize rt, rn, imm12, opc
+        @rt    = rt
+        @rn    = rn
+        @imm12 = imm12
+        @opc   = opc
+      end
+
+      def encode
+        self.LDRSB_unsigned(@opc, @imm12, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def LDRSB_unsigned opc, imm12, rn, rt
+        insn = 0b00_111_0_01_00_0_00000000000_00000_00000
+        insn |= ((opc & 0x3) << 22)
+        insn |= ((imm12 & 0xfff) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/ldrsh_imm.rb

@@ -0,0 +1,37 @@
+module AArch64
+  module Instructions
+    # LDRSH (immediate) -- A64
+    # Load Register Signed Halfword (immediate)
+    # LDRSH  <Wt>, [<Xn|SP>], #<simm>
+    # LDRSH  <Xt>, [<Xn|SP>], #<simm>
+    # LDRSH  <Wt>, [<Xn|SP>, #<simm>]!
+    # LDRSH  <Xt>, [<Xn|SP>, #<simm>]!
+    # LDRSH  <Wt>, [<Xn|SP>{, #<pimm>}]
+    # LDRSH  <Xt>, [<Xn|SP>{, #<pimm>}]
+    class LDRSH_imm
+      def initialize rt, rn, imm9, option, opc
+        @rt     = rt
+        @rn     = rn
+        @imm9   = imm9
+        @option = option
+        @opc    = opc
+      end
+
+      def encode
+        self.LDRSH_imm(@opc, @imm9, @option, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def LDRSH_imm opc, imm9, option, rn, rt
+        insn = 0b01_111_0_00_00_0_000000000_00_00000_00000
+        insn |= ((opc & 0x3) << 22)
+        insn |= ((imm9 & 0x1ff) << 12)
+        insn |= ((option & 0x3) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/ldrsh_reg.rb

@@ -0,0 +1,35 @@
+module AArch64
+  module Instructions
+    # LDRSH (register) -- A64
+    # Load Register Signed Halfword (register)
+    # LDRSH  <Wt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
+    # LDRSH  <Xt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
+    class LDRSH_reg
+      def initialize rt, rn, rm, s, option, opc
+        @rt     = rt
+        @rn     = rn
+        @rm     = rm
+        @s      = s
+        @option = option
+        @opc    = opc
+      end
+
+      def encode
+        self.LDRSH_reg(@opc, @rm.to_i, @option, @s, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def LDRSH_reg opc, rm, option, s, rn, rt
+        insn = 0b01_111_0_00_00_1_00000_000_0_10_00000_00000
+        insn |= ((opc & 0x3) << 22)
+        insn |= ((rm & 0x1f) << 16)
+        insn |= ((option & 0x7) << 13)
+        insn |= ((s & 0x1) << 12)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end