aarch64 1.0.0

data/lib/aarch64/instructions/ccmp_reg.rb

@@ -0,0 +1,33 @@
+module AArch64
+  module Instructions
+    # CCMP (register) -- A64
+    # Conditional Compare (register)
+    # CCMP  <Wn>, <Wm>, #<nzcv>, <cond>
+    # CCMP  <Xn>, <Xm>, #<nzcv>, <cond>
+    class CCMP_reg
+      def initialize rn, rm, nzcv, cond, sf
+        @rn   = rn
+        @rm   = rm
+        @nzcv = nzcv
+        @cond = cond
+        @sf   = sf
+      end
+
+      def encode
+        CCMP_reg(@sf, @rm.to_i, @cond, @rn.to_i, @nzcv)
+      end
+
+      private
+
+      def CCMP_reg sf, rm, cond, rn, nzcv
+        insn = 0b0_1_1_11010010_00000_0000_0_0_00000_0_0000
+        insn |= ((sf & 0x1) << 31)
+        insn |= ((rm & 0x1f) << 16)
+        insn |= ((cond & 0xf) << 12)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (nzcv & 0xf)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/cfinv.rb

@@ -0,0 +1,19 @@
+module AArch64
+  module Instructions
+    # CFINV -- A64
+    # Invert Carry Flag
+    # CFINV
+    class CFINV
+      def encode
+        self.CFINV
+      end
+
+      private
+
+      def CFINV
+        insn = 0b1101010100_0_0_0_000_0100_0000_000_11111
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/clrex.rb

@@ -0,0 +1,24 @@
+module AArch64
+  module Instructions
+    # CLREX -- A64
+    # Clear Exclusive
+    # CLREX  {#<imm>}
+    class CLREX
+      def initialize imm
+        @imm = imm
+      end
+
+      def encode
+        CLREX(@imm)
+      end
+
+      private
+
+      def CLREX crm
+        insn = 0b1101010100_0_00_011_0011_0000_010_11111
+        insn |= ((crm & 0xf) << 8)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/cls_int.rb

@@ -0,0 +1,29 @@
+module AArch64
+  module Instructions
+    # CLS -- A64
+    # Count Leading Sign bits
+    # CLS  <Wd>, <Wn>
+    # CLS  <Xd>, <Xn>
+    class CLS_int
+      def initialize rd, rn, sf
+        @rd = rd
+        @rn = rn
+        @sf = sf
+      end
+
+      def encode
+        CLS_int(@sf, @rn.to_i, @rd.to_i)
+      end
+
+      private
+
+      def CLS_int sf, rn, rd
+        insn = 0b0_1_0_11010110_00000_00010_1_00000_00000
+        insn |= ((sf & 0x1) << 31)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/clz_int.rb

@@ -0,0 +1,29 @@
+module AArch64
+  module Instructions
+    # CLZ -- A64
+    # Count Leading Zeros
+    # CLZ  <Wd>, <Wn>
+    # CLZ  <Xd>, <Xn>
+    class CLZ_int
+      def initialize rd, rn, sf
+        @rd = rd
+        @rn = rn
+        @sf = sf
+      end
+
+      def encode
+        CLZ_int(@sf, @rn.to_i, @rd.to_i)
+      end
+
+      private
+
+      def CLZ_int sf, rn, rd
+        insn = 0b0_1_0_11010110_00000_00010_0_00000_00000
+        insn |= ((sf & 0x1) << 31)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/crc32.rb

@@ -0,0 +1,35 @@
+module AArch64
+  module Instructions
+    # CRC32B, CRC32H, CRC32W, CRC32X -- A64
+    # CRC32 checksum
+    # CRC32B  <Wd>, <Wn>, <Wm>
+    # CRC32H  <Wd>, <Wn>, <Wm>
+    # CRC32W  <Wd>, <Wn>, <Wm>
+    # CRC32X  <Wd>, <Wn>, <Xm>
+    class CRC32
+      def initialize rd, rn, rm, sz, sf
+        @rd = rd
+        @rn = rn
+        @rm = rm
+        @sz = sz
+        @sf = sf
+      end
+
+      def encode
+        self.CRC32(@sf, @rm.to_i, @sz, @rn.to_i, @rd.to_i)
+      end
+
+      private
+
+      def CRC32 sf, rm, sz, rn, rd
+        insn = 0b0_0_0_11010110_00000_010_0_00_00000_00000
+        insn |= ((sf & 0x1) << 31)
+        insn |= ((rm & 0x1f) << 16)
+        insn |= ((sz & 0x3) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/crc32c.rb

@@ -0,0 +1,35 @@
+module AArch64
+  module Instructions
+    # CRC32CB, CRC32CH, CRC32CW, CRC32CX -- A64
+    # CRC32C checksum
+    # CRC32CB  <Wd>, <Wn>, <Wm>
+    # CRC32CH  <Wd>, <Wn>, <Wm>
+    # CRC32CW  <Wd>, <Wn>, <Wm>
+    # CRC32CX  <Wd>, <Wn>, <Xm>
+    class CRC32C
+      def initialize rd, rn, rm, sz, sf
+        @rd = rd
+        @rn = rn
+        @rm = rm
+        @sz = sz
+        @sf = sf
+      end
+
+      def encode
+        self.CRC32C(@sf, @rm.to_i, @sz, @rn.to_i, @rd.to_i)
+      end
+
+      private
+
+      def CRC32C sf, rm, sz, rn, rd
+        insn = 0b0_0_0_11010110_00000_010_1_00_00000_00000
+        insn |= ((sf & 0x1) << 31)
+        insn |= ((rm & 0x1f) << 16)
+        insn |= ((sz & 0x3) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/csdb.rb

@@ -0,0 +1,19 @@
+module AArch64
+  module Instructions
+    # CSDB -- A64
+    # Consumption of Speculative Data Barrier
+    # CSDB
+    class CSDB
+      def encode
+        self.CSDB
+      end
+
+      private
+
+      def CSDB
+        insn = 0b1101010100_0_00_011_0010_0010_100_11111
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/csel.rb

@@ -0,0 +1,33 @@
+module AArch64
+  module Instructions
+    # CSEL -- A64
+    # Conditional Select
+    # CSEL  <Wd>, <Wn>, <Wm>, <cond>
+    # CSEL  <Xd>, <Xn>, <Xm>, <cond>
+    class CSEL
+      def initialize rd, rn, rm, cond, sf
+        @rd   = rd
+        @rn   = rn
+        @rm   = rm
+        @cond = cond
+        @sf   = sf
+      end
+
+      def encode
+        self.CSEL @sf, @rm.to_i, @cond, @rn.to_i, @rd.to_i
+      end
+
+      private
+
+      def CSEL sf, rm, cond, rn, rd
+        insn = 0b0_0_0_11010100_00000_0000_0_0_00000_00000
+        insn |= ((sf & 0x1) << 31)
+        insn |= ((rm & 0x1f) << 16)
+        insn |= ((cond & 0xf) << 12)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/csinc.rb

@@ -0,0 +1,33 @@
+module AArch64
+  module Instructions
+    # CSINC -- A64
+    # Conditional Select Increment
+    # CSINC  <Wd>, <Wn>, <Wm>, <cond>
+    # CSINC  <Xd>, <Xn>, <Xm>, <cond>
+    class CSINC
+      def initialize rd, rn, rm, cond, sf
+        @rd   = rd
+        @rn   = rn
+        @rm   = rm
+        @cond = cond
+        @sf   = sf
+      end
+
+      def encode
+        CSINC(@sf, @rm.to_i, @cond, @rn.to_i, @rd.to_i)
+      end
+
+      private
+
+      def CSINC sf, rm, cond, rn, rd
+        insn = 0b0_0_0_11010100_00000_0000_0_1_00000_00000
+        insn |= ((sf & 0x1) << 31)
+        insn |= ((rm & 0x1f) << 16)
+        insn |= ((cond & 0xf) << 12)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/csinv.rb

@@ -0,0 +1,33 @@
+module AArch64
+  module Instructions
+    # CSINV -- A64
+    # Conditional Select Invert
+    # CSINV  <Wd>, <Wn>, <Wm>, <cond>
+    # CSINV  <Xd>, <Xn>, <Xm>, <cond>
+    class CSINV
+      def initialize rd, rn, rm, cond, sf
+        @rd   = rd
+        @rn   = rn
+        @rm   = rm
+        @cond = cond
+        @sf   = sf
+      end
+
+      def encode
+        CSINV(@sf, @rm.to_i, @cond, @rn.to_i, @rd.to_i)
+      end
+
+      private
+
+      def CSINV sf, rm, cond, rn, rd
+        insn = 0b0_1_0_11010100_00000_0000_0_0_00000_00000
+        insn |= ((sf & 0x1) << 31)
+        insn |= ((rm & 0x1f) << 16)
+        insn |= ((cond & 0xf) << 12)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/csneg.rb

@@ -0,0 +1,33 @@
+module AArch64
+  module Instructions
+    # CSNEG -- A64
+    # Conditional Select Negation
+    # CSNEG  <Wd>, <Wn>, <Wm>, <cond>
+    # CSNEG  <Xd>, <Xn>, <Xm>, <cond>
+    class CSNEG
+      def initialize rd, rn, rm, cond, sf
+        @rd   = rd
+        @rn   = rn
+        @rm   = rm
+        @cond = cond
+        @sf   = sf
+      end
+
+      def encode
+        self.CSNEG(@sf, @rm.to_i, @cond, @rn.to_i, @rd.to_i)
+      end
+
+      private
+
+      def CSNEG sf, rm, cond, rn, rd
+        insn = 0b0_1_0_11010100_00000_0000_0_1_00000_00000
+        insn |= ((sf & 0x1) << 31)
+        insn |= ((rm & 0x1f) << 16)
+        insn |= ((cond & 0xf) << 12)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/dcps.rb

@@ -0,0 +1,26 @@
+module AArch64
+  module Instructions
+    # DCPS1 -- A64
+    # Debug Change PE State to EL1.
+    # DCPS1  {#<imm>}
+    class DCPS
+      def initialize imm, ll
+        @imm = imm
+        @ll  = ll
+      end
+
+      def encode
+        self.DCPS @imm, @ll
+      end
+
+      private
+
+      def DCPS imm16, ll
+        insn = 0b11010100_101_0000000000000000_000_00
+        insn |= ((imm16 & 0xffff) << 5)
+        insn |= (ll & 0x3)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/dgh.rb

@@ -0,0 +1,19 @@
+module AArch64
+  module Instructions
+    # DGH -- A64
+    # Data Gathering Hint
+    # DGH
+    class DGH
+      def encode
+        self.DGH
+      end
+
+      private
+
+      def DGH
+        insn = 0b1101010100_0_00_011_0010_0000_110_11111
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/dmb.rb

@@ -0,0 +1,24 @@
+module AArch64
+  module Instructions
+    # DMB -- A64
+    # Data Memory Barrier
+    # DMB  <option>|#<imm>
+    class DMB
+      def initialize imm
+        @imm = imm
+      end
+
+      def encode
+        self.DMB(@imm)
+      end
+
+      private
+
+      def DMB crm
+        insn = 0b1101010100_0_00_011_0011_0000_1_01_11111
+        insn |= ((crm & 0xf) << 8)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/drps.rb

@@ -0,0 +1,19 @@
+module AArch64
+  module Instructions
+    # DRPS -- A64
+    # Debug restore process state
+    # DRPS
+    class DRPS
+      def encode
+        self.DRPS
+      end
+
+      private
+
+      def DRPS
+        insn = 0b1101011_0101_11111_000000_11111_00000
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/dsb.rb

@@ -0,0 +1,25 @@
+module AArch64
+  module Instructions
+    # DSB -- A64
+    # Data Synchronization Barrier
+    # DSB  <option>|#<imm>
+    # DSB  <option>nXS|#<imm>
+    class DSB
+      def initialize imm
+        @imm = imm
+      end
+
+      def encode
+        self.DSB(@imm)
+      end
+
+      private
+
+      def DSB crm
+        insn = 0b1101010100_0_00_011_0011_0000_1_00_11111
+        insn |= ((crm & 0xf) << 8)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/eon.rb

@@ -0,0 +1,35 @@
+module AArch64
+  module Instructions
+    # EON (shifted register) -- A64
+    # Bitwise Exclusive OR NOT (shifted register)
+    # EON  <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
+    # EON  <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
+    class EON
+      def initialize rd, rn, rm, shift, imm, sf
+        @rd    = rd
+        @rn    = rn
+        @rm    = rm
+        @shift = shift
+        @imm   = imm
+        @sf    = sf
+      end
+
+      def encode
+        self.EON(@sf, @shift, @rm.to_i, @imm, @rn.to_i, @rd.to_i)
+      end
+
+      private
+
+      def EON sf, shift, rm, imm6, rn, rd
+        insn = 0b0_10_01010_00_1_00000_000000_00000_00000
+        insn |= ((sf & 0x1) << 31)
+        insn |= ((shift & 0x3) << 22)
+        insn |= ((rm & 0x1f) << 16)
+        insn |= ((imm6 & 0x3f) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/eor_log_imm.rb

@@ -0,0 +1,35 @@
+module AArch64
+  module Instructions
+    # EOR (immediate) -- A64
+    # Bitwise Exclusive OR (immediate)
+    # EOR  <Wd|WSP>, <Wn>, #<imm>
+    # EOR  <Xd|SP>, <Xn>, #<imm>
+    class EOR_log_imm
+      def initialize rd, rn, n, immr, imms, sf
+        @rd   = rd
+        @rn   = rn
+        @n    = n
+        @immr = immr
+        @imms = imms
+        @sf   = sf
+      end
+
+      def encode
+        self.EOR_log_imm(@sf, @n, @immr, @imms, @rn.to_i, @rd.to_i)
+      end
+
+      private
+
+      def EOR_log_imm sf, n, immr, imms, rn, rd
+        insn = 0b0_10_100100_0_000000_000000_00000_00000
+        insn |= ((sf & 0x1) << 31)
+        insn |= ((n & 0x1) << 22)
+        insn |= ((immr & 0x3f) << 16)
+        insn |= ((imms & 0x3f) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/eor_log_shift.rb

@@ -0,0 +1,35 @@
+module AArch64
+  module Instructions
+    # EOR (shifted register) -- A64
+    # Bitwise Exclusive OR (shifted register)
+    # EOR  <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
+    # EOR  <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
+    class EOR_log_shift
+      def initialize rd, rn, rm, shift, imm6, sf
+        @rd    = rd
+        @rn    = rn
+        @rm    = rm
+        @shift = shift
+        @imm6  = imm6
+        @sf    = sf
+      end
+
+      def encode
+        self.EOR_log_shift(@sf, @shift, @rm.to_i, @imm6, @rn.to_i, @rd.to_i)
+      end
+
+      private
+
+      def EOR_log_shift sf, shift, rm, imm6, rn, rd
+        insn = 0b0_10_01010_00_0_00000_000000_00000_00000
+        insn |= ((sf & 0x1) << 31)
+        insn |= ((shift & 0x3) << 22)
+        insn |= ((rm & 0x1f) << 16)
+        insn |= ((imm6 & 0x3f) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/eret.rb

@@ -0,0 +1,19 @@
+module AArch64
+  module Instructions
+    # ERET -- A64
+    # Exception Return
+    # ERET
+    class ERET
+      def encode
+        self.ERET
+      end
+
+      private
+
+      def ERET
+        insn = 0b1101011_0_100_11111_0000_0_0_11111_00000
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/ereta.rb

@@ -0,0 +1,25 @@
+module AArch64
+  module Instructions
+    # ERETAA, ERETAB -- A64
+    # Exception Return, with pointer authentication
+    # ERETAA
+    # ERETAB
+    class ERETA
+      def initialize m
+        @m = m
+      end
+
+      def encode
+        self.ERETA(@m)
+      end
+
+      private
+
+      def ERETA m
+        insn = 0b1101011_0_100_11111_0000_1_0_11111_11111
+        insn |= ((m & 0x1) << 10)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/esb.rb

@@ -0,0 +1,19 @@
+module AArch64
+  module Instructions
+    # ESB -- A64
+    # Error Synchronization Barrier
+    # ESB
+    class ESB
+      def encode
+        self.ESB
+      end
+
+      private
+
+      def ESB
+        insn = 0b1101010100_0_00_011_0010_0010_000_11111
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/extr.rb

@@ -0,0 +1,34 @@
+module AArch64
+  module Instructions
+    # EXTR -- A64
+    # Extract register
+    # EXTR  <Wd>, <Wn>, <Wm>, #<lsb>
+    # EXTR  <Xd>, <Xn>, <Xm>, #<lsb>
+    class EXTR
+      def initialize rd, rn, rm, lsb, sf
+        @rd  = rd
+        @rn  = rn
+        @rm  = rm
+        @lsb = lsb
+        @sf  = sf
+      end
+
+      def encode
+        self.EXTR(@sf, @sf, @rm.to_i, @lsb, @rn.to_i, @rd.to_i)
+      end
+
+      private
+
+      def EXTR sf, n, rm, imms, rn, rd
+        insn = 0b0_00_100111_0_0_00000_000000_00000_00000
+        insn |= ((sf & 0x1) << 31)
+        insn |= ((n & 0x1) << 22)
+        insn |= ((rm & 0x1f) << 16)
+        insn |= ((imms & 0x3f) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end