aarch64 1.0.0

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Files changed (281) hide show
  1. checksums.yaml +7 -0
  2. data/CODE_OF_CONDUCT.md +77 -0
  3. data/Gemfile +3 -0
  4. data/LICENSE +201 -0
  5. data/README.md +77 -0
  6. data/Rakefile +168 -0
  7. data/aarch64.gemspec +21 -0
  8. data/bin/build_instructions.rb +102 -0
  9. data/lib/aarch64/instructions/adc.rb +31 -0
  10. data/lib/aarch64/instructions/adcs.rb +30 -0
  11. data/lib/aarch64/instructions/add_addsub_ext.rb +35 -0
  12. data/lib/aarch64/instructions/add_addsub_imm.rb +32 -0
  13. data/lib/aarch64/instructions/add_addsub_shift.rb +35 -0
  14. data/lib/aarch64/instructions/addg.rb +30 -0
  15. data/lib/aarch64/instructions/adds_addsub_ext.rb +35 -0
  16. data/lib/aarch64/instructions/adds_addsub_imm.rb +33 -0
  17. data/lib/aarch64/instructions/adds_addsub_shift.rb +35 -0
  18. data/lib/aarch64/instructions/adr.rb +28 -0
  19. data/lib/aarch64/instructions/adrp.rb +28 -0
  20. data/lib/aarch64/instructions/and_log_imm.rb +35 -0
  21. data/lib/aarch64/instructions/and_log_shift.rb +35 -0
  22. data/lib/aarch64/instructions/ands_log_imm.rb +35 -0
  23. data/lib/aarch64/instructions/ands_log_shift.rb +35 -0
  24. data/lib/aarch64/instructions/asrv.rb +31 -0
  25. data/lib/aarch64/instructions/autda.rb +32 -0
  26. data/lib/aarch64/instructions/autdb.rb +32 -0
  27. data/lib/aarch64/instructions/autia.rb +35 -0
  28. data/lib/aarch64/instructions/autib.rb +35 -0
  29. data/lib/aarch64/instructions/axflag.rb +18 -0
  30. data/lib/aarch64/instructions/b_cond.rb +26 -0
  31. data/lib/aarch64/instructions/b_uncond.rb +24 -0
  32. data/lib/aarch64/instructions/bc_cond.rb +26 -0
  33. data/lib/aarch64/instructions/bfm.rb +34 -0
  34. data/lib/aarch64/instructions/bic_log_shift.rb +35 -0
  35. data/lib/aarch64/instructions/bics.rb +35 -0
  36. data/lib/aarch64/instructions/bl.rb +24 -0
  37. data/lib/aarch64/instructions/blr.rb +24 -0
  38. data/lib/aarch64/instructions/blra.rb +33 -0
  39. data/lib/aarch64/instructions/br.rb +24 -0
  40. data/lib/aarch64/instructions/bra.rb +33 -0
  41. data/lib/aarch64/instructions/brk.rb +24 -0
  42. data/lib/aarch64/instructions/bti.rb +24 -0
  43. data/lib/aarch64/instructions/cas.rb +41 -0
  44. data/lib/aarch64/instructions/casb.rb +35 -0
  45. data/lib/aarch64/instructions/cash.rb +35 -0
  46. data/lib/aarch64/instructions/casp.rb +41 -0
  47. data/lib/aarch64/instructions/cbnz.rb +29 -0
  48. data/lib/aarch64/instructions/cbz.rb +29 -0
  49. data/lib/aarch64/instructions/ccmn_imm.rb +33 -0
  50. data/lib/aarch64/instructions/ccmn_reg.rb +33 -0
  51. data/lib/aarch64/instructions/ccmp_imm.rb +33 -0
  52. data/lib/aarch64/instructions/ccmp_reg.rb +33 -0
  53. data/lib/aarch64/instructions/cfinv.rb +19 -0
  54. data/lib/aarch64/instructions/clrex.rb +24 -0
  55. data/lib/aarch64/instructions/cls_int.rb +29 -0
  56. data/lib/aarch64/instructions/clz_int.rb +29 -0
  57. data/lib/aarch64/instructions/crc32.rb +35 -0
  58. data/lib/aarch64/instructions/crc32c.rb +35 -0
  59. data/lib/aarch64/instructions/csdb.rb +19 -0
  60. data/lib/aarch64/instructions/csel.rb +33 -0
  61. data/lib/aarch64/instructions/csinc.rb +33 -0
  62. data/lib/aarch64/instructions/csinv.rb +33 -0
  63. data/lib/aarch64/instructions/csneg.rb +33 -0
  64. data/lib/aarch64/instructions/dcps.rb +26 -0
  65. data/lib/aarch64/instructions/dgh.rb +19 -0
  66. data/lib/aarch64/instructions/dmb.rb +24 -0
  67. data/lib/aarch64/instructions/drps.rb +19 -0
  68. data/lib/aarch64/instructions/dsb.rb +25 -0
  69. data/lib/aarch64/instructions/eon.rb +35 -0
  70. data/lib/aarch64/instructions/eor_log_imm.rb +35 -0
  71. data/lib/aarch64/instructions/eor_log_shift.rb +35 -0
  72. data/lib/aarch64/instructions/eret.rb +19 -0
  73. data/lib/aarch64/instructions/ereta.rb +25 -0
  74. data/lib/aarch64/instructions/esb.rb +19 -0
  75. data/lib/aarch64/instructions/extr.rb +34 -0
  76. data/lib/aarch64/instructions/gmi.rb +28 -0
  77. data/lib/aarch64/instructions/hint.rb +26 -0
  78. data/lib/aarch64/instructions/hlt.rb +24 -0
  79. data/lib/aarch64/instructions/hvc.rb +24 -0
  80. data/lib/aarch64/instructions/irg.rb +28 -0
  81. data/lib/aarch64/instructions/isb.rb +24 -0
  82. data/lib/aarch64/instructions/ld64b.rb +26 -0
  83. data/lib/aarch64/instructions/ldadd.rb +41 -0
  84. data/lib/aarch64/instructions/ldaddb.rb +35 -0
  85. data/lib/aarch64/instructions/ldaddh.rb +35 -0
  86. data/lib/aarch64/instructions/ldapr.rb +29 -0
  87. data/lib/aarch64/instructions/ldaprb.rb +26 -0
  88. data/lib/aarch64/instructions/ldaprh.rb +26 -0
  89. data/lib/aarch64/instructions/ldapur_gen.rb +33 -0
  90. data/lib/aarch64/instructions/ldar.rb +29 -0
  91. data/lib/aarch64/instructions/ldaxp.rb +31 -0
  92. data/lib/aarch64/instructions/ldaxr.rb +29 -0
  93. data/lib/aarch64/instructions/ldclr.rb +41 -0
  94. data/lib/aarch64/instructions/ldclrb.rb +37 -0
  95. data/lib/aarch64/instructions/ldeor.rb +41 -0
  96. data/lib/aarch64/instructions/ldg.rb +28 -0
  97. data/lib/aarch64/instructions/ldgm.rb +26 -0
  98. data/lib/aarch64/instructions/ldlar.rb +29 -0
  99. data/lib/aarch64/instructions/ldnp_gen.rb +33 -0
  100. data/lib/aarch64/instructions/ldp_gen.rb +39 -0
  101. data/lib/aarch64/instructions/ldpsw.rb +34 -0
  102. data/lib/aarch64/instructions/ldr_imm_gen.rb +35 -0
  103. data/lib/aarch64/instructions/ldr_imm_unsigned.rb +31 -0
  104. data/lib/aarch64/instructions/ldr_lit_gen.rb +29 -0
  105. data/lib/aarch64/instructions/ldr_reg_gen.rb +35 -0
  106. data/lib/aarch64/instructions/ldra.rb +37 -0
  107. data/lib/aarch64/instructions/ldrb_imm.rb +32 -0
  108. data/lib/aarch64/instructions/ldrb_reg.rb +33 -0
  109. data/lib/aarch64/instructions/ldrb_unsigned.rb +28 -0
  110. data/lib/aarch64/instructions/ldrh_imm.rb +32 -0
  111. data/lib/aarch64/instructions/ldrh_reg.rb +32 -0
  112. data/lib/aarch64/instructions/ldrh_unsigned.rb +28 -0
  113. data/lib/aarch64/instructions/ldrsb_imm.rb +37 -0
  114. data/lib/aarch64/instructions/ldrsb_reg.rb +37 -0
  115. data/lib/aarch64/instructions/ldrsb_unsigned.rb +35 -0
  116. data/lib/aarch64/instructions/ldrsh_imm.rb +37 -0
  117. data/lib/aarch64/instructions/ldrsh_reg.rb +35 -0
  118. data/lib/aarch64/instructions/ldrsh_unsigned.rb +31 -0
  119. data/lib/aarch64/instructions/ldrsw_imm.rb +32 -0
  120. data/lib/aarch64/instructions/ldrsw_lit.rb +26 -0
  121. data/lib/aarch64/instructions/ldrsw_reg.rb +32 -0
  122. data/lib/aarch64/instructions/ldrsw_unsigned.rb +30 -0
  123. data/lib/aarch64/instructions/ldset.rb +41 -0
  124. data/lib/aarch64/instructions/ldsetb.rb +35 -0
  125. data/lib/aarch64/instructions/ldseth.rb +35 -0
  126. data/lib/aarch64/instructions/ldsmax.rb +41 -0
  127. data/lib/aarch64/instructions/ldsmaxb.rb +35 -0
  128. data/lib/aarch64/instructions/ldsmaxh.rb +35 -0
  129. data/lib/aarch64/instructions/ldsmin.rb +41 -0
  130. data/lib/aarch64/instructions/ldsminb.rb +35 -0
  131. data/lib/aarch64/instructions/ldsminh.rb +35 -0
  132. data/lib/aarch64/instructions/ldtr.rb +31 -0
  133. data/lib/aarch64/instructions/ldtrb.rb +28 -0
  134. data/lib/aarch64/instructions/ldtrh.rb +28 -0
  135. data/lib/aarch64/instructions/ldtrsb.rb +31 -0
  136. data/lib/aarch64/instructions/ldtrsh.rb +31 -0
  137. data/lib/aarch64/instructions/ldtrsw.rb +28 -0
  138. data/lib/aarch64/instructions/ldumax.rb +41 -0
  139. data/lib/aarch64/instructions/ldumaxb.rb +35 -0
  140. data/lib/aarch64/instructions/ldumaxh.rb +35 -0
  141. data/lib/aarch64/instructions/ldumin.rb +41 -0
  142. data/lib/aarch64/instructions/lduminb.rb +35 -0
  143. data/lib/aarch64/instructions/lduminh.rb +35 -0
  144. data/lib/aarch64/instructions/ldur_gen.rb +31 -0
  145. data/lib/aarch64/instructions/ldursb.rb +31 -0
  146. data/lib/aarch64/instructions/ldursh.rb +31 -0
  147. data/lib/aarch64/instructions/ldursw.rb +28 -0
  148. data/lib/aarch64/instructions/ldxp.rb +31 -0
  149. data/lib/aarch64/instructions/ldxr.rb +29 -0
  150. data/lib/aarch64/instructions/lslv.rb +31 -0
  151. data/lib/aarch64/instructions/lsrv.rb +31 -0
  152. data/lib/aarch64/instructions/madd.rb +33 -0
  153. data/lib/aarch64/instructions/movk.rb +31 -0
  154. data/lib/aarch64/instructions/movn.rb +31 -0
  155. data/lib/aarch64/instructions/movz.rb +31 -0
  156. data/lib/aarch64/instructions/mrs.rb +34 -0
  157. data/lib/aarch64/instructions/msr_imm.rb +28 -0
  158. data/lib/aarch64/instructions/msr_reg.rb +34 -0
  159. data/lib/aarch64/instructions/msub.rb +33 -0
  160. data/lib/aarch64/instructions/nop.rb +19 -0
  161. data/lib/aarch64/instructions/orn_log_shift.rb +35 -0
  162. data/lib/aarch64/instructions/orr_log_imm.rb +35 -0
  163. data/lib/aarch64/instructions/orr_log_shift.rb +35 -0
  164. data/lib/aarch64/instructions/pacda.rb +29 -0
  165. data/lib/aarch64/instructions/pacdb.rb +29 -0
  166. data/lib/aarch64/instructions/pacga.rb +28 -0
  167. data/lib/aarch64/instructions/pacia.rb +32 -0
  168. data/lib/aarch64/instructions/pacia2.rb +28 -0
  169. data/lib/aarch64/instructions/pacib.rb +32 -0
  170. data/lib/aarch64/instructions/prfm_imm.rb +28 -0
  171. data/lib/aarch64/instructions/prfm_lit.rb +26 -0
  172. data/lib/aarch64/instructions/prfm_reg.rb +32 -0
  173. data/lib/aarch64/instructions/prfum.rb +28 -0
  174. data/lib/aarch64/instructions/psb.rb +19 -0
  175. data/lib/aarch64/instructions/rbit_int.rb +29 -0
  176. data/lib/aarch64/instructions/ret.rb +24 -0
  177. data/lib/aarch64/instructions/reta.rb +25 -0
  178. data/lib/aarch64/instructions/rev.rb +31 -0
  179. data/lib/aarch64/instructions/rmif.rb +28 -0
  180. data/lib/aarch64/instructions/rorv.rb +31 -0
  181. data/lib/aarch64/instructions/sb.rb +19 -0
  182. data/lib/aarch64/instructions/sbc.rb +31 -0
  183. data/lib/aarch64/instructions/sbcs.rb +31 -0
  184. data/lib/aarch64/instructions/sbfm.rb +34 -0
  185. data/lib/aarch64/instructions/sdiv.rb +31 -0
  186. data/lib/aarch64/instructions/setf.rb +27 -0
  187. data/lib/aarch64/instructions/setgp.rb +25 -0
  188. data/lib/aarch64/instructions/setgpn.rb +25 -0
  189. data/lib/aarch64/instructions/setgpt.rb +25 -0
  190. data/lib/aarch64/instructions/setgptn.rb +25 -0
  191. data/lib/aarch64/instructions/setp.rb +25 -0
  192. data/lib/aarch64/instructions/setpn.rb +25 -0
  193. data/lib/aarch64/instructions/setpt.rb +25 -0
  194. data/lib/aarch64/instructions/setptn.rb +25 -0
  195. data/lib/aarch64/instructions/sev.rb +18 -0
  196. data/lib/aarch64/instructions/sevl.rb +18 -0
  197. data/lib/aarch64/instructions/smaddl.rb +30 -0
  198. data/lib/aarch64/instructions/smc.rb +24 -0
  199. data/lib/aarch64/instructions/smsubl.rb +30 -0
  200. data/lib/aarch64/instructions/smulh.rb +28 -0
  201. data/lib/aarch64/instructions/st2g.rb +32 -0
  202. data/lib/aarch64/instructions/st64b.rb +26 -0
  203. data/lib/aarch64/instructions/st64bv.rb +28 -0
  204. data/lib/aarch64/instructions/st64bv0.rb +28 -0
  205. data/lib/aarch64/instructions/stg.rb +32 -0
  206. data/lib/aarch64/instructions/stgm.rb +26 -0
  207. data/lib/aarch64/instructions/stgp.rb +34 -0
  208. data/lib/aarch64/instructions/stllr.rb +29 -0
  209. data/lib/aarch64/instructions/stllrb.rb +26 -0
  210. data/lib/aarch64/instructions/stllrh.rb +26 -0
  211. data/lib/aarch64/instructions/stlr.rb +29 -0
  212. data/lib/aarch64/instructions/stlrb.rb +26 -0
  213. data/lib/aarch64/instructions/stlrh.rb +26 -0
  214. data/lib/aarch64/instructions/stlur_gen.rb +31 -0
  215. data/lib/aarch64/instructions/stlxp.rb +33 -0
  216. data/lib/aarch64/instructions/stlxr.rb +31 -0
  217. data/lib/aarch64/instructions/stlxrb.rb +28 -0
  218. data/lib/aarch64/instructions/stlxrh.rb +28 -0
  219. data/lib/aarch64/instructions/stnp_gen.rb +33 -0
  220. data/lib/aarch64/instructions/stp_gen.rb +39 -0
  221. data/lib/aarch64/instructions/str_imm_gen.rb +37 -0
  222. data/lib/aarch64/instructions/str_imm_unsigned.rb +31 -0
  223. data/lib/aarch64/instructions/str_reg_gen.rb +35 -0
  224. data/lib/aarch64/instructions/strb_imm.rb +32 -0
  225. data/lib/aarch64/instructions/strb_imm_unsigned.rb +28 -0
  226. data/lib/aarch64/instructions/strb_reg.rb +33 -0
  227. data/lib/aarch64/instructions/strh_imm.rb +32 -0
  228. data/lib/aarch64/instructions/strh_imm_unsigned.rb +28 -0
  229. data/lib/aarch64/instructions/strh_reg.rb +32 -0
  230. data/lib/aarch64/instructions/sttr.rb +31 -0
  231. data/lib/aarch64/instructions/stur_gen.rb +31 -0
  232. data/lib/aarch64/instructions/stxp.rb +33 -0
  233. data/lib/aarch64/instructions/stxr.rb +31 -0
  234. data/lib/aarch64/instructions/stxrb.rb +28 -0
  235. data/lib/aarch64/instructions/stxrh.rb +28 -0
  236. data/lib/aarch64/instructions/stz2g.rb +32 -0
  237. data/lib/aarch64/instructions/stzg.rb +32 -0
  238. data/lib/aarch64/instructions/stzgm.rb +26 -0
  239. data/lib/aarch64/instructions/sub_addsub_ext.rb +35 -0
  240. data/lib/aarch64/instructions/sub_addsub_imm.rb +33 -0
  241. data/lib/aarch64/instructions/sub_addsub_shift.rb +35 -0
  242. data/lib/aarch64/instructions/subg.rb +30 -0
  243. data/lib/aarch64/instructions/subp.rb +28 -0
  244. data/lib/aarch64/instructions/subps.rb +28 -0
  245. data/lib/aarch64/instructions/subs_addsub_ext.rb +35 -0
  246. data/lib/aarch64/instructions/subs_addsub_imm.rb +33 -0
  247. data/lib/aarch64/instructions/subs_addsub_shift.rb +35 -0
  248. data/lib/aarch64/instructions/svc.rb +24 -0
  249. data/lib/aarch64/instructions/swp.rb +41 -0
  250. data/lib/aarch64/instructions/swpb.rb +35 -0
  251. data/lib/aarch64/instructions/swph.rb +35 -0
  252. data/lib/aarch64/instructions/sys.rb +32 -0
  253. data/lib/aarch64/instructions/sysl.rb +32 -0
  254. data/lib/aarch64/instructions/tbnz.rb +30 -0
  255. data/lib/aarch64/instructions/tbz.rb +30 -0
  256. data/lib/aarch64/instructions/tsb.rb +18 -0
  257. data/lib/aarch64/instructions/ubfm.rb +34 -0
  258. data/lib/aarch64/instructions/udf_perm_undef.rb +24 -0
  259. data/lib/aarch64/instructions/udiv.rb +31 -0
  260. data/lib/aarch64/instructions/umaddl.rb +30 -0
  261. data/lib/aarch64/instructions/umsubl.rb +30 -0
  262. data/lib/aarch64/instructions/umulh.rb +28 -0
  263. data/lib/aarch64/instructions/wfe.rb +19 -0
  264. data/lib/aarch64/instructions/wfet.rb +24 -0
  265. data/lib/aarch64/instructions/wfi.rb +19 -0
  266. data/lib/aarch64/instructions/wfit.rb +24 -0
  267. data/lib/aarch64/instructions/xaflag.rb +19 -0
  268. data/lib/aarch64/instructions/xpac.rb +28 -0
  269. data/lib/aarch64/instructions/xpaclri.rb +18 -0
  270. data/lib/aarch64/instructions/yield.rb +19 -0
  271. data/lib/aarch64/instructions.rb +266 -0
  272. data/lib/aarch64/system_registers/mrs_msr_64.rb +395 -0
  273. data/lib/aarch64/utils.rb +325 -0
  274. data/lib/aarch64/version.rb +3 -0
  275. data/lib/aarch64.rb +2857 -0
  276. data/test/all_adds_test.rb +129 -0
  277. data/test/base_instructions_test.rb +9263 -0
  278. data/test/dsl_test.rb +11 -0
  279. data/test/helper.rb +51 -0
  280. data/test/not_supported_yet_test.rb +55 -0
  281. metadata +382 -0
@@ -0,0 +1,31 @@
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+ module AArch64
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+ module Instructions
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+ # LDRSH (immediate) -- A64
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+ # Load Register Signed Halfword (immediate)
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+ # LDRSH <Wt>, [<Xn|SP>{, #<pimm>}]
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+ # LDRSH <Xt>, [<Xn|SP>{, #<pimm>}]
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+ class LDRSH_unsigned
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+ def initialize rt, rn, imm12, opc
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+ @rt = rt
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+ @rn = rn
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+ @imm12 = imm12
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+ @opc = opc
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+ end
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+
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+ def encode
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+ self.LDRSH_unsigned(@opc, @imm12, @rn.to_i, @rt.to_i)
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+ end
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+
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+ private
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+
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+ def LDRSH_unsigned opc, imm12, rn, rt
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+ insn = 0b01_111_0_01_00_0_00000000000_00000_00000
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+ insn |= ((opc & 0x3) << 22)
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+ insn |= ((imm12 & 0xfff) << 10)
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+ insn |= ((rn & 0x1f) << 5)
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+ insn |= (rt & 0x1f)
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+ insn
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+ end
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+ end
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+ end
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+ end
@@ -0,0 +1,32 @@
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+ module AArch64
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+ module Instructions
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+ # LDRSW (immediate) -- A64
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+ # Load Register Signed Word (immediate)
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+ # LDRSW <Xt>, [<Xn|SP>], #<simm>
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+ # LDRSW <Xt>, [<Xn|SP>, #<simm>]!
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+ # LDRSW <Xt>, [<Xn|SP>{, #<pimm>}]
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+ class LDRSW_imm
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+ def initialize rt, rn, imm9, option
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+ @rt = rt
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+ @rn = rn
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+ @imm9 = imm9
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+ @option = option
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+ end
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+
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+ def encode
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+ self.LDRSW_imm(@imm9, @rn.to_i, @rt.to_i, @option)
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+ end
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+
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+ private
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+
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+ def LDRSW_imm imm9, rn, rt, option
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+ insn = 0b10_111_0_00_10_0_000000000_01_00000_00000
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+ insn |= ((imm9 & 0x1ff) << 12)
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+ insn |= ((option & 0x3) << 10)
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+ insn |= ((rn & 0x1f) << 5)
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+ insn |= (rt & 0x1f)
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+ insn
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+ end
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+ end
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+ end
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+ end
@@ -0,0 +1,26 @@
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+ module AArch64
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+ module Instructions
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+ # LDRSW (literal) -- A64
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+ # Load Register Signed Word (literal)
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+ # LDRSW <Xt>, <label>
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+ class LDRSW_lit
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+ def initialize rt, imm19
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+ @rt = rt
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+ @imm19 = imm19
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+ end
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+
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+ def encode
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+ self.LDRSW_lit(@imm19.to_i / 4, @rt.to_i)
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+ end
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+
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+ private
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+
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+ def LDRSW_lit imm19, rt
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+ insn = 0b10_011_0_00_0000000000000000000_00000
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+ insn |= ((imm19 & 0x7ffff) << 5)
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+ insn |= (rt & 0x1f)
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+ insn
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+ end
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+ end
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+ end
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+ end
@@ -0,0 +1,32 @@
1
+ module AArch64
2
+ module Instructions
3
+ # LDRSW (register) -- A64
4
+ # Load Register Signed Word (register)
5
+ # LDRSW <Xt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
6
+ class LDRSW_reg
7
+ def initialize rt, rn, rm, s, option
8
+ @rt = rt
9
+ @rn = rn
10
+ @rm = rm
11
+ @s = s
12
+ @option = option
13
+ end
14
+
15
+ def encode
16
+ self.LDRSW_reg(@rm.to_i, @option, @s, @rn.to_i, @rt.to_i)
17
+ end
18
+
19
+ private
20
+
21
+ def LDRSW_reg rm, option, s, rn, rt
22
+ insn = 0b10_111_0_00_10_1_00000_000_0_10_00000_00000
23
+ insn |= ((rm & 0x1f) << 16)
24
+ insn |= ((option & 0x7) << 13)
25
+ insn |= ((s & 0x1) << 12)
26
+ insn |= ((rn & 0x1f) << 5)
27
+ insn |= (rt & 0x1f)
28
+ insn
29
+ end
30
+ end
31
+ end
32
+ end
@@ -0,0 +1,30 @@
1
+ module AArch64
2
+ module Instructions
3
+ # LDRSW (immediate) -- A64
4
+ # Load Register Signed Word (immediate)
5
+ # LDRSW <Xt>, [<Xn|SP>], #<simm>
6
+ # LDRSW <Xt>, [<Xn|SP>, #<simm>]!
7
+ # LDRSW <Xt>, [<Xn|SP>{, #<pimm>}]
8
+ class LDRSW_unsigned
9
+ def initialize rt, rn, imm12
10
+ @rt = rt
11
+ @rn = rn
12
+ @imm12 = imm12
13
+ end
14
+
15
+ def encode
16
+ self.LDRSW_unsigned(@imm12, @rn.to_i, @rt.to_i)
17
+ end
18
+
19
+ private
20
+
21
+ def LDRSW_unsigned imm12, rn, rt
22
+ insn = 0b10_111_0_01_10_0_00000000000_00000_00000
23
+ insn |= ((imm12 & 0xfff) << 10)
24
+ insn |= ((rn & 0x1f) << 5)
25
+ insn |= (rt & 0x1f)
26
+ insn
27
+ end
28
+ end
29
+ end
30
+ end
@@ -0,0 +1,41 @@
1
+ module AArch64
2
+ module Instructions
3
+ # LDSET, LDSETA, LDSETAL, LDSETL -- A64
4
+ # Atomic bit set on word or doubleword in memory
5
+ # LDSET <Ws>, <Wt>, [<Xn|SP>]
6
+ # LDSETA <Ws>, <Wt>, [<Xn|SP>]
7
+ # LDSETAL <Ws>, <Wt>, [<Xn|SP>]
8
+ # LDSETL <Ws>, <Wt>, [<Xn|SP>]
9
+ # LDSET <Xs>, <Xt>, [<Xn|SP>]
10
+ # LDSETA <Xs>, <Xt>, [<Xn|SP>]
11
+ # LDSETAL <Xs>, <Xt>, [<Xn|SP>]
12
+ # LDSETL <Xs>, <Xt>, [<Xn|SP>]
13
+ class LDSET
14
+ def initialize rs, rt, rn, size, a, r
15
+ @rs = rs
16
+ @rt = rt
17
+ @rn = rn
18
+ @size = size
19
+ @a = a
20
+ @r = r
21
+ end
22
+
23
+ def encode
24
+ self.LDSET(@size, @a, @r.to_i, @rs.to_i, @rn.to_i, @rt.to_i)
25
+ end
26
+
27
+ private
28
+
29
+ def LDSET size, a, r, rs, rn, rt
30
+ insn = 0b00_111_0_00_0_0_1_00000_0_011_00_00000_00000
31
+ insn |= ((size & 0x3) << 30)
32
+ insn |= ((a & 0x1) << 23)
33
+ insn |= ((r & 0x1) << 22)
34
+ insn |= ((rs & 0x1f) << 16)
35
+ insn |= ((rn & 0x1f) << 5)
36
+ insn |= (rt & 0x1f)
37
+ insn
38
+ end
39
+ end
40
+ end
41
+ end
@@ -0,0 +1,35 @@
1
+ module AArch64
2
+ module Instructions
3
+ # LDSETB, LDSETAB, LDSETALB, LDSETLB -- A64
4
+ # Atomic bit set on byte in memory
5
+ # LDSETAB <Ws>, <Wt>, [<Xn|SP>]
6
+ # LDSETALB <Ws>, <Wt>, [<Xn|SP>]
7
+ # LDSETB <Ws>, <Wt>, [<Xn|SP>]
8
+ # LDSETLB <Ws>, <Wt>, [<Xn|SP>]
9
+ class LDSETB
10
+ def initialize rs, rt, rn, a, r
11
+ @rs = rs
12
+ @rt = rt
13
+ @rn = rn
14
+ @a = a
15
+ @r = r
16
+ end
17
+
18
+ def encode
19
+ self.LDSETB(@a, @r.to_i, @rs.to_i, @rn.to_i, @rt.to_i)
20
+ end
21
+
22
+ private
23
+
24
+ def LDSETB a, r, rs, rn, rt
25
+ insn = 0b00_111_0_00_0_0_1_00000_0_011_00_00000_00000
26
+ insn |= ((a & 0x1) << 23)
27
+ insn |= ((r & 0x1) << 22)
28
+ insn |= ((rs & 0x1f) << 16)
29
+ insn |= ((rn & 0x1f) << 5)
30
+ insn |= (rt & 0x1f)
31
+ insn
32
+ end
33
+ end
34
+ end
35
+ end
@@ -0,0 +1,35 @@
1
+ module AArch64
2
+ module Instructions
3
+ # LDSETH, LDSETAH, LDSETALH, LDSETLH -- A64
4
+ # Atomic bit set on halfword in memory
5
+ # LDSETAH <Ws>, <Wt>, [<Xn|SP>]
6
+ # LDSETALH <Ws>, <Wt>, [<Xn|SP>]
7
+ # LDSETH <Ws>, <Wt>, [<Xn|SP>]
8
+ # LDSETLH <Ws>, <Wt>, [<Xn|SP>]
9
+ class LDSETH
10
+ def initialize rs, rt, rn, a, r
11
+ @rs = rs
12
+ @rt = rt
13
+ @rn = rn
14
+ @a = a
15
+ @r = r
16
+ end
17
+
18
+ def encode
19
+ self.LDSETH(@a, @r.to_i, @rs.to_i, @rn.to_i, @rt.to_i)
20
+ end
21
+
22
+ private
23
+
24
+ def LDSETH a, r, rs, rn, rt
25
+ insn = 0b01_111_0_00_0_0_1_00000_0_011_00_00000_00000
26
+ insn |= ((a & 0x1) << 23)
27
+ insn |= ((r & 0x1) << 22)
28
+ insn |= ((rs & 0x1f) << 16)
29
+ insn |= ((rn & 0x1f) << 5)
30
+ insn |= (rt & 0x1f)
31
+ insn
32
+ end
33
+ end
34
+ end
35
+ end
@@ -0,0 +1,41 @@
1
+ module AArch64
2
+ module Instructions
3
+ # LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL -- A64
4
+ # Atomic signed maximum on word or doubleword in memory
5
+ # LDSMAX <Ws>, <Wt>, [<Xn|SP>]
6
+ # LDSMAXA <Ws>, <Wt>, [<Xn|SP>]
7
+ # LDSMAXAL <Ws>, <Wt>, [<Xn|SP>]
8
+ # LDSMAXL <Ws>, <Wt>, [<Xn|SP>]
9
+ # LDSMAX <Xs>, <Xt>, [<Xn|SP>]
10
+ # LDSMAXA <Xs>, <Xt>, [<Xn|SP>]
11
+ # LDSMAXAL <Xs>, <Xt>, [<Xn|SP>]
12
+ # LDSMAXL <Xs>, <Xt>, [<Xn|SP>]
13
+ class LDSMAX
14
+ def initialize rs, rt, rn, size, a, r
15
+ @rs = rs
16
+ @rt = rt
17
+ @rn = rn
18
+ @size = size
19
+ @a = a
20
+ @r = r
21
+ end
22
+
23
+ def encode
24
+ self.LDSMAX(@size, @a, @r.to_i, @rs.to_i, @rn.to_i, @rt.to_i)
25
+ end
26
+
27
+ private
28
+
29
+ def LDSMAX size, a, r, rs, rn, rt
30
+ insn = 0b00_111_0_00_0_0_1_00000_0_100_00_00000_00000
31
+ insn |= ((size & 0x3) << 30)
32
+ insn |= ((a & 0x1) << 23)
33
+ insn |= ((r & 0x1) << 22)
34
+ insn |= ((rs & 0x1f) << 16)
35
+ insn |= ((rn & 0x1f) << 5)
36
+ insn |= (rt & 0x1f)
37
+ insn
38
+ end
39
+ end
40
+ end
41
+ end
@@ -0,0 +1,35 @@
1
+ module AArch64
2
+ module Instructions
3
+ # LDSMAXB, LDSMAXAB, LDSMAXALB, LDSMAXLB -- A64
4
+ # Atomic signed maximum on byte in memory
5
+ # LDSMAXAB <Ws>, <Wt>, [<Xn|SP>]
6
+ # LDSMAXALB <Ws>, <Wt>, [<Xn|SP>]
7
+ # LDSMAXB <Ws>, <Wt>, [<Xn|SP>]
8
+ # LDSMAXLB <Ws>, <Wt>, [<Xn|SP>]
9
+ class LDSMAXB
10
+ def initialize rs, rt, rn, a, r
11
+ @rs = rs
12
+ @rt = rt
13
+ @rn = rn
14
+ @a = a
15
+ @r = r
16
+ end
17
+
18
+ def encode
19
+ self.LDSMAXB(@a, @r.to_i, @rs.to_i, @rn.to_i, @rt.to_i)
20
+ end
21
+
22
+ private
23
+
24
+ def LDSMAXB a, r, rs, rn, rt
25
+ insn = 0b00_111_0_00_0_0_1_00000_0_100_00_00000_00000
26
+ insn |= ((a & 0x1) << 23)
27
+ insn |= ((r & 0x1) << 22)
28
+ insn |= ((rs & 0x1f) << 16)
29
+ insn |= ((rn & 0x1f) << 5)
30
+ insn |= (rt & 0x1f)
31
+ insn
32
+ end
33
+ end
34
+ end
35
+ end
@@ -0,0 +1,35 @@
1
+ module AArch64
2
+ module Instructions
3
+ # LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLH -- A64
4
+ # Atomic signed maximum on halfword in memory
5
+ # LDSMAXAH <Ws>, <Wt>, [<Xn|SP>]
6
+ # LDSMAXALH <Ws>, <Wt>, [<Xn|SP>]
7
+ # LDSMAXH <Ws>, <Wt>, [<Xn|SP>]
8
+ # LDSMAXLH <Ws>, <Wt>, [<Xn|SP>]
9
+ class LDSMAXH
10
+ def initialize rs, rt, rn, a, r
11
+ @rs = rs
12
+ @rt = rt
13
+ @rn = rn
14
+ @a = a
15
+ @r = r
16
+ end
17
+
18
+ def encode
19
+ self.LDSMAXH(@a, @r.to_i, @rs.to_i, @rn.to_i, @rt.to_i)
20
+ end
21
+
22
+ private
23
+
24
+ def LDSMAXH a, r, rs, rn, rt
25
+ insn = 0b01_111_0_00_0_0_1_00000_0_100_00_00000_00000
26
+ insn |= ((a & 0x1) << 23)
27
+ insn |= ((r & 0x1) << 22)
28
+ insn |= ((rs & 0x1f) << 16)
29
+ insn |= ((rn & 0x1f) << 5)
30
+ insn |= (rt & 0x1f)
31
+ insn
32
+ end
33
+ end
34
+ end
35
+ end
@@ -0,0 +1,41 @@
1
+ module AArch64
2
+ module Instructions
3
+ # LDSMIN, LDSMINA, LDSMINAL, LDSMINL -- A64
4
+ # Atomic signed minimum on word or doubleword in memory
5
+ # LDSMIN <Ws>, <Wt>, [<Xn|SP>]
6
+ # LDSMINA <Ws>, <Wt>, [<Xn|SP>]
7
+ # LDSMINAL <Ws>, <Wt>, [<Xn|SP>]
8
+ # LDSMINL <Ws>, <Wt>, [<Xn|SP>]
9
+ # LDSMIN <Xs>, <Xt>, [<Xn|SP>]
10
+ # LDSMINA <Xs>, <Xt>, [<Xn|SP>]
11
+ # LDSMINAL <Xs>, <Xt>, [<Xn|SP>]
12
+ # LDSMINL <Xs>, <Xt>, [<Xn|SP>]
13
+ class LDSMIN
14
+ def initialize rs, rt, rn, size, a, r
15
+ @rs = rs
16
+ @rt = rt
17
+ @rn = rn
18
+ @size = size
19
+ @a = a
20
+ @r = r
21
+ end
22
+
23
+ def encode
24
+ self.LDSMIN(@size, @a, @r.to_i, @rs.to_i, @rn.to_i, @rt.to_i)
25
+ end
26
+
27
+ private
28
+
29
+ def LDSMIN size, a, r, rs, rn, rt
30
+ insn = 0b00_111_0_00_0_0_1_00000_0_101_00_00000_00000
31
+ insn |= ((size & 0x3) << 30)
32
+ insn |= ((a & 0x1) << 23)
33
+ insn |= ((r & 0x1) << 22)
34
+ insn |= ((rs & 0x1f) << 16)
35
+ insn |= ((rn & 0x1f) << 5)
36
+ insn |= (rt & 0x1f)
37
+ insn
38
+ end
39
+ end
40
+ end
41
+ end
@@ -0,0 +1,35 @@
1
+ module AArch64
2
+ module Instructions
3
+ # LDSMINB, LDSMINAB, LDSMINALB, LDSMINLB -- A64
4
+ # Atomic signed minimum on byte in memory
5
+ # LDSMINAB <Ws>, <Wt>, [<Xn|SP>]
6
+ # LDSMINALB <Ws>, <Wt>, [<Xn|SP>]
7
+ # LDSMINB <Ws>, <Wt>, [<Xn|SP>]
8
+ # LDSMINLB <Ws>, <Wt>, [<Xn|SP>]
9
+ class LDSMINB
10
+ def initialize rs, rt, rn, a, r
11
+ @rs = rs
12
+ @rt = rt
13
+ @rn = rn
14
+ @a = a
15
+ @r = r
16
+ end
17
+
18
+ def encode
19
+ self.LDSMINB(@a, @r.to_i, @rs.to_i, @rn.to_i, @rt.to_i)
20
+ end
21
+
22
+ private
23
+
24
+ def LDSMINB a, r, rs, rn, rt
25
+ insn = 0b00_111_0_00_0_0_1_00000_0_101_00_00000_00000
26
+ insn |= ((a & 0x1) << 23)
27
+ insn |= ((r & 0x1) << 22)
28
+ insn |= ((rs & 0x1f) << 16)
29
+ insn |= ((rn & 0x1f) << 5)
30
+ insn |= (rt & 0x1f)
31
+ insn
32
+ end
33
+ end
34
+ end
35
+ end
@@ -0,0 +1,35 @@
1
+ module AArch64
2
+ module Instructions
3
+ # LDSMINH, LDSMINAH, LDSMINALH, LDSMINLH -- A64
4
+ # Atomic signed minimum on halfword in memory
5
+ # LDSMINAH <Ws>, <Wt>, [<Xn|SP>]
6
+ # LDSMINALH <Ws>, <Wt>, [<Xn|SP>]
7
+ # LDSMINH <Ws>, <Wt>, [<Xn|SP>]
8
+ # LDSMINLH <Ws>, <Wt>, [<Xn|SP>]
9
+ class LDSMINH
10
+ def initialize rs, rt, rn, a, r
11
+ @rs = rs
12
+ @rt = rt
13
+ @rn = rn
14
+ @a = a
15
+ @r = r
16
+ end
17
+
18
+ def encode
19
+ self.LDSMINH(@a, @r.to_i, @rs.to_i, @rn.to_i, @rt.to_i)
20
+ end
21
+
22
+ private
23
+
24
+ def LDSMINH a, r, rs, rn, rt
25
+ insn = 0b01_111_0_00_0_0_1_00000_0_101_00_00000_00000
26
+ insn |= ((a & 0x1) << 23)
27
+ insn |= ((r & 0x1) << 22)
28
+ insn |= ((rs & 0x1f) << 16)
29
+ insn |= ((rn & 0x1f) << 5)
30
+ insn |= (rt & 0x1f)
31
+ insn
32
+ end
33
+ end
34
+ end
35
+ end
@@ -0,0 +1,31 @@
1
+ module AArch64
2
+ module Instructions
3
+ # LDTR -- A64
4
+ # Load Register (unprivileged)
5
+ # LDTR <Wt>, [<Xn|SP>{, #<simm>}]
6
+ # LDTR <Xt>, [<Xn|SP>{, #<simm>}]
7
+ class LDTR
8
+ def initialize rt, rn, imm9, size
9
+ @rt = rt
10
+ @rn = rn
11
+ @imm9 = imm9
12
+ @size = size
13
+ end
14
+
15
+ def encode
16
+ self.LDTR(@size, @imm9, @rn.to_i, @rt.to_i)
17
+ end
18
+
19
+ private
20
+
21
+ def LDTR size, imm9, rn, rt
22
+ insn = 0b00_111_0_00_01_0_000000000_10_00000_00000
23
+ insn |= ((size & 0x3) << 30)
24
+ insn |= ((imm9 & 0x1ff) << 12)
25
+ insn |= ((rn & 0x1f) << 5)
26
+ insn |= (rt & 0x1f)
27
+ insn
28
+ end
29
+ end
30
+ end
31
+ end
@@ -0,0 +1,28 @@
1
+ module AArch64
2
+ module Instructions
3
+ # LDTRB -- A64
4
+ # Load Register Byte (unprivileged)
5
+ # LDTRB <Wt>, [<Xn|SP>{, #<simm>}]
6
+ class LDTRB
7
+ def initialize rt, rn, imm9
8
+ @rt = rt
9
+ @rn = rn
10
+ @imm9 = imm9
11
+ end
12
+
13
+ def encode
14
+ self.LDTRB(@imm9, @rn.to_i, @rt.to_i)
15
+ end
16
+
17
+ private
18
+
19
+ def LDTRB imm9, rn, rt
20
+ insn = 0b00_111_0_00_01_0_000000000_10_00000_00000
21
+ insn |= ((imm9 & 0x1ff) << 12)
22
+ insn |= ((rn & 0x1f) << 5)
23
+ insn |= (rt & 0x1f)
24
+ insn
25
+ end
26
+ end
27
+ end
28
+ end
@@ -0,0 +1,28 @@
1
+ module AArch64
2
+ module Instructions
3
+ # LDTRH -- A64
4
+ # Load Register Halfword (unprivileged)
5
+ # LDTRH <Wt>, [<Xn|SP>{, #<simm>}]
6
+ class LDTRH
7
+ def initialize rt, rn, imm9
8
+ @rt = rt
9
+ @rn = rn
10
+ @imm9 = imm9
11
+ end
12
+
13
+ def encode
14
+ self.LDTRH(@imm9, @rn.to_i, @rt.to_i)
15
+ end
16
+
17
+ private
18
+
19
+ def LDTRH imm9, rn, rt
20
+ insn = 0b01_111_0_00_01_0_000000000_10_00000_00000
21
+ insn |= ((imm9 & 0x1ff) << 12)
22
+ insn |= ((rn & 0x1f) << 5)
23
+ insn |= (rt & 0x1f)
24
+ insn
25
+ end
26
+ end
27
+ end
28
+ end
@@ -0,0 +1,31 @@
1
+ module AArch64
2
+ module Instructions
3
+ # LDTRSB -- A64
4
+ # Load Register Signed Byte (unprivileged)
5
+ # LDTRSB <Wt>, [<Xn|SP>{, #<simm>}]
6
+ # LDTRSB <Xt>, [<Xn|SP>{, #<simm>}]
7
+ class LDTRSB
8
+ def initialize rt, rn, imm9, opc
9
+ @rt = rt
10
+ @rn = rn
11
+ @imm9 = imm9
12
+ @opc = opc
13
+ end
14
+
15
+ def encode
16
+ self.LDTRSB(@opc, @imm9, @rn.to_i, @rt.to_i)
17
+ end
18
+
19
+ private
20
+
21
+ def LDTRSB opc, imm9, rn, rt
22
+ insn = 0b00_111_0_00_00_0_000000000_10_00000_00000
23
+ insn |= ((opc & 0x3) << 22)
24
+ insn |= ((imm9 & 0x1ff) << 12)
25
+ insn |= ((rn & 0x1f) << 5)
26
+ insn |= (rt & 0x1f)
27
+ insn
28
+ end
29
+ end
30
+ end
31
+ end
@@ -0,0 +1,31 @@
1
+ module AArch64
2
+ module Instructions
3
+ # LDTRSH -- A64
4
+ # Load Register Signed Halfword (unprivileged)
5
+ # LDTRSH <Wt>, [<Xn|SP>{, #<simm>}]
6
+ # LDTRSH <Xt>, [<Xn|SP>{, #<simm>}]
7
+ class LDTRSH
8
+ def initialize rt, rn, imm9, opc
9
+ @rt = rt
10
+ @rn = rn
11
+ @imm9 = imm9
12
+ @opc = opc
13
+ end
14
+
15
+ def encode
16
+ self.LDTRSH(@opc, @imm9, @rn.to_i, @rt.to_i)
17
+ end
18
+
19
+ private
20
+
21
+ def LDTRSH opc, imm9, rn, rt
22
+ insn = 0b01_111_0_00_00_0_000000000_10_00000_00000
23
+ insn |= ((opc & 0x3) << 22)
24
+ insn |= ((imm9 & 0x1ff) << 12)
25
+ insn |= ((rn & 0x1f) << 5)
26
+ insn |= (rt & 0x1f)
27
+ insn
28
+ end
29
+ end
30
+ end
31
+ end
@@ -0,0 +1,28 @@
1
+ module AArch64
2
+ module Instructions
3
+ # LDTRSW -- A64
4
+ # Load Register Signed Word (unprivileged)
5
+ # LDTRSW <Xt>, [<Xn|SP>{, #<simm>}]
6
+ class LDTRSW
7
+ def initialize rt, rn, imm9
8
+ @rt = rt
9
+ @rn = rn
10
+ @imm9 = imm9
11
+ end
12
+
13
+ def encode
14
+ self.LDTRSW(@imm9, @rn.to_i, @rt.to_i)
15
+ end
16
+
17
+ private
18
+
19
+ def LDTRSW imm9, rn, rt
20
+ insn = 0b10_111_0_00_10_0_000000000_10_00000_00000
21
+ insn |= ((imm9 & 0x1ff) << 12)
22
+ insn |= ((rn & 0x1f) << 5)
23
+ insn |= (rt & 0x1f)
24
+ insn
25
+ end
26
+ end
27
+ end
28
+ end