aarch64 1.0.0
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- checksums.yaml +7 -0
- data/CODE_OF_CONDUCT.md +77 -0
- data/Gemfile +3 -0
- data/LICENSE +201 -0
- data/README.md +77 -0
- data/Rakefile +168 -0
- data/aarch64.gemspec +21 -0
- data/bin/build_instructions.rb +102 -0
- data/lib/aarch64/instructions/adc.rb +31 -0
- data/lib/aarch64/instructions/adcs.rb +30 -0
- data/lib/aarch64/instructions/add_addsub_ext.rb +35 -0
- data/lib/aarch64/instructions/add_addsub_imm.rb +32 -0
- data/lib/aarch64/instructions/add_addsub_shift.rb +35 -0
- data/lib/aarch64/instructions/addg.rb +30 -0
- data/lib/aarch64/instructions/adds_addsub_ext.rb +35 -0
- data/lib/aarch64/instructions/adds_addsub_imm.rb +33 -0
- data/lib/aarch64/instructions/adds_addsub_shift.rb +35 -0
- data/lib/aarch64/instructions/adr.rb +28 -0
- data/lib/aarch64/instructions/adrp.rb +28 -0
- data/lib/aarch64/instructions/and_log_imm.rb +35 -0
- data/lib/aarch64/instructions/and_log_shift.rb +35 -0
- data/lib/aarch64/instructions/ands_log_imm.rb +35 -0
- data/lib/aarch64/instructions/ands_log_shift.rb +35 -0
- data/lib/aarch64/instructions/asrv.rb +31 -0
- data/lib/aarch64/instructions/autda.rb +32 -0
- data/lib/aarch64/instructions/autdb.rb +32 -0
- data/lib/aarch64/instructions/autia.rb +35 -0
- data/lib/aarch64/instructions/autib.rb +35 -0
- data/lib/aarch64/instructions/axflag.rb +18 -0
- data/lib/aarch64/instructions/b_cond.rb +26 -0
- data/lib/aarch64/instructions/b_uncond.rb +24 -0
- data/lib/aarch64/instructions/bc_cond.rb +26 -0
- data/lib/aarch64/instructions/bfm.rb +34 -0
- data/lib/aarch64/instructions/bic_log_shift.rb +35 -0
- data/lib/aarch64/instructions/bics.rb +35 -0
- data/lib/aarch64/instructions/bl.rb +24 -0
- data/lib/aarch64/instructions/blr.rb +24 -0
- data/lib/aarch64/instructions/blra.rb +33 -0
- data/lib/aarch64/instructions/br.rb +24 -0
- data/lib/aarch64/instructions/bra.rb +33 -0
- data/lib/aarch64/instructions/brk.rb +24 -0
- data/lib/aarch64/instructions/bti.rb +24 -0
- data/lib/aarch64/instructions/cas.rb +41 -0
- data/lib/aarch64/instructions/casb.rb +35 -0
- data/lib/aarch64/instructions/cash.rb +35 -0
- data/lib/aarch64/instructions/casp.rb +41 -0
- data/lib/aarch64/instructions/cbnz.rb +29 -0
- data/lib/aarch64/instructions/cbz.rb +29 -0
- data/lib/aarch64/instructions/ccmn_imm.rb +33 -0
- data/lib/aarch64/instructions/ccmn_reg.rb +33 -0
- data/lib/aarch64/instructions/ccmp_imm.rb +33 -0
- data/lib/aarch64/instructions/ccmp_reg.rb +33 -0
- data/lib/aarch64/instructions/cfinv.rb +19 -0
- data/lib/aarch64/instructions/clrex.rb +24 -0
- data/lib/aarch64/instructions/cls_int.rb +29 -0
- data/lib/aarch64/instructions/clz_int.rb +29 -0
- data/lib/aarch64/instructions/crc32.rb +35 -0
- data/lib/aarch64/instructions/crc32c.rb +35 -0
- data/lib/aarch64/instructions/csdb.rb +19 -0
- data/lib/aarch64/instructions/csel.rb +33 -0
- data/lib/aarch64/instructions/csinc.rb +33 -0
- data/lib/aarch64/instructions/csinv.rb +33 -0
- data/lib/aarch64/instructions/csneg.rb +33 -0
- data/lib/aarch64/instructions/dcps.rb +26 -0
- data/lib/aarch64/instructions/dgh.rb +19 -0
- data/lib/aarch64/instructions/dmb.rb +24 -0
- data/lib/aarch64/instructions/drps.rb +19 -0
- data/lib/aarch64/instructions/dsb.rb +25 -0
- data/lib/aarch64/instructions/eon.rb +35 -0
- data/lib/aarch64/instructions/eor_log_imm.rb +35 -0
- data/lib/aarch64/instructions/eor_log_shift.rb +35 -0
- data/lib/aarch64/instructions/eret.rb +19 -0
- data/lib/aarch64/instructions/ereta.rb +25 -0
- data/lib/aarch64/instructions/esb.rb +19 -0
- data/lib/aarch64/instructions/extr.rb +34 -0
- data/lib/aarch64/instructions/gmi.rb +28 -0
- data/lib/aarch64/instructions/hint.rb +26 -0
- data/lib/aarch64/instructions/hlt.rb +24 -0
- data/lib/aarch64/instructions/hvc.rb +24 -0
- data/lib/aarch64/instructions/irg.rb +28 -0
- data/lib/aarch64/instructions/isb.rb +24 -0
- data/lib/aarch64/instructions/ld64b.rb +26 -0
- data/lib/aarch64/instructions/ldadd.rb +41 -0
- data/lib/aarch64/instructions/ldaddb.rb +35 -0
- data/lib/aarch64/instructions/ldaddh.rb +35 -0
- data/lib/aarch64/instructions/ldapr.rb +29 -0
- data/lib/aarch64/instructions/ldaprb.rb +26 -0
- data/lib/aarch64/instructions/ldaprh.rb +26 -0
- data/lib/aarch64/instructions/ldapur_gen.rb +33 -0
- data/lib/aarch64/instructions/ldar.rb +29 -0
- data/lib/aarch64/instructions/ldaxp.rb +31 -0
- data/lib/aarch64/instructions/ldaxr.rb +29 -0
- data/lib/aarch64/instructions/ldclr.rb +41 -0
- data/lib/aarch64/instructions/ldclrb.rb +37 -0
- data/lib/aarch64/instructions/ldeor.rb +41 -0
- data/lib/aarch64/instructions/ldg.rb +28 -0
- data/lib/aarch64/instructions/ldgm.rb +26 -0
- data/lib/aarch64/instructions/ldlar.rb +29 -0
- data/lib/aarch64/instructions/ldnp_gen.rb +33 -0
- data/lib/aarch64/instructions/ldp_gen.rb +39 -0
- data/lib/aarch64/instructions/ldpsw.rb +34 -0
- data/lib/aarch64/instructions/ldr_imm_gen.rb +35 -0
- data/lib/aarch64/instructions/ldr_imm_unsigned.rb +31 -0
- data/lib/aarch64/instructions/ldr_lit_gen.rb +29 -0
- data/lib/aarch64/instructions/ldr_reg_gen.rb +35 -0
- data/lib/aarch64/instructions/ldra.rb +37 -0
- data/lib/aarch64/instructions/ldrb_imm.rb +32 -0
- data/lib/aarch64/instructions/ldrb_reg.rb +33 -0
- data/lib/aarch64/instructions/ldrb_unsigned.rb +28 -0
- data/lib/aarch64/instructions/ldrh_imm.rb +32 -0
- data/lib/aarch64/instructions/ldrh_reg.rb +32 -0
- data/lib/aarch64/instructions/ldrh_unsigned.rb +28 -0
- data/lib/aarch64/instructions/ldrsb_imm.rb +37 -0
- data/lib/aarch64/instructions/ldrsb_reg.rb +37 -0
- data/lib/aarch64/instructions/ldrsb_unsigned.rb +35 -0
- data/lib/aarch64/instructions/ldrsh_imm.rb +37 -0
- data/lib/aarch64/instructions/ldrsh_reg.rb +35 -0
- data/lib/aarch64/instructions/ldrsh_unsigned.rb +31 -0
- data/lib/aarch64/instructions/ldrsw_imm.rb +32 -0
- data/lib/aarch64/instructions/ldrsw_lit.rb +26 -0
- data/lib/aarch64/instructions/ldrsw_reg.rb +32 -0
- data/lib/aarch64/instructions/ldrsw_unsigned.rb +30 -0
- data/lib/aarch64/instructions/ldset.rb +41 -0
- data/lib/aarch64/instructions/ldsetb.rb +35 -0
- data/lib/aarch64/instructions/ldseth.rb +35 -0
- data/lib/aarch64/instructions/ldsmax.rb +41 -0
- data/lib/aarch64/instructions/ldsmaxb.rb +35 -0
- data/lib/aarch64/instructions/ldsmaxh.rb +35 -0
- data/lib/aarch64/instructions/ldsmin.rb +41 -0
- data/lib/aarch64/instructions/ldsminb.rb +35 -0
- data/lib/aarch64/instructions/ldsminh.rb +35 -0
- data/lib/aarch64/instructions/ldtr.rb +31 -0
- data/lib/aarch64/instructions/ldtrb.rb +28 -0
- data/lib/aarch64/instructions/ldtrh.rb +28 -0
- data/lib/aarch64/instructions/ldtrsb.rb +31 -0
- data/lib/aarch64/instructions/ldtrsh.rb +31 -0
- data/lib/aarch64/instructions/ldtrsw.rb +28 -0
- data/lib/aarch64/instructions/ldumax.rb +41 -0
- data/lib/aarch64/instructions/ldumaxb.rb +35 -0
- data/lib/aarch64/instructions/ldumaxh.rb +35 -0
- data/lib/aarch64/instructions/ldumin.rb +41 -0
- data/lib/aarch64/instructions/lduminb.rb +35 -0
- data/lib/aarch64/instructions/lduminh.rb +35 -0
- data/lib/aarch64/instructions/ldur_gen.rb +31 -0
- data/lib/aarch64/instructions/ldursb.rb +31 -0
- data/lib/aarch64/instructions/ldursh.rb +31 -0
- data/lib/aarch64/instructions/ldursw.rb +28 -0
- data/lib/aarch64/instructions/ldxp.rb +31 -0
- data/lib/aarch64/instructions/ldxr.rb +29 -0
- data/lib/aarch64/instructions/lslv.rb +31 -0
- data/lib/aarch64/instructions/lsrv.rb +31 -0
- data/lib/aarch64/instructions/madd.rb +33 -0
- data/lib/aarch64/instructions/movk.rb +31 -0
- data/lib/aarch64/instructions/movn.rb +31 -0
- data/lib/aarch64/instructions/movz.rb +31 -0
- data/lib/aarch64/instructions/mrs.rb +34 -0
- data/lib/aarch64/instructions/msr_imm.rb +28 -0
- data/lib/aarch64/instructions/msr_reg.rb +34 -0
- data/lib/aarch64/instructions/msub.rb +33 -0
- data/lib/aarch64/instructions/nop.rb +19 -0
- data/lib/aarch64/instructions/orn_log_shift.rb +35 -0
- data/lib/aarch64/instructions/orr_log_imm.rb +35 -0
- data/lib/aarch64/instructions/orr_log_shift.rb +35 -0
- data/lib/aarch64/instructions/pacda.rb +29 -0
- data/lib/aarch64/instructions/pacdb.rb +29 -0
- data/lib/aarch64/instructions/pacga.rb +28 -0
- data/lib/aarch64/instructions/pacia.rb +32 -0
- data/lib/aarch64/instructions/pacia2.rb +28 -0
- data/lib/aarch64/instructions/pacib.rb +32 -0
- data/lib/aarch64/instructions/prfm_imm.rb +28 -0
- data/lib/aarch64/instructions/prfm_lit.rb +26 -0
- data/lib/aarch64/instructions/prfm_reg.rb +32 -0
- data/lib/aarch64/instructions/prfum.rb +28 -0
- data/lib/aarch64/instructions/psb.rb +19 -0
- data/lib/aarch64/instructions/rbit_int.rb +29 -0
- data/lib/aarch64/instructions/ret.rb +24 -0
- data/lib/aarch64/instructions/reta.rb +25 -0
- data/lib/aarch64/instructions/rev.rb +31 -0
- data/lib/aarch64/instructions/rmif.rb +28 -0
- data/lib/aarch64/instructions/rorv.rb +31 -0
- data/lib/aarch64/instructions/sb.rb +19 -0
- data/lib/aarch64/instructions/sbc.rb +31 -0
- data/lib/aarch64/instructions/sbcs.rb +31 -0
- data/lib/aarch64/instructions/sbfm.rb +34 -0
- data/lib/aarch64/instructions/sdiv.rb +31 -0
- data/lib/aarch64/instructions/setf.rb +27 -0
- data/lib/aarch64/instructions/setgp.rb +25 -0
- data/lib/aarch64/instructions/setgpn.rb +25 -0
- data/lib/aarch64/instructions/setgpt.rb +25 -0
- data/lib/aarch64/instructions/setgptn.rb +25 -0
- data/lib/aarch64/instructions/setp.rb +25 -0
- data/lib/aarch64/instructions/setpn.rb +25 -0
- data/lib/aarch64/instructions/setpt.rb +25 -0
- data/lib/aarch64/instructions/setptn.rb +25 -0
- data/lib/aarch64/instructions/sev.rb +18 -0
- data/lib/aarch64/instructions/sevl.rb +18 -0
- data/lib/aarch64/instructions/smaddl.rb +30 -0
- data/lib/aarch64/instructions/smc.rb +24 -0
- data/lib/aarch64/instructions/smsubl.rb +30 -0
- data/lib/aarch64/instructions/smulh.rb +28 -0
- data/lib/aarch64/instructions/st2g.rb +32 -0
- data/lib/aarch64/instructions/st64b.rb +26 -0
- data/lib/aarch64/instructions/st64bv.rb +28 -0
- data/lib/aarch64/instructions/st64bv0.rb +28 -0
- data/lib/aarch64/instructions/stg.rb +32 -0
- data/lib/aarch64/instructions/stgm.rb +26 -0
- data/lib/aarch64/instructions/stgp.rb +34 -0
- data/lib/aarch64/instructions/stllr.rb +29 -0
- data/lib/aarch64/instructions/stllrb.rb +26 -0
- data/lib/aarch64/instructions/stllrh.rb +26 -0
- data/lib/aarch64/instructions/stlr.rb +29 -0
- data/lib/aarch64/instructions/stlrb.rb +26 -0
- data/lib/aarch64/instructions/stlrh.rb +26 -0
- data/lib/aarch64/instructions/stlur_gen.rb +31 -0
- data/lib/aarch64/instructions/stlxp.rb +33 -0
- data/lib/aarch64/instructions/stlxr.rb +31 -0
- data/lib/aarch64/instructions/stlxrb.rb +28 -0
- data/lib/aarch64/instructions/stlxrh.rb +28 -0
- data/lib/aarch64/instructions/stnp_gen.rb +33 -0
- data/lib/aarch64/instructions/stp_gen.rb +39 -0
- data/lib/aarch64/instructions/str_imm_gen.rb +37 -0
- data/lib/aarch64/instructions/str_imm_unsigned.rb +31 -0
- data/lib/aarch64/instructions/str_reg_gen.rb +35 -0
- data/lib/aarch64/instructions/strb_imm.rb +32 -0
- data/lib/aarch64/instructions/strb_imm_unsigned.rb +28 -0
- data/lib/aarch64/instructions/strb_reg.rb +33 -0
- data/lib/aarch64/instructions/strh_imm.rb +32 -0
- data/lib/aarch64/instructions/strh_imm_unsigned.rb +28 -0
- data/lib/aarch64/instructions/strh_reg.rb +32 -0
- data/lib/aarch64/instructions/sttr.rb +31 -0
- data/lib/aarch64/instructions/stur_gen.rb +31 -0
- data/lib/aarch64/instructions/stxp.rb +33 -0
- data/lib/aarch64/instructions/stxr.rb +31 -0
- data/lib/aarch64/instructions/stxrb.rb +28 -0
- data/lib/aarch64/instructions/stxrh.rb +28 -0
- data/lib/aarch64/instructions/stz2g.rb +32 -0
- data/lib/aarch64/instructions/stzg.rb +32 -0
- data/lib/aarch64/instructions/stzgm.rb +26 -0
- data/lib/aarch64/instructions/sub_addsub_ext.rb +35 -0
- data/lib/aarch64/instructions/sub_addsub_imm.rb +33 -0
- data/lib/aarch64/instructions/sub_addsub_shift.rb +35 -0
- data/lib/aarch64/instructions/subg.rb +30 -0
- data/lib/aarch64/instructions/subp.rb +28 -0
- data/lib/aarch64/instructions/subps.rb +28 -0
- data/lib/aarch64/instructions/subs_addsub_ext.rb +35 -0
- data/lib/aarch64/instructions/subs_addsub_imm.rb +33 -0
- data/lib/aarch64/instructions/subs_addsub_shift.rb +35 -0
- data/lib/aarch64/instructions/svc.rb +24 -0
- data/lib/aarch64/instructions/swp.rb +41 -0
- data/lib/aarch64/instructions/swpb.rb +35 -0
- data/lib/aarch64/instructions/swph.rb +35 -0
- data/lib/aarch64/instructions/sys.rb +32 -0
- data/lib/aarch64/instructions/sysl.rb +32 -0
- data/lib/aarch64/instructions/tbnz.rb +30 -0
- data/lib/aarch64/instructions/tbz.rb +30 -0
- data/lib/aarch64/instructions/tsb.rb +18 -0
- data/lib/aarch64/instructions/ubfm.rb +34 -0
- data/lib/aarch64/instructions/udf_perm_undef.rb +24 -0
- data/lib/aarch64/instructions/udiv.rb +31 -0
- data/lib/aarch64/instructions/umaddl.rb +30 -0
- data/lib/aarch64/instructions/umsubl.rb +30 -0
- data/lib/aarch64/instructions/umulh.rb +28 -0
- data/lib/aarch64/instructions/wfe.rb +19 -0
- data/lib/aarch64/instructions/wfet.rb +24 -0
- data/lib/aarch64/instructions/wfi.rb +19 -0
- data/lib/aarch64/instructions/wfit.rb +24 -0
- data/lib/aarch64/instructions/xaflag.rb +19 -0
- data/lib/aarch64/instructions/xpac.rb +28 -0
- data/lib/aarch64/instructions/xpaclri.rb +18 -0
- data/lib/aarch64/instructions/yield.rb +19 -0
- data/lib/aarch64/instructions.rb +266 -0
- data/lib/aarch64/system_registers/mrs_msr_64.rb +395 -0
- data/lib/aarch64/utils.rb +325 -0
- data/lib/aarch64/version.rb +3 -0
- data/lib/aarch64.rb +2857 -0
- data/test/all_adds_test.rb +129 -0
- data/test/base_instructions_test.rb +9263 -0
- data/test/dsl_test.rb +11 -0
- data/test/helper.rb +51 -0
- data/test/not_supported_yet_test.rb +55 -0
- metadata +382 -0
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module AArch64
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module Instructions
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# GMI -- A64
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# Tag Mask Insert
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# GMI <Xd>, <Xn|SP>, <Xm>
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class GMI
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def initialize rd, rn, rm
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@rd = rd
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@rn = rn
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@rm = rm
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end
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def encode
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self.GMI(@rm.to_i, @rn.to_i, @rd.to_i)
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end
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private
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def GMI xm, xn, xd
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insn = 0b1_0_0_11010110_00000_0_0_0_1_0_1_00000_00000
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insn |= ((xm & 0x1f) << 16)
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insn |= ((xn & 0x1f) << 5)
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insn |= (xd & 0x1f)
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insn
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end
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end
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end
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end
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module AArch64
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module Instructions
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# HINT -- A64
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# Hint instruction
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# HINT #<imm>
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class HINT
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def initialize crm, op2
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@crm = crm
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@op2 = op2
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end
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def encode
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HINT(@crm, @op2)
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end
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private
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def HINT crm, op2
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insn = 0b1101010100_0_00_011_0010_0000_000_11111
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insn |= ((crm & 0xf) << 8)
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insn |= ((op2 & 0x7) << 5)
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insn
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end
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end
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end
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end
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module AArch64
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module Instructions
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# HLT -- A64
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# Halt instruction
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# HLT #<imm>
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class HLT
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def initialize imm
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@imm = imm
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end
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def encode
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self.HLT(@imm)
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end
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private
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def HLT imm16
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insn = 0b11010100_010_0000000000000000_000_00
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insn |= ((imm16 & 0xffff) << 5)
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insn
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end
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end
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end
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end
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module AArch64
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module Instructions
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# HVC -- A64
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# Hypervisor Call
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# HVC #<imm>
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class HVC
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def initialize imm
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@imm = imm
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end
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def encode
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self.HVC @imm
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end
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private
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17
|
+
def HVC imm16
|
18
|
+
insn = 0b11010100_000_0000000000000000_000_10
|
19
|
+
insn |= ((imm16 & 0xffff) << 5)
|
20
|
+
insn
|
21
|
+
end
|
22
|
+
end
|
23
|
+
end
|
24
|
+
end
|
@@ -0,0 +1,28 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# IRG -- A64
|
4
|
+
# Insert Random Tag
|
5
|
+
# IRG <Xd|SP>, <Xn|SP>{, <Xm>}
|
6
|
+
class IRG
|
7
|
+
def initialize rd, rn, rm
|
8
|
+
@rd = rd
|
9
|
+
@rn = rn
|
10
|
+
@rm = rm
|
11
|
+
end
|
12
|
+
|
13
|
+
def encode
|
14
|
+
self.IRG(@rm.to_i, @rn.to_i, @rd.to_i)
|
15
|
+
end
|
16
|
+
|
17
|
+
private
|
18
|
+
|
19
|
+
def IRG xm, xn, xd
|
20
|
+
insn = 0b1_0_0_11010110_00000_0_0_0_1_0_0_00000_00000
|
21
|
+
insn |= ((xm & 0x1f) << 16)
|
22
|
+
insn |= ((xn & 0x1f) << 5)
|
23
|
+
insn |= (xd & 0x1f)
|
24
|
+
insn
|
25
|
+
end
|
26
|
+
end
|
27
|
+
end
|
28
|
+
end
|
@@ -0,0 +1,24 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# ISB -- A64
|
4
|
+
# Instruction Synchronization Barrier
|
5
|
+
# ISB {<option>|#<imm>}
|
6
|
+
class ISB
|
7
|
+
def initialize imm
|
8
|
+
@imm = imm
|
9
|
+
end
|
10
|
+
|
11
|
+
def encode
|
12
|
+
self.ISB @imm
|
13
|
+
end
|
14
|
+
|
15
|
+
private
|
16
|
+
|
17
|
+
def ISB crm
|
18
|
+
insn = 0b1101010100_0_00_011_0011_0000_1_10_11111
|
19
|
+
insn |= ((crm & 0xf) << 8)
|
20
|
+
insn
|
21
|
+
end
|
22
|
+
end
|
23
|
+
end
|
24
|
+
end
|
@@ -0,0 +1,26 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# LD64B -- A64
|
4
|
+
# Single-copy Atomic 64-byte Load
|
5
|
+
# LD64B <Xt>, [<Xn|SP> {,#0}]
|
6
|
+
class LD64B
|
7
|
+
def initialize rt, rn
|
8
|
+
@rt = rt
|
9
|
+
@rn = rn
|
10
|
+
end
|
11
|
+
|
12
|
+
def encode
|
13
|
+
self.LD64B(@rn.to_i, @rt.to_i)
|
14
|
+
end
|
15
|
+
|
16
|
+
private
|
17
|
+
|
18
|
+
def LD64B rn, rt
|
19
|
+
insn = 0b11_111_0_00_0_0_1_11111_1_101_00_00000_00000
|
20
|
+
insn |= ((rn & 0x1f) << 5)
|
21
|
+
insn |= (rt & 0x1f)
|
22
|
+
insn
|
23
|
+
end
|
24
|
+
end
|
25
|
+
end
|
26
|
+
end
|
@@ -0,0 +1,41 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# LDADD, LDADDA, LDADDAL, LDADDL -- A64
|
4
|
+
# Atomic add on word or doubleword in memory
|
5
|
+
# LDADD <Ws>, <Wt>, [<Xn|SP>]
|
6
|
+
# LDADDA <Ws>, <Wt>, [<Xn|SP>]
|
7
|
+
# LDADDAL <Ws>, <Wt>, [<Xn|SP>]
|
8
|
+
# LDADDL <Ws>, <Wt>, [<Xn|SP>]
|
9
|
+
# LDADD <Xs>, <Xt>, [<Xn|SP>]
|
10
|
+
# LDADDA <Xs>, <Xt>, [<Xn|SP>]
|
11
|
+
# LDADDAL <Xs>, <Xt>, [<Xn|SP>]
|
12
|
+
# LDADDL <Xs>, <Xt>, [<Xn|SP>]
|
13
|
+
class LDADD
|
14
|
+
def initialize rs, rt, rn, size, a, r
|
15
|
+
@rs = rs
|
16
|
+
@rt = rt
|
17
|
+
@rn = rn
|
18
|
+
@size = size
|
19
|
+
@a = a
|
20
|
+
@r = r
|
21
|
+
end
|
22
|
+
|
23
|
+
def encode
|
24
|
+
self.LDADD(@size, @a, @r, @rs.to_i, @rn.to_i, @rt.to_i)
|
25
|
+
end
|
26
|
+
|
27
|
+
private
|
28
|
+
|
29
|
+
def LDADD size, a, r, rs, rn, rt
|
30
|
+
insn = 0b00_111_0_00_0_0_1_00000_0_000_00_00000_00000
|
31
|
+
insn |= ((size & 0x3) << 30)
|
32
|
+
insn |= ((a & 0x1) << 23)
|
33
|
+
insn |= ((r & 0x1) << 22)
|
34
|
+
insn |= ((rs & 0x1f) << 16)
|
35
|
+
insn |= ((rn & 0x1f) << 5)
|
36
|
+
insn |= (rt & 0x1f)
|
37
|
+
insn
|
38
|
+
end
|
39
|
+
end
|
40
|
+
end
|
41
|
+
end
|
@@ -0,0 +1,35 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# LDADDB, LDADDAB, LDADDALB, LDADDLB -- A64
|
4
|
+
# Atomic add on byte in memory
|
5
|
+
# LDADDAB <Ws>, <Wt>, [<Xn|SP>]
|
6
|
+
# LDADDALB <Ws>, <Wt>, [<Xn|SP>]
|
7
|
+
# LDADDB <Ws>, <Wt>, [<Xn|SP>]
|
8
|
+
# LDADDLB <Ws>, <Wt>, [<Xn|SP>]
|
9
|
+
class LDADDB
|
10
|
+
def initialize rs, rt, rn, a, r
|
11
|
+
@rs = rs
|
12
|
+
@rt = rt
|
13
|
+
@rn = rn
|
14
|
+
@a = a
|
15
|
+
@r = r
|
16
|
+
end
|
17
|
+
|
18
|
+
def encode
|
19
|
+
self.LDADDB(@a, @r, @rs.to_i, @rn.to_i, @rt.to_i)
|
20
|
+
end
|
21
|
+
|
22
|
+
private
|
23
|
+
|
24
|
+
def LDADDB a, r, rs, rn, rt
|
25
|
+
insn = 0b00_111_0_00_0_0_1_00000_0_000_00_00000_00000
|
26
|
+
insn |= ((a & 0x1) << 23)
|
27
|
+
insn |= ((r & 0x1) << 22)
|
28
|
+
insn |= ((rs & 0x1f) << 16)
|
29
|
+
insn |= ((rn & 0x1f) << 5)
|
30
|
+
insn |= (rt & 0x1f)
|
31
|
+
insn
|
32
|
+
end
|
33
|
+
end
|
34
|
+
end
|
35
|
+
end
|
@@ -0,0 +1,35 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# LDADDH, LDADDAH, LDADDALH, LDADDLH -- A64
|
4
|
+
# Atomic add on halfword in memory
|
5
|
+
# LDADDAH <Ws>, <Wt>, [<Xn|SP>]
|
6
|
+
# LDADDALH <Ws>, <Wt>, [<Xn|SP>]
|
7
|
+
# LDADDH <Ws>, <Wt>, [<Xn|SP>]
|
8
|
+
# LDADDLH <Ws>, <Wt>, [<Xn|SP>]
|
9
|
+
class LDADDH
|
10
|
+
def initialize rs, rt, rn, a, r
|
11
|
+
@rs = rs
|
12
|
+
@rt = rt
|
13
|
+
@rn = rn
|
14
|
+
@a = a
|
15
|
+
@r = r
|
16
|
+
end
|
17
|
+
|
18
|
+
def encode
|
19
|
+
self.LDADDH(@a, @r, @rs.to_i, @rn.to_i, @rt.to_i)
|
20
|
+
end
|
21
|
+
|
22
|
+
private
|
23
|
+
|
24
|
+
def LDADDH a, r, rs, rn, rt
|
25
|
+
insn = 0b01_111_0_00_0_0_1_00000_0_000_00_00000_00000
|
26
|
+
insn |= ((a & 0x1) << 23)
|
27
|
+
insn |= ((r & 0x1) << 22)
|
28
|
+
insn |= ((rs & 0x1f) << 16)
|
29
|
+
insn |= ((rn & 0x1f) << 5)
|
30
|
+
insn |= (rt & 0x1f)
|
31
|
+
insn
|
32
|
+
end
|
33
|
+
end
|
34
|
+
end
|
35
|
+
end
|
@@ -0,0 +1,29 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# LDAPR -- A64
|
4
|
+
# Load-Acquire RCpc Register
|
5
|
+
# LDAPR <Wt>, [<Xn|SP> {,#0}]
|
6
|
+
# LDAPR <Xt>, [<Xn|SP> {,#0}]
|
7
|
+
class LDAPR
|
8
|
+
def initialize rt, rn, size
|
9
|
+
@rt = rt
|
10
|
+
@rn = rn
|
11
|
+
@size = size
|
12
|
+
end
|
13
|
+
|
14
|
+
def encode
|
15
|
+
self.LDAPR(@size, @rn.to_i, @rt.to_i)
|
16
|
+
end
|
17
|
+
|
18
|
+
private
|
19
|
+
|
20
|
+
def LDAPR size, rn, rt
|
21
|
+
insn = 0b00_111_0_00_1_0_1_11111_1_100_00_00000_00000
|
22
|
+
insn |= ((size & 0x3) << 30)
|
23
|
+
insn |= ((rn & 0x1f) << 5)
|
24
|
+
insn |= (rt & 0x1f)
|
25
|
+
insn
|
26
|
+
end
|
27
|
+
end
|
28
|
+
end
|
29
|
+
end
|
@@ -0,0 +1,26 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# LDAPRB -- A64
|
4
|
+
# Load-Acquire RCpc Register Byte
|
5
|
+
# LDAPRB <Wt>, [<Xn|SP> {,#0}]
|
6
|
+
class LDAPRB
|
7
|
+
def initialize rt, rn
|
8
|
+
@rt = rt
|
9
|
+
@rn = rn
|
10
|
+
end
|
11
|
+
|
12
|
+
def encode
|
13
|
+
self.LDAPRB(@rn.to_i, @rt.to_i)
|
14
|
+
end
|
15
|
+
|
16
|
+
private
|
17
|
+
|
18
|
+
def LDAPRB rn, rt
|
19
|
+
insn = 0b00_111_0_00_1_0_1_11111_1_100_00_00000_00000
|
20
|
+
insn |= ((rn & 0x1f) << 5)
|
21
|
+
insn |= (rt & 0x1f)
|
22
|
+
insn
|
23
|
+
end
|
24
|
+
end
|
25
|
+
end
|
26
|
+
end
|
@@ -0,0 +1,26 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# LDAPRH -- A64
|
4
|
+
# Load-Acquire RCpc Register Halfword
|
5
|
+
# LDAPRH <Wt>, [<Xn|SP> {,#0}]
|
6
|
+
class LDAPRH
|
7
|
+
def initialize rt, rn
|
8
|
+
@rt = rt
|
9
|
+
@rn = rn
|
10
|
+
end
|
11
|
+
|
12
|
+
def encode
|
13
|
+
self.LDAPRH(@rn.to_i, @rt.to_i)
|
14
|
+
end
|
15
|
+
|
16
|
+
private
|
17
|
+
|
18
|
+
def LDAPRH rn, rt
|
19
|
+
insn = 0b01_111_0_00_1_0_1_11111_1_100_00_00000_00000
|
20
|
+
insn |= ((rn & 0x1f) << 5)
|
21
|
+
insn |= (rt & 0x1f)
|
22
|
+
insn
|
23
|
+
end
|
24
|
+
end
|
25
|
+
end
|
26
|
+
end
|
@@ -0,0 +1,33 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# LDAPUR -- A64
|
4
|
+
# Load-Acquire RCpc Register (unscaled)
|
5
|
+
# LDAPUR <Wt>, [<Xn|SP>{, #<simm>}]
|
6
|
+
# LDAPUR <Xt>, [<Xn|SP>{, #<simm>}]
|
7
|
+
class LDAPUR_gen
|
8
|
+
def initialize size, opc, rt, rn, simm
|
9
|
+
@size = size
|
10
|
+
@opc = opc
|
11
|
+
@rt = rt
|
12
|
+
@rn = rn
|
13
|
+
@simm = simm
|
14
|
+
end
|
15
|
+
|
16
|
+
def encode
|
17
|
+
self.LDAPUR_gen(@size, @opc, @simm, @rn.to_i, @rt.to_i)
|
18
|
+
end
|
19
|
+
|
20
|
+
private
|
21
|
+
|
22
|
+
def LDAPUR_gen size, opc, imm9, rn, rt
|
23
|
+
insn = 0b00_011001_00_0_000000000_00_00000_00000
|
24
|
+
insn |= ((size & 0x3) << 30)
|
25
|
+
insn |= ((opc & 0x3) << 22)
|
26
|
+
insn |= ((imm9 & 0x1ff) << 12)
|
27
|
+
insn |= ((rn & 0x1f) << 5)
|
28
|
+
insn |= (rt & 0x1f)
|
29
|
+
insn
|
30
|
+
end
|
31
|
+
end
|
32
|
+
end
|
33
|
+
end
|
@@ -0,0 +1,29 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# LDAR -- A64
|
4
|
+
# Load-Acquire Register
|
5
|
+
# LDAR <Wt>, [<Xn|SP>{,#0}]
|
6
|
+
# LDAR <Xt>, [<Xn|SP>{,#0}]
|
7
|
+
class LDAR
|
8
|
+
def initialize rt, rn, size
|
9
|
+
@rt = rt
|
10
|
+
@rn = rn
|
11
|
+
@size = size
|
12
|
+
end
|
13
|
+
|
14
|
+
def encode
|
15
|
+
self.LDAR @size, @rn.to_i, @rt.to_i
|
16
|
+
end
|
17
|
+
|
18
|
+
private
|
19
|
+
|
20
|
+
def LDAR size, rn, rt
|
21
|
+
insn = 0b00_001000_1_1_0_11111_1_11111_00000_00000
|
22
|
+
insn |= ((size & 0x3) << 30)
|
23
|
+
insn |= ((rn & 0x1f) << 5)
|
24
|
+
insn |= (rt & 0x1f)
|
25
|
+
insn
|
26
|
+
end
|
27
|
+
end
|
28
|
+
end
|
29
|
+
end
|
@@ -0,0 +1,31 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# LDAXP -- A64
|
4
|
+
# Load-Acquire Exclusive Pair of Registers
|
5
|
+
# LDAXP <Wt1>, <Wt2>, [<Xn|SP>{,#0}]
|
6
|
+
# LDAXP <Xt1>, <Xt2>, [<Xn|SP>{,#0}]
|
7
|
+
class LDAXP
|
8
|
+
def initialize rt1, rt2, rn, sf
|
9
|
+
@rt1 = rt1
|
10
|
+
@rt2 = rt2
|
11
|
+
@rn = rn
|
12
|
+
@sf = sf
|
13
|
+
end
|
14
|
+
|
15
|
+
def encode
|
16
|
+
self.LDAXP(@sf, @rt2.to_i, @rn.to_i, @rt1.to_i)
|
17
|
+
end
|
18
|
+
|
19
|
+
private
|
20
|
+
|
21
|
+
def LDAXP sz, rt2, rn, rt
|
22
|
+
insn = 0b1_0_001000_0_1_1_11111_1_00000_00000_00000
|
23
|
+
insn |= ((sz & 0x1) << 30)
|
24
|
+
insn |= ((rt2 & 0x1f) << 10)
|
25
|
+
insn |= ((rn & 0x1f) << 5)
|
26
|
+
insn |= (rt & 0x1f)
|
27
|
+
insn
|
28
|
+
end
|
29
|
+
end
|
30
|
+
end
|
31
|
+
end
|
@@ -0,0 +1,29 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# LDAXR -- A64
|
4
|
+
# Load-Acquire Exclusive Register
|
5
|
+
# LDAXR <Wt>, [<Xn|SP>{,#0}]
|
6
|
+
# LDAXR <Xt>, [<Xn|SP>{,#0}]
|
7
|
+
class LDAXR
|
8
|
+
def initialize rt, rn, size
|
9
|
+
@rt = rt
|
10
|
+
@rn = rn
|
11
|
+
@size = size
|
12
|
+
end
|
13
|
+
|
14
|
+
def encode
|
15
|
+
self.LDAXR(@size, @rn.to_i, @rt.to_i)
|
16
|
+
end
|
17
|
+
|
18
|
+
private
|
19
|
+
|
20
|
+
def LDAXR size, rn, rt
|
21
|
+
insn = 0b00_001000_0_1_0_11111_1_11111_00000_00000
|
22
|
+
insn |= ((size & 0x3) << 30)
|
23
|
+
insn |= ((rn & 0x1f) << 5)
|
24
|
+
insn |= (rt & 0x1f)
|
25
|
+
insn
|
26
|
+
end
|
27
|
+
end
|
28
|
+
end
|
29
|
+
end
|
@@ -0,0 +1,41 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# LDCLR, LDCLRA, LDCLRAL, LDCLRL -- A64
|
4
|
+
# Atomic bit clear on word or doubleword in memory
|
5
|
+
# LDCLR <Ws>, <Wt>, [<Xn|SP>]
|
6
|
+
# LDCLRA <Ws>, <Wt>, [<Xn|SP>]
|
7
|
+
# LDCLRAL <Ws>, <Wt>, [<Xn|SP>]
|
8
|
+
# LDCLRL <Ws>, <Wt>, [<Xn|SP>]
|
9
|
+
# LDCLR <Xs>, <Xt>, [<Xn|SP>]
|
10
|
+
# LDCLRA <Xs>, <Xt>, [<Xn|SP>]
|
11
|
+
# LDCLRAL <Xs>, <Xt>, [<Xn|SP>]
|
12
|
+
# LDCLRL <Xs>, <Xt>, [<Xn|SP>]
|
13
|
+
class LDCLR
|
14
|
+
def initialize rs, rt, rn, a, r, size
|
15
|
+
@rs = rs
|
16
|
+
@rt = rt
|
17
|
+
@rn = rn
|
18
|
+
@a = a
|
19
|
+
@r = r
|
20
|
+
@size = size
|
21
|
+
end
|
22
|
+
|
23
|
+
def encode
|
24
|
+
self.LDCLR(@size, @a, @r, @rs.to_i, @rn.to_i, @rt.to_i)
|
25
|
+
end
|
26
|
+
|
27
|
+
private
|
28
|
+
|
29
|
+
def LDCLR size, a, r, rs, rn, rt
|
30
|
+
insn = 0b00_111_0_00_0_0_1_00000_0_001_00_00000_00000
|
31
|
+
insn |= ((size & 0x3) << 30)
|
32
|
+
insn |= ((a & 0x1) << 23)
|
33
|
+
insn |= ((r & 0x1) << 22)
|
34
|
+
insn |= ((rs & 0x1f) << 16)
|
35
|
+
insn |= ((rn & 0x1f) << 5)
|
36
|
+
insn |= (rt & 0x1f)
|
37
|
+
insn
|
38
|
+
end
|
39
|
+
end
|
40
|
+
end
|
41
|
+
end
|
@@ -0,0 +1,37 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# LDCLRB, LDCLRAB, LDCLRALB, LDCLRLB -- A64
|
4
|
+
# Atomic bit clear on byte in memory
|
5
|
+
# LDCLRAB <Ws>, <Wt>, [<Xn|SP>]
|
6
|
+
# LDCLRALB <Ws>, <Wt>, [<Xn|SP>]
|
7
|
+
# LDCLRB <Ws>, <Wt>, [<Xn|SP>]
|
8
|
+
# LDCLRLB <Ws>, <Wt>, [<Xn|SP>]
|
9
|
+
class LDCLRB
|
10
|
+
def initialize rs, rt, rn, a, r, size
|
11
|
+
@rs = rs
|
12
|
+
@rt = rt
|
13
|
+
@rn = rn
|
14
|
+
@a = a
|
15
|
+
@r = r
|
16
|
+
@size = size
|
17
|
+
end
|
18
|
+
|
19
|
+
def encode
|
20
|
+
self.LDCLRB(@size, @a, @r, @rs.to_i, @rn.to_i, @rt.to_i)
|
21
|
+
end
|
22
|
+
|
23
|
+
private
|
24
|
+
|
25
|
+
def LDCLRB size, a, r, rs, rn, rt
|
26
|
+
insn = 0b00_111_0_00_0_0_1_00000_0_001_00_00000_00000
|
27
|
+
insn |= ((size & 0x3) << 30)
|
28
|
+
insn |= ((a & 0x1) << 23)
|
29
|
+
insn |= ((r & 0x1) << 22)
|
30
|
+
insn |= ((rs & 0x1f) << 16)
|
31
|
+
insn |= ((rn & 0x1f) << 5)
|
32
|
+
insn |= (rt & 0x1f)
|
33
|
+
insn
|
34
|
+
end
|
35
|
+
end
|
36
|
+
end
|
37
|
+
end
|
@@ -0,0 +1,41 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# LDEOR, LDEORA, LDEORAL, LDEORL -- A64
|
4
|
+
# Atomic exclusive OR on word or doubleword in memory
|
5
|
+
# LDEOR <Ws>, <Wt>, [<Xn|SP>]
|
6
|
+
# LDEORA <Ws>, <Wt>, [<Xn|SP>]
|
7
|
+
# LDEORAL <Ws>, <Wt>, [<Xn|SP>]
|
8
|
+
# LDEORL <Ws>, <Wt>, [<Xn|SP>]
|
9
|
+
# LDEOR <Xs>, <Xt>, [<Xn|SP>]
|
10
|
+
# LDEORA <Xs>, <Xt>, [<Xn|SP>]
|
11
|
+
# LDEORAL <Xs>, <Xt>, [<Xn|SP>]
|
12
|
+
# LDEORL <Xs>, <Xt>, [<Xn|SP>]
|
13
|
+
class LDEOR
|
14
|
+
def initialize rs, rt, rn, a, r, size
|
15
|
+
@rs = rs
|
16
|
+
@rt = rt
|
17
|
+
@rn = rn
|
18
|
+
@a = a
|
19
|
+
@r = r
|
20
|
+
@size = size
|
21
|
+
end
|
22
|
+
|
23
|
+
def encode
|
24
|
+
self.LDEOR(@size, @a, @r, @rs.to_i, @rn.to_i, @rt.to_i)
|
25
|
+
end
|
26
|
+
|
27
|
+
private
|
28
|
+
|
29
|
+
def LDEOR size, a, r, rs, rn, rt
|
30
|
+
insn = 0b00_111_0_00_0_0_1_00000_0_010_00_00000_00000
|
31
|
+
insn |= ((size & 0x3) << 30)
|
32
|
+
insn |= ((a & 0x1) << 23)
|
33
|
+
insn |= ((r & 0x1) << 22)
|
34
|
+
insn |= ((rs & 0x1f) << 16)
|
35
|
+
insn |= ((rn & 0x1f) << 5)
|
36
|
+
insn |= (rt & 0x1f)
|
37
|
+
insn
|
38
|
+
end
|
39
|
+
end
|
40
|
+
end
|
41
|
+
end
|
@@ -0,0 +1,28 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# LDG -- A64
|
4
|
+
# Load Allocation Tag
|
5
|
+
# LDG <Xt>, [<Xn|SP>{, #<simm>}]
|
6
|
+
class LDG
|
7
|
+
def initialize xt, xn, imm9
|
8
|
+
@xt = xt
|
9
|
+
@xn = xn
|
10
|
+
@imm9 = imm9
|
11
|
+
end
|
12
|
+
|
13
|
+
def encode
|
14
|
+
self.LDG(@imm9, @xn.to_i, @xt.to_i)
|
15
|
+
end
|
16
|
+
|
17
|
+
private
|
18
|
+
|
19
|
+
def LDG imm9, xn, xt
|
20
|
+
insn = 0b11011001_0_1_1_000000000_0_0_00000_00000
|
21
|
+
insn |= ((imm9 & 0x1ff) << 12)
|
22
|
+
insn |= ((xn & 0x1f) << 5)
|
23
|
+
insn |= (xt & 0x1f)
|
24
|
+
insn
|
25
|
+
end
|
26
|
+
end
|
27
|
+
end
|
28
|
+
end
|
@@ -0,0 +1,26 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# LDGM -- A64
|
4
|
+
# Load Tag Multiple
|
5
|
+
# LDGM <Xt>, [<Xn|SP>]
|
6
|
+
class LDGM
|
7
|
+
def initialize xt, xn
|
8
|
+
@xt = xt
|
9
|
+
@xn = xn
|
10
|
+
end
|
11
|
+
|
12
|
+
def encode
|
13
|
+
self.LDGM(@xn.to_i, @xt.to_i)
|
14
|
+
end
|
15
|
+
|
16
|
+
private
|
17
|
+
|
18
|
+
def LDGM xn, xt
|
19
|
+
insn = 0b11011001_1_1_1_0_0_0_0_0_0_0_0_0_0_0_00000_00000
|
20
|
+
insn |= ((xn & 0x1f) << 5)
|
21
|
+
insn |= (xt & 0x1f)
|
22
|
+
insn
|
23
|
+
end
|
24
|
+
end
|
25
|
+
end
|
26
|
+
end
|