aarch64 1.0.0

data/lib/aarch64/instructions/gmi.rb

@@ -0,0 +1,28 @@
+module AArch64
+  module Instructions
+    # GMI -- A64
+    # Tag Mask Insert
+    # GMI  <Xd>, <Xn|SP>, <Xm>
+    class GMI
+      def initialize rd, rn, rm
+        @rd = rd
+        @rn = rn
+        @rm = rm
+      end
+
+      def encode
+        self.GMI(@rm.to_i, @rn.to_i, @rd.to_i)
+      end
+
+      private
+
+      def GMI xm, xn, xd
+        insn = 0b1_0_0_11010110_00000_0_0_0_1_0_1_00000_00000
+        insn |= ((xm & 0x1f) << 16)
+        insn |= ((xn & 0x1f) << 5)
+        insn |= (xd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/hint.rb

@@ -0,0 +1,26 @@
+module AArch64
+  module Instructions
+    # HINT -- A64
+    # Hint instruction
+    # HINT  #<imm>
+    class HINT
+      def initialize crm, op2
+        @crm = crm
+        @op2 = op2
+      end
+
+      def encode
+        HINT(@crm, @op2)
+      end
+
+      private
+
+      def HINT crm, op2
+        insn = 0b1101010100_0_00_011_0010_0000_000_11111
+        insn |= ((crm & 0xf) << 8)
+        insn |= ((op2 & 0x7) << 5)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/hlt.rb

@@ -0,0 +1,24 @@
+module AArch64
+  module Instructions
+    # HLT -- A64
+    # Halt instruction
+    # HLT  #<imm>
+    class HLT
+      def initialize imm
+        @imm = imm
+      end
+
+      def encode
+        self.HLT(@imm)
+      end
+
+      private
+
+      def HLT imm16
+        insn = 0b11010100_010_0000000000000000_000_00
+        insn |= ((imm16 & 0xffff) << 5)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/hvc.rb

@@ -0,0 +1,24 @@
+module AArch64
+  module Instructions
+    # HVC -- A64
+    # Hypervisor Call
+    # HVC  #<imm>
+    class HVC
+      def initialize imm
+        @imm = imm
+      end
+
+      def encode
+        self.HVC @imm
+      end
+
+      private
+
+      def HVC imm16
+        insn = 0b11010100_000_0000000000000000_000_10
+        insn |= ((imm16 & 0xffff) << 5)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/irg.rb

@@ -0,0 +1,28 @@
+module AArch64
+  module Instructions
+    # IRG -- A64
+    # Insert Random Tag
+    # IRG  <Xd|SP>, <Xn|SP>{, <Xm>}
+    class IRG
+      def initialize rd, rn, rm
+        @rd = rd
+        @rn = rn
+        @rm = rm
+      end
+
+      def encode
+        self.IRG(@rm.to_i, @rn.to_i, @rd.to_i)
+      end
+
+      private
+
+      def IRG xm, xn, xd
+        insn = 0b1_0_0_11010110_00000_0_0_0_1_0_0_00000_00000
+        insn |= ((xm & 0x1f) << 16)
+        insn |= ((xn & 0x1f) << 5)
+        insn |= (xd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/isb.rb

@@ -0,0 +1,24 @@
+module AArch64
+  module Instructions
+    # ISB -- A64
+    # Instruction Synchronization Barrier
+    # ISB  {<option>|#<imm>}
+    class ISB
+      def initialize imm
+        @imm = imm
+      end
+
+      def encode
+        self.ISB @imm
+      end
+
+      private
+
+      def ISB crm
+        insn = 0b1101010100_0_00_011_0011_0000_1_10_11111
+        insn |= ((crm & 0xf) << 8)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/ld64b.rb

@@ -0,0 +1,26 @@
+module AArch64
+  module Instructions
+    # LD64B -- A64
+    # Single-copy Atomic 64-byte Load
+    # LD64B  <Xt>, [<Xn|SP> {,#0}]
+    class LD64B
+      def initialize rt, rn
+        @rt = rt
+        @rn = rn
+      end
+
+      def encode
+        self.LD64B(@rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def LD64B rn, rt
+        insn = 0b11_111_0_00_0_0_1_11111_1_101_00_00000_00000
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/ldadd.rb

@@ -0,0 +1,41 @@
+module AArch64
+  module Instructions
+    # LDADD, LDADDA, LDADDAL, LDADDL -- A64
+    # Atomic add on word or doubleword in memory
+    # LDADD  <Ws>, <Wt>, [<Xn|SP>]
+    # LDADDA  <Ws>, <Wt>, [<Xn|SP>]
+    # LDADDAL  <Ws>, <Wt>, [<Xn|SP>]
+    # LDADDL  <Ws>, <Wt>, [<Xn|SP>]
+    # LDADD  <Xs>, <Xt>, [<Xn|SP>]
+    # LDADDA  <Xs>, <Xt>, [<Xn|SP>]
+    # LDADDAL  <Xs>, <Xt>, [<Xn|SP>]
+    # LDADDL  <Xs>, <Xt>, [<Xn|SP>]
+    class LDADD
+      def initialize rs, rt, rn, size, a, r
+        @rs   = rs
+        @rt   = rt
+        @rn   = rn
+        @size = size
+        @a    = a
+        @r    = r
+      end
+
+      def encode
+        self.LDADD(@size, @a, @r, @rs.to_i, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def LDADD size, a, r, rs, rn, rt
+        insn = 0b00_111_0_00_0_0_1_00000_0_000_00_00000_00000
+        insn |= ((size & 0x3) << 30)
+        insn |= ((a & 0x1) << 23)
+        insn |= ((r & 0x1) << 22)
+        insn |= ((rs & 0x1f) << 16)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/ldaddb.rb

@@ -0,0 +1,35 @@
+module AArch64
+  module Instructions
+    # LDADDB, LDADDAB, LDADDALB, LDADDLB -- A64
+    # Atomic add on byte in memory
+    # LDADDAB  <Ws>, <Wt>, [<Xn|SP>]
+    # LDADDALB  <Ws>, <Wt>, [<Xn|SP>]
+    # LDADDB  <Ws>, <Wt>, [<Xn|SP>]
+    # LDADDLB  <Ws>, <Wt>, [<Xn|SP>]
+    class LDADDB
+      def initialize rs, rt, rn, a, r
+        @rs = rs
+        @rt = rt
+        @rn = rn
+        @a  = a
+        @r  = r
+      end
+
+      def encode
+        self.LDADDB(@a, @r, @rs.to_i, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def LDADDB a, r, rs, rn, rt
+        insn = 0b00_111_0_00_0_0_1_00000_0_000_00_00000_00000
+        insn |= ((a & 0x1) << 23)
+        insn |= ((r & 0x1) << 22)
+        insn |= ((rs & 0x1f) << 16)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/ldaddh.rb

@@ -0,0 +1,35 @@
+module AArch64
+  module Instructions
+    # LDADDH, LDADDAH, LDADDALH, LDADDLH -- A64
+    # Atomic add on halfword in memory
+    # LDADDAH  <Ws>, <Wt>, [<Xn|SP>]
+    # LDADDALH  <Ws>, <Wt>, [<Xn|SP>]
+    # LDADDH  <Ws>, <Wt>, [<Xn|SP>]
+    # LDADDLH  <Ws>, <Wt>, [<Xn|SP>]
+    class LDADDH
+      def initialize rs, rt, rn, a, r
+        @rs = rs
+        @rt = rt
+        @rn = rn
+        @a  = a
+        @r  = r
+      end
+
+      def encode
+        self.LDADDH(@a, @r, @rs.to_i, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def LDADDH a, r, rs, rn, rt
+        insn = 0b01_111_0_00_0_0_1_00000_0_000_00_00000_00000
+        insn |= ((a & 0x1) << 23)
+        insn |= ((r & 0x1) << 22)
+        insn |= ((rs & 0x1f) << 16)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/ldapr.rb

@@ -0,0 +1,29 @@
+module AArch64
+  module Instructions
+    # LDAPR -- A64
+    # Load-Acquire RCpc Register
+    # LDAPR  <Wt>, [<Xn|SP> {,#0}]
+    # LDAPR  <Xt>, [<Xn|SP> {,#0}]
+    class LDAPR
+      def initialize rt, rn, size
+        @rt   = rt
+        @rn   = rn
+        @size = size
+      end
+
+      def encode
+        self.LDAPR(@size, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def LDAPR size, rn, rt
+        insn = 0b00_111_0_00_1_0_1_11111_1_100_00_00000_00000
+        insn |= ((size & 0x3) << 30)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/ldaprb.rb

@@ -0,0 +1,26 @@
+module AArch64
+  module Instructions
+    # LDAPRB -- A64
+    # Load-Acquire RCpc Register Byte
+    # LDAPRB  <Wt>, [<Xn|SP> {,#0}]
+    class LDAPRB
+      def initialize rt, rn
+        @rt = rt
+        @rn = rn
+      end
+
+      def encode
+        self.LDAPRB(@rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def LDAPRB rn, rt
+        insn = 0b00_111_0_00_1_0_1_11111_1_100_00_00000_00000
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/ldaprh.rb

@@ -0,0 +1,26 @@
+module AArch64
+  module Instructions
+    # LDAPRH -- A64
+    # Load-Acquire RCpc Register Halfword
+    # LDAPRH  <Wt>, [<Xn|SP> {,#0}]
+    class LDAPRH
+      def initialize rt, rn
+        @rt = rt
+        @rn = rn
+      end
+
+      def encode
+        self.LDAPRH(@rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def LDAPRH rn, rt
+        insn = 0b01_111_0_00_1_0_1_11111_1_100_00_00000_00000
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/ldapur_gen.rb

@@ -0,0 +1,33 @@
+module AArch64
+  module Instructions
+    # LDAPUR -- A64
+    # Load-Acquire RCpc Register (unscaled)
+    # LDAPUR  <Wt>, [<Xn|SP>{, #<simm>}]
+    # LDAPUR  <Xt>, [<Xn|SP>{, #<simm>}]
+    class LDAPUR_gen
+      def initialize size, opc, rt, rn, simm
+        @size = size
+        @opc  = opc
+        @rt   = rt
+        @rn   = rn
+        @simm = simm
+      end
+
+      def encode
+        self.LDAPUR_gen(@size, @opc, @simm, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def LDAPUR_gen size, opc, imm9, rn, rt
+        insn = 0b00_011001_00_0_000000000_00_00000_00000
+        insn |= ((size & 0x3) << 30)
+        insn |= ((opc & 0x3) << 22)
+        insn |= ((imm9 & 0x1ff) << 12)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/ldar.rb

@@ -0,0 +1,29 @@
+module AArch64
+  module Instructions
+    # LDAR -- A64
+    # Load-Acquire Register
+    # LDAR  <Wt>, [<Xn|SP>{,#0}]
+    # LDAR  <Xt>, [<Xn|SP>{,#0}]
+    class LDAR
+      def initialize rt, rn, size
+        @rt   = rt
+        @rn   = rn
+        @size = size
+      end
+
+      def encode
+        self.LDAR @size, @rn.to_i, @rt.to_i
+      end
+
+      private
+
+      def LDAR size, rn, rt
+        insn = 0b00_001000_1_1_0_11111_1_11111_00000_00000
+        insn |= ((size & 0x3) << 30)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/ldaxp.rb

@@ -0,0 +1,31 @@
+module AArch64
+  module Instructions
+    # LDAXP -- A64
+    # Load-Acquire Exclusive Pair of Registers
+    # LDAXP  <Wt1>, <Wt2>, [<Xn|SP>{,#0}]
+    # LDAXP  <Xt1>, <Xt2>, [<Xn|SP>{,#0}]
+    class LDAXP
+      def initialize rt1, rt2, rn, sf
+        @rt1 = rt1
+        @rt2 = rt2
+        @rn  = rn
+        @sf  = sf
+      end
+
+      def encode
+        self.LDAXP(@sf, @rt2.to_i, @rn.to_i, @rt1.to_i)
+      end
+
+      private
+
+      def LDAXP sz, rt2, rn, rt
+        insn = 0b1_0_001000_0_1_1_11111_1_00000_00000_00000
+        insn |= ((sz & 0x1) << 30)
+        insn |= ((rt2 & 0x1f) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/ldaxr.rb

@@ -0,0 +1,29 @@
+module AArch64
+  module Instructions
+    # LDAXR -- A64
+    # Load-Acquire Exclusive Register
+    # LDAXR  <Wt>, [<Xn|SP>{,#0}]
+    # LDAXR  <Xt>, [<Xn|SP>{,#0}]
+    class LDAXR
+      def initialize rt, rn, size
+        @rt   = rt
+        @rn   = rn
+        @size = size
+      end
+
+      def encode
+        self.LDAXR(@size, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def LDAXR size, rn, rt
+        insn = 0b00_001000_0_1_0_11111_1_11111_00000_00000
+        insn |= ((size & 0x3) << 30)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/ldclr.rb

@@ -0,0 +1,41 @@
+module AArch64
+  module Instructions
+    # LDCLR, LDCLRA, LDCLRAL, LDCLRL -- A64
+    # Atomic bit clear on word or doubleword in memory
+    # LDCLR  <Ws>, <Wt>, [<Xn|SP>]
+    # LDCLRA  <Ws>, <Wt>, [<Xn|SP>]
+    # LDCLRAL  <Ws>, <Wt>, [<Xn|SP>]
+    # LDCLRL  <Ws>, <Wt>, [<Xn|SP>]
+    # LDCLR  <Xs>, <Xt>, [<Xn|SP>]
+    # LDCLRA  <Xs>, <Xt>, [<Xn|SP>]
+    # LDCLRAL  <Xs>, <Xt>, [<Xn|SP>]
+    # LDCLRL  <Xs>, <Xt>, [<Xn|SP>]
+    class LDCLR
+      def initialize rs, rt, rn, a, r, size
+        @rs   = rs
+        @rt   = rt
+        @rn   = rn
+        @a    = a
+        @r    = r
+        @size = size
+      end
+
+      def encode
+        self.LDCLR(@size, @a, @r, @rs.to_i, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def LDCLR size, a, r, rs, rn, rt
+        insn = 0b00_111_0_00_0_0_1_00000_0_001_00_00000_00000
+        insn |= ((size & 0x3) << 30)
+        insn |= ((a & 0x1) << 23)
+        insn |= ((r & 0x1) << 22)
+        insn |= ((rs & 0x1f) << 16)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/ldclrb.rb

@@ -0,0 +1,37 @@
+module AArch64
+  module Instructions
+    # LDCLRB, LDCLRAB, LDCLRALB, LDCLRLB -- A64
+    # Atomic bit clear on byte in memory
+    # LDCLRAB  <Ws>, <Wt>, [<Xn|SP>]
+    # LDCLRALB  <Ws>, <Wt>, [<Xn|SP>]
+    # LDCLRB  <Ws>, <Wt>, [<Xn|SP>]
+    # LDCLRLB  <Ws>, <Wt>, [<Xn|SP>]
+    class LDCLRB
+      def initialize rs, rt, rn, a, r, size
+        @rs   = rs
+        @rt   = rt
+        @rn   = rn
+        @a    = a
+        @r    = r
+        @size = size
+      end
+
+      def encode
+        self.LDCLRB(@size, @a, @r, @rs.to_i, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def LDCLRB size, a, r, rs, rn, rt
+        insn = 0b00_111_0_00_0_0_1_00000_0_001_00_00000_00000
+        insn |= ((size & 0x3) << 30)
+        insn |= ((a & 0x1) << 23)
+        insn |= ((r & 0x1) << 22)
+        insn |= ((rs & 0x1f) << 16)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/ldeor.rb

@@ -0,0 +1,41 @@
+module AArch64
+  module Instructions
+    # LDEOR, LDEORA, LDEORAL, LDEORL -- A64
+    # Atomic exclusive OR on word or doubleword in memory
+    # LDEOR  <Ws>, <Wt>, [<Xn|SP>]
+    # LDEORA  <Ws>, <Wt>, [<Xn|SP>]
+    # LDEORAL  <Ws>, <Wt>, [<Xn|SP>]
+    # LDEORL  <Ws>, <Wt>, [<Xn|SP>]
+    # LDEOR  <Xs>, <Xt>, [<Xn|SP>]
+    # LDEORA  <Xs>, <Xt>, [<Xn|SP>]
+    # LDEORAL  <Xs>, <Xt>, [<Xn|SP>]
+    # LDEORL  <Xs>, <Xt>, [<Xn|SP>]
+    class LDEOR
+      def initialize rs, rt, rn, a, r, size
+        @rs   = rs
+        @rt   = rt
+        @rn   = rn
+        @a    = a
+        @r    = r
+        @size = size
+      end
+
+      def encode
+        self.LDEOR(@size, @a, @r, @rs.to_i, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def LDEOR size, a, r, rs, rn, rt
+        insn = 0b00_111_0_00_0_0_1_00000_0_010_00_00000_00000
+        insn |= ((size & 0x3) << 30)
+        insn |= ((a & 0x1) << 23)
+        insn |= ((r & 0x1) << 22)
+        insn |= ((rs & 0x1f) << 16)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/ldg.rb

@@ -0,0 +1,28 @@
+module AArch64
+  module Instructions
+    # LDG -- A64
+    # Load Allocation Tag
+    # LDG  <Xt>, [<Xn|SP>{, #<simm>}]
+    class LDG
+      def initialize xt, xn, imm9
+        @xt   = xt
+        @xn   = xn
+        @imm9 = imm9
+      end
+
+      def encode
+        self.LDG(@imm9, @xn.to_i, @xt.to_i)
+      end
+
+      private
+
+      def LDG imm9, xn, xt
+        insn = 0b11011001_0_1_1_000000000_0_0_00000_00000
+        insn |= ((imm9 & 0x1ff) << 12)
+        insn |= ((xn & 0x1f) << 5)
+        insn |= (xt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/ldgm.rb

@@ -0,0 +1,26 @@
+module AArch64
+  module Instructions
+    # LDGM -- A64
+    # Load Tag Multiple
+    # LDGM  <Xt>, [<Xn|SP>]
+    class LDGM
+      def initialize xt, xn
+        @xt = xt
+        @xn = xn
+      end
+
+      def encode
+        self.LDGM(@xn.to_i, @xt.to_i)
+      end
+
+      private
+
+      def LDGM xn, xt
+        insn = 0b11011001_1_1_1_0_0_0_0_0_0_0_0_0_0_0_00000_00000
+        insn |= ((xn & 0x1f) << 5)
+        insn |= (xt & 0x1f)
+        insn
+      end
+    end
+  end
+end