aarch64 1.0.0

data/lib/aarch64/instructions/stgm.rb

@@ -0,0 +1,26 @@
+module AArch64
+  module Instructions
+    # STGM -- A64
+    # Store Tag Multiple
+    # STGM  <Xt>, [<Xn|SP>]
+    class STGM
+      def initialize xt, xn
+        @xt = xt
+        @xn = xn
+      end
+
+      def encode
+        self.STGM(@xn.to_i, @xt.to_i)
+      end
+
+      private
+
+      def STGM xn, xt
+        insn = 0b11011001_1_0_1_0_0_0_0_0_0_0_0_0_0_0_00000_00000
+        insn |= ((xn & 0x1f) << 5)
+        insn |= (xt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/stgp.rb

@@ -0,0 +1,34 @@
+module AArch64
+  module Instructions
+    # STGP -- A64
+    # Store Allocation Tag and Pair of registers
+    # STGP  <Xt1>, <Xt2>, [<Xn|SP>], #<imm>
+    # STGP  <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]!
+    # STGP  <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]
+    class STGP
+      def initialize xt, xt2, xn, simm7, option
+        @xt     = xt
+        @xt2    = xt2
+        @xn     = xn
+        @simm7  = simm7
+        @option = option
+      end
+
+      def encode
+        self.STGP(@option, @simm7, @xt2.to_i, @xn.to_i, @xt.to_i)
+      end
+
+      private
+
+      def STGP option, simm7, xt2, xn, xt
+        insn = 0b0_1_101_0_000_0_0000000_00000_00000_00000
+        insn |= ((option & 0x3) << 23)
+        insn |= ((simm7 & 0x7f) << 15)
+        insn |= ((xt2 & 0x1f) << 10)
+        insn |= ((xn & 0x1f) << 5)
+        insn |= (xt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/stllr.rb

@@ -0,0 +1,29 @@
+module AArch64
+  module Instructions
+    # STLLR -- A64
+    # Store LORelease Register
+    # STLLR  <Wt>, [<Xn|SP>{,#0}]
+    # STLLR  <Xt>, [<Xn|SP>{,#0}]
+    class STLLR
+      def initialize rt, rn, size
+        @rt   = rt
+        @rn   = rn
+        @size = size
+      end
+
+      def encode
+        self.STLLR(@size, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def STLLR size, rn, rt
+        insn = 0b00_001000_1_0_0_11111_0_11111_00000_00000
+        insn |= ((size & 0x3) << 30)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/stllrb.rb

@@ -0,0 +1,26 @@
+module AArch64
+  module Instructions
+    # STLLRB -- A64
+    # Store LORelease Register Byte
+    # STLLRB  <Wt>, [<Xn|SP>{,#0}]
+    class STLLRB
+      def initialize rt, rn
+        @rt = rt
+        @rn = rn
+      end
+
+      def encode
+        self.STLLRB(@rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def STLLRB rn, rt
+        insn = 0b00_001000_1_0_0_11111_0_11111_00000_00000
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/stllrh.rb

@@ -0,0 +1,26 @@
+module AArch64
+  module Instructions
+    # STLLRH -- A64
+    # Store LORelease Register Halfword
+    # STLLRH  <Wt>, [<Xn|SP>{,#0}]
+    class STLLRH
+      def initialize rt, rn
+        @rt = rt
+        @rn = rn
+      end
+
+      def encode
+        self.STLLRH(@rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def STLLRH rn, rt
+        insn = 0b01_001000_1_0_0_11111_0_11111_00000_00000
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/stlr.rb

@@ -0,0 +1,29 @@
+module AArch64
+  module Instructions
+    # STLR -- A64
+    # Store-Release Register
+    # STLR  <Wt>, [<Xn|SP>{,#0}]
+    # STLR  <Xt>, [<Xn|SP>{,#0}]
+    class STLR
+      def initialize rt, rn, size
+        @rt   = rt
+        @rn   = rn
+        @size = size
+      end
+
+      def encode
+        self.STLR(@size, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def STLR size, rn, rt
+        insn = 0b00_001000_1_0_0_11111_1_11111_00000_00000
+        insn |= ((size & 0x3) << 30)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/stlrb.rb

@@ -0,0 +1,26 @@
+module AArch64
+  module Instructions
+    # STLRB -- A64
+    # Store-Release Register Byte
+    # STLRB  <Wt>, [<Xn|SP>{,#0}]
+    class STLRB
+      def initialize rt, rn
+        @rt = rt
+        @rn = rn
+      end
+
+      def encode
+        self.STLRB(@rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def STLRB rn, rt
+        insn = 0b00_001000_1_0_0_11111_1_11111_00000_00000
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/stlrh.rb

@@ -0,0 +1,26 @@
+module AArch64
+  module Instructions
+    # STLRH -- A64
+    # Store-Release Register Halfword
+    # STLRH  <Wt>, [<Xn|SP>{,#0}]
+    class STLRH
+      def initialize rt, rn
+        @rt = rt
+        @rn = rn
+      end
+
+      def encode
+        self.STLRH(@rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def STLRH rn, rt
+        insn = 0b01_001000_1_0_0_11111_1_11111_00000_00000
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/stlur_gen.rb

@@ -0,0 +1,31 @@
+module AArch64
+  module Instructions
+    # STLUR -- A64
+    # Store-Release Register (unscaled)
+    # STLUR  <Wt>, [<Xn|SP>{, #<simm>}]
+    # STLUR  <Xt>, [<Xn|SP>{, #<simm>}]
+    class STLUR_gen
+      def initialize rt, rn, imm9, size
+        @rt   = rt
+        @rn   = rn
+        @imm9 = imm9
+        @size = size
+      end
+
+      def encode
+        self.STLUR_gen(@size, @imm9, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def STLUR_gen size, imm9, rn, rt
+        insn = 0b00_011001_00_0_000000000_00_00000_00000
+        insn |= ((size & 0x3) << 30)
+        insn |= ((imm9 & 0x1ff) << 12)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/stlxp.rb

@@ -0,0 +1,33 @@
+module AArch64
+  module Instructions
+    # STLXP -- A64
+    # Store-Release Exclusive Pair of registers
+    # STLXP  <Ws>, <Wt1>, <Wt2>, [<Xn|SP>{,#0}]
+    # STLXP  <Ws>, <Xt1>, <Xt2>, [<Xn|SP>{,#0}]
+    class STLXP
+      def initialize rs, rt, rt2, rn, sz
+        @rs  = rs
+        @rt  = rt
+        @rt2 = rt2
+        @rn  = rn
+        @sz  = sz
+      end
+
+      def encode
+        self.STLXP(@sz, @rs.to_i, @rt2.to_i, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def STLXP sz, rs, rt2, rn, rt
+        insn = 0b1_0_001000_0_0_1_00000_1_00000_00000_00000
+        insn |= ((sz & 0x1) << 30)
+        insn |= ((rs & 0x1f) << 16)
+        insn |= ((rt2 & 0x1f) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/stlxr.rb

@@ -0,0 +1,31 @@
+module AArch64
+  module Instructions
+    # STLXR -- A64
+    # Store-Release Exclusive Register
+    # STLXR  <Ws>, <Wt>, [<Xn|SP>{,#0}]
+    # STLXR  <Ws>, <Xt>, [<Xn|SP>{,#0}]
+    class STLXR
+      def initialize rs, rt, rn, size
+        @rs   = rs
+        @rt   = rt
+        @rn   = rn
+        @size = size
+      end
+
+      def encode
+        self.STLXR(@size, @rs.to_i, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def STLXR size, rs, rn, rt
+        insn = 0b00_001000_0_0_0_00000_1_11111_00000_00000
+        insn |= ((size & 0x3) << 30)
+        insn |= ((rs & 0x1f) << 16)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/stlxrb.rb

@@ -0,0 +1,28 @@
+module AArch64
+  module Instructions
+    # STLXRB -- A64
+    # Store-Release Exclusive Register Byte
+    # STLXRB  <Ws>, <Wt>, [<Xn|SP>{,#0}]
+    class STLXRB
+      def initialize rs, rt, rn
+        @rs = rs
+        @rt = rt
+        @rn = rn
+      end
+
+      def encode
+        self.STLXRB(@rs.to_i, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def STLXRB rs, rn, rt
+        insn = 0b00_001000_0_0_0_00000_1_11111_00000_00000
+        insn |= ((rs & 0x1f) << 16)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/stlxrh.rb

@@ -0,0 +1,28 @@
+module AArch64
+  module Instructions
+    # STLXRH -- A64
+    # Store-Release Exclusive Register Halfword
+    # STLXRH  <Ws>, <Wt>, [<Xn|SP>{,#0}]
+    class STLXRH
+      def initialize rs, rt, rn
+        @rs = rs
+        @rt = rt
+        @rn = rn
+      end
+
+      def encode
+        self.STLXRH(@rs.to_i, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def STLXRH rs, rn, rt
+        insn = 0b01_001000_0_0_0_00000_1_11111_00000_00000
+        insn |= ((rs & 0x1f) << 16)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/stnp_gen.rb

@@ -0,0 +1,33 @@
+module AArch64
+  module Instructions
+    # STNP -- A64
+    # Store Pair of Registers, with non-temporal hint
+    # STNP  <Wt1>, <Wt2>, [<Xn|SP>{, #<imm>}]
+    # STNP  <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]
+    class STNP_gen
+      def initialize rt, rt2, rn, imm7, opc
+        @rt   = rt
+        @rt2  = rt2
+        @rn   = rn
+        @imm7 = imm7
+        @opc  = opc
+      end
+
+      def encode
+        self.STNP_gen(@opc, @imm7, @rt2.to_i, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def STNP_gen opc, imm7, rt2, rn, rt
+        insn = 0b00_101_0_000_0_0000000_00000_00000_00000
+        insn |= ((opc & 0x3) << 30)
+        insn |= ((imm7 & 0x7f) << 15)
+        insn |= ((rt2 & 0x1f) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/stp_gen.rb

@@ -0,0 +1,39 @@
+module AArch64
+  module Instructions
+    # STP -- A64
+    # Store Pair of Registers
+    # STP  <Wt1>, <Wt2>, [<Xn|SP>], #<imm>
+    # STP  <Xt1>, <Xt2>, [<Xn|SP>], #<imm>
+    # STP  <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]!
+    # STP  <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]!
+    # STP  <Wt1>, <Wt2>, [<Xn|SP>{, #<imm>}]
+    # STP  <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]
+    class STP_gen
+      def initialize rt, rt2, rn, imm7, opc, option
+        @rt     = rt
+        @rt2    = rt2
+        @rn     = rn
+        @imm7   = imm7
+        @opc    = opc
+        @option = option
+      end
+
+      def encode
+        self.STP_gen(@opc, @option, @imm7, @rt2.to_i, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def STP_gen opc, option, imm7, rt2, rn, rt
+        insn = 0b00_101_0_000_0_0000000_00000_00000_00000
+        insn |= ((opc & 0x3) << 30)
+        insn |= ((option & 0x7) << 23)
+        insn |= ((imm7 & 0x7f) << 15)
+        insn |= ((rt2 & 0x1f) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/str_imm_gen.rb

@@ -0,0 +1,37 @@
+module AArch64
+  module Instructions
+    # STR (immediate) -- A64
+    # Store Register (immediate)
+    # STR  <Wt>, [<Xn|SP>], #<simm>
+    # STR  <Xt>, [<Xn|SP>], #<simm>
+    # STR  <Wt>, [<Xn|SP>, #<simm>]!
+    # STR  <Xt>, [<Xn|SP>, #<simm>]!
+    # STR  <Wt>, [<Xn|SP>{, #<pimm>}]
+    # STR  <Xt>, [<Xn|SP>{, #<pimm>}]
+    class STR_imm_gen
+      def initialize rt, rn, imm9, opt, size
+        @rt   = rt
+        @rn   = rn
+        @imm9 = imm9
+        @opt  = opt
+        @size = size
+      end
+
+      def encode
+        self.STR_imm_gen(@size, @imm9, @opt, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def STR_imm_gen size, imm9, opt, rn, rt
+        insn = 0b00_111_0_00_00_0_000000000_00_00000_00000
+        insn |= ((size & 0x3) << 30)
+        insn |= ((imm9 & 0x1ff) << 12)
+        insn |= ((opt & 0x3) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/str_imm_unsigned.rb

@@ -0,0 +1,31 @@
+module AArch64
+  module Instructions
+    # STR (immediate) -- A64
+    # Store Register (immediate)
+    # STR  <Wt>, [<Xn|SP>{, #<pimm>}]
+    # STR  <Xt>, [<Xn|SP>{, #<pimm>}]
+    class STR_imm_unsigned
+      def initialize rt, rn, imm12, size
+        @rt    = rt
+        @rn    = rn
+        @imm12 = imm12
+        @size  = size
+      end
+
+      def encode
+        self.STR_imm_gen(@size, @imm12, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def STR_imm_gen size, imm12, rn, rt
+        insn = 0b00_111_0_01_00_0_000000000_00_00000_00000
+        insn |= ((size & 0x3) << 30)
+        insn |= ((imm12 & 0xfff) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/str_reg_gen.rb

@@ -0,0 +1,35 @@
+module AArch64
+  module Instructions
+    # STR (register) -- A64
+    # Store Register (register)
+    # STR  <Wt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
+    # STR  <Xt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
+    class STR_reg_gen
+      def initialize rt, rn, rm, option, s, size
+        @rt     = rt
+        @rn     = rn
+        @rm     = rm
+        @option = option
+        @s      = s
+        @size   = size
+      end
+
+      def encode
+        self.STR_reg_gen(@size, @rm.to_i, @option, @s, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def STR_reg_gen size, rm, option, s, rn, rt
+        insn = 0b00_111_0_00_00_1_00000_000_0_10_00000_00000
+        insn |= ((size & 0x3) << 30)
+        insn |= ((rm & 0x1f) << 16)
+        insn |= ((option & 0x7) << 13)
+        insn |= ((s & 0x1) << 12)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/strb_imm.rb

@@ -0,0 +1,32 @@
+module AArch64
+  module Instructions
+    # STRB (immediate) -- A64
+    # Store Register Byte (immediate)
+    # STRB  <Wt>, [<Xn|SP>], #<simm>
+    # STRB  <Wt>, [<Xn|SP>, #<simm>]!
+    # STRB  <Wt>, [<Xn|SP>{, #<pimm>}]
+    class STRB_imm
+      def initialize rt, rn, imm9, opt
+        @rt   = rt
+        @rn   = rn
+        @imm9 = imm9
+        @opt  = opt
+      end
+
+      def encode
+        self.STRB_imm(@imm9, @opt, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def STRB_imm imm9, opt, rn, rt
+        insn = 0b00_111_0_00_00_0_000000000_00_00000_00000
+        insn |= ((imm9 & 0x1ff) << 12)
+        insn |= ((opt & 0x3) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/strb_imm_unsigned.rb

@@ -0,0 +1,28 @@
+module AArch64
+  module Instructions
+    # STRB (immediate) -- A64
+    # Store Register Byte (immediate)
+    # STRB  <Wt>, [<Xn|SP>{, #<pimm>}]
+    class STRB_imm_unsigned
+      def initialize rt, rn, imm12
+        @rt    = rt
+        @rn    = rn
+        @imm12 = imm12
+      end
+
+      def encode
+        self.STRB_imm_unsigned(@imm12, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def STRB_imm_unsigned imm12, rn, rt
+        insn = 0b00_111_0_01_00_0_000000000_00_00000_00000
+        insn |= ((imm12 & 0xfff) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/strb_reg.rb

@@ -0,0 +1,33 @@
+module AArch64
+  module Instructions
+    # STRB (register) -- A64
+    # Store Register Byte (register)
+    # STRB  <Wt>, [<Xn|SP>, (<Wm>|<Xm>), <extend> {<amount>}]
+    # STRB  <Wt>, [<Xn|SP>, <Xm>{, LSL <amount>}]
+    class STRB_reg
+      def initialize rt, rn, rm, option, s
+        @rt     = rt
+        @rn     = rn
+        @rm     = rm
+        @option = option
+        @s      = s
+      end
+
+      def encode
+        self.STRB_reg(@rm.to_i, @option, @s, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def STRB_reg rm, option, s, rn, rt
+        insn = 0b00_111_0_00_00_1_00000_000_0_10_00000_00000
+        insn |= ((rm & 0x1f) << 16)
+        insn |= ((option & 0x7) << 13)
+        insn |= ((s & 0x1) << 12)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/strh_imm.rb

@@ -0,0 +1,32 @@
+module AArch64
+  module Instructions
+    # STRH (immediate) -- A64
+    # Store Register Halfword (immediate)
+    # STRH  <Wt>, [<Xn|SP>], #<simm>
+    # STRH  <Wt>, [<Xn|SP>, #<simm>]!
+    # STRH  <Wt>, [<Xn|SP>{, #<pimm>}]
+    class STRH_imm
+      def initialize rt, rn, imm9, opt
+        @rt   = rt
+        @rn   = rn
+        @imm9 = imm9
+        @opt  = opt
+      end
+
+      def encode
+        self.STRH_imm(@imm9, @opt, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def STRH_imm imm9, opt, rn, rt
+        insn = 0b01_111_0_00_00_0_000000000_00_00000_00000
+        insn |= ((imm9 & 0x1ff) << 12)
+        insn |= ((opt & 0x3) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end