aarch64 1.0.0
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- checksums.yaml +7 -0
- data/CODE_OF_CONDUCT.md +77 -0
- data/Gemfile +3 -0
- data/LICENSE +201 -0
- data/README.md +77 -0
- data/Rakefile +168 -0
- data/aarch64.gemspec +21 -0
- data/bin/build_instructions.rb +102 -0
- data/lib/aarch64/instructions/adc.rb +31 -0
- data/lib/aarch64/instructions/adcs.rb +30 -0
- data/lib/aarch64/instructions/add_addsub_ext.rb +35 -0
- data/lib/aarch64/instructions/add_addsub_imm.rb +32 -0
- data/lib/aarch64/instructions/add_addsub_shift.rb +35 -0
- data/lib/aarch64/instructions/addg.rb +30 -0
- data/lib/aarch64/instructions/adds_addsub_ext.rb +35 -0
- data/lib/aarch64/instructions/adds_addsub_imm.rb +33 -0
- data/lib/aarch64/instructions/adds_addsub_shift.rb +35 -0
- data/lib/aarch64/instructions/adr.rb +28 -0
- data/lib/aarch64/instructions/adrp.rb +28 -0
- data/lib/aarch64/instructions/and_log_imm.rb +35 -0
- data/lib/aarch64/instructions/and_log_shift.rb +35 -0
- data/lib/aarch64/instructions/ands_log_imm.rb +35 -0
- data/lib/aarch64/instructions/ands_log_shift.rb +35 -0
- data/lib/aarch64/instructions/asrv.rb +31 -0
- data/lib/aarch64/instructions/autda.rb +32 -0
- data/lib/aarch64/instructions/autdb.rb +32 -0
- data/lib/aarch64/instructions/autia.rb +35 -0
- data/lib/aarch64/instructions/autib.rb +35 -0
- data/lib/aarch64/instructions/axflag.rb +18 -0
- data/lib/aarch64/instructions/b_cond.rb +26 -0
- data/lib/aarch64/instructions/b_uncond.rb +24 -0
- data/lib/aarch64/instructions/bc_cond.rb +26 -0
- data/lib/aarch64/instructions/bfm.rb +34 -0
- data/lib/aarch64/instructions/bic_log_shift.rb +35 -0
- data/lib/aarch64/instructions/bics.rb +35 -0
- data/lib/aarch64/instructions/bl.rb +24 -0
- data/lib/aarch64/instructions/blr.rb +24 -0
- data/lib/aarch64/instructions/blra.rb +33 -0
- data/lib/aarch64/instructions/br.rb +24 -0
- data/lib/aarch64/instructions/bra.rb +33 -0
- data/lib/aarch64/instructions/brk.rb +24 -0
- data/lib/aarch64/instructions/bti.rb +24 -0
- data/lib/aarch64/instructions/cas.rb +41 -0
- data/lib/aarch64/instructions/casb.rb +35 -0
- data/lib/aarch64/instructions/cash.rb +35 -0
- data/lib/aarch64/instructions/casp.rb +41 -0
- data/lib/aarch64/instructions/cbnz.rb +29 -0
- data/lib/aarch64/instructions/cbz.rb +29 -0
- data/lib/aarch64/instructions/ccmn_imm.rb +33 -0
- data/lib/aarch64/instructions/ccmn_reg.rb +33 -0
- data/lib/aarch64/instructions/ccmp_imm.rb +33 -0
- data/lib/aarch64/instructions/ccmp_reg.rb +33 -0
- data/lib/aarch64/instructions/cfinv.rb +19 -0
- data/lib/aarch64/instructions/clrex.rb +24 -0
- data/lib/aarch64/instructions/cls_int.rb +29 -0
- data/lib/aarch64/instructions/clz_int.rb +29 -0
- data/lib/aarch64/instructions/crc32.rb +35 -0
- data/lib/aarch64/instructions/crc32c.rb +35 -0
- data/lib/aarch64/instructions/csdb.rb +19 -0
- data/lib/aarch64/instructions/csel.rb +33 -0
- data/lib/aarch64/instructions/csinc.rb +33 -0
- data/lib/aarch64/instructions/csinv.rb +33 -0
- data/lib/aarch64/instructions/csneg.rb +33 -0
- data/lib/aarch64/instructions/dcps.rb +26 -0
- data/lib/aarch64/instructions/dgh.rb +19 -0
- data/lib/aarch64/instructions/dmb.rb +24 -0
- data/lib/aarch64/instructions/drps.rb +19 -0
- data/lib/aarch64/instructions/dsb.rb +25 -0
- data/lib/aarch64/instructions/eon.rb +35 -0
- data/lib/aarch64/instructions/eor_log_imm.rb +35 -0
- data/lib/aarch64/instructions/eor_log_shift.rb +35 -0
- data/lib/aarch64/instructions/eret.rb +19 -0
- data/lib/aarch64/instructions/ereta.rb +25 -0
- data/lib/aarch64/instructions/esb.rb +19 -0
- data/lib/aarch64/instructions/extr.rb +34 -0
- data/lib/aarch64/instructions/gmi.rb +28 -0
- data/lib/aarch64/instructions/hint.rb +26 -0
- data/lib/aarch64/instructions/hlt.rb +24 -0
- data/lib/aarch64/instructions/hvc.rb +24 -0
- data/lib/aarch64/instructions/irg.rb +28 -0
- data/lib/aarch64/instructions/isb.rb +24 -0
- data/lib/aarch64/instructions/ld64b.rb +26 -0
- data/lib/aarch64/instructions/ldadd.rb +41 -0
- data/lib/aarch64/instructions/ldaddb.rb +35 -0
- data/lib/aarch64/instructions/ldaddh.rb +35 -0
- data/lib/aarch64/instructions/ldapr.rb +29 -0
- data/lib/aarch64/instructions/ldaprb.rb +26 -0
- data/lib/aarch64/instructions/ldaprh.rb +26 -0
- data/lib/aarch64/instructions/ldapur_gen.rb +33 -0
- data/lib/aarch64/instructions/ldar.rb +29 -0
- data/lib/aarch64/instructions/ldaxp.rb +31 -0
- data/lib/aarch64/instructions/ldaxr.rb +29 -0
- data/lib/aarch64/instructions/ldclr.rb +41 -0
- data/lib/aarch64/instructions/ldclrb.rb +37 -0
- data/lib/aarch64/instructions/ldeor.rb +41 -0
- data/lib/aarch64/instructions/ldg.rb +28 -0
- data/lib/aarch64/instructions/ldgm.rb +26 -0
- data/lib/aarch64/instructions/ldlar.rb +29 -0
- data/lib/aarch64/instructions/ldnp_gen.rb +33 -0
- data/lib/aarch64/instructions/ldp_gen.rb +39 -0
- data/lib/aarch64/instructions/ldpsw.rb +34 -0
- data/lib/aarch64/instructions/ldr_imm_gen.rb +35 -0
- data/lib/aarch64/instructions/ldr_imm_unsigned.rb +31 -0
- data/lib/aarch64/instructions/ldr_lit_gen.rb +29 -0
- data/lib/aarch64/instructions/ldr_reg_gen.rb +35 -0
- data/lib/aarch64/instructions/ldra.rb +37 -0
- data/lib/aarch64/instructions/ldrb_imm.rb +32 -0
- data/lib/aarch64/instructions/ldrb_reg.rb +33 -0
- data/lib/aarch64/instructions/ldrb_unsigned.rb +28 -0
- data/lib/aarch64/instructions/ldrh_imm.rb +32 -0
- data/lib/aarch64/instructions/ldrh_reg.rb +32 -0
- data/lib/aarch64/instructions/ldrh_unsigned.rb +28 -0
- data/lib/aarch64/instructions/ldrsb_imm.rb +37 -0
- data/lib/aarch64/instructions/ldrsb_reg.rb +37 -0
- data/lib/aarch64/instructions/ldrsb_unsigned.rb +35 -0
- data/lib/aarch64/instructions/ldrsh_imm.rb +37 -0
- data/lib/aarch64/instructions/ldrsh_reg.rb +35 -0
- data/lib/aarch64/instructions/ldrsh_unsigned.rb +31 -0
- data/lib/aarch64/instructions/ldrsw_imm.rb +32 -0
- data/lib/aarch64/instructions/ldrsw_lit.rb +26 -0
- data/lib/aarch64/instructions/ldrsw_reg.rb +32 -0
- data/lib/aarch64/instructions/ldrsw_unsigned.rb +30 -0
- data/lib/aarch64/instructions/ldset.rb +41 -0
- data/lib/aarch64/instructions/ldsetb.rb +35 -0
- data/lib/aarch64/instructions/ldseth.rb +35 -0
- data/lib/aarch64/instructions/ldsmax.rb +41 -0
- data/lib/aarch64/instructions/ldsmaxb.rb +35 -0
- data/lib/aarch64/instructions/ldsmaxh.rb +35 -0
- data/lib/aarch64/instructions/ldsmin.rb +41 -0
- data/lib/aarch64/instructions/ldsminb.rb +35 -0
- data/lib/aarch64/instructions/ldsminh.rb +35 -0
- data/lib/aarch64/instructions/ldtr.rb +31 -0
- data/lib/aarch64/instructions/ldtrb.rb +28 -0
- data/lib/aarch64/instructions/ldtrh.rb +28 -0
- data/lib/aarch64/instructions/ldtrsb.rb +31 -0
- data/lib/aarch64/instructions/ldtrsh.rb +31 -0
- data/lib/aarch64/instructions/ldtrsw.rb +28 -0
- data/lib/aarch64/instructions/ldumax.rb +41 -0
- data/lib/aarch64/instructions/ldumaxb.rb +35 -0
- data/lib/aarch64/instructions/ldumaxh.rb +35 -0
- data/lib/aarch64/instructions/ldumin.rb +41 -0
- data/lib/aarch64/instructions/lduminb.rb +35 -0
- data/lib/aarch64/instructions/lduminh.rb +35 -0
- data/lib/aarch64/instructions/ldur_gen.rb +31 -0
- data/lib/aarch64/instructions/ldursb.rb +31 -0
- data/lib/aarch64/instructions/ldursh.rb +31 -0
- data/lib/aarch64/instructions/ldursw.rb +28 -0
- data/lib/aarch64/instructions/ldxp.rb +31 -0
- data/lib/aarch64/instructions/ldxr.rb +29 -0
- data/lib/aarch64/instructions/lslv.rb +31 -0
- data/lib/aarch64/instructions/lsrv.rb +31 -0
- data/lib/aarch64/instructions/madd.rb +33 -0
- data/lib/aarch64/instructions/movk.rb +31 -0
- data/lib/aarch64/instructions/movn.rb +31 -0
- data/lib/aarch64/instructions/movz.rb +31 -0
- data/lib/aarch64/instructions/mrs.rb +34 -0
- data/lib/aarch64/instructions/msr_imm.rb +28 -0
- data/lib/aarch64/instructions/msr_reg.rb +34 -0
- data/lib/aarch64/instructions/msub.rb +33 -0
- data/lib/aarch64/instructions/nop.rb +19 -0
- data/lib/aarch64/instructions/orn_log_shift.rb +35 -0
- data/lib/aarch64/instructions/orr_log_imm.rb +35 -0
- data/lib/aarch64/instructions/orr_log_shift.rb +35 -0
- data/lib/aarch64/instructions/pacda.rb +29 -0
- data/lib/aarch64/instructions/pacdb.rb +29 -0
- data/lib/aarch64/instructions/pacga.rb +28 -0
- data/lib/aarch64/instructions/pacia.rb +32 -0
- data/lib/aarch64/instructions/pacia2.rb +28 -0
- data/lib/aarch64/instructions/pacib.rb +32 -0
- data/lib/aarch64/instructions/prfm_imm.rb +28 -0
- data/lib/aarch64/instructions/prfm_lit.rb +26 -0
- data/lib/aarch64/instructions/prfm_reg.rb +32 -0
- data/lib/aarch64/instructions/prfum.rb +28 -0
- data/lib/aarch64/instructions/psb.rb +19 -0
- data/lib/aarch64/instructions/rbit_int.rb +29 -0
- data/lib/aarch64/instructions/ret.rb +24 -0
- data/lib/aarch64/instructions/reta.rb +25 -0
- data/lib/aarch64/instructions/rev.rb +31 -0
- data/lib/aarch64/instructions/rmif.rb +28 -0
- data/lib/aarch64/instructions/rorv.rb +31 -0
- data/lib/aarch64/instructions/sb.rb +19 -0
- data/lib/aarch64/instructions/sbc.rb +31 -0
- data/lib/aarch64/instructions/sbcs.rb +31 -0
- data/lib/aarch64/instructions/sbfm.rb +34 -0
- data/lib/aarch64/instructions/sdiv.rb +31 -0
- data/lib/aarch64/instructions/setf.rb +27 -0
- data/lib/aarch64/instructions/setgp.rb +25 -0
- data/lib/aarch64/instructions/setgpn.rb +25 -0
- data/lib/aarch64/instructions/setgpt.rb +25 -0
- data/lib/aarch64/instructions/setgptn.rb +25 -0
- data/lib/aarch64/instructions/setp.rb +25 -0
- data/lib/aarch64/instructions/setpn.rb +25 -0
- data/lib/aarch64/instructions/setpt.rb +25 -0
- data/lib/aarch64/instructions/setptn.rb +25 -0
- data/lib/aarch64/instructions/sev.rb +18 -0
- data/lib/aarch64/instructions/sevl.rb +18 -0
- data/lib/aarch64/instructions/smaddl.rb +30 -0
- data/lib/aarch64/instructions/smc.rb +24 -0
- data/lib/aarch64/instructions/smsubl.rb +30 -0
- data/lib/aarch64/instructions/smulh.rb +28 -0
- data/lib/aarch64/instructions/st2g.rb +32 -0
- data/lib/aarch64/instructions/st64b.rb +26 -0
- data/lib/aarch64/instructions/st64bv.rb +28 -0
- data/lib/aarch64/instructions/st64bv0.rb +28 -0
- data/lib/aarch64/instructions/stg.rb +32 -0
- data/lib/aarch64/instructions/stgm.rb +26 -0
- data/lib/aarch64/instructions/stgp.rb +34 -0
- data/lib/aarch64/instructions/stllr.rb +29 -0
- data/lib/aarch64/instructions/stllrb.rb +26 -0
- data/lib/aarch64/instructions/stllrh.rb +26 -0
- data/lib/aarch64/instructions/stlr.rb +29 -0
- data/lib/aarch64/instructions/stlrb.rb +26 -0
- data/lib/aarch64/instructions/stlrh.rb +26 -0
- data/lib/aarch64/instructions/stlur_gen.rb +31 -0
- data/lib/aarch64/instructions/stlxp.rb +33 -0
- data/lib/aarch64/instructions/stlxr.rb +31 -0
- data/lib/aarch64/instructions/stlxrb.rb +28 -0
- data/lib/aarch64/instructions/stlxrh.rb +28 -0
- data/lib/aarch64/instructions/stnp_gen.rb +33 -0
- data/lib/aarch64/instructions/stp_gen.rb +39 -0
- data/lib/aarch64/instructions/str_imm_gen.rb +37 -0
- data/lib/aarch64/instructions/str_imm_unsigned.rb +31 -0
- data/lib/aarch64/instructions/str_reg_gen.rb +35 -0
- data/lib/aarch64/instructions/strb_imm.rb +32 -0
- data/lib/aarch64/instructions/strb_imm_unsigned.rb +28 -0
- data/lib/aarch64/instructions/strb_reg.rb +33 -0
- data/lib/aarch64/instructions/strh_imm.rb +32 -0
- data/lib/aarch64/instructions/strh_imm_unsigned.rb +28 -0
- data/lib/aarch64/instructions/strh_reg.rb +32 -0
- data/lib/aarch64/instructions/sttr.rb +31 -0
- data/lib/aarch64/instructions/stur_gen.rb +31 -0
- data/lib/aarch64/instructions/stxp.rb +33 -0
- data/lib/aarch64/instructions/stxr.rb +31 -0
- data/lib/aarch64/instructions/stxrb.rb +28 -0
- data/lib/aarch64/instructions/stxrh.rb +28 -0
- data/lib/aarch64/instructions/stz2g.rb +32 -0
- data/lib/aarch64/instructions/stzg.rb +32 -0
- data/lib/aarch64/instructions/stzgm.rb +26 -0
- data/lib/aarch64/instructions/sub_addsub_ext.rb +35 -0
- data/lib/aarch64/instructions/sub_addsub_imm.rb +33 -0
- data/lib/aarch64/instructions/sub_addsub_shift.rb +35 -0
- data/lib/aarch64/instructions/subg.rb +30 -0
- data/lib/aarch64/instructions/subp.rb +28 -0
- data/lib/aarch64/instructions/subps.rb +28 -0
- data/lib/aarch64/instructions/subs_addsub_ext.rb +35 -0
- data/lib/aarch64/instructions/subs_addsub_imm.rb +33 -0
- data/lib/aarch64/instructions/subs_addsub_shift.rb +35 -0
- data/lib/aarch64/instructions/svc.rb +24 -0
- data/lib/aarch64/instructions/swp.rb +41 -0
- data/lib/aarch64/instructions/swpb.rb +35 -0
- data/lib/aarch64/instructions/swph.rb +35 -0
- data/lib/aarch64/instructions/sys.rb +32 -0
- data/lib/aarch64/instructions/sysl.rb +32 -0
- data/lib/aarch64/instructions/tbnz.rb +30 -0
- data/lib/aarch64/instructions/tbz.rb +30 -0
- data/lib/aarch64/instructions/tsb.rb +18 -0
- data/lib/aarch64/instructions/ubfm.rb +34 -0
- data/lib/aarch64/instructions/udf_perm_undef.rb +24 -0
- data/lib/aarch64/instructions/udiv.rb +31 -0
- data/lib/aarch64/instructions/umaddl.rb +30 -0
- data/lib/aarch64/instructions/umsubl.rb +30 -0
- data/lib/aarch64/instructions/umulh.rb +28 -0
- data/lib/aarch64/instructions/wfe.rb +19 -0
- data/lib/aarch64/instructions/wfet.rb +24 -0
- data/lib/aarch64/instructions/wfi.rb +19 -0
- data/lib/aarch64/instructions/wfit.rb +24 -0
- data/lib/aarch64/instructions/xaflag.rb +19 -0
- data/lib/aarch64/instructions/xpac.rb +28 -0
- data/lib/aarch64/instructions/xpaclri.rb +18 -0
- data/lib/aarch64/instructions/yield.rb +19 -0
- data/lib/aarch64/instructions.rb +266 -0
- data/lib/aarch64/system_registers/mrs_msr_64.rb +395 -0
- data/lib/aarch64/utils.rb +325 -0
- data/lib/aarch64/version.rb +3 -0
- data/lib/aarch64.rb +2857 -0
- data/test/all_adds_test.rb +129 -0
- data/test/base_instructions_test.rb +9263 -0
- data/test/dsl_test.rb +11 -0
- data/test/helper.rb +51 -0
- data/test/not_supported_yet_test.rb +55 -0
- metadata +382 -0
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module AArch64
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module Instructions
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# STGM -- A64
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# Store Tag Multiple
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# STGM <Xt>, [<Xn|SP>]
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class STGM
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def initialize xt, xn
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@xt = xt
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@xn = xn
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end
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def encode
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self.STGM(@xn.to_i, @xt.to_i)
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end
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private
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def STGM xn, xt
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insn = 0b11011001_1_0_1_0_0_0_0_0_0_0_0_0_0_0_00000_00000
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insn |= ((xn & 0x1f) << 5)
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insn |= (xt & 0x1f)
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insn
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end
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end
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end
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end
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module AArch64
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module Instructions
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# STGP -- A64
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# Store Allocation Tag and Pair of registers
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# STGP <Xt1>, <Xt2>, [<Xn|SP>], #<imm>
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# STGP <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]!
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# STGP <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]
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class STGP
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def initialize xt, xt2, xn, simm7, option
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@xt = xt
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@xt2 = xt2
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@xn = xn
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@simm7 = simm7
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@option = option
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end
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def encode
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self.STGP(@option, @simm7, @xt2.to_i, @xn.to_i, @xt.to_i)
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end
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private
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def STGP option, simm7, xt2, xn, xt
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insn = 0b0_1_101_0_000_0_0000000_00000_00000_00000
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insn |= ((option & 0x3) << 23)
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insn |= ((simm7 & 0x7f) << 15)
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insn |= ((xt2 & 0x1f) << 10)
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insn |= ((xn & 0x1f) << 5)
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insn |= (xt & 0x1f)
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insn
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end
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end
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end
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end
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module AArch64
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module Instructions
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# STLLR -- A64
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# Store LORelease Register
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# STLLR <Wt>, [<Xn|SP>{,#0}]
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# STLLR <Xt>, [<Xn|SP>{,#0}]
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class STLLR
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def initialize rt, rn, size
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@rt = rt
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@rn = rn
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@size = size
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end
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def encode
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self.STLLR(@size, @rn.to_i, @rt.to_i)
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end
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private
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def STLLR size, rn, rt
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insn = 0b00_001000_1_0_0_11111_0_11111_00000_00000
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insn |= ((size & 0x3) << 30)
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23
|
+
insn |= ((rn & 0x1f) << 5)
|
24
|
+
insn |= (rt & 0x1f)
|
25
|
+
insn
|
26
|
+
end
|
27
|
+
end
|
28
|
+
end
|
29
|
+
end
|
@@ -0,0 +1,26 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# STLLRB -- A64
|
4
|
+
# Store LORelease Register Byte
|
5
|
+
# STLLRB <Wt>, [<Xn|SP>{,#0}]
|
6
|
+
class STLLRB
|
7
|
+
def initialize rt, rn
|
8
|
+
@rt = rt
|
9
|
+
@rn = rn
|
10
|
+
end
|
11
|
+
|
12
|
+
def encode
|
13
|
+
self.STLLRB(@rn.to_i, @rt.to_i)
|
14
|
+
end
|
15
|
+
|
16
|
+
private
|
17
|
+
|
18
|
+
def STLLRB rn, rt
|
19
|
+
insn = 0b00_001000_1_0_0_11111_0_11111_00000_00000
|
20
|
+
insn |= ((rn & 0x1f) << 5)
|
21
|
+
insn |= (rt & 0x1f)
|
22
|
+
insn
|
23
|
+
end
|
24
|
+
end
|
25
|
+
end
|
26
|
+
end
|
@@ -0,0 +1,26 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# STLLRH -- A64
|
4
|
+
# Store LORelease Register Halfword
|
5
|
+
# STLLRH <Wt>, [<Xn|SP>{,#0}]
|
6
|
+
class STLLRH
|
7
|
+
def initialize rt, rn
|
8
|
+
@rt = rt
|
9
|
+
@rn = rn
|
10
|
+
end
|
11
|
+
|
12
|
+
def encode
|
13
|
+
self.STLLRH(@rn.to_i, @rt.to_i)
|
14
|
+
end
|
15
|
+
|
16
|
+
private
|
17
|
+
|
18
|
+
def STLLRH rn, rt
|
19
|
+
insn = 0b01_001000_1_0_0_11111_0_11111_00000_00000
|
20
|
+
insn |= ((rn & 0x1f) << 5)
|
21
|
+
insn |= (rt & 0x1f)
|
22
|
+
insn
|
23
|
+
end
|
24
|
+
end
|
25
|
+
end
|
26
|
+
end
|
@@ -0,0 +1,29 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# STLR -- A64
|
4
|
+
# Store-Release Register
|
5
|
+
# STLR <Wt>, [<Xn|SP>{,#0}]
|
6
|
+
# STLR <Xt>, [<Xn|SP>{,#0}]
|
7
|
+
class STLR
|
8
|
+
def initialize rt, rn, size
|
9
|
+
@rt = rt
|
10
|
+
@rn = rn
|
11
|
+
@size = size
|
12
|
+
end
|
13
|
+
|
14
|
+
def encode
|
15
|
+
self.STLR(@size, @rn.to_i, @rt.to_i)
|
16
|
+
end
|
17
|
+
|
18
|
+
private
|
19
|
+
|
20
|
+
def STLR size, rn, rt
|
21
|
+
insn = 0b00_001000_1_0_0_11111_1_11111_00000_00000
|
22
|
+
insn |= ((size & 0x3) << 30)
|
23
|
+
insn |= ((rn & 0x1f) << 5)
|
24
|
+
insn |= (rt & 0x1f)
|
25
|
+
insn
|
26
|
+
end
|
27
|
+
end
|
28
|
+
end
|
29
|
+
end
|
@@ -0,0 +1,26 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# STLRB -- A64
|
4
|
+
# Store-Release Register Byte
|
5
|
+
# STLRB <Wt>, [<Xn|SP>{,#0}]
|
6
|
+
class STLRB
|
7
|
+
def initialize rt, rn
|
8
|
+
@rt = rt
|
9
|
+
@rn = rn
|
10
|
+
end
|
11
|
+
|
12
|
+
def encode
|
13
|
+
self.STLRB(@rn.to_i, @rt.to_i)
|
14
|
+
end
|
15
|
+
|
16
|
+
private
|
17
|
+
|
18
|
+
def STLRB rn, rt
|
19
|
+
insn = 0b00_001000_1_0_0_11111_1_11111_00000_00000
|
20
|
+
insn |= ((rn & 0x1f) << 5)
|
21
|
+
insn |= (rt & 0x1f)
|
22
|
+
insn
|
23
|
+
end
|
24
|
+
end
|
25
|
+
end
|
26
|
+
end
|
@@ -0,0 +1,26 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# STLRH -- A64
|
4
|
+
# Store-Release Register Halfword
|
5
|
+
# STLRH <Wt>, [<Xn|SP>{,#0}]
|
6
|
+
class STLRH
|
7
|
+
def initialize rt, rn
|
8
|
+
@rt = rt
|
9
|
+
@rn = rn
|
10
|
+
end
|
11
|
+
|
12
|
+
def encode
|
13
|
+
self.STLRH(@rn.to_i, @rt.to_i)
|
14
|
+
end
|
15
|
+
|
16
|
+
private
|
17
|
+
|
18
|
+
def STLRH rn, rt
|
19
|
+
insn = 0b01_001000_1_0_0_11111_1_11111_00000_00000
|
20
|
+
insn |= ((rn & 0x1f) << 5)
|
21
|
+
insn |= (rt & 0x1f)
|
22
|
+
insn
|
23
|
+
end
|
24
|
+
end
|
25
|
+
end
|
26
|
+
end
|
@@ -0,0 +1,31 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# STLUR -- A64
|
4
|
+
# Store-Release Register (unscaled)
|
5
|
+
# STLUR <Wt>, [<Xn|SP>{, #<simm>}]
|
6
|
+
# STLUR <Xt>, [<Xn|SP>{, #<simm>}]
|
7
|
+
class STLUR_gen
|
8
|
+
def initialize rt, rn, imm9, size
|
9
|
+
@rt = rt
|
10
|
+
@rn = rn
|
11
|
+
@imm9 = imm9
|
12
|
+
@size = size
|
13
|
+
end
|
14
|
+
|
15
|
+
def encode
|
16
|
+
self.STLUR_gen(@size, @imm9, @rn.to_i, @rt.to_i)
|
17
|
+
end
|
18
|
+
|
19
|
+
private
|
20
|
+
|
21
|
+
def STLUR_gen size, imm9, rn, rt
|
22
|
+
insn = 0b00_011001_00_0_000000000_00_00000_00000
|
23
|
+
insn |= ((size & 0x3) << 30)
|
24
|
+
insn |= ((imm9 & 0x1ff) << 12)
|
25
|
+
insn |= ((rn & 0x1f) << 5)
|
26
|
+
insn |= (rt & 0x1f)
|
27
|
+
insn
|
28
|
+
end
|
29
|
+
end
|
30
|
+
end
|
31
|
+
end
|
@@ -0,0 +1,33 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# STLXP -- A64
|
4
|
+
# Store-Release Exclusive Pair of registers
|
5
|
+
# STLXP <Ws>, <Wt1>, <Wt2>, [<Xn|SP>{,#0}]
|
6
|
+
# STLXP <Ws>, <Xt1>, <Xt2>, [<Xn|SP>{,#0}]
|
7
|
+
class STLXP
|
8
|
+
def initialize rs, rt, rt2, rn, sz
|
9
|
+
@rs = rs
|
10
|
+
@rt = rt
|
11
|
+
@rt2 = rt2
|
12
|
+
@rn = rn
|
13
|
+
@sz = sz
|
14
|
+
end
|
15
|
+
|
16
|
+
def encode
|
17
|
+
self.STLXP(@sz, @rs.to_i, @rt2.to_i, @rn.to_i, @rt.to_i)
|
18
|
+
end
|
19
|
+
|
20
|
+
private
|
21
|
+
|
22
|
+
def STLXP sz, rs, rt2, rn, rt
|
23
|
+
insn = 0b1_0_001000_0_0_1_00000_1_00000_00000_00000
|
24
|
+
insn |= ((sz & 0x1) << 30)
|
25
|
+
insn |= ((rs & 0x1f) << 16)
|
26
|
+
insn |= ((rt2 & 0x1f) << 10)
|
27
|
+
insn |= ((rn & 0x1f) << 5)
|
28
|
+
insn |= (rt & 0x1f)
|
29
|
+
insn
|
30
|
+
end
|
31
|
+
end
|
32
|
+
end
|
33
|
+
end
|
@@ -0,0 +1,31 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# STLXR -- A64
|
4
|
+
# Store-Release Exclusive Register
|
5
|
+
# STLXR <Ws>, <Wt>, [<Xn|SP>{,#0}]
|
6
|
+
# STLXR <Ws>, <Xt>, [<Xn|SP>{,#0}]
|
7
|
+
class STLXR
|
8
|
+
def initialize rs, rt, rn, size
|
9
|
+
@rs = rs
|
10
|
+
@rt = rt
|
11
|
+
@rn = rn
|
12
|
+
@size = size
|
13
|
+
end
|
14
|
+
|
15
|
+
def encode
|
16
|
+
self.STLXR(@size, @rs.to_i, @rn.to_i, @rt.to_i)
|
17
|
+
end
|
18
|
+
|
19
|
+
private
|
20
|
+
|
21
|
+
def STLXR size, rs, rn, rt
|
22
|
+
insn = 0b00_001000_0_0_0_00000_1_11111_00000_00000
|
23
|
+
insn |= ((size & 0x3) << 30)
|
24
|
+
insn |= ((rs & 0x1f) << 16)
|
25
|
+
insn |= ((rn & 0x1f) << 5)
|
26
|
+
insn |= (rt & 0x1f)
|
27
|
+
insn
|
28
|
+
end
|
29
|
+
end
|
30
|
+
end
|
31
|
+
end
|
@@ -0,0 +1,28 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# STLXRB -- A64
|
4
|
+
# Store-Release Exclusive Register Byte
|
5
|
+
# STLXRB <Ws>, <Wt>, [<Xn|SP>{,#0}]
|
6
|
+
class STLXRB
|
7
|
+
def initialize rs, rt, rn
|
8
|
+
@rs = rs
|
9
|
+
@rt = rt
|
10
|
+
@rn = rn
|
11
|
+
end
|
12
|
+
|
13
|
+
def encode
|
14
|
+
self.STLXRB(@rs.to_i, @rn.to_i, @rt.to_i)
|
15
|
+
end
|
16
|
+
|
17
|
+
private
|
18
|
+
|
19
|
+
def STLXRB rs, rn, rt
|
20
|
+
insn = 0b00_001000_0_0_0_00000_1_11111_00000_00000
|
21
|
+
insn |= ((rs & 0x1f) << 16)
|
22
|
+
insn |= ((rn & 0x1f) << 5)
|
23
|
+
insn |= (rt & 0x1f)
|
24
|
+
insn
|
25
|
+
end
|
26
|
+
end
|
27
|
+
end
|
28
|
+
end
|
@@ -0,0 +1,28 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# STLXRH -- A64
|
4
|
+
# Store-Release Exclusive Register Halfword
|
5
|
+
# STLXRH <Ws>, <Wt>, [<Xn|SP>{,#0}]
|
6
|
+
class STLXRH
|
7
|
+
def initialize rs, rt, rn
|
8
|
+
@rs = rs
|
9
|
+
@rt = rt
|
10
|
+
@rn = rn
|
11
|
+
end
|
12
|
+
|
13
|
+
def encode
|
14
|
+
self.STLXRH(@rs.to_i, @rn.to_i, @rt.to_i)
|
15
|
+
end
|
16
|
+
|
17
|
+
private
|
18
|
+
|
19
|
+
def STLXRH rs, rn, rt
|
20
|
+
insn = 0b01_001000_0_0_0_00000_1_11111_00000_00000
|
21
|
+
insn |= ((rs & 0x1f) << 16)
|
22
|
+
insn |= ((rn & 0x1f) << 5)
|
23
|
+
insn |= (rt & 0x1f)
|
24
|
+
insn
|
25
|
+
end
|
26
|
+
end
|
27
|
+
end
|
28
|
+
end
|
@@ -0,0 +1,33 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# STNP -- A64
|
4
|
+
# Store Pair of Registers, with non-temporal hint
|
5
|
+
# STNP <Wt1>, <Wt2>, [<Xn|SP>{, #<imm>}]
|
6
|
+
# STNP <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]
|
7
|
+
class STNP_gen
|
8
|
+
def initialize rt, rt2, rn, imm7, opc
|
9
|
+
@rt = rt
|
10
|
+
@rt2 = rt2
|
11
|
+
@rn = rn
|
12
|
+
@imm7 = imm7
|
13
|
+
@opc = opc
|
14
|
+
end
|
15
|
+
|
16
|
+
def encode
|
17
|
+
self.STNP_gen(@opc, @imm7, @rt2.to_i, @rn.to_i, @rt.to_i)
|
18
|
+
end
|
19
|
+
|
20
|
+
private
|
21
|
+
|
22
|
+
def STNP_gen opc, imm7, rt2, rn, rt
|
23
|
+
insn = 0b00_101_0_000_0_0000000_00000_00000_00000
|
24
|
+
insn |= ((opc & 0x3) << 30)
|
25
|
+
insn |= ((imm7 & 0x7f) << 15)
|
26
|
+
insn |= ((rt2 & 0x1f) << 10)
|
27
|
+
insn |= ((rn & 0x1f) << 5)
|
28
|
+
insn |= (rt & 0x1f)
|
29
|
+
insn
|
30
|
+
end
|
31
|
+
end
|
32
|
+
end
|
33
|
+
end
|
@@ -0,0 +1,39 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# STP -- A64
|
4
|
+
# Store Pair of Registers
|
5
|
+
# STP <Wt1>, <Wt2>, [<Xn|SP>], #<imm>
|
6
|
+
# STP <Xt1>, <Xt2>, [<Xn|SP>], #<imm>
|
7
|
+
# STP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]!
|
8
|
+
# STP <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]!
|
9
|
+
# STP <Wt1>, <Wt2>, [<Xn|SP>{, #<imm>}]
|
10
|
+
# STP <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]
|
11
|
+
class STP_gen
|
12
|
+
def initialize rt, rt2, rn, imm7, opc, option
|
13
|
+
@rt = rt
|
14
|
+
@rt2 = rt2
|
15
|
+
@rn = rn
|
16
|
+
@imm7 = imm7
|
17
|
+
@opc = opc
|
18
|
+
@option = option
|
19
|
+
end
|
20
|
+
|
21
|
+
def encode
|
22
|
+
self.STP_gen(@opc, @option, @imm7, @rt2.to_i, @rn.to_i, @rt.to_i)
|
23
|
+
end
|
24
|
+
|
25
|
+
private
|
26
|
+
|
27
|
+
def STP_gen opc, option, imm7, rt2, rn, rt
|
28
|
+
insn = 0b00_101_0_000_0_0000000_00000_00000_00000
|
29
|
+
insn |= ((opc & 0x3) << 30)
|
30
|
+
insn |= ((option & 0x7) << 23)
|
31
|
+
insn |= ((imm7 & 0x7f) << 15)
|
32
|
+
insn |= ((rt2 & 0x1f) << 10)
|
33
|
+
insn |= ((rn & 0x1f) << 5)
|
34
|
+
insn |= (rt & 0x1f)
|
35
|
+
insn
|
36
|
+
end
|
37
|
+
end
|
38
|
+
end
|
39
|
+
end
|
@@ -0,0 +1,37 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# STR (immediate) -- A64
|
4
|
+
# Store Register (immediate)
|
5
|
+
# STR <Wt>, [<Xn|SP>], #<simm>
|
6
|
+
# STR <Xt>, [<Xn|SP>], #<simm>
|
7
|
+
# STR <Wt>, [<Xn|SP>, #<simm>]!
|
8
|
+
# STR <Xt>, [<Xn|SP>, #<simm>]!
|
9
|
+
# STR <Wt>, [<Xn|SP>{, #<pimm>}]
|
10
|
+
# STR <Xt>, [<Xn|SP>{, #<pimm>}]
|
11
|
+
class STR_imm_gen
|
12
|
+
def initialize rt, rn, imm9, opt, size
|
13
|
+
@rt = rt
|
14
|
+
@rn = rn
|
15
|
+
@imm9 = imm9
|
16
|
+
@opt = opt
|
17
|
+
@size = size
|
18
|
+
end
|
19
|
+
|
20
|
+
def encode
|
21
|
+
self.STR_imm_gen(@size, @imm9, @opt, @rn.to_i, @rt.to_i)
|
22
|
+
end
|
23
|
+
|
24
|
+
private
|
25
|
+
|
26
|
+
def STR_imm_gen size, imm9, opt, rn, rt
|
27
|
+
insn = 0b00_111_0_00_00_0_000000000_00_00000_00000
|
28
|
+
insn |= ((size & 0x3) << 30)
|
29
|
+
insn |= ((imm9 & 0x1ff) << 12)
|
30
|
+
insn |= ((opt & 0x3) << 10)
|
31
|
+
insn |= ((rn & 0x1f) << 5)
|
32
|
+
insn |= (rt & 0x1f)
|
33
|
+
insn
|
34
|
+
end
|
35
|
+
end
|
36
|
+
end
|
37
|
+
end
|
@@ -0,0 +1,31 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# STR (immediate) -- A64
|
4
|
+
# Store Register (immediate)
|
5
|
+
# STR <Wt>, [<Xn|SP>{, #<pimm>}]
|
6
|
+
# STR <Xt>, [<Xn|SP>{, #<pimm>}]
|
7
|
+
class STR_imm_unsigned
|
8
|
+
def initialize rt, rn, imm12, size
|
9
|
+
@rt = rt
|
10
|
+
@rn = rn
|
11
|
+
@imm12 = imm12
|
12
|
+
@size = size
|
13
|
+
end
|
14
|
+
|
15
|
+
def encode
|
16
|
+
self.STR_imm_gen(@size, @imm12, @rn.to_i, @rt.to_i)
|
17
|
+
end
|
18
|
+
|
19
|
+
private
|
20
|
+
|
21
|
+
def STR_imm_gen size, imm12, rn, rt
|
22
|
+
insn = 0b00_111_0_01_00_0_000000000_00_00000_00000
|
23
|
+
insn |= ((size & 0x3) << 30)
|
24
|
+
insn |= ((imm12 & 0xfff) << 10)
|
25
|
+
insn |= ((rn & 0x1f) << 5)
|
26
|
+
insn |= (rt & 0x1f)
|
27
|
+
insn
|
28
|
+
end
|
29
|
+
end
|
30
|
+
end
|
31
|
+
end
|
@@ -0,0 +1,35 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# STR (register) -- A64
|
4
|
+
# Store Register (register)
|
5
|
+
# STR <Wt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
|
6
|
+
# STR <Xt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
|
7
|
+
class STR_reg_gen
|
8
|
+
def initialize rt, rn, rm, option, s, size
|
9
|
+
@rt = rt
|
10
|
+
@rn = rn
|
11
|
+
@rm = rm
|
12
|
+
@option = option
|
13
|
+
@s = s
|
14
|
+
@size = size
|
15
|
+
end
|
16
|
+
|
17
|
+
def encode
|
18
|
+
self.STR_reg_gen(@size, @rm.to_i, @option, @s, @rn.to_i, @rt.to_i)
|
19
|
+
end
|
20
|
+
|
21
|
+
private
|
22
|
+
|
23
|
+
def STR_reg_gen size, rm, option, s, rn, rt
|
24
|
+
insn = 0b00_111_0_00_00_1_00000_000_0_10_00000_00000
|
25
|
+
insn |= ((size & 0x3) << 30)
|
26
|
+
insn |= ((rm & 0x1f) << 16)
|
27
|
+
insn |= ((option & 0x7) << 13)
|
28
|
+
insn |= ((s & 0x1) << 12)
|
29
|
+
insn |= ((rn & 0x1f) << 5)
|
30
|
+
insn |= (rt & 0x1f)
|
31
|
+
insn
|
32
|
+
end
|
33
|
+
end
|
34
|
+
end
|
35
|
+
end
|
@@ -0,0 +1,32 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# STRB (immediate) -- A64
|
4
|
+
# Store Register Byte (immediate)
|
5
|
+
# STRB <Wt>, [<Xn|SP>], #<simm>
|
6
|
+
# STRB <Wt>, [<Xn|SP>, #<simm>]!
|
7
|
+
# STRB <Wt>, [<Xn|SP>{, #<pimm>}]
|
8
|
+
class STRB_imm
|
9
|
+
def initialize rt, rn, imm9, opt
|
10
|
+
@rt = rt
|
11
|
+
@rn = rn
|
12
|
+
@imm9 = imm9
|
13
|
+
@opt = opt
|
14
|
+
end
|
15
|
+
|
16
|
+
def encode
|
17
|
+
self.STRB_imm(@imm9, @opt, @rn.to_i, @rt.to_i)
|
18
|
+
end
|
19
|
+
|
20
|
+
private
|
21
|
+
|
22
|
+
def STRB_imm imm9, opt, rn, rt
|
23
|
+
insn = 0b00_111_0_00_00_0_000000000_00_00000_00000
|
24
|
+
insn |= ((imm9 & 0x1ff) << 12)
|
25
|
+
insn |= ((opt & 0x3) << 10)
|
26
|
+
insn |= ((rn & 0x1f) << 5)
|
27
|
+
insn |= (rt & 0x1f)
|
28
|
+
insn
|
29
|
+
end
|
30
|
+
end
|
31
|
+
end
|
32
|
+
end
|
@@ -0,0 +1,28 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# STRB (immediate) -- A64
|
4
|
+
# Store Register Byte (immediate)
|
5
|
+
# STRB <Wt>, [<Xn|SP>{, #<pimm>}]
|
6
|
+
class STRB_imm_unsigned
|
7
|
+
def initialize rt, rn, imm12
|
8
|
+
@rt = rt
|
9
|
+
@rn = rn
|
10
|
+
@imm12 = imm12
|
11
|
+
end
|
12
|
+
|
13
|
+
def encode
|
14
|
+
self.STRB_imm_unsigned(@imm12, @rn.to_i, @rt.to_i)
|
15
|
+
end
|
16
|
+
|
17
|
+
private
|
18
|
+
|
19
|
+
def STRB_imm_unsigned imm12, rn, rt
|
20
|
+
insn = 0b00_111_0_01_00_0_000000000_00_00000_00000
|
21
|
+
insn |= ((imm12 & 0xfff) << 10)
|
22
|
+
insn |= ((rn & 0x1f) << 5)
|
23
|
+
insn |= (rt & 0x1f)
|
24
|
+
insn
|
25
|
+
end
|
26
|
+
end
|
27
|
+
end
|
28
|
+
end
|
@@ -0,0 +1,33 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# STRB (register) -- A64
|
4
|
+
# Store Register Byte (register)
|
5
|
+
# STRB <Wt>, [<Xn|SP>, (<Wm>|<Xm>), <extend> {<amount>}]
|
6
|
+
# STRB <Wt>, [<Xn|SP>, <Xm>{, LSL <amount>}]
|
7
|
+
class STRB_reg
|
8
|
+
def initialize rt, rn, rm, option, s
|
9
|
+
@rt = rt
|
10
|
+
@rn = rn
|
11
|
+
@rm = rm
|
12
|
+
@option = option
|
13
|
+
@s = s
|
14
|
+
end
|
15
|
+
|
16
|
+
def encode
|
17
|
+
self.STRB_reg(@rm.to_i, @option, @s, @rn.to_i, @rt.to_i)
|
18
|
+
end
|
19
|
+
|
20
|
+
private
|
21
|
+
|
22
|
+
def STRB_reg rm, option, s, rn, rt
|
23
|
+
insn = 0b00_111_0_00_00_1_00000_000_0_10_00000_00000
|
24
|
+
insn |= ((rm & 0x1f) << 16)
|
25
|
+
insn |= ((option & 0x7) << 13)
|
26
|
+
insn |= ((s & 0x1) << 12)
|
27
|
+
insn |= ((rn & 0x1f) << 5)
|
28
|
+
insn |= (rt & 0x1f)
|
29
|
+
insn
|
30
|
+
end
|
31
|
+
end
|
32
|
+
end
|
33
|
+
end
|
@@ -0,0 +1,32 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# STRH (immediate) -- A64
|
4
|
+
# Store Register Halfword (immediate)
|
5
|
+
# STRH <Wt>, [<Xn|SP>], #<simm>
|
6
|
+
# STRH <Wt>, [<Xn|SP>, #<simm>]!
|
7
|
+
# STRH <Wt>, [<Xn|SP>{, #<pimm>}]
|
8
|
+
class STRH_imm
|
9
|
+
def initialize rt, rn, imm9, opt
|
10
|
+
@rt = rt
|
11
|
+
@rn = rn
|
12
|
+
@imm9 = imm9
|
13
|
+
@opt = opt
|
14
|
+
end
|
15
|
+
|
16
|
+
def encode
|
17
|
+
self.STRH_imm(@imm9, @opt, @rn.to_i, @rt.to_i)
|
18
|
+
end
|
19
|
+
|
20
|
+
private
|
21
|
+
|
22
|
+
def STRH_imm imm9, opt, rn, rt
|
23
|
+
insn = 0b01_111_0_00_00_0_000000000_00_00000_00000
|
24
|
+
insn |= ((imm9 & 0x1ff) << 12)
|
25
|
+
insn |= ((opt & 0x3) << 10)
|
26
|
+
insn |= ((rn & 0x1f) << 5)
|
27
|
+
insn |= (rt & 0x1f)
|
28
|
+
insn
|
29
|
+
end
|
30
|
+
end
|
31
|
+
end
|
32
|
+
end
|