aarch64 1.0.0

data/lib/aarch64/instructions/strh_imm_unsigned.rb

@@ -0,0 +1,28 @@
+module AArch64
+  module Instructions
+    # STRH (immediate) -- A64
+    # Store Register Halfword (immediate)
+    # STRH  <Wt>, [<Xn|SP>{, #<pimm>}]
+    class STRH_imm_unsigned
+      def initialize rt, rn, imm12
+        @rt    = rt
+        @rn    = rn
+        @imm12 = imm12
+      end
+
+      def encode
+        self.STRH_imm_unsigned(@imm12, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def STRH_imm_unsigned imm12, rn, rt
+        insn = 0b01_111_0_01_00_0_000000000_00_00000_00000
+        insn |= ((imm12 & 0xfff) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/strh_reg.rb

@@ -0,0 +1,32 @@
+module AArch64
+  module Instructions
+    # STRH (register) -- A64
+    # Store Register Halfword (register)
+    # STRH  <Wt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
+    class STRH_reg
+      def initialize rt, rn, rm, option, s
+        @rt     = rt
+        @rn     = rn
+        @rm     = rm
+        @option = option
+        @s      = s
+      end
+
+      def encode
+        self.STRH_reg(@rm.to_i, @option, @s, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def STRH_reg rm, option, s, rn, rt
+        insn = 0b01_111_0_00_00_1_00000_000_0_10_00000_00000
+        insn |= ((rm & 0x1f) << 16)
+        insn |= ((option & 0x7) << 13)
+        insn |= ((s & 0x1) << 12)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/sttr.rb

@@ -0,0 +1,31 @@
+module AArch64
+  module Instructions
+    # STTR -- A64
+    # Store Register (unprivileged)
+    # STTR  <Wt>, [<Xn|SP>{, #<simm>}]
+    # STTR  <Xt>, [<Xn|SP>{, #<simm>}]
+    class STTR
+      def initialize rt, rn, imm9, size
+        @rt   = rt
+        @rn   = rn
+        @imm9 = imm9
+        @size = size
+      end
+
+      def encode
+        self.STTR(@size, @imm9, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def STTR size, imm9, rn, rt
+        insn = 0b00_111_0_00_00_0_000000000_10_00000_00000
+        insn |= ((size & 0x3) << 30)
+        insn |= ((imm9 & 0x1ff) << 12)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/stur_gen.rb

@@ -0,0 +1,31 @@
+module AArch64
+  module Instructions
+    # STUR -- A64
+    # Store Register (unscaled)
+    # STUR  <Wt>, [<Xn|SP>{, #<simm>}]
+    # STUR  <Xt>, [<Xn|SP>{, #<simm>}]
+    class STUR_gen
+      def initialize rt, rn, imm9, size
+        @rt   = rt
+        @rn   = rn
+        @imm9 = imm9
+        @size = size
+      end
+
+      def encode
+        self.STUR_gen(@size, @imm9, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def STUR_gen size, imm9, rn, rt
+        insn = 0b00_111_0_00_00_0_000000000_00_00000_00000
+        insn |= ((size & 0x3) << 30)
+        insn |= ((imm9 & 0x1ff) << 12)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/stxp.rb

@@ -0,0 +1,33 @@
+module AArch64
+  module Instructions
+    # STXP -- A64
+    # Store Exclusive Pair of registers
+    # STXP  <Ws>, <Wt1>, <Wt2>, [<Xn|SP>{,#0}]
+    # STXP  <Ws>, <Xt1>, <Xt2>, [<Xn|SP>{,#0}]
+    class STXP
+      def initialize rs, rt1, rt2, rn, sf
+        @rs  = rs
+        @rt1 = rt1
+        @rt2 = rt2
+        @rn  = rn
+        @sf  = sf
+      end
+
+      def encode
+        self.STXP(@sf, @rs.to_i, @rt2.to_i, @rn.to_i, @rt1.to_i)
+      end
+
+      private
+
+      def STXP sz, rs, rt2, rn, rt
+        insn = 0b1_0_001000_0_0_1_00000_0_00000_00000_00000
+        insn |= ((sz & 0x1) << 30)
+        insn |= ((rs & 0x1f) << 16)
+        insn |= ((rt2 & 0x1f) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/stxr.rb

@@ -0,0 +1,31 @@
+module AArch64
+  module Instructions
+    # STXR -- A64
+    # Store Exclusive Register
+    # STXR  <Ws>, <Wt>, [<Xn|SP>{,#0}]
+    # STXR  <Ws>, <Xt>, [<Xn|SP>{,#0}]
+    class STXR
+      def initialize rs, rt, rn, size
+        @rs   = rs
+        @rt   = rt
+        @rn   = rn
+        @size = size
+      end
+
+      def encode
+        self.STXR(@size, @rs.to_i, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def STXR size, rs, rn, rt
+        insn = 0b00_001000_0_0_0_00000_0_11111_00000_00000
+        insn |= ((size & 0x3) << 30)
+        insn |= ((rs & 0x1f) << 16)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/stxrb.rb

@@ -0,0 +1,28 @@
+module AArch64
+  module Instructions
+    # STXRB -- A64
+    # Store Exclusive Register Byte
+    # STXRB  <Ws>, <Wt>, [<Xn|SP>{,#0}]
+    class STXRB
+      def initialize rs, rt, rn
+        @rs = rs
+        @rt = rt
+        @rn = rn
+      end
+
+      def encode
+        self.STXRB(@rs.to_i, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def STXRB rs, rn, rt
+        insn = 0b00_001000_0_0_0_00000_0_11111_00000_00000
+        insn |= ((rs & 0x1f) << 16)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/stxrh.rb

@@ -0,0 +1,28 @@
+module AArch64
+  module Instructions
+    # STXRH -- A64
+    # Store Exclusive Register Halfword
+    # STXRH  <Ws>, <Wt>, [<Xn|SP>{,#0}]
+    class STXRH
+      def initialize rs, rt, rn
+        @rs = rs
+        @rt = rt
+        @rn = rn
+      end
+
+      def encode
+        self.STXRH(@rs.to_i, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def STXRH rs, rn, rt
+        insn = 0b01_001000_0_0_0_00000_0_11111_00000_00000
+        insn |= ((rs & 0x1f) << 16)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/stz2g.rb

@@ -0,0 +1,32 @@
+module AArch64
+  module Instructions
+    # STZ2G -- A64
+    # Store Allocation Tags, Zeroing
+    # STZ2G  <Xt|SP>, [<Xn|SP>], #<simm>
+    # STZ2G  <Xt|SP>, [<Xn|SP>, #<simm>]!
+    # STZ2G  <Xt|SP>, [<Xn|SP>{, #<simm>}]
+    class STZ2G
+      def initialize xt, xn, imm9, opt
+        @xt   = xt
+        @xn   = xn
+        @imm9 = imm9
+        @opt  = opt
+      end
+
+      def encode
+        self.STZ2G(@imm9, @opt, @xn.to_i, @xt.to_i)
+      end
+
+      private
+
+      def STZ2G imm9, opt, xn, xt
+        insn = 0b11011001_1_1_1_000000000_00_00000_00000
+        insn |= ((imm9 & 0x1ff) << 12)
+        insn |= ((opt & 0x3) << 10)
+        insn |= ((xn & 0x1f) << 5)
+        insn |= (xt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/stzg.rb

@@ -0,0 +1,32 @@
+module AArch64
+  module Instructions
+    # STZG -- A64
+    # Store Allocation Tag, Zeroing
+    # STZG  <Xt|SP>, [<Xn|SP>], #<simm>
+    # STZG  <Xt|SP>, [<Xn|SP>, #<simm>]!
+    # STZG  <Xt|SP>, [<Xn|SP>{, #<simm>}]
+    class STZG
+      def initialize xt, xn, imm9, opt
+        @xt   = xt
+        @xn   = xn
+        @imm9 = imm9
+        @opt  = opt
+      end
+
+      def encode
+        self.STZG(@imm9, @opt, @xn.to_i, @xt.to_i)
+      end
+
+      private
+
+      def STZG imm9, opt, xn, xt
+        insn = 0b11011001_0_1_1_000000000_00_00000_00000
+        insn |= ((imm9 & 0x1ff) << 12)
+        insn |= ((opt & 0x3) << 10)
+        insn |= ((xn & 0x1f) << 5)
+        insn |= (xt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/stzgm.rb

@@ -0,0 +1,26 @@
+module AArch64
+  module Instructions
+    # STZGM -- A64
+    # Store Tag and Zero Multiple
+    # STZGM  <Xt>, [<Xn|SP>]
+    class STZGM
+      def initialize rt, rn
+        @rt = rt
+        @rn = rn
+      end
+
+      def encode
+        self.STZGM(@rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def STZGM xn, xt
+        insn = 0b11011001_0_0_1_0_0_0_0_0_0_0_0_0_0_0_00000_00000
+        insn |= ((xn & 0x1f) << 5)
+        insn |= (xt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/sub_addsub_ext.rb

@@ -0,0 +1,35 @@
+module AArch64
+  module Instructions
+    # SUB (extended register) -- A64
+    # Subtract (extended register)
+    # SUB  <Wd|WSP>, <Wn|WSP>, <Wm>{, <extend> {#<amount>}}
+    # SUB  <Xd|SP>, <Xn|SP>, <R><m>{, <extend> {#<amount>}}
+    class SUB_addsub_ext
+      def initialize rd, rn, rm, extend, amount, sf
+        @rd     = rd
+        @rn     = rn
+        @rm     = rm
+        @extend = extend
+        @amount = amount
+        @sf     = sf
+      end
+
+      def encode
+        self.SUB_addsub_ext(@sf, @rm.to_i, @extend, @amount, @rn.to_i, @rd.to_i)
+      end
+
+      private
+
+      def SUB_addsub_ext sf, rm, option, imm3, rn, rd
+        insn = 0b0_1_0_01011_00_1_00000_000_000_00000_00000
+        insn |= ((sf & 0x1) << 31)
+        insn |= ((rm & 0x1f) << 16)
+        insn |= ((option & 0x7) << 13)
+        insn |= ((imm3 & 0x7) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/sub_addsub_imm.rb

@@ -0,0 +1,33 @@
+module AArch64
+  module Instructions
+    # SUB (immediate) -- A64
+    # Subtract (immediate)
+    # SUB  <Wd|WSP>, <Wn|WSP>, #<imm>{, <shift>}
+    # SUB  <Xd|SP>, <Xn|SP>, #<imm>{, <shift>}
+    class SUB_addsub_imm
+      def initialize rd, rn, imm, shift, sf
+        @rd    = rd
+        @rn    = rn
+        @imm   = imm
+        @shift = shift
+        @sf    = sf
+      end
+
+      def encode
+        self.SUB_addsub_imm(@sf, @shift, @imm, @rn.to_i, @rd.to_i)
+      end
+
+      private
+
+      def SUB_addsub_imm sf, sh, imm12, rn, rd
+        insn = 0b0_1_0_100010_0_000000000000_00000_00000
+        insn |= ((sf & 0x1) << 31)
+        insn |= ((sh & 0x1) << 22)
+        insn |= ((imm12 & 0xfff) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/sub_addsub_shift.rb

@@ -0,0 +1,35 @@
+module AArch64
+  module Instructions
+    # SUB (shifted register) -- A64
+    # Subtract (shifted register)
+    # SUB  <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
+    # SUB  <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
+    class SUB_addsub_shift
+      def initialize rd, rn, rm, shift, amount, sf
+        @rd     = rd
+        @rn     = rn
+        @rm     = rm
+        @shift  = shift
+        @amount = amount
+        @sf     = sf
+      end
+
+      def encode
+        self.SUB_addsub_shift(@sf, @shift, @rm.to_i, @amount, @rn.to_i, @rd.to_i)
+      end
+
+      private
+
+      def SUB_addsub_shift sf, shift, rm, imm6, rn, rd
+        insn = 0b0_1_0_01011_00_0_00000_000000_00000_00000
+        insn |= ((sf & 0x1) << 31)
+        insn |= ((shift & 0x3) << 22)
+        insn |= ((rm & 0x1f) << 16)
+        insn |= ((imm6 & 0x3f) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/subg.rb

@@ -0,0 +1,30 @@
+module AArch64
+  module Instructions
+    # SUBG -- A64
+    # Subtract with Tag
+    # SUBG  <Xd|SP>, <Xn|SP>, #<uimm6>, #<uimm4>
+    class SUBG
+      def initialize xd, xn, uimm6, uimm4
+        @xd    = xd
+        @xn    = xn
+        @uimm6 = uimm6
+        @uimm4 = uimm4
+      end
+
+      def encode
+        self.SUBG(@uimm6, @uimm4, @xn.to_i, @xd.to_i)
+      end
+
+      private
+
+      def SUBG uimm6, uimm4, xn, xd
+        insn = 0b1_1_0_100011_0_000000_00_0000_00000_00000
+        insn |= ((uimm6 & 0x3f) << 16)
+        insn |= ((uimm4 & 0xf) << 10)
+        insn |= ((xn & 0x1f) << 5)
+        insn |= (xd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/subp.rb

@@ -0,0 +1,28 @@
+module AArch64
+  module Instructions
+    # SUBP -- A64
+    # Subtract Pointer
+    # SUBP  <Xd>, <Xn|SP>, <Xm|SP>
+    class SUBP
+      def initialize xd, xn, xm
+        @xd = xd
+        @xn = xn
+        @xm = xm
+      end
+
+      def encode
+        self.SUBP(@xm.to_i, @xn.to_i, @xm.to_i)
+      end
+
+      private
+
+      def SUBP xm, xn, xd
+        insn = 0b1_0_0_11010110_00000_0_0_0_0_0_0_00000_00000
+        insn |= ((xm & 0x1f) << 16)
+        insn |= ((xn & 0x1f) << 5)
+        insn |= (xd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/subps.rb

@@ -0,0 +1,28 @@
+module AArch64
+  module Instructions
+    # SUBPS -- A64
+    # Subtract Pointer, setting Flags
+    # SUBPS  <Xd>, <Xn|SP>, <Xm|SP>
+    class SUBPS
+      def initialize xd, xn, xm
+        @xd = xd
+        @xn = xn
+        @xm = xm
+      end
+
+      def encode
+        self.SUBPS(@xm.to_i, @xn.to_i, @xd.to_i)
+      end
+
+      private
+
+      def SUBPS xm, xn, xd
+        insn = 0b1_0_1_11010110_00000_0_0_0_0_0_0_00000_00000
+        insn |= ((xm & 0x1f) << 16)
+        insn |= ((xn & 0x1f) << 5)
+        insn |= (xd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/subs_addsub_ext.rb

@@ -0,0 +1,35 @@
+module AArch64
+  module Instructions
+    # SUBS (extended register) -- A64
+    # Subtract (extended register), setting flags
+    # SUBS  <Wd>, <Wn|WSP>, <Wm>{, <extend> {#<amount>}}
+    # SUBS  <Xd>, <Xn|SP>, <R><m>{, <extend> {#<amount>}}
+    class SUBS_addsub_ext
+      def initialize rd, rn, rm, extend, amount, sf
+        @rd     = rd
+        @rn     = rn
+        @rm     = rm
+        @extend = extend
+        @amount = amount
+        @sf     = sf
+      end
+
+      def encode
+        SUBS_addsub_ext(@sf, @rm.to_i, @extend, @amount, @rn.to_i, @rd.to_i)
+      end
+
+      private
+
+      def SUBS_addsub_ext sf, rm, option, imm3, rn, rd
+        insn = 0b0_1_1_01011_00_1_00000_000_000_00000_00000
+        insn |= ((sf & 0x1) << 31)
+        insn |= ((rm & 0x1f) << 16)
+        insn |= ((option & 0x7) << 13)
+        insn |= ((imm3 & 0x7) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/subs_addsub_imm.rb

@@ -0,0 +1,33 @@
+module AArch64
+  module Instructions
+    # SUBS (immediate) -- A64
+    # Subtract (immediate), setting flags
+    # SUBS  <Wd>, <Wn|WSP>, #<imm>{, <shift>}
+    # SUBS  <Xd>, <Xn|SP>, #<imm>{, <shift>}
+    class SUBS_addsub_imm
+      def initialize rd, rn, imm, shift, sf
+        @rd    = rd
+        @rn    = rn
+        @imm   = imm
+        @shift = shift
+        @sf    = sf
+      end
+
+      def encode
+        SUBS_addsub_imm(@sf, @shift, @imm, @rn.to_i, @rd.to_i)
+      end
+
+      private
+
+      def SUBS_addsub_imm sf, sh, imm12, rn, rd
+        insn = 0b0_1_1_100010_0_000000000000_00000_00000
+        insn |= ((sf & 0x1) << 31)
+        insn |= ((sh & 0x1) << 22)
+        insn |= ((imm12 & 0xfff) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/subs_addsub_shift.rb

@@ -0,0 +1,35 @@
+module AArch64
+  module Instructions
+    # SUBS (shifted register) -- A64
+    # Subtract (shifted register), setting flags
+    # SUBS  <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
+    # SUBS  <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
+    class SUBS_addsub_shift
+      def initialize rd, rn, rm, shift, amount, sf
+        @rd     = rd
+        @rn     = rn
+        @rm     = rm
+        @shift  = shift
+        @amount = amount
+        @sf     = sf
+      end
+
+      def encode
+        SUBS_addsub_shift(@sf, @shift, @rm.to_i, @amount, @rn.to_i, @rd.to_i)
+      end
+
+      private
+
+      def SUBS_addsub_shift sf, shift, rm, imm6, rn, rd
+        insn = 0b0_1_1_01011_00_0_00000_000000_00000_00000
+        insn |= ((sf & 0x1) << 31)
+        insn |= ((shift & 0x3) << 22)
+        insn |= ((rm & 0x1f) << 16)
+        insn |= ((imm6 & 0x3f) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/svc.rb

@@ -0,0 +1,24 @@
+module AArch64
+  module Instructions
+    # SVC -- A64
+    # Supervisor Call
+    # SVC  #<imm>
+    class SVC
+      def initialize imm
+        @imm = imm
+      end
+
+      def encode
+        self.SVC(@imm)
+      end
+
+      private
+
+      def SVC imm16
+        insn = 0b11010100_000_0000000000000000_000_01
+        insn |= ((imm16 & 0xffff) << 5)
+        insn
+      end
+    end
+  end
+end