aarch64 1.0.0
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- checksums.yaml +7 -0
- data/CODE_OF_CONDUCT.md +77 -0
- data/Gemfile +3 -0
- data/LICENSE +201 -0
- data/README.md +77 -0
- data/Rakefile +168 -0
- data/aarch64.gemspec +21 -0
- data/bin/build_instructions.rb +102 -0
- data/lib/aarch64/instructions/adc.rb +31 -0
- data/lib/aarch64/instructions/adcs.rb +30 -0
- data/lib/aarch64/instructions/add_addsub_ext.rb +35 -0
- data/lib/aarch64/instructions/add_addsub_imm.rb +32 -0
- data/lib/aarch64/instructions/add_addsub_shift.rb +35 -0
- data/lib/aarch64/instructions/addg.rb +30 -0
- data/lib/aarch64/instructions/adds_addsub_ext.rb +35 -0
- data/lib/aarch64/instructions/adds_addsub_imm.rb +33 -0
- data/lib/aarch64/instructions/adds_addsub_shift.rb +35 -0
- data/lib/aarch64/instructions/adr.rb +28 -0
- data/lib/aarch64/instructions/adrp.rb +28 -0
- data/lib/aarch64/instructions/and_log_imm.rb +35 -0
- data/lib/aarch64/instructions/and_log_shift.rb +35 -0
- data/lib/aarch64/instructions/ands_log_imm.rb +35 -0
- data/lib/aarch64/instructions/ands_log_shift.rb +35 -0
- data/lib/aarch64/instructions/asrv.rb +31 -0
- data/lib/aarch64/instructions/autda.rb +32 -0
- data/lib/aarch64/instructions/autdb.rb +32 -0
- data/lib/aarch64/instructions/autia.rb +35 -0
- data/lib/aarch64/instructions/autib.rb +35 -0
- data/lib/aarch64/instructions/axflag.rb +18 -0
- data/lib/aarch64/instructions/b_cond.rb +26 -0
- data/lib/aarch64/instructions/b_uncond.rb +24 -0
- data/lib/aarch64/instructions/bc_cond.rb +26 -0
- data/lib/aarch64/instructions/bfm.rb +34 -0
- data/lib/aarch64/instructions/bic_log_shift.rb +35 -0
- data/lib/aarch64/instructions/bics.rb +35 -0
- data/lib/aarch64/instructions/bl.rb +24 -0
- data/lib/aarch64/instructions/blr.rb +24 -0
- data/lib/aarch64/instructions/blra.rb +33 -0
- data/lib/aarch64/instructions/br.rb +24 -0
- data/lib/aarch64/instructions/bra.rb +33 -0
- data/lib/aarch64/instructions/brk.rb +24 -0
- data/lib/aarch64/instructions/bti.rb +24 -0
- data/lib/aarch64/instructions/cas.rb +41 -0
- data/lib/aarch64/instructions/casb.rb +35 -0
- data/lib/aarch64/instructions/cash.rb +35 -0
- data/lib/aarch64/instructions/casp.rb +41 -0
- data/lib/aarch64/instructions/cbnz.rb +29 -0
- data/lib/aarch64/instructions/cbz.rb +29 -0
- data/lib/aarch64/instructions/ccmn_imm.rb +33 -0
- data/lib/aarch64/instructions/ccmn_reg.rb +33 -0
- data/lib/aarch64/instructions/ccmp_imm.rb +33 -0
- data/lib/aarch64/instructions/ccmp_reg.rb +33 -0
- data/lib/aarch64/instructions/cfinv.rb +19 -0
- data/lib/aarch64/instructions/clrex.rb +24 -0
- data/lib/aarch64/instructions/cls_int.rb +29 -0
- data/lib/aarch64/instructions/clz_int.rb +29 -0
- data/lib/aarch64/instructions/crc32.rb +35 -0
- data/lib/aarch64/instructions/crc32c.rb +35 -0
- data/lib/aarch64/instructions/csdb.rb +19 -0
- data/lib/aarch64/instructions/csel.rb +33 -0
- data/lib/aarch64/instructions/csinc.rb +33 -0
- data/lib/aarch64/instructions/csinv.rb +33 -0
- data/lib/aarch64/instructions/csneg.rb +33 -0
- data/lib/aarch64/instructions/dcps.rb +26 -0
- data/lib/aarch64/instructions/dgh.rb +19 -0
- data/lib/aarch64/instructions/dmb.rb +24 -0
- data/lib/aarch64/instructions/drps.rb +19 -0
- data/lib/aarch64/instructions/dsb.rb +25 -0
- data/lib/aarch64/instructions/eon.rb +35 -0
- data/lib/aarch64/instructions/eor_log_imm.rb +35 -0
- data/lib/aarch64/instructions/eor_log_shift.rb +35 -0
- data/lib/aarch64/instructions/eret.rb +19 -0
- data/lib/aarch64/instructions/ereta.rb +25 -0
- data/lib/aarch64/instructions/esb.rb +19 -0
- data/lib/aarch64/instructions/extr.rb +34 -0
- data/lib/aarch64/instructions/gmi.rb +28 -0
- data/lib/aarch64/instructions/hint.rb +26 -0
- data/lib/aarch64/instructions/hlt.rb +24 -0
- data/lib/aarch64/instructions/hvc.rb +24 -0
- data/lib/aarch64/instructions/irg.rb +28 -0
- data/lib/aarch64/instructions/isb.rb +24 -0
- data/lib/aarch64/instructions/ld64b.rb +26 -0
- data/lib/aarch64/instructions/ldadd.rb +41 -0
- data/lib/aarch64/instructions/ldaddb.rb +35 -0
- data/lib/aarch64/instructions/ldaddh.rb +35 -0
- data/lib/aarch64/instructions/ldapr.rb +29 -0
- data/lib/aarch64/instructions/ldaprb.rb +26 -0
- data/lib/aarch64/instructions/ldaprh.rb +26 -0
- data/lib/aarch64/instructions/ldapur_gen.rb +33 -0
- data/lib/aarch64/instructions/ldar.rb +29 -0
- data/lib/aarch64/instructions/ldaxp.rb +31 -0
- data/lib/aarch64/instructions/ldaxr.rb +29 -0
- data/lib/aarch64/instructions/ldclr.rb +41 -0
- data/lib/aarch64/instructions/ldclrb.rb +37 -0
- data/lib/aarch64/instructions/ldeor.rb +41 -0
- data/lib/aarch64/instructions/ldg.rb +28 -0
- data/lib/aarch64/instructions/ldgm.rb +26 -0
- data/lib/aarch64/instructions/ldlar.rb +29 -0
- data/lib/aarch64/instructions/ldnp_gen.rb +33 -0
- data/lib/aarch64/instructions/ldp_gen.rb +39 -0
- data/lib/aarch64/instructions/ldpsw.rb +34 -0
- data/lib/aarch64/instructions/ldr_imm_gen.rb +35 -0
- data/lib/aarch64/instructions/ldr_imm_unsigned.rb +31 -0
- data/lib/aarch64/instructions/ldr_lit_gen.rb +29 -0
- data/lib/aarch64/instructions/ldr_reg_gen.rb +35 -0
- data/lib/aarch64/instructions/ldra.rb +37 -0
- data/lib/aarch64/instructions/ldrb_imm.rb +32 -0
- data/lib/aarch64/instructions/ldrb_reg.rb +33 -0
- data/lib/aarch64/instructions/ldrb_unsigned.rb +28 -0
- data/lib/aarch64/instructions/ldrh_imm.rb +32 -0
- data/lib/aarch64/instructions/ldrh_reg.rb +32 -0
- data/lib/aarch64/instructions/ldrh_unsigned.rb +28 -0
- data/lib/aarch64/instructions/ldrsb_imm.rb +37 -0
- data/lib/aarch64/instructions/ldrsb_reg.rb +37 -0
- data/lib/aarch64/instructions/ldrsb_unsigned.rb +35 -0
- data/lib/aarch64/instructions/ldrsh_imm.rb +37 -0
- data/lib/aarch64/instructions/ldrsh_reg.rb +35 -0
- data/lib/aarch64/instructions/ldrsh_unsigned.rb +31 -0
- data/lib/aarch64/instructions/ldrsw_imm.rb +32 -0
- data/lib/aarch64/instructions/ldrsw_lit.rb +26 -0
- data/lib/aarch64/instructions/ldrsw_reg.rb +32 -0
- data/lib/aarch64/instructions/ldrsw_unsigned.rb +30 -0
- data/lib/aarch64/instructions/ldset.rb +41 -0
- data/lib/aarch64/instructions/ldsetb.rb +35 -0
- data/lib/aarch64/instructions/ldseth.rb +35 -0
- data/lib/aarch64/instructions/ldsmax.rb +41 -0
- data/lib/aarch64/instructions/ldsmaxb.rb +35 -0
- data/lib/aarch64/instructions/ldsmaxh.rb +35 -0
- data/lib/aarch64/instructions/ldsmin.rb +41 -0
- data/lib/aarch64/instructions/ldsminb.rb +35 -0
- data/lib/aarch64/instructions/ldsminh.rb +35 -0
- data/lib/aarch64/instructions/ldtr.rb +31 -0
- data/lib/aarch64/instructions/ldtrb.rb +28 -0
- data/lib/aarch64/instructions/ldtrh.rb +28 -0
- data/lib/aarch64/instructions/ldtrsb.rb +31 -0
- data/lib/aarch64/instructions/ldtrsh.rb +31 -0
- data/lib/aarch64/instructions/ldtrsw.rb +28 -0
- data/lib/aarch64/instructions/ldumax.rb +41 -0
- data/lib/aarch64/instructions/ldumaxb.rb +35 -0
- data/lib/aarch64/instructions/ldumaxh.rb +35 -0
- data/lib/aarch64/instructions/ldumin.rb +41 -0
- data/lib/aarch64/instructions/lduminb.rb +35 -0
- data/lib/aarch64/instructions/lduminh.rb +35 -0
- data/lib/aarch64/instructions/ldur_gen.rb +31 -0
- data/lib/aarch64/instructions/ldursb.rb +31 -0
- data/lib/aarch64/instructions/ldursh.rb +31 -0
- data/lib/aarch64/instructions/ldursw.rb +28 -0
- data/lib/aarch64/instructions/ldxp.rb +31 -0
- data/lib/aarch64/instructions/ldxr.rb +29 -0
- data/lib/aarch64/instructions/lslv.rb +31 -0
- data/lib/aarch64/instructions/lsrv.rb +31 -0
- data/lib/aarch64/instructions/madd.rb +33 -0
- data/lib/aarch64/instructions/movk.rb +31 -0
- data/lib/aarch64/instructions/movn.rb +31 -0
- data/lib/aarch64/instructions/movz.rb +31 -0
- data/lib/aarch64/instructions/mrs.rb +34 -0
- data/lib/aarch64/instructions/msr_imm.rb +28 -0
- data/lib/aarch64/instructions/msr_reg.rb +34 -0
- data/lib/aarch64/instructions/msub.rb +33 -0
- data/lib/aarch64/instructions/nop.rb +19 -0
- data/lib/aarch64/instructions/orn_log_shift.rb +35 -0
- data/lib/aarch64/instructions/orr_log_imm.rb +35 -0
- data/lib/aarch64/instructions/orr_log_shift.rb +35 -0
- data/lib/aarch64/instructions/pacda.rb +29 -0
- data/lib/aarch64/instructions/pacdb.rb +29 -0
- data/lib/aarch64/instructions/pacga.rb +28 -0
- data/lib/aarch64/instructions/pacia.rb +32 -0
- data/lib/aarch64/instructions/pacia2.rb +28 -0
- data/lib/aarch64/instructions/pacib.rb +32 -0
- data/lib/aarch64/instructions/prfm_imm.rb +28 -0
- data/lib/aarch64/instructions/prfm_lit.rb +26 -0
- data/lib/aarch64/instructions/prfm_reg.rb +32 -0
- data/lib/aarch64/instructions/prfum.rb +28 -0
- data/lib/aarch64/instructions/psb.rb +19 -0
- data/lib/aarch64/instructions/rbit_int.rb +29 -0
- data/lib/aarch64/instructions/ret.rb +24 -0
- data/lib/aarch64/instructions/reta.rb +25 -0
- data/lib/aarch64/instructions/rev.rb +31 -0
- data/lib/aarch64/instructions/rmif.rb +28 -0
- data/lib/aarch64/instructions/rorv.rb +31 -0
- data/lib/aarch64/instructions/sb.rb +19 -0
- data/lib/aarch64/instructions/sbc.rb +31 -0
- data/lib/aarch64/instructions/sbcs.rb +31 -0
- data/lib/aarch64/instructions/sbfm.rb +34 -0
- data/lib/aarch64/instructions/sdiv.rb +31 -0
- data/lib/aarch64/instructions/setf.rb +27 -0
- data/lib/aarch64/instructions/setgp.rb +25 -0
- data/lib/aarch64/instructions/setgpn.rb +25 -0
- data/lib/aarch64/instructions/setgpt.rb +25 -0
- data/lib/aarch64/instructions/setgptn.rb +25 -0
- data/lib/aarch64/instructions/setp.rb +25 -0
- data/lib/aarch64/instructions/setpn.rb +25 -0
- data/lib/aarch64/instructions/setpt.rb +25 -0
- data/lib/aarch64/instructions/setptn.rb +25 -0
- data/lib/aarch64/instructions/sev.rb +18 -0
- data/lib/aarch64/instructions/sevl.rb +18 -0
- data/lib/aarch64/instructions/smaddl.rb +30 -0
- data/lib/aarch64/instructions/smc.rb +24 -0
- data/lib/aarch64/instructions/smsubl.rb +30 -0
- data/lib/aarch64/instructions/smulh.rb +28 -0
- data/lib/aarch64/instructions/st2g.rb +32 -0
- data/lib/aarch64/instructions/st64b.rb +26 -0
- data/lib/aarch64/instructions/st64bv.rb +28 -0
- data/lib/aarch64/instructions/st64bv0.rb +28 -0
- data/lib/aarch64/instructions/stg.rb +32 -0
- data/lib/aarch64/instructions/stgm.rb +26 -0
- data/lib/aarch64/instructions/stgp.rb +34 -0
- data/lib/aarch64/instructions/stllr.rb +29 -0
- data/lib/aarch64/instructions/stllrb.rb +26 -0
- data/lib/aarch64/instructions/stllrh.rb +26 -0
- data/lib/aarch64/instructions/stlr.rb +29 -0
- data/lib/aarch64/instructions/stlrb.rb +26 -0
- data/lib/aarch64/instructions/stlrh.rb +26 -0
- data/lib/aarch64/instructions/stlur_gen.rb +31 -0
- data/lib/aarch64/instructions/stlxp.rb +33 -0
- data/lib/aarch64/instructions/stlxr.rb +31 -0
- data/lib/aarch64/instructions/stlxrb.rb +28 -0
- data/lib/aarch64/instructions/stlxrh.rb +28 -0
- data/lib/aarch64/instructions/stnp_gen.rb +33 -0
- data/lib/aarch64/instructions/stp_gen.rb +39 -0
- data/lib/aarch64/instructions/str_imm_gen.rb +37 -0
- data/lib/aarch64/instructions/str_imm_unsigned.rb +31 -0
- data/lib/aarch64/instructions/str_reg_gen.rb +35 -0
- data/lib/aarch64/instructions/strb_imm.rb +32 -0
- data/lib/aarch64/instructions/strb_imm_unsigned.rb +28 -0
- data/lib/aarch64/instructions/strb_reg.rb +33 -0
- data/lib/aarch64/instructions/strh_imm.rb +32 -0
- data/lib/aarch64/instructions/strh_imm_unsigned.rb +28 -0
- data/lib/aarch64/instructions/strh_reg.rb +32 -0
- data/lib/aarch64/instructions/sttr.rb +31 -0
- data/lib/aarch64/instructions/stur_gen.rb +31 -0
- data/lib/aarch64/instructions/stxp.rb +33 -0
- data/lib/aarch64/instructions/stxr.rb +31 -0
- data/lib/aarch64/instructions/stxrb.rb +28 -0
- data/lib/aarch64/instructions/stxrh.rb +28 -0
- data/lib/aarch64/instructions/stz2g.rb +32 -0
- data/lib/aarch64/instructions/stzg.rb +32 -0
- data/lib/aarch64/instructions/stzgm.rb +26 -0
- data/lib/aarch64/instructions/sub_addsub_ext.rb +35 -0
- data/lib/aarch64/instructions/sub_addsub_imm.rb +33 -0
- data/lib/aarch64/instructions/sub_addsub_shift.rb +35 -0
- data/lib/aarch64/instructions/subg.rb +30 -0
- data/lib/aarch64/instructions/subp.rb +28 -0
- data/lib/aarch64/instructions/subps.rb +28 -0
- data/lib/aarch64/instructions/subs_addsub_ext.rb +35 -0
- data/lib/aarch64/instructions/subs_addsub_imm.rb +33 -0
- data/lib/aarch64/instructions/subs_addsub_shift.rb +35 -0
- data/lib/aarch64/instructions/svc.rb +24 -0
- data/lib/aarch64/instructions/swp.rb +41 -0
- data/lib/aarch64/instructions/swpb.rb +35 -0
- data/lib/aarch64/instructions/swph.rb +35 -0
- data/lib/aarch64/instructions/sys.rb +32 -0
- data/lib/aarch64/instructions/sysl.rb +32 -0
- data/lib/aarch64/instructions/tbnz.rb +30 -0
- data/lib/aarch64/instructions/tbz.rb +30 -0
- data/lib/aarch64/instructions/tsb.rb +18 -0
- data/lib/aarch64/instructions/ubfm.rb +34 -0
- data/lib/aarch64/instructions/udf_perm_undef.rb +24 -0
- data/lib/aarch64/instructions/udiv.rb +31 -0
- data/lib/aarch64/instructions/umaddl.rb +30 -0
- data/lib/aarch64/instructions/umsubl.rb +30 -0
- data/lib/aarch64/instructions/umulh.rb +28 -0
- data/lib/aarch64/instructions/wfe.rb +19 -0
- data/lib/aarch64/instructions/wfet.rb +24 -0
- data/lib/aarch64/instructions/wfi.rb +19 -0
- data/lib/aarch64/instructions/wfit.rb +24 -0
- data/lib/aarch64/instructions/xaflag.rb +19 -0
- data/lib/aarch64/instructions/xpac.rb +28 -0
- data/lib/aarch64/instructions/xpaclri.rb +18 -0
- data/lib/aarch64/instructions/yield.rb +19 -0
- data/lib/aarch64/instructions.rb +266 -0
- data/lib/aarch64/system_registers/mrs_msr_64.rb +395 -0
- data/lib/aarch64/utils.rb +325 -0
- data/lib/aarch64/version.rb +3 -0
- data/lib/aarch64.rb +2857 -0
- data/test/all_adds_test.rb +129 -0
- data/test/base_instructions_test.rb +9263 -0
- data/test/dsl_test.rb +11 -0
- data/test/helper.rb +51 -0
- data/test/not_supported_yet_test.rb +55 -0
- metadata +382 -0
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module AArch64
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module Instructions
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# ADC -- A64
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# Add with Carry
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# ADC <Wd>, <Wn>, <Wm>
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# ADC <Xd>, <Xn>, <Xm>
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class ADC
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def initialize rd, rn, rm, sf
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@rd = rd
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@rn = rn
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@rm = rm
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@sf = sf
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end
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def encode
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self.ADC(@sf, @rm.to_i, @rn.to_i, @rd.to_i)
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end
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private
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def ADC sf, rm, rn, rd
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insn = 0b0_0_0_11010000_00000_000000_00000_00000
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insn |= ((sf & 0x1) << 31)
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insn |= ((rm & 0x1f) << 16)
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insn |= ((rn & 0x1f) << 5)
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insn |= (rd & 0x1f)
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insn
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end
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end
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end
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end
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module AArch64
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module Instructions
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# ADCS -- A64
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# Add with Carry, setting flags
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# ADCS <Wd>, <Wn>, <Wm>
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class ADCS
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def initialize rd, rn, rm, sf
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@rd = rd
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@rn = rn
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@rm = rm
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@sf = sf
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end
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def encode
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self.ADCS(@sf, @rm.to_i, @rn.to_i, @rd.to_i)
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end
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private
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def ADCS sf, rm, rn, rd
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insn = 0b0_0_1_11010000_00000_000000_00000_00000
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insn |= ((sf & 0x1) << 31)
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insn |= ((rm & 0x1f) << 16)
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insn |= ((rn & 0x1f) << 5)
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insn |= (rd & 0x1f)
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insn
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end
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end
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end
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end
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module AArch64
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module Instructions
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# ADD (extended register) -- A64
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# Add (extended register)
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# ADD <Wd|WSP>, <Wn|WSP>, <Wm>{, <extend> {#<amount>}}
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# ADD <Xd|SP>, <Xn|SP>, <R><m>{, <extend> {#<amount>}}
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class ADD_addsub_ext
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def initialize rd, rn, rm, extend, amount, sf
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@rd = rd
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@rn = rn
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@rm = rm
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@extend = extend
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@amount = amount
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@sf = sf
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end
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def encode
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self.ADD_addsub_ext(@sf, @rm.to_i, @extend, @amount, @rn.to_i, @rd.to_i)
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end
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private
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def ADD_addsub_ext sf, rm, option, imm3, rn, rd
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insn = 0b0_0_0_01011_00_1_00000_000_000_00000_00000
|
25
|
+
insn |= ((sf & 0x1) << 31)
|
26
|
+
insn |= ((rm & 0x1f) << 16)
|
27
|
+
insn |= ((option & 0x7) << 13)
|
28
|
+
insn |= ((imm3 & 0x7) << 10)
|
29
|
+
insn |= ((rn & 0x1f) << 5)
|
30
|
+
insn |= (rd & 0x1f)
|
31
|
+
insn
|
32
|
+
end
|
33
|
+
end
|
34
|
+
end
|
35
|
+
end
|
@@ -0,0 +1,32 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# ADD (immediate) -- A64
|
4
|
+
# Add (immediate)
|
5
|
+
# ADD <Wd|WSP>, <Wn|WSP>, #<imm>{, <shift>}
|
6
|
+
class ADD_addsub_imm
|
7
|
+
def initialize rd, rn, imm12, sh, sf
|
8
|
+
@rd = rd
|
9
|
+
@rn = rn
|
10
|
+
@imm12 = imm12
|
11
|
+
@sh = sh
|
12
|
+
@sf = sf
|
13
|
+
end
|
14
|
+
|
15
|
+
def encode
|
16
|
+
ADD_addsub_imm(@sf, @sh, @imm12, @rn.to_i, @rd.to_i)
|
17
|
+
end
|
18
|
+
|
19
|
+
private
|
20
|
+
|
21
|
+
def ADD_addsub_imm sf, sh, imm12, rn, rd
|
22
|
+
insn = 0b0_0_0_100010_0_000000000000_00000_00000
|
23
|
+
insn |= ((sf & 0x1) << 31)
|
24
|
+
insn |= ((sh & 0x1) << 22)
|
25
|
+
insn |= ((imm12 & 0xfff) << 10)
|
26
|
+
insn |= ((rn & 0x1f) << 5)
|
27
|
+
insn |= (rd & 0x1f)
|
28
|
+
insn
|
29
|
+
end
|
30
|
+
end
|
31
|
+
end
|
32
|
+
end
|
@@ -0,0 +1,35 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# ADD (shifted register) -- A64
|
4
|
+
# Add (shifted register)
|
5
|
+
# ADD <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
|
6
|
+
# ADD <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
|
7
|
+
class ADD_addsub_shift
|
8
|
+
def initialize xd, xn, xm, shift, amount, sf
|
9
|
+
@xd = xd
|
10
|
+
@xn = xn
|
11
|
+
@xm = xm
|
12
|
+
@shift = shift
|
13
|
+
@amount = amount
|
14
|
+
@sf = sf
|
15
|
+
end
|
16
|
+
|
17
|
+
def encode
|
18
|
+
ADD_addsub_shift(@sf, @shift, @xm.to_i, @amount, @xn.to_i, @xd.to_i)
|
19
|
+
end
|
20
|
+
|
21
|
+
private
|
22
|
+
|
23
|
+
def ADD_addsub_shift sf, shift, rm, imm6, rn, rd
|
24
|
+
insn = 0b0_0_0_01011_00_0_00000_000000_00000_00000
|
25
|
+
insn |= ((sf & 0x1) << 31)
|
26
|
+
insn |= ((shift & 0x3) << 22)
|
27
|
+
insn |= ((rm & 0x1f) << 16)
|
28
|
+
insn |= ((imm6 & 0x3f) << 10)
|
29
|
+
insn |= ((rn & 0x1f) << 5)
|
30
|
+
insn |= (rd & 0x1f)
|
31
|
+
insn
|
32
|
+
end
|
33
|
+
end
|
34
|
+
end
|
35
|
+
end
|
@@ -0,0 +1,30 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# ADDG -- A64
|
4
|
+
# Add with Tag
|
5
|
+
# ADDG <Xd|SP>, <Xn|SP>, #<uimm6>, #<uimm4>
|
6
|
+
class ADDG
|
7
|
+
def initialize xd, xn, imm6, imm4
|
8
|
+
@xd = xd
|
9
|
+
@xn = xn
|
10
|
+
@imm6 = imm6
|
11
|
+
@imm4 = imm4
|
12
|
+
end
|
13
|
+
|
14
|
+
def encode
|
15
|
+
ADDG(@imm6, @imm4, @xn.to_i, @xd.to_i)
|
16
|
+
end
|
17
|
+
|
18
|
+
private
|
19
|
+
|
20
|
+
def ADDG uimm6, uimm4, xn, xd
|
21
|
+
insn = 0b1_0_0_100011_0_000000_00_0000_00000_00000
|
22
|
+
insn |= ((uimm6 & 0x3f) << 16)
|
23
|
+
insn |= ((uimm4 & 0xf) << 10)
|
24
|
+
insn |= ((xn & 0x1f) << 5)
|
25
|
+
insn |= (xd & 0x1f)
|
26
|
+
insn
|
27
|
+
end
|
28
|
+
end
|
29
|
+
end
|
30
|
+
end
|
@@ -0,0 +1,35 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# ADDS (extended register) -- A64
|
4
|
+
# Add (extended register), setting flags
|
5
|
+
# ADDS <Wd>, <Wn|WSP>, <Wm>{, <extend> {#<amount>}}
|
6
|
+
# ADDS <Xd>, <Xn|SP>, <R><m>{, <extend> {#<amount>}}
|
7
|
+
class ADDS_addsub_ext
|
8
|
+
def initialize d, n, m, extend, amount, sf
|
9
|
+
@d = d
|
10
|
+
@n = n
|
11
|
+
@m = m
|
12
|
+
@extend = extend
|
13
|
+
@amount = amount
|
14
|
+
@sf = sf
|
15
|
+
end
|
16
|
+
|
17
|
+
def encode
|
18
|
+
ADDS_addsub_ext(@sf, @m.to_i, @extend, @amount, @n.to_i, @d.to_i)
|
19
|
+
end
|
20
|
+
|
21
|
+
private
|
22
|
+
|
23
|
+
def ADDS_addsub_ext sf, rm, option, imm3, rn, rd
|
24
|
+
insn = 0b0_0_1_01011_00_1_00000_000_000_00000_00000
|
25
|
+
insn |= ((sf & 0x1) << 31)
|
26
|
+
insn |= ((rm & 0x1f) << 16)
|
27
|
+
insn |= ((option & 0x7) << 13)
|
28
|
+
insn |= ((imm3 & 0x7) << 10)
|
29
|
+
insn |= ((rn & 0x1f) << 5)
|
30
|
+
insn |= (rd & 0x1f)
|
31
|
+
insn
|
32
|
+
end
|
33
|
+
end
|
34
|
+
end
|
35
|
+
end
|
@@ -0,0 +1,33 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# ADDS (immediate) -- A64
|
4
|
+
# Add (immediate), setting flags
|
5
|
+
# ADDS <Wd>, <Wn|WSP>, #<imm>{, <shift>}
|
6
|
+
# ADDS <Xd>, <Xn|SP>, #<imm>{, <shift>}
|
7
|
+
class ADDS_addsub_imm
|
8
|
+
def initialize d, n, imm, shift, sf
|
9
|
+
@d = d
|
10
|
+
@n = n
|
11
|
+
@imm = imm
|
12
|
+
@shift = shift
|
13
|
+
@sf = sf
|
14
|
+
end
|
15
|
+
|
16
|
+
def encode
|
17
|
+
ADDS_addsub_imm(@sf, @shift, @imm, @n.to_i, @d.to_i)
|
18
|
+
end
|
19
|
+
|
20
|
+
private
|
21
|
+
|
22
|
+
def ADDS_addsub_imm sf, sh, imm12, rn, rd
|
23
|
+
insn = 0b0_0_1_100010_0_000000000000_00000_00000
|
24
|
+
insn |= ((sf & 0x1) << 31)
|
25
|
+
insn |= ((sh & 0x1) << 22)
|
26
|
+
insn |= ((imm12 & 0xfff) << 10)
|
27
|
+
insn |= ((rn & 0x1f) << 5)
|
28
|
+
insn |= (rd & 0x1f)
|
29
|
+
insn
|
30
|
+
end
|
31
|
+
end
|
32
|
+
end
|
33
|
+
end
|
@@ -0,0 +1,35 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# ADDS (shifted register) -- A64
|
4
|
+
# Add (shifted register), setting flags
|
5
|
+
# ADDS <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
|
6
|
+
# ADDS <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
|
7
|
+
class ADDS_addsub_shift
|
8
|
+
def initialize xd, xn, xm, shift, amount, sf
|
9
|
+
@xd = xd
|
10
|
+
@xn = xn
|
11
|
+
@xm = xm
|
12
|
+
@shift = shift
|
13
|
+
@amount = amount
|
14
|
+
@sf = sf
|
15
|
+
end
|
16
|
+
|
17
|
+
def encode
|
18
|
+
ADDS_addsub_shift(@sf, @shift, @xm.to_i, @amount, @xn.to_i, @xd.to_i)
|
19
|
+
end
|
20
|
+
|
21
|
+
private
|
22
|
+
|
23
|
+
def ADDS_addsub_shift sf, shift, rm, imm6, rn, rd
|
24
|
+
insn = 0b0_0_1_01011_00_0_00000_000000_00000_00000
|
25
|
+
insn |= ((sf & 0x1) << 31)
|
26
|
+
insn |= ((shift & 0x3) << 22)
|
27
|
+
insn |= ((rm & 0x1f) << 16)
|
28
|
+
insn |= ((imm6 & 0x3f) << 10)
|
29
|
+
insn |= ((rn & 0x1f) << 5)
|
30
|
+
insn |= (rd & 0x1f)
|
31
|
+
insn
|
32
|
+
end
|
33
|
+
end
|
34
|
+
end
|
35
|
+
end
|
@@ -0,0 +1,28 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# ADR -- A64
|
4
|
+
# Form PC-relative address
|
5
|
+
# ADR <Xd>, <label>
|
6
|
+
class ADR
|
7
|
+
def initialize xd, label
|
8
|
+
@xd = xd
|
9
|
+
@label = label
|
10
|
+
end
|
11
|
+
|
12
|
+
def encode
|
13
|
+
label = @label.to_i
|
14
|
+
ADR(label, label >> 2, @xd.to_i)
|
15
|
+
end
|
16
|
+
|
17
|
+
private
|
18
|
+
|
19
|
+
def ADR immlo, immhi, rd
|
20
|
+
insn = 0b0_00_10000_0000000000000000000_00000
|
21
|
+
insn |= ((immlo & 0x3) << 29)
|
22
|
+
insn |= ((immhi & 0x7ffff) << 5)
|
23
|
+
insn |= (rd & 0x1f)
|
24
|
+
insn
|
25
|
+
end
|
26
|
+
end
|
27
|
+
end
|
28
|
+
end
|
@@ -0,0 +1,28 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# ADRP -- A64
|
4
|
+
# Form PC-relative address to 4KB page
|
5
|
+
# ADRP <Xd>, <label>
|
6
|
+
class ADRP
|
7
|
+
def initialize xd, label
|
8
|
+
@xd = xd
|
9
|
+
@label = label
|
10
|
+
end
|
11
|
+
|
12
|
+
def encode
|
13
|
+
label = @label.to_i / 1000
|
14
|
+
ADRP(label, label >> 2, @xd.to_i)
|
15
|
+
end
|
16
|
+
|
17
|
+
private
|
18
|
+
|
19
|
+
def ADRP immlo, immhi, rd
|
20
|
+
insn = 0b1_00_10000_0000000000000000000_00000
|
21
|
+
insn |= ((immlo & 0x3) << 29)
|
22
|
+
insn |= ((immhi & 0x7ffff) << 5)
|
23
|
+
insn |= (rd & 0x1f)
|
24
|
+
insn
|
25
|
+
end
|
26
|
+
end
|
27
|
+
end
|
28
|
+
end
|
@@ -0,0 +1,35 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# AND (immediate) -- A64
|
4
|
+
# Bitwise AND (immediate)
|
5
|
+
# AND <Wd|WSP>, <Wn>, #<imm>
|
6
|
+
# AND <Xd|SP>, <Xn>, #<imm>
|
7
|
+
class AND_log_imm
|
8
|
+
def initialize rd, rn, immr, imms, n, sf
|
9
|
+
@rd = rd
|
10
|
+
@rn = rn
|
11
|
+
@immr = immr
|
12
|
+
@imms = imms
|
13
|
+
@n = n
|
14
|
+
@sf = sf
|
15
|
+
end
|
16
|
+
|
17
|
+
def encode
|
18
|
+
self.AND_log_imm(@sf, @n, @immr, @imms, @rn.to_i, @rd.to_i)
|
19
|
+
end
|
20
|
+
|
21
|
+
private
|
22
|
+
|
23
|
+
def AND_log_imm sf, n, immr, imms, rn, rd
|
24
|
+
insn = 0b0_00_100100_0_000000_000000_00000_00000
|
25
|
+
insn |= ((sf & 0x1) << 31)
|
26
|
+
insn |= ((n & 0x1) << 22)
|
27
|
+
insn |= ((immr & 0x3f) << 16)
|
28
|
+
insn |= ((imms & 0x3f) << 10)
|
29
|
+
insn |= ((rn & 0x1f) << 5)
|
30
|
+
insn |= (rd & 0x1f)
|
31
|
+
insn
|
32
|
+
end
|
33
|
+
end
|
34
|
+
end
|
35
|
+
end
|
@@ -0,0 +1,35 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# AND (shifted register) -- A64
|
4
|
+
# Bitwise AND (shifted register)
|
5
|
+
# AND <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
|
6
|
+
# AND <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
|
7
|
+
class AND_log_shift
|
8
|
+
def initialize xd, xn, xm, shift, amount, sf
|
9
|
+
@xd = xd
|
10
|
+
@xn = xn
|
11
|
+
@xm = xm
|
12
|
+
@shift = shift
|
13
|
+
@amount = amount
|
14
|
+
@sf = sf
|
15
|
+
end
|
16
|
+
|
17
|
+
def encode
|
18
|
+
AND_log_shift(@sf, @shift, @xm.to_i, @amount, @xn.to_i, @xd.to_i)
|
19
|
+
end
|
20
|
+
|
21
|
+
private
|
22
|
+
|
23
|
+
def AND_log_shift sf, shift, rm, imm6, rn, rd
|
24
|
+
insn = 0b0_00_01010_00_0_00000_000000_00000_00000
|
25
|
+
insn |= ((sf & 0x1) << 31)
|
26
|
+
insn |= ((shift & 0x3) << 22)
|
27
|
+
insn |= ((rm & 0x1f) << 16)
|
28
|
+
insn |= ((imm6 & 0x3f) << 10)
|
29
|
+
insn |= ((rn & 0x1f) << 5)
|
30
|
+
insn |= (rd & 0x1f)
|
31
|
+
insn
|
32
|
+
end
|
33
|
+
end
|
34
|
+
end
|
35
|
+
end
|
@@ -0,0 +1,35 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# ANDS (immediate) -- A64
|
4
|
+
# Bitwise AND (immediate), setting flags
|
5
|
+
# ANDS <Wd>, <Wn>, #<imm>
|
6
|
+
# ANDS <Xd>, <Xn>, #<imm>
|
7
|
+
class ANDS_log_imm
|
8
|
+
def initialize rd, rn, immr, imms, n, sf
|
9
|
+
@rd = rd
|
10
|
+
@rn = rn
|
11
|
+
@immr = immr
|
12
|
+
@imms = imms
|
13
|
+
@n = n
|
14
|
+
@sf = sf
|
15
|
+
end
|
16
|
+
|
17
|
+
def encode
|
18
|
+
self.ANDS_log_imm(@sf, @n, @immr, @imms, @rn.to_i, @rd.to_i)
|
19
|
+
end
|
20
|
+
|
21
|
+
private
|
22
|
+
|
23
|
+
def ANDS_log_imm sf, n, immr, imms, rn, rd
|
24
|
+
insn = 0b0_11_100100_0_000000_000000_00000_00000
|
25
|
+
insn |= ((sf & 0x1) << 31)
|
26
|
+
insn |= ((n & 0x1) << 22)
|
27
|
+
insn |= ((immr & 0x3f) << 16)
|
28
|
+
insn |= ((imms & 0x3f) << 10)
|
29
|
+
insn |= ((rn & 0x1f) << 5)
|
30
|
+
insn |= (rd & 0x1f)
|
31
|
+
insn
|
32
|
+
end
|
33
|
+
end
|
34
|
+
end
|
35
|
+
end
|
@@ -0,0 +1,35 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# ANDS (shifted register) -- A64
|
4
|
+
# Bitwise AND (shifted register), setting flags
|
5
|
+
# ANDS <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
|
6
|
+
# ANDS <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
|
7
|
+
class ANDS_log_shift
|
8
|
+
def initialize xd, xn, xm, shift, amount, sf
|
9
|
+
@xd = xd
|
10
|
+
@xn = xn
|
11
|
+
@xm = xm
|
12
|
+
@shift = shift
|
13
|
+
@amount = amount
|
14
|
+
@sf = sf
|
15
|
+
end
|
16
|
+
|
17
|
+
def encode
|
18
|
+
ANDS_log_shift(@sf, @shift, @xm.to_i, @amount, @xn.to_i, @xd.to_i)
|
19
|
+
end
|
20
|
+
|
21
|
+
private
|
22
|
+
|
23
|
+
def ANDS_log_shift sf, shift, rm, imm6, rn, rd
|
24
|
+
insn = 0b0_11_01010_00_0_00000_000000_00000_00000
|
25
|
+
insn |= ((sf & 0x1) << 31)
|
26
|
+
insn |= ((shift & 0x3) << 22)
|
27
|
+
insn |= ((rm & 0x1f) << 16)
|
28
|
+
insn |= ((imm6 & 0x3f) << 10)
|
29
|
+
insn |= ((rn & 0x1f) << 5)
|
30
|
+
insn |= (rd & 0x1f)
|
31
|
+
insn
|
32
|
+
end
|
33
|
+
end
|
34
|
+
end
|
35
|
+
end
|
@@ -0,0 +1,31 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# ASRV -- A64
|
4
|
+
# Arithmetic Shift Right Variable
|
5
|
+
# ASRV <Wd>, <Wn>, <Wm>
|
6
|
+
# ASRV <Xd>, <Xn>, <Xm>
|
7
|
+
class ASRV
|
8
|
+
def initialize rd, rn, rm, sf
|
9
|
+
@rd = rd
|
10
|
+
@rn = rn
|
11
|
+
@rm = rm
|
12
|
+
@sf = sf
|
13
|
+
end
|
14
|
+
|
15
|
+
def encode
|
16
|
+
self.ASRV(@sf, @rm.to_i, @rn.to_i, @rd.to_i)
|
17
|
+
end
|
18
|
+
|
19
|
+
private
|
20
|
+
|
21
|
+
def ASRV sf, rm, rn, rd
|
22
|
+
insn = 0b0_0_0_11010110_00000_0010_10_00000_00000
|
23
|
+
insn |= ((sf & 0x1) << 31)
|
24
|
+
insn |= ((rm & 0x1f) << 16)
|
25
|
+
insn |= ((rn & 0x1f) << 5)
|
26
|
+
insn |= (rd & 0x1f)
|
27
|
+
insn
|
28
|
+
end
|
29
|
+
end
|
30
|
+
end
|
31
|
+
end
|
@@ -0,0 +1,32 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# AUTDA, AUTDZA -- A64
|
4
|
+
# Authenticate Data address, using key A
|
5
|
+
# AUTDA <Xd>, <Xn|SP>
|
6
|
+
# AUTDZA <Xd>
|
7
|
+
class AUTDA
|
8
|
+
def initialize d, n
|
9
|
+
@d = d
|
10
|
+
@n = n
|
11
|
+
end
|
12
|
+
|
13
|
+
def encode
|
14
|
+
if @n.integer?
|
15
|
+
AUTDA(1, @n.to_i, @d.to_i)
|
16
|
+
else
|
17
|
+
AUTDA(0, @n.to_i, @d.to_i)
|
18
|
+
end
|
19
|
+
end
|
20
|
+
|
21
|
+
private
|
22
|
+
|
23
|
+
def AUTDA z, rn, rd
|
24
|
+
insn = 0b1_1_0_11010110_00001_0_0_0_110_00000_00000
|
25
|
+
insn |= ((z & 0x1) << 13)
|
26
|
+
insn |= ((rn & 0x1f) << 5)
|
27
|
+
insn |= (rd & 0x1f)
|
28
|
+
insn
|
29
|
+
end
|
30
|
+
end
|
31
|
+
end
|
32
|
+
end
|
@@ -0,0 +1,32 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# AUTDB, AUTDZB -- A64
|
4
|
+
# Authenticate Data address, using key B
|
5
|
+
# AUTDB <Xd>, <Xn|SP>
|
6
|
+
# AUTDZB <Xd>
|
7
|
+
class AUTDB
|
8
|
+
def initialize d, n
|
9
|
+
@d = d
|
10
|
+
@n = n
|
11
|
+
end
|
12
|
+
|
13
|
+
def encode
|
14
|
+
if @n.integer?
|
15
|
+
AUTDB(1, @n.to_i, @d.to_i)
|
16
|
+
else
|
17
|
+
AUTDB(0, @n.to_i, @d.to_i)
|
18
|
+
end
|
19
|
+
end
|
20
|
+
|
21
|
+
private
|
22
|
+
|
23
|
+
def AUTDB z, rn, rd
|
24
|
+
insn = 0b1_1_0_11010110_00001_0_0_0_111_00000_00000
|
25
|
+
insn |= ((z & 0x1) << 13)
|
26
|
+
insn |= ((rn & 0x1f) << 5)
|
27
|
+
insn |= (rd & 0x1f)
|
28
|
+
insn
|
29
|
+
end
|
30
|
+
end
|
31
|
+
end
|
32
|
+
end
|
@@ -0,0 +1,35 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZA -- A64
|
4
|
+
# Authenticate Instruction address, using key A
|
5
|
+
# AUTIA <Xd>, <Xn|SP>
|
6
|
+
# AUTIZA <Xd>
|
7
|
+
# AUTIA1716
|
8
|
+
# AUTIASP
|
9
|
+
# AUTIAZ
|
10
|
+
class AUTIA
|
11
|
+
def initialize d, n
|
12
|
+
@d = d
|
13
|
+
@n = n
|
14
|
+
end
|
15
|
+
|
16
|
+
def encode
|
17
|
+
if @n.integer?
|
18
|
+
AUTIA(1, @n.to_i, @d.to_i)
|
19
|
+
else
|
20
|
+
AUTIA(0, @n.to_i, @d.to_i)
|
21
|
+
end
|
22
|
+
end
|
23
|
+
|
24
|
+
private
|
25
|
+
|
26
|
+
def AUTIA z, rn, rd
|
27
|
+
insn = 0b1_1_0_11010110_00001_0_0_0_100_00000_00000
|
28
|
+
insn |= ((z & 0x1) << 13)
|
29
|
+
insn |= ((rn & 0x1f) << 5)
|
30
|
+
insn |= (rd & 0x1f)
|
31
|
+
insn
|
32
|
+
end
|
33
|
+
end
|
34
|
+
end
|
35
|
+
end
|
@@ -0,0 +1,35 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZB -- A64
|
4
|
+
# Authenticate Instruction address, using key B
|
5
|
+
# AUTIB <Xd>, <Xn|SP>
|
6
|
+
# AUTIZB <Xd>
|
7
|
+
# AUTIB1716
|
8
|
+
# AUTIBSP
|
9
|
+
# AUTIBZ
|
10
|
+
class AUTIB
|
11
|
+
def initialize d, n
|
12
|
+
@d = d
|
13
|
+
@n = n
|
14
|
+
end
|
15
|
+
|
16
|
+
def encode
|
17
|
+
if @n.integer?
|
18
|
+
AUTIB(1, @n.to_i, @d.to_i)
|
19
|
+
else
|
20
|
+
AUTIB(0, @n.to_i, @d.to_i)
|
21
|
+
end
|
22
|
+
end
|
23
|
+
|
24
|
+
private
|
25
|
+
|
26
|
+
def AUTIB z, rn, rd
|
27
|
+
insn = 0b1_1_0_11010110_00001_0_0_0_101_00000_00000
|
28
|
+
insn |= ((z & 0x1) << 13)
|
29
|
+
insn |= ((rn & 0x1f) << 5)
|
30
|
+
insn |= (rd & 0x1f)
|
31
|
+
insn
|
32
|
+
end
|
33
|
+
end
|
34
|
+
end
|
35
|
+
end
|
@@ -0,0 +1,18 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# AXFLAG -- A64
|
4
|
+
# Convert floating-point condition flags from Arm to external format
|
5
|
+
# AXFLAG
|
6
|
+
class AXFLAG
|
7
|
+
def encode
|
8
|
+
self.AXFLAG
|
9
|
+
end
|
10
|
+
|
11
|
+
private
|
12
|
+
|
13
|
+
def AXFLAG
|
14
|
+
0b1101010100_0_00_000_0100_0000_010_11111
|
15
|
+
end
|
16
|
+
end
|
17
|
+
end
|
18
|
+
end
|