aarch64 1.0.0

data/lib/aarch64/instructions/adc.rb

@@ -0,0 +1,31 @@
+module AArch64
+  module Instructions
+    # ADC -- A64
+    # Add with Carry
+    # ADC  <Wd>, <Wn>, <Wm>
+    # ADC  <Xd>, <Xn>, <Xm>
+    class ADC
+      def initialize rd, rn, rm, sf
+        @rd = rd
+        @rn = rn
+        @rm = rm
+        @sf = sf
+      end
+
+      def encode
+        self.ADC(@sf, @rm.to_i, @rn.to_i, @rd.to_i)
+      end
+
+      private
+
+      def ADC sf, rm, rn, rd
+        insn = 0b0_0_0_11010000_00000_000000_00000_00000
+        insn |= ((sf & 0x1) << 31)
+        insn |= ((rm & 0x1f) << 16)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/adcs.rb

@@ -0,0 +1,30 @@
+module AArch64
+  module Instructions
+    # ADCS -- A64
+    # Add with Carry, setting flags
+    # ADCS  <Wd>, <Wn>, <Wm>
+    class ADCS
+      def initialize rd, rn, rm, sf
+        @rd = rd
+        @rn = rn
+        @rm = rm
+        @sf = sf
+      end
+
+      def encode
+        self.ADCS(@sf, @rm.to_i, @rn.to_i, @rd.to_i)
+      end
+
+      private
+
+      def ADCS sf, rm, rn, rd
+        insn = 0b0_0_1_11010000_00000_000000_00000_00000
+        insn |= ((sf & 0x1) << 31)
+        insn |= ((rm & 0x1f) << 16)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/add_addsub_ext.rb

@@ -0,0 +1,35 @@
+module AArch64
+  module Instructions
+    # ADD (extended register) -- A64
+    # Add (extended register)
+    # ADD  <Wd|WSP>, <Wn|WSP>, <Wm>{, <extend> {#<amount>}}
+    # ADD  <Xd|SP>, <Xn|SP>, <R><m>{, <extend> {#<amount>}}
+    class ADD_addsub_ext
+      def initialize rd, rn, rm, extend, amount, sf
+        @rd     = rd
+        @rn     = rn
+        @rm     = rm
+        @extend = extend
+        @amount = amount
+        @sf     = sf
+      end
+
+      def encode
+        self.ADD_addsub_ext(@sf, @rm.to_i, @extend, @amount, @rn.to_i, @rd.to_i)
+      end
+
+      private
+
+      def ADD_addsub_ext sf, rm, option, imm3, rn, rd
+        insn = 0b0_0_0_01011_00_1_00000_000_000_00000_00000
+        insn |= ((sf & 0x1) << 31)
+        insn |= ((rm & 0x1f) << 16)
+        insn |= ((option & 0x7) << 13)
+        insn |= ((imm3 & 0x7) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/add_addsub_imm.rb

@@ -0,0 +1,32 @@
+module AArch64
+  module Instructions
+    # ADD (immediate) -- A64
+    # Add (immediate)
+    # ADD  <Wd|WSP>, <Wn|WSP>, #<imm>{, <shift>}
+    class ADD_addsub_imm
+      def initialize rd, rn, imm12, sh, sf
+        @rd    = rd
+        @rn    = rn
+        @imm12 = imm12
+        @sh    = sh
+        @sf    = sf
+      end
+
+      def encode
+        ADD_addsub_imm(@sf, @sh, @imm12, @rn.to_i, @rd.to_i)
+      end
+
+      private
+
+      def ADD_addsub_imm sf, sh, imm12, rn, rd
+        insn = 0b0_0_0_100010_0_000000000000_00000_00000
+        insn |= ((sf & 0x1) << 31)
+        insn |= ((sh & 0x1) << 22)
+        insn |= ((imm12 & 0xfff) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/add_addsub_shift.rb

@@ -0,0 +1,35 @@
+module AArch64
+  module Instructions
+    # ADD (shifted register) -- A64
+    # Add (shifted register)
+    # ADD  <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
+    # ADD  <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
+    class ADD_addsub_shift
+      def initialize xd, xn, xm, shift, amount, sf
+        @xd     = xd
+        @xn     = xn
+        @xm     = xm
+        @shift  = shift
+        @amount = amount
+        @sf     = sf
+      end
+
+      def encode
+        ADD_addsub_shift(@sf, @shift, @xm.to_i, @amount, @xn.to_i, @xd.to_i)
+      end
+
+      private
+
+      def ADD_addsub_shift sf, shift, rm, imm6, rn, rd
+        insn = 0b0_0_0_01011_00_0_00000_000000_00000_00000
+        insn |= ((sf & 0x1) << 31)
+        insn |= ((shift & 0x3) << 22)
+        insn |= ((rm & 0x1f) << 16)
+        insn |= ((imm6 & 0x3f) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/addg.rb

@@ -0,0 +1,30 @@
+module AArch64
+  module Instructions
+    # ADDG -- A64
+    # Add with Tag
+    # ADDG  <Xd|SP>, <Xn|SP>, #<uimm6>, #<uimm4>
+    class ADDG
+      def initialize xd, xn, imm6, imm4
+        @xd   = xd
+        @xn   = xn
+        @imm6 = imm6
+        @imm4 = imm4
+      end
+
+      def encode
+        ADDG(@imm6, @imm4, @xn.to_i, @xd.to_i)
+      end
+
+      private
+
+      def ADDG uimm6, uimm4, xn, xd
+        insn = 0b1_0_0_100011_0_000000_00_0000_00000_00000
+        insn |= ((uimm6 & 0x3f) << 16)
+        insn |= ((uimm4 & 0xf) << 10)
+        insn |= ((xn & 0x1f) << 5)
+        insn |= (xd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/adds_addsub_ext.rb

@@ -0,0 +1,35 @@
+module AArch64
+  module Instructions
+    # ADDS (extended register) -- A64
+    # Add (extended register), setting flags
+    # ADDS  <Wd>, <Wn|WSP>, <Wm>{, <extend> {#<amount>}}
+    # ADDS  <Xd>, <Xn|SP>, <R><m>{, <extend> {#<amount>}}
+    class ADDS_addsub_ext
+      def initialize d, n, m, extend, amount, sf
+        @d      = d
+        @n      = n
+        @m      = m
+        @extend = extend
+        @amount = amount
+        @sf     = sf
+      end
+
+      def encode
+        ADDS_addsub_ext(@sf, @m.to_i, @extend, @amount, @n.to_i, @d.to_i)
+      end
+
+      private
+
+      def ADDS_addsub_ext sf, rm, option, imm3, rn, rd
+        insn = 0b0_0_1_01011_00_1_00000_000_000_00000_00000
+        insn |= ((sf & 0x1) << 31)
+        insn |= ((rm & 0x1f) << 16)
+        insn |= ((option & 0x7) << 13)
+        insn |= ((imm3 & 0x7) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/adds_addsub_imm.rb

@@ -0,0 +1,33 @@
+module AArch64
+  module Instructions
+    # ADDS (immediate) -- A64
+    # Add (immediate), setting flags
+    # ADDS  <Wd>, <Wn|WSP>, #<imm>{, <shift>}
+    # ADDS  <Xd>, <Xn|SP>, #<imm>{, <shift>}
+    class ADDS_addsub_imm
+      def initialize d, n, imm, shift, sf
+        @d     = d
+        @n     = n
+        @imm   = imm
+        @shift = shift
+        @sf    = sf
+      end
+
+      def encode
+        ADDS_addsub_imm(@sf, @shift, @imm, @n.to_i, @d.to_i)
+      end
+
+      private
+
+      def ADDS_addsub_imm sf, sh, imm12, rn, rd
+        insn = 0b0_0_1_100010_0_000000000000_00000_00000
+        insn |= ((sf & 0x1) << 31)
+        insn |= ((sh & 0x1) << 22)
+        insn |= ((imm12 & 0xfff) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/adds_addsub_shift.rb

@@ -0,0 +1,35 @@
+module AArch64
+  module Instructions
+    # ADDS (shifted register) -- A64
+    # Add (shifted register), setting flags
+    # ADDS  <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
+    # ADDS  <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
+    class ADDS_addsub_shift
+      def initialize xd, xn, xm, shift, amount, sf
+        @xd     = xd
+        @xn     = xn
+        @xm     = xm
+        @shift  = shift
+        @amount = amount
+        @sf     = sf
+      end
+
+      def encode
+        ADDS_addsub_shift(@sf, @shift, @xm.to_i, @amount, @xn.to_i, @xd.to_i)
+      end
+
+      private
+
+      def ADDS_addsub_shift sf, shift, rm, imm6, rn, rd
+        insn = 0b0_0_1_01011_00_0_00000_000000_00000_00000
+        insn |= ((sf & 0x1) << 31)
+        insn |= ((shift & 0x3) << 22)
+        insn |= ((rm & 0x1f) << 16)
+        insn |= ((imm6 & 0x3f) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/adr.rb

@@ -0,0 +1,28 @@
+module AArch64
+  module Instructions
+    # ADR -- A64
+    # Form PC-relative address
+    # ADR  <Xd>, <label>
+    class ADR
+      def initialize xd, label
+        @xd    = xd
+        @label = label
+      end
+
+      def encode
+        label = @label.to_i
+        ADR(label, label >> 2, @xd.to_i)
+      end
+
+      private
+
+      def ADR immlo, immhi, rd
+        insn = 0b0_00_10000_0000000000000000000_00000
+        insn |= ((immlo & 0x3) << 29)
+        insn |= ((immhi & 0x7ffff) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/adrp.rb

@@ -0,0 +1,28 @@
+module AArch64
+  module Instructions
+    # ADRP -- A64
+    # Form PC-relative address to 4KB page
+    # ADRP  <Xd>, <label>
+    class ADRP
+      def initialize xd, label
+        @xd    = xd
+        @label = label
+      end
+
+      def encode
+        label = @label.to_i / 1000
+        ADRP(label, label >> 2, @xd.to_i)
+      end
+
+      private
+
+      def ADRP immlo, immhi, rd
+        insn = 0b1_00_10000_0000000000000000000_00000
+        insn |= ((immlo & 0x3) << 29)
+        insn |= ((immhi & 0x7ffff) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/and_log_imm.rb

@@ -0,0 +1,35 @@
+module AArch64
+  module Instructions
+    # AND (immediate) -- A64
+    # Bitwise AND (immediate)
+    # AND  <Wd|WSP>, <Wn>, #<imm>
+    # AND  <Xd|SP>, <Xn>, #<imm>
+    class AND_log_imm
+      def initialize rd, rn, immr, imms, n, sf
+        @rd   = rd
+        @rn   = rn
+        @immr = immr
+        @imms = imms
+        @n    = n
+        @sf   = sf
+      end
+
+      def encode
+        self.AND_log_imm(@sf, @n, @immr, @imms, @rn.to_i, @rd.to_i)
+      end
+
+      private
+
+      def AND_log_imm sf, n, immr, imms, rn, rd
+        insn = 0b0_00_100100_0_000000_000000_00000_00000
+        insn |= ((sf & 0x1) << 31)
+        insn |= ((n & 0x1) << 22)
+        insn |= ((immr & 0x3f) << 16)
+        insn |= ((imms & 0x3f) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/and_log_shift.rb

@@ -0,0 +1,35 @@
+module AArch64
+  module Instructions
+    # AND (shifted register) -- A64
+    # Bitwise AND (shifted register)
+    # AND  <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
+    # AND  <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
+    class AND_log_shift
+      def initialize xd, xn, xm, shift, amount, sf
+        @xd     = xd
+        @xn     = xn
+        @xm     = xm
+        @shift  = shift
+        @amount = amount
+        @sf     = sf
+      end
+
+      def encode
+        AND_log_shift(@sf, @shift, @xm.to_i, @amount, @xn.to_i, @xd.to_i)
+      end
+
+      private
+
+      def AND_log_shift sf, shift, rm, imm6, rn, rd
+        insn = 0b0_00_01010_00_0_00000_000000_00000_00000
+        insn |= ((sf & 0x1) << 31)
+        insn |= ((shift & 0x3) << 22)
+        insn |= ((rm & 0x1f) << 16)
+        insn |= ((imm6 & 0x3f) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/ands_log_imm.rb

@@ -0,0 +1,35 @@
+module AArch64
+  module Instructions
+    # ANDS (immediate) -- A64
+    # Bitwise AND (immediate), setting flags
+    # ANDS  <Wd>, <Wn>, #<imm>
+    # ANDS  <Xd>, <Xn>, #<imm>
+    class ANDS_log_imm
+      def initialize rd, rn, immr, imms, n, sf
+        @rd   = rd
+        @rn   = rn
+        @immr = immr
+        @imms = imms
+        @n    = n
+        @sf   = sf
+      end
+
+      def encode
+        self.ANDS_log_imm(@sf, @n, @immr, @imms, @rn.to_i, @rd.to_i)
+      end
+
+      private
+
+      def ANDS_log_imm sf, n, immr, imms, rn, rd
+        insn = 0b0_11_100100_0_000000_000000_00000_00000
+        insn |= ((sf & 0x1) << 31)
+        insn |= ((n & 0x1) << 22)
+        insn |= ((immr & 0x3f) << 16)
+        insn |= ((imms & 0x3f) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/ands_log_shift.rb

@@ -0,0 +1,35 @@
+module AArch64
+  module Instructions
+    # ANDS (shifted register) -- A64
+    # Bitwise AND (shifted register), setting flags
+    # ANDS  <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
+    # ANDS  <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
+    class ANDS_log_shift
+      def initialize xd, xn, xm, shift, amount, sf
+        @xd     = xd
+        @xn     = xn
+        @xm     = xm
+        @shift  = shift
+        @amount = amount
+        @sf     = sf
+      end
+
+      def encode
+        ANDS_log_shift(@sf, @shift, @xm.to_i, @amount, @xn.to_i, @xd.to_i)
+      end
+
+      private
+
+      def ANDS_log_shift sf, shift, rm, imm6, rn, rd
+        insn = 0b0_11_01010_00_0_00000_000000_00000_00000
+        insn |= ((sf & 0x1) << 31)
+        insn |= ((shift & 0x3) << 22)
+        insn |= ((rm & 0x1f) << 16)
+        insn |= ((imm6 & 0x3f) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/asrv.rb

@@ -0,0 +1,31 @@
+module AArch64
+  module Instructions
+    # ASRV -- A64
+    # Arithmetic Shift Right Variable
+    # ASRV  <Wd>, <Wn>, <Wm>
+    # ASRV  <Xd>, <Xn>, <Xm>
+    class ASRV
+      def initialize rd, rn, rm, sf
+        @rd = rd
+        @rn = rn
+        @rm = rm
+        @sf = sf
+      end
+
+      def encode
+        self.ASRV(@sf, @rm.to_i, @rn.to_i, @rd.to_i)
+      end
+
+      private
+
+      def ASRV sf, rm, rn, rd
+        insn = 0b0_0_0_11010110_00000_0010_10_00000_00000
+        insn |= ((sf & 0x1) << 31)
+        insn |= ((rm & 0x1f) << 16)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/autda.rb

@@ -0,0 +1,32 @@
+module AArch64
+  module Instructions
+    # AUTDA, AUTDZA -- A64
+    # Authenticate Data address, using key A
+    # AUTDA  <Xd>, <Xn|SP>
+    # AUTDZA  <Xd>
+    class AUTDA
+      def initialize d, n
+        @d = d
+        @n = n
+      end
+
+      def encode
+        if @n.integer?
+          AUTDA(1, @n.to_i, @d.to_i)
+        else
+          AUTDA(0, @n.to_i, @d.to_i)
+        end
+      end
+
+      private
+
+      def AUTDA z, rn, rd
+        insn = 0b1_1_0_11010110_00001_0_0_0_110_00000_00000
+        insn |= ((z & 0x1) << 13)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/autdb.rb

@@ -0,0 +1,32 @@
+module AArch64
+  module Instructions
+    # AUTDB, AUTDZB -- A64
+    # Authenticate Data address, using key B
+    # AUTDB  <Xd>, <Xn|SP>
+    # AUTDZB  <Xd>
+    class AUTDB
+      def initialize d, n
+        @d = d
+        @n = n
+      end
+
+      def encode
+        if @n.integer?
+          AUTDB(1, @n.to_i, @d.to_i)
+        else
+          AUTDB(0, @n.to_i, @d.to_i)
+        end
+      end
+
+      private
+
+      def AUTDB z, rn, rd
+        insn = 0b1_1_0_11010110_00001_0_0_0_111_00000_00000
+        insn |= ((z & 0x1) << 13)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/autia.rb

@@ -0,0 +1,35 @@
+module AArch64
+  module Instructions
+    # AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZA -- A64
+    # Authenticate Instruction address, using key A
+    # AUTIA  <Xd>, <Xn|SP>
+    # AUTIZA  <Xd>
+    # AUTIA1716
+    # AUTIASP
+    # AUTIAZ
+    class AUTIA
+      def initialize d, n
+        @d = d
+        @n = n
+      end
+
+      def encode
+        if @n.integer?
+          AUTIA(1, @n.to_i, @d.to_i)
+        else
+          AUTIA(0, @n.to_i, @d.to_i)
+        end
+      end
+
+      private
+
+      def AUTIA z, rn, rd
+        insn = 0b1_1_0_11010110_00001_0_0_0_100_00000_00000
+        insn |= ((z & 0x1) << 13)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/autib.rb

@@ -0,0 +1,35 @@
+module AArch64
+  module Instructions
+    # AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZB -- A64
+    # Authenticate Instruction address, using key B
+    # AUTIB  <Xd>, <Xn|SP>
+    # AUTIZB  <Xd>
+    # AUTIB1716
+    # AUTIBSP
+    # AUTIBZ
+    class AUTIB
+      def initialize d, n
+        @d = d
+        @n = n
+      end
+
+      def encode
+        if @n.integer?
+          AUTIB(1, @n.to_i, @d.to_i)
+        else
+          AUTIB(0, @n.to_i, @d.to_i)
+        end
+      end
+
+      private
+
+      def AUTIB z, rn, rd
+        insn = 0b1_1_0_11010110_00001_0_0_0_101_00000_00000
+        insn |= ((z & 0x1) << 13)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/axflag.rb

@@ -0,0 +1,18 @@
+module AArch64
+  module Instructions
+    # AXFLAG -- A64
+    # Convert floating-point condition flags from Arm to external format
+    # AXFLAG
+    class AXFLAG
+      def encode
+        self.AXFLAG
+      end
+
+      private
+
+      def AXFLAG
+        0b1101010100_0_00_000_0100_0000_010_11111
+      end
+    end
+  end
+end