aarch64 1.0.0
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- checksums.yaml +7 -0
- data/CODE_OF_CONDUCT.md +77 -0
- data/Gemfile +3 -0
- data/LICENSE +201 -0
- data/README.md +77 -0
- data/Rakefile +168 -0
- data/aarch64.gemspec +21 -0
- data/bin/build_instructions.rb +102 -0
- data/lib/aarch64/instructions/adc.rb +31 -0
- data/lib/aarch64/instructions/adcs.rb +30 -0
- data/lib/aarch64/instructions/add_addsub_ext.rb +35 -0
- data/lib/aarch64/instructions/add_addsub_imm.rb +32 -0
- data/lib/aarch64/instructions/add_addsub_shift.rb +35 -0
- data/lib/aarch64/instructions/addg.rb +30 -0
- data/lib/aarch64/instructions/adds_addsub_ext.rb +35 -0
- data/lib/aarch64/instructions/adds_addsub_imm.rb +33 -0
- data/lib/aarch64/instructions/adds_addsub_shift.rb +35 -0
- data/lib/aarch64/instructions/adr.rb +28 -0
- data/lib/aarch64/instructions/adrp.rb +28 -0
- data/lib/aarch64/instructions/and_log_imm.rb +35 -0
- data/lib/aarch64/instructions/and_log_shift.rb +35 -0
- data/lib/aarch64/instructions/ands_log_imm.rb +35 -0
- data/lib/aarch64/instructions/ands_log_shift.rb +35 -0
- data/lib/aarch64/instructions/asrv.rb +31 -0
- data/lib/aarch64/instructions/autda.rb +32 -0
- data/lib/aarch64/instructions/autdb.rb +32 -0
- data/lib/aarch64/instructions/autia.rb +35 -0
- data/lib/aarch64/instructions/autib.rb +35 -0
- data/lib/aarch64/instructions/axflag.rb +18 -0
- data/lib/aarch64/instructions/b_cond.rb +26 -0
- data/lib/aarch64/instructions/b_uncond.rb +24 -0
- data/lib/aarch64/instructions/bc_cond.rb +26 -0
- data/lib/aarch64/instructions/bfm.rb +34 -0
- data/lib/aarch64/instructions/bic_log_shift.rb +35 -0
- data/lib/aarch64/instructions/bics.rb +35 -0
- data/lib/aarch64/instructions/bl.rb +24 -0
- data/lib/aarch64/instructions/blr.rb +24 -0
- data/lib/aarch64/instructions/blra.rb +33 -0
- data/lib/aarch64/instructions/br.rb +24 -0
- data/lib/aarch64/instructions/bra.rb +33 -0
- data/lib/aarch64/instructions/brk.rb +24 -0
- data/lib/aarch64/instructions/bti.rb +24 -0
- data/lib/aarch64/instructions/cas.rb +41 -0
- data/lib/aarch64/instructions/casb.rb +35 -0
- data/lib/aarch64/instructions/cash.rb +35 -0
- data/lib/aarch64/instructions/casp.rb +41 -0
- data/lib/aarch64/instructions/cbnz.rb +29 -0
- data/lib/aarch64/instructions/cbz.rb +29 -0
- data/lib/aarch64/instructions/ccmn_imm.rb +33 -0
- data/lib/aarch64/instructions/ccmn_reg.rb +33 -0
- data/lib/aarch64/instructions/ccmp_imm.rb +33 -0
- data/lib/aarch64/instructions/ccmp_reg.rb +33 -0
- data/lib/aarch64/instructions/cfinv.rb +19 -0
- data/lib/aarch64/instructions/clrex.rb +24 -0
- data/lib/aarch64/instructions/cls_int.rb +29 -0
- data/lib/aarch64/instructions/clz_int.rb +29 -0
- data/lib/aarch64/instructions/crc32.rb +35 -0
- data/lib/aarch64/instructions/crc32c.rb +35 -0
- data/lib/aarch64/instructions/csdb.rb +19 -0
- data/lib/aarch64/instructions/csel.rb +33 -0
- data/lib/aarch64/instructions/csinc.rb +33 -0
- data/lib/aarch64/instructions/csinv.rb +33 -0
- data/lib/aarch64/instructions/csneg.rb +33 -0
- data/lib/aarch64/instructions/dcps.rb +26 -0
- data/lib/aarch64/instructions/dgh.rb +19 -0
- data/lib/aarch64/instructions/dmb.rb +24 -0
- data/lib/aarch64/instructions/drps.rb +19 -0
- data/lib/aarch64/instructions/dsb.rb +25 -0
- data/lib/aarch64/instructions/eon.rb +35 -0
- data/lib/aarch64/instructions/eor_log_imm.rb +35 -0
- data/lib/aarch64/instructions/eor_log_shift.rb +35 -0
- data/lib/aarch64/instructions/eret.rb +19 -0
- data/lib/aarch64/instructions/ereta.rb +25 -0
- data/lib/aarch64/instructions/esb.rb +19 -0
- data/lib/aarch64/instructions/extr.rb +34 -0
- data/lib/aarch64/instructions/gmi.rb +28 -0
- data/lib/aarch64/instructions/hint.rb +26 -0
- data/lib/aarch64/instructions/hlt.rb +24 -0
- data/lib/aarch64/instructions/hvc.rb +24 -0
- data/lib/aarch64/instructions/irg.rb +28 -0
- data/lib/aarch64/instructions/isb.rb +24 -0
- data/lib/aarch64/instructions/ld64b.rb +26 -0
- data/lib/aarch64/instructions/ldadd.rb +41 -0
- data/lib/aarch64/instructions/ldaddb.rb +35 -0
- data/lib/aarch64/instructions/ldaddh.rb +35 -0
- data/lib/aarch64/instructions/ldapr.rb +29 -0
- data/lib/aarch64/instructions/ldaprb.rb +26 -0
- data/lib/aarch64/instructions/ldaprh.rb +26 -0
- data/lib/aarch64/instructions/ldapur_gen.rb +33 -0
- data/lib/aarch64/instructions/ldar.rb +29 -0
- data/lib/aarch64/instructions/ldaxp.rb +31 -0
- data/lib/aarch64/instructions/ldaxr.rb +29 -0
- data/lib/aarch64/instructions/ldclr.rb +41 -0
- data/lib/aarch64/instructions/ldclrb.rb +37 -0
- data/lib/aarch64/instructions/ldeor.rb +41 -0
- data/lib/aarch64/instructions/ldg.rb +28 -0
- data/lib/aarch64/instructions/ldgm.rb +26 -0
- data/lib/aarch64/instructions/ldlar.rb +29 -0
- data/lib/aarch64/instructions/ldnp_gen.rb +33 -0
- data/lib/aarch64/instructions/ldp_gen.rb +39 -0
- data/lib/aarch64/instructions/ldpsw.rb +34 -0
- data/lib/aarch64/instructions/ldr_imm_gen.rb +35 -0
- data/lib/aarch64/instructions/ldr_imm_unsigned.rb +31 -0
- data/lib/aarch64/instructions/ldr_lit_gen.rb +29 -0
- data/lib/aarch64/instructions/ldr_reg_gen.rb +35 -0
- data/lib/aarch64/instructions/ldra.rb +37 -0
- data/lib/aarch64/instructions/ldrb_imm.rb +32 -0
- data/lib/aarch64/instructions/ldrb_reg.rb +33 -0
- data/lib/aarch64/instructions/ldrb_unsigned.rb +28 -0
- data/lib/aarch64/instructions/ldrh_imm.rb +32 -0
- data/lib/aarch64/instructions/ldrh_reg.rb +32 -0
- data/lib/aarch64/instructions/ldrh_unsigned.rb +28 -0
- data/lib/aarch64/instructions/ldrsb_imm.rb +37 -0
- data/lib/aarch64/instructions/ldrsb_reg.rb +37 -0
- data/lib/aarch64/instructions/ldrsb_unsigned.rb +35 -0
- data/lib/aarch64/instructions/ldrsh_imm.rb +37 -0
- data/lib/aarch64/instructions/ldrsh_reg.rb +35 -0
- data/lib/aarch64/instructions/ldrsh_unsigned.rb +31 -0
- data/lib/aarch64/instructions/ldrsw_imm.rb +32 -0
- data/lib/aarch64/instructions/ldrsw_lit.rb +26 -0
- data/lib/aarch64/instructions/ldrsw_reg.rb +32 -0
- data/lib/aarch64/instructions/ldrsw_unsigned.rb +30 -0
- data/lib/aarch64/instructions/ldset.rb +41 -0
- data/lib/aarch64/instructions/ldsetb.rb +35 -0
- data/lib/aarch64/instructions/ldseth.rb +35 -0
- data/lib/aarch64/instructions/ldsmax.rb +41 -0
- data/lib/aarch64/instructions/ldsmaxb.rb +35 -0
- data/lib/aarch64/instructions/ldsmaxh.rb +35 -0
- data/lib/aarch64/instructions/ldsmin.rb +41 -0
- data/lib/aarch64/instructions/ldsminb.rb +35 -0
- data/lib/aarch64/instructions/ldsminh.rb +35 -0
- data/lib/aarch64/instructions/ldtr.rb +31 -0
- data/lib/aarch64/instructions/ldtrb.rb +28 -0
- data/lib/aarch64/instructions/ldtrh.rb +28 -0
- data/lib/aarch64/instructions/ldtrsb.rb +31 -0
- data/lib/aarch64/instructions/ldtrsh.rb +31 -0
- data/lib/aarch64/instructions/ldtrsw.rb +28 -0
- data/lib/aarch64/instructions/ldumax.rb +41 -0
- data/lib/aarch64/instructions/ldumaxb.rb +35 -0
- data/lib/aarch64/instructions/ldumaxh.rb +35 -0
- data/lib/aarch64/instructions/ldumin.rb +41 -0
- data/lib/aarch64/instructions/lduminb.rb +35 -0
- data/lib/aarch64/instructions/lduminh.rb +35 -0
- data/lib/aarch64/instructions/ldur_gen.rb +31 -0
- data/lib/aarch64/instructions/ldursb.rb +31 -0
- data/lib/aarch64/instructions/ldursh.rb +31 -0
- data/lib/aarch64/instructions/ldursw.rb +28 -0
- data/lib/aarch64/instructions/ldxp.rb +31 -0
- data/lib/aarch64/instructions/ldxr.rb +29 -0
- data/lib/aarch64/instructions/lslv.rb +31 -0
- data/lib/aarch64/instructions/lsrv.rb +31 -0
- data/lib/aarch64/instructions/madd.rb +33 -0
- data/lib/aarch64/instructions/movk.rb +31 -0
- data/lib/aarch64/instructions/movn.rb +31 -0
- data/lib/aarch64/instructions/movz.rb +31 -0
- data/lib/aarch64/instructions/mrs.rb +34 -0
- data/lib/aarch64/instructions/msr_imm.rb +28 -0
- data/lib/aarch64/instructions/msr_reg.rb +34 -0
- data/lib/aarch64/instructions/msub.rb +33 -0
- data/lib/aarch64/instructions/nop.rb +19 -0
- data/lib/aarch64/instructions/orn_log_shift.rb +35 -0
- data/lib/aarch64/instructions/orr_log_imm.rb +35 -0
- data/lib/aarch64/instructions/orr_log_shift.rb +35 -0
- data/lib/aarch64/instructions/pacda.rb +29 -0
- data/lib/aarch64/instructions/pacdb.rb +29 -0
- data/lib/aarch64/instructions/pacga.rb +28 -0
- data/lib/aarch64/instructions/pacia.rb +32 -0
- data/lib/aarch64/instructions/pacia2.rb +28 -0
- data/lib/aarch64/instructions/pacib.rb +32 -0
- data/lib/aarch64/instructions/prfm_imm.rb +28 -0
- data/lib/aarch64/instructions/prfm_lit.rb +26 -0
- data/lib/aarch64/instructions/prfm_reg.rb +32 -0
- data/lib/aarch64/instructions/prfum.rb +28 -0
- data/lib/aarch64/instructions/psb.rb +19 -0
- data/lib/aarch64/instructions/rbit_int.rb +29 -0
- data/lib/aarch64/instructions/ret.rb +24 -0
- data/lib/aarch64/instructions/reta.rb +25 -0
- data/lib/aarch64/instructions/rev.rb +31 -0
- data/lib/aarch64/instructions/rmif.rb +28 -0
- data/lib/aarch64/instructions/rorv.rb +31 -0
- data/lib/aarch64/instructions/sb.rb +19 -0
- data/lib/aarch64/instructions/sbc.rb +31 -0
- data/lib/aarch64/instructions/sbcs.rb +31 -0
- data/lib/aarch64/instructions/sbfm.rb +34 -0
- data/lib/aarch64/instructions/sdiv.rb +31 -0
- data/lib/aarch64/instructions/setf.rb +27 -0
- data/lib/aarch64/instructions/setgp.rb +25 -0
- data/lib/aarch64/instructions/setgpn.rb +25 -0
- data/lib/aarch64/instructions/setgpt.rb +25 -0
- data/lib/aarch64/instructions/setgptn.rb +25 -0
- data/lib/aarch64/instructions/setp.rb +25 -0
- data/lib/aarch64/instructions/setpn.rb +25 -0
- data/lib/aarch64/instructions/setpt.rb +25 -0
- data/lib/aarch64/instructions/setptn.rb +25 -0
- data/lib/aarch64/instructions/sev.rb +18 -0
- data/lib/aarch64/instructions/sevl.rb +18 -0
- data/lib/aarch64/instructions/smaddl.rb +30 -0
- data/lib/aarch64/instructions/smc.rb +24 -0
- data/lib/aarch64/instructions/smsubl.rb +30 -0
- data/lib/aarch64/instructions/smulh.rb +28 -0
- data/lib/aarch64/instructions/st2g.rb +32 -0
- data/lib/aarch64/instructions/st64b.rb +26 -0
- data/lib/aarch64/instructions/st64bv.rb +28 -0
- data/lib/aarch64/instructions/st64bv0.rb +28 -0
- data/lib/aarch64/instructions/stg.rb +32 -0
- data/lib/aarch64/instructions/stgm.rb +26 -0
- data/lib/aarch64/instructions/stgp.rb +34 -0
- data/lib/aarch64/instructions/stllr.rb +29 -0
- data/lib/aarch64/instructions/stllrb.rb +26 -0
- data/lib/aarch64/instructions/stllrh.rb +26 -0
- data/lib/aarch64/instructions/stlr.rb +29 -0
- data/lib/aarch64/instructions/stlrb.rb +26 -0
- data/lib/aarch64/instructions/stlrh.rb +26 -0
- data/lib/aarch64/instructions/stlur_gen.rb +31 -0
- data/lib/aarch64/instructions/stlxp.rb +33 -0
- data/lib/aarch64/instructions/stlxr.rb +31 -0
- data/lib/aarch64/instructions/stlxrb.rb +28 -0
- data/lib/aarch64/instructions/stlxrh.rb +28 -0
- data/lib/aarch64/instructions/stnp_gen.rb +33 -0
- data/lib/aarch64/instructions/stp_gen.rb +39 -0
- data/lib/aarch64/instructions/str_imm_gen.rb +37 -0
- data/lib/aarch64/instructions/str_imm_unsigned.rb +31 -0
- data/lib/aarch64/instructions/str_reg_gen.rb +35 -0
- data/lib/aarch64/instructions/strb_imm.rb +32 -0
- data/lib/aarch64/instructions/strb_imm_unsigned.rb +28 -0
- data/lib/aarch64/instructions/strb_reg.rb +33 -0
- data/lib/aarch64/instructions/strh_imm.rb +32 -0
- data/lib/aarch64/instructions/strh_imm_unsigned.rb +28 -0
- data/lib/aarch64/instructions/strh_reg.rb +32 -0
- data/lib/aarch64/instructions/sttr.rb +31 -0
- data/lib/aarch64/instructions/stur_gen.rb +31 -0
- data/lib/aarch64/instructions/stxp.rb +33 -0
- data/lib/aarch64/instructions/stxr.rb +31 -0
- data/lib/aarch64/instructions/stxrb.rb +28 -0
- data/lib/aarch64/instructions/stxrh.rb +28 -0
- data/lib/aarch64/instructions/stz2g.rb +32 -0
- data/lib/aarch64/instructions/stzg.rb +32 -0
- data/lib/aarch64/instructions/stzgm.rb +26 -0
- data/lib/aarch64/instructions/sub_addsub_ext.rb +35 -0
- data/lib/aarch64/instructions/sub_addsub_imm.rb +33 -0
- data/lib/aarch64/instructions/sub_addsub_shift.rb +35 -0
- data/lib/aarch64/instructions/subg.rb +30 -0
- data/lib/aarch64/instructions/subp.rb +28 -0
- data/lib/aarch64/instructions/subps.rb +28 -0
- data/lib/aarch64/instructions/subs_addsub_ext.rb +35 -0
- data/lib/aarch64/instructions/subs_addsub_imm.rb +33 -0
- data/lib/aarch64/instructions/subs_addsub_shift.rb +35 -0
- data/lib/aarch64/instructions/svc.rb +24 -0
- data/lib/aarch64/instructions/swp.rb +41 -0
- data/lib/aarch64/instructions/swpb.rb +35 -0
- data/lib/aarch64/instructions/swph.rb +35 -0
- data/lib/aarch64/instructions/sys.rb +32 -0
- data/lib/aarch64/instructions/sysl.rb +32 -0
- data/lib/aarch64/instructions/tbnz.rb +30 -0
- data/lib/aarch64/instructions/tbz.rb +30 -0
- data/lib/aarch64/instructions/tsb.rb +18 -0
- data/lib/aarch64/instructions/ubfm.rb +34 -0
- data/lib/aarch64/instructions/udf_perm_undef.rb +24 -0
- data/lib/aarch64/instructions/udiv.rb +31 -0
- data/lib/aarch64/instructions/umaddl.rb +30 -0
- data/lib/aarch64/instructions/umsubl.rb +30 -0
- data/lib/aarch64/instructions/umulh.rb +28 -0
- data/lib/aarch64/instructions/wfe.rb +19 -0
- data/lib/aarch64/instructions/wfet.rb +24 -0
- data/lib/aarch64/instructions/wfi.rb +19 -0
- data/lib/aarch64/instructions/wfit.rb +24 -0
- data/lib/aarch64/instructions/xaflag.rb +19 -0
- data/lib/aarch64/instructions/xpac.rb +28 -0
- data/lib/aarch64/instructions/xpaclri.rb +18 -0
- data/lib/aarch64/instructions/yield.rb +19 -0
- data/lib/aarch64/instructions.rb +266 -0
- data/lib/aarch64/system_registers/mrs_msr_64.rb +395 -0
- data/lib/aarch64/utils.rb +325 -0
- data/lib/aarch64/version.rb +3 -0
- data/lib/aarch64.rb +2857 -0
- data/test/all_adds_test.rb +129 -0
- data/test/base_instructions_test.rb +9263 -0
- data/test/dsl_test.rb +11 -0
- data/test/helper.rb +51 -0
- data/test/not_supported_yet_test.rb +55 -0
- metadata +382 -0
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module AArch64
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module Instructions
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# LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL -- A64
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# Atomic unsigned maximum on word or doubleword in memory
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# LDUMAX <Ws>, <Wt>, [<Xn|SP>]
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# LDUMAXA <Ws>, <Wt>, [<Xn|SP>]
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# LDUMAXAL <Ws>, <Wt>, [<Xn|SP>]
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# LDUMAXL <Ws>, <Wt>, [<Xn|SP>]
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# LDUMAX <Xs>, <Xt>, [<Xn|SP>]
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# LDUMAXA <Xs>, <Xt>, [<Xn|SP>]
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# LDUMAXAL <Xs>, <Xt>, [<Xn|SP>]
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# LDUMAXL <Xs>, <Xt>, [<Xn|SP>]
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class LDUMAX
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def initialize rs, rt, rn, size, a, r
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@rs = rs
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@rt = rt
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@rn = rn
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@size = size
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@a = a
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@r = r
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end
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def encode
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self.LDUMAX(@size, @a, @r.to_i, @rs.to_i, @rn.to_i, @rt.to_i)
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end
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private
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def LDUMAX size, a, r, rs, rn, rt
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insn = 0b00_111_0_00_0_0_1_00000_0_110_00_00000_00000
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insn |= ((size & 0x3) << 30)
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insn |= ((a & 0x1) << 23)
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insn |= ((r & 0x1) << 22)
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insn |= ((rs & 0x1f) << 16)
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insn |= ((rn & 0x1f) << 5)
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insn |= (rt & 0x1f)
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insn
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end
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end
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end
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end
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module AArch64
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module Instructions
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# LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLB -- A64
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# Atomic unsigned maximum on byte in memory
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# LDUMAXAB <Ws>, <Wt>, [<Xn|SP>]
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# LDUMAXALB <Ws>, <Wt>, [<Xn|SP>]
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# LDUMAXB <Ws>, <Wt>, [<Xn|SP>]
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# LDUMAXLB <Ws>, <Wt>, [<Xn|SP>]
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class LDUMAXB
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def initialize rs, rt, rn, a, r
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@rs = rs
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@rt = rt
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@rn = rn
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@a = a
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@r = r
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end
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def encode
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self.LDUMAXB(@a, @r.to_i, @rs.to_i, @rn.to_i, @rt.to_i)
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end
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private
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def LDUMAXB a, r, rs, rn, rt
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insn = 0b00_111_0_00_0_0_1_00000_0_110_00_00000_00000
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insn |= ((a & 0x1) << 23)
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insn |= ((r & 0x1) << 22)
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insn |= ((rs & 0x1f) << 16)
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insn |= ((rn & 0x1f) << 5)
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insn |= (rt & 0x1f)
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insn
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end
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end
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end
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end
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@@ -0,0 +1,35 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLH -- A64
|
4
|
+
# Atomic unsigned maximum on halfword in memory
|
5
|
+
# LDUMAXAH <Ws>, <Wt>, [<Xn|SP>]
|
6
|
+
# LDUMAXALH <Ws>, <Wt>, [<Xn|SP>]
|
7
|
+
# LDUMAXH <Ws>, <Wt>, [<Xn|SP>]
|
8
|
+
# LDUMAXLH <Ws>, <Wt>, [<Xn|SP>]
|
9
|
+
class LDUMAXH
|
10
|
+
def initialize rs, rt, rn, a, r
|
11
|
+
@rs = rs
|
12
|
+
@rt = rt
|
13
|
+
@rn = rn
|
14
|
+
@a = a
|
15
|
+
@r = r
|
16
|
+
end
|
17
|
+
|
18
|
+
def encode
|
19
|
+
self.LDUMAXH(@a, @r.to_i, @rs.to_i, @rn.to_i, @rt.to_i)
|
20
|
+
end
|
21
|
+
|
22
|
+
private
|
23
|
+
|
24
|
+
def LDUMAXH a, r, rs, rn, rt
|
25
|
+
insn = 0b01_111_0_00_0_0_1_00000_0_110_00_00000_00000
|
26
|
+
insn |= ((a & 0x1) << 23)
|
27
|
+
insn |= ((r & 0x1) << 22)
|
28
|
+
insn |= ((rs & 0x1f) << 16)
|
29
|
+
insn |= ((rn & 0x1f) << 5)
|
30
|
+
insn |= (rt & 0x1f)
|
31
|
+
insn
|
32
|
+
end
|
33
|
+
end
|
34
|
+
end
|
35
|
+
end
|
@@ -0,0 +1,41 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# LDUMIN, LDUMINA, LDUMINAL, LDUMINL -- A64
|
4
|
+
# Atomic unsigned minimum on word or doubleword in memory
|
5
|
+
# LDUMIN <Ws>, <Wt>, [<Xn|SP>]
|
6
|
+
# LDUMINA <Ws>, <Wt>, [<Xn|SP>]
|
7
|
+
# LDUMINAL <Ws>, <Wt>, [<Xn|SP>]
|
8
|
+
# LDUMINL <Ws>, <Wt>, [<Xn|SP>]
|
9
|
+
# LDUMIN <Xs>, <Xt>, [<Xn|SP>]
|
10
|
+
# LDUMINA <Xs>, <Xt>, [<Xn|SP>]
|
11
|
+
# LDUMINAL <Xs>, <Xt>, [<Xn|SP>]
|
12
|
+
# LDUMINL <Xs>, <Xt>, [<Xn|SP>]
|
13
|
+
class LDUMIN
|
14
|
+
def initialize rs, rt, rn, size, a, r
|
15
|
+
@rs = rs
|
16
|
+
@rt = rt
|
17
|
+
@rn = rn
|
18
|
+
@size = size
|
19
|
+
@a = a
|
20
|
+
@r = r
|
21
|
+
end
|
22
|
+
|
23
|
+
def encode
|
24
|
+
self.LDUMIN(@size, @a, @r.to_i, @rs.to_i, @rn.to_i, @rt.to_i)
|
25
|
+
end
|
26
|
+
|
27
|
+
private
|
28
|
+
|
29
|
+
def LDUMIN size, a, r, rs, rn, rt
|
30
|
+
insn = 0b00_111_0_00_0_0_1_00000_0_111_00_00000_00000
|
31
|
+
insn |= ((size & 0x3) << 30)
|
32
|
+
insn |= ((a & 0x1) << 23)
|
33
|
+
insn |= ((r & 0x1) << 22)
|
34
|
+
insn |= ((rs & 0x1f) << 16)
|
35
|
+
insn |= ((rn & 0x1f) << 5)
|
36
|
+
insn |= (rt & 0x1f)
|
37
|
+
insn
|
38
|
+
end
|
39
|
+
end
|
40
|
+
end
|
41
|
+
end
|
@@ -0,0 +1,35 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# LDUMINB, LDUMINAB, LDUMINALB, LDUMINLB -- A64
|
4
|
+
# Atomic unsigned minimum on byte in memory
|
5
|
+
# LDUMINAB <Ws>, <Wt>, [<Xn|SP>]
|
6
|
+
# LDUMINALB <Ws>, <Wt>, [<Xn|SP>]
|
7
|
+
# LDUMINB <Ws>, <Wt>, [<Xn|SP>]
|
8
|
+
# LDUMINLB <Ws>, <Wt>, [<Xn|SP>]
|
9
|
+
class LDUMINB
|
10
|
+
def initialize rs, rt, rn, a, r
|
11
|
+
@rs = rs
|
12
|
+
@rt = rt
|
13
|
+
@rn = rn
|
14
|
+
@a = a
|
15
|
+
@r = r
|
16
|
+
end
|
17
|
+
|
18
|
+
def encode
|
19
|
+
self.LDUMINB(@a, @r.to_i, @rs.to_i, @rn.to_i, @rt.to_i)
|
20
|
+
end
|
21
|
+
|
22
|
+
private
|
23
|
+
|
24
|
+
def LDUMINB a, r, rs, rn, rt
|
25
|
+
insn = 0b00_111_0_00_0_0_1_00000_0_111_00_00000_00000
|
26
|
+
insn |= ((a & 0x1) << 23)
|
27
|
+
insn |= ((r & 0x1) << 22)
|
28
|
+
insn |= ((rs & 0x1f) << 16)
|
29
|
+
insn |= ((rn & 0x1f) << 5)
|
30
|
+
insn |= (rt & 0x1f)
|
31
|
+
insn
|
32
|
+
end
|
33
|
+
end
|
34
|
+
end
|
35
|
+
end
|
@@ -0,0 +1,35 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# LDUMINH, LDUMINAH, LDUMINALH, LDUMINLH -- A64
|
4
|
+
# Atomic unsigned minimum on halfword in memory
|
5
|
+
# LDUMINAH <Ws>, <Wt>, [<Xn|SP>]
|
6
|
+
# LDUMINALH <Ws>, <Wt>, [<Xn|SP>]
|
7
|
+
# LDUMINH <Ws>, <Wt>, [<Xn|SP>]
|
8
|
+
# LDUMINLH <Ws>, <Wt>, [<Xn|SP>]
|
9
|
+
class LDUMINH
|
10
|
+
def initialize rs, rt, rn, a, r
|
11
|
+
@rs = rs
|
12
|
+
@rt = rt
|
13
|
+
@rn = rn
|
14
|
+
@a = a
|
15
|
+
@r = r
|
16
|
+
end
|
17
|
+
|
18
|
+
def encode
|
19
|
+
self.LDUMINH(@a, @r.to_i, @rs.to_i, @rn.to_i, @rt.to_i)
|
20
|
+
end
|
21
|
+
|
22
|
+
private
|
23
|
+
|
24
|
+
def LDUMINH a, r, rs, rn, rt
|
25
|
+
insn = 0b01_111_0_00_0_0_1_00000_0_111_00_00000_00000
|
26
|
+
insn |= ((a & 0x1) << 23)
|
27
|
+
insn |= ((r & 0x1) << 22)
|
28
|
+
insn |= ((rs & 0x1f) << 16)
|
29
|
+
insn |= ((rn & 0x1f) << 5)
|
30
|
+
insn |= (rt & 0x1f)
|
31
|
+
insn
|
32
|
+
end
|
33
|
+
end
|
34
|
+
end
|
35
|
+
end
|
@@ -0,0 +1,31 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# LDUR -- A64
|
4
|
+
# Load Register (unscaled)
|
5
|
+
# LDUR <Wt>, [<Xn|SP>{, #<simm>}]
|
6
|
+
# LDUR <Xt>, [<Xn|SP>{, #<simm>}]
|
7
|
+
class LDUR_gen
|
8
|
+
def initialize rt, rn, imm9, size
|
9
|
+
@rt = rt
|
10
|
+
@rn = rn
|
11
|
+
@imm9 = imm9
|
12
|
+
@size = size
|
13
|
+
end
|
14
|
+
|
15
|
+
def encode
|
16
|
+
self.LDUR_gen(@size, @imm9, @rn.to_i, @rt.to_i)
|
17
|
+
end
|
18
|
+
|
19
|
+
private
|
20
|
+
|
21
|
+
def LDUR_gen size, imm9, rn, rt
|
22
|
+
insn = 0b00_111_0_00_01_0_000000000_00_00000_00000
|
23
|
+
insn |= ((size & 0x3) << 30)
|
24
|
+
insn |= ((imm9 & 0x1ff) << 12)
|
25
|
+
insn |= ((rn & 0x1f) << 5)
|
26
|
+
insn |= (rt & 0x1f)
|
27
|
+
insn
|
28
|
+
end
|
29
|
+
end
|
30
|
+
end
|
31
|
+
end
|
@@ -0,0 +1,31 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# LDURSB -- A64
|
4
|
+
# Load Register Signed Byte (unscaled)
|
5
|
+
# LDURSB <Wt>, [<Xn|SP>{, #<simm>}]
|
6
|
+
# LDURSB <Xt>, [<Xn|SP>{, #<simm>}]
|
7
|
+
class LDURSB
|
8
|
+
def initialize rt, rn, imm9, opc
|
9
|
+
@rt = rt
|
10
|
+
@rn = rn
|
11
|
+
@imm9 = imm9
|
12
|
+
@opc = opc
|
13
|
+
end
|
14
|
+
|
15
|
+
def encode
|
16
|
+
self.LDURSB(@opc, @imm9, @rn.to_i, @rt.to_i)
|
17
|
+
end
|
18
|
+
|
19
|
+
private
|
20
|
+
|
21
|
+
def LDURSB opc, imm9, rn, rt
|
22
|
+
insn = 0b00_111_0_00_00_0_000000000_00_00000_00000
|
23
|
+
insn |= ((opc & 0x3) << 22)
|
24
|
+
insn |= ((imm9 & 0x1ff) << 12)
|
25
|
+
insn |= ((rn & 0x1f) << 5)
|
26
|
+
insn |= (rt & 0x1f)
|
27
|
+
insn
|
28
|
+
end
|
29
|
+
end
|
30
|
+
end
|
31
|
+
end
|
@@ -0,0 +1,31 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# LDURSH -- A64
|
4
|
+
# Load Register Signed Halfword (unscaled)
|
5
|
+
# LDURSH <Wt>, [<Xn|SP>{, #<simm>}]
|
6
|
+
# LDURSH <Xt>, [<Xn|SP>{, #<simm>}]
|
7
|
+
class LDURSH
|
8
|
+
def initialize rt, rn, imm9, opc
|
9
|
+
@rt = rt
|
10
|
+
@rn = rn
|
11
|
+
@imm9 = imm9
|
12
|
+
@opc = opc
|
13
|
+
end
|
14
|
+
|
15
|
+
def encode
|
16
|
+
self.LDURSH(@opc, @imm9, @rn.to_i, @rt.to_i)
|
17
|
+
end
|
18
|
+
|
19
|
+
private
|
20
|
+
|
21
|
+
def LDURSH opc, imm9, rn, rt
|
22
|
+
insn = 0b01_111_0_00_00_0_000000000_00_00000_00000
|
23
|
+
insn |= ((opc & 0x3) << 22)
|
24
|
+
insn |= ((imm9 & 0x1ff) << 12)
|
25
|
+
insn |= ((rn & 0x1f) << 5)
|
26
|
+
insn |= (rt & 0x1f)
|
27
|
+
insn
|
28
|
+
end
|
29
|
+
end
|
30
|
+
end
|
31
|
+
end
|
@@ -0,0 +1,28 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# LDURSW -- A64
|
4
|
+
# Load Register Signed Word (unscaled)
|
5
|
+
# LDURSW <Xt>, [<Xn|SP>{, #<simm>}]
|
6
|
+
class LDURSW
|
7
|
+
def initialize rt, rn, imm9
|
8
|
+
@rt = rt
|
9
|
+
@rn = rn
|
10
|
+
@imm9 = imm9
|
11
|
+
end
|
12
|
+
|
13
|
+
def encode
|
14
|
+
self.LDURSW(@imm9, @rn.to_i, @rt.to_i)
|
15
|
+
end
|
16
|
+
|
17
|
+
private
|
18
|
+
|
19
|
+
def LDURSW imm9, rn, rt
|
20
|
+
insn = 0b10_111_0_00_10_0_000000000_00_00000_00000
|
21
|
+
insn |= ((imm9 & 0x1ff) << 12)
|
22
|
+
insn |= ((rn & 0x1f) << 5)
|
23
|
+
insn |= (rt & 0x1f)
|
24
|
+
insn
|
25
|
+
end
|
26
|
+
end
|
27
|
+
end
|
28
|
+
end
|
@@ -0,0 +1,31 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# LDXP -- A64
|
4
|
+
# Load Exclusive Pair of Registers
|
5
|
+
# LDXP <Wt1>, <Wt2>, [<Xn|SP>{,#0}]
|
6
|
+
# LDXP <Xt1>, <Xt2>, [<Xn|SP>{,#0}]
|
7
|
+
class LDXP
|
8
|
+
def initialize rt, rt2, rn, sz
|
9
|
+
@rt = rt
|
10
|
+
@rt2 = rt2
|
11
|
+
@rn = rn
|
12
|
+
@sz = sz
|
13
|
+
end
|
14
|
+
|
15
|
+
def encode
|
16
|
+
self.LDXP(@sz, @rt2.to_i, @rn.to_i, @rt.to_i)
|
17
|
+
end
|
18
|
+
|
19
|
+
private
|
20
|
+
|
21
|
+
def LDXP sz, rt2, rn, rt
|
22
|
+
insn = 0b1_0_001000_0_1_1_11111_0_00000_00000_00000
|
23
|
+
insn |= ((sz & 0x1) << 30)
|
24
|
+
insn |= ((rt2 & 0x1f) << 10)
|
25
|
+
insn |= ((rn & 0x1f) << 5)
|
26
|
+
insn |= (rt & 0x1f)
|
27
|
+
insn
|
28
|
+
end
|
29
|
+
end
|
30
|
+
end
|
31
|
+
end
|
@@ -0,0 +1,29 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# LDXR -- A64
|
4
|
+
# Load Exclusive Register
|
5
|
+
# LDXR <Wt>, [<Xn|SP>{,#0}]
|
6
|
+
# LDXR <Xt>, [<Xn|SP>{,#0}]
|
7
|
+
class LDXR
|
8
|
+
def initialize rt, rn, size
|
9
|
+
@rt = rt
|
10
|
+
@rn = rn
|
11
|
+
@size = size
|
12
|
+
end
|
13
|
+
|
14
|
+
def encode
|
15
|
+
self.LDXR(@size, @rn.to_i, @rt.to_i)
|
16
|
+
end
|
17
|
+
|
18
|
+
private
|
19
|
+
|
20
|
+
def LDXR size, rn, rt
|
21
|
+
insn = 0b00_001000_0_1_0_11111_0_11111_00000_00000
|
22
|
+
insn |= ((size & 0x3) << 30)
|
23
|
+
insn |= ((rn & 0x1f) << 5)
|
24
|
+
insn |= (rt & 0x1f)
|
25
|
+
insn
|
26
|
+
end
|
27
|
+
end
|
28
|
+
end
|
29
|
+
end
|
@@ -0,0 +1,31 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# LSLV -- A64
|
4
|
+
# Logical Shift Left Variable
|
5
|
+
# LSLV <Wd>, <Wn>, <Wm>
|
6
|
+
# LSLV <Xd>, <Xn>, <Xm>
|
7
|
+
class LSLV
|
8
|
+
def initialize rd, rn, rm, sf
|
9
|
+
@rd = rd
|
10
|
+
@rn = rn
|
11
|
+
@rm = rm
|
12
|
+
@sf = sf
|
13
|
+
end
|
14
|
+
|
15
|
+
def encode
|
16
|
+
self.LSLV(@sf, @rm.to_i, @rn.to_i, @rd.to_i)
|
17
|
+
end
|
18
|
+
|
19
|
+
private
|
20
|
+
|
21
|
+
def LSLV sf, rm, rn, rd
|
22
|
+
insn = 0b0_0_0_11010110_00000_0010_00_00000_00000
|
23
|
+
insn |= ((sf & 0x1) << 31)
|
24
|
+
insn |= ((rm & 0x1f) << 16)
|
25
|
+
insn |= ((rn & 0x1f) << 5)
|
26
|
+
insn |= (rd & 0x1f)
|
27
|
+
insn
|
28
|
+
end
|
29
|
+
end
|
30
|
+
end
|
31
|
+
end
|
@@ -0,0 +1,31 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# LSRV -- A64
|
4
|
+
# Logical Shift Right Variable
|
5
|
+
# LSRV <Wd>, <Wn>, <Wm>
|
6
|
+
# LSRV <Xd>, <Xn>, <Xm>
|
7
|
+
class LSRV
|
8
|
+
def initialize rd, rn, rm, sf
|
9
|
+
@rd = rd
|
10
|
+
@rn = rn
|
11
|
+
@rm = rm
|
12
|
+
@sf = sf
|
13
|
+
end
|
14
|
+
|
15
|
+
def encode
|
16
|
+
self.LSRV(@sf, @rm.to_i, @rn.to_i, @rd.to_i)
|
17
|
+
end
|
18
|
+
|
19
|
+
private
|
20
|
+
|
21
|
+
def LSRV sf, rm, rn, rd
|
22
|
+
insn = 0b0_0_0_11010110_00000_0010_01_00000_00000
|
23
|
+
insn |= ((sf & 0x1) << 31)
|
24
|
+
insn |= ((rm & 0x1f) << 16)
|
25
|
+
insn |= ((rn & 0x1f) << 5)
|
26
|
+
insn |= (rd & 0x1f)
|
27
|
+
insn
|
28
|
+
end
|
29
|
+
end
|
30
|
+
end
|
31
|
+
end
|
@@ -0,0 +1,33 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# MADD -- A64
|
4
|
+
# Multiply-Add
|
5
|
+
# MADD <Wd>, <Wn>, <Wm>, <Wa>
|
6
|
+
# MADD <Xd>, <Xn>, <Xm>, <Xa>
|
7
|
+
class MADD
|
8
|
+
def initialize rd, rn, rm, ra, sf
|
9
|
+
@rd = rd
|
10
|
+
@rn = rn
|
11
|
+
@rm = rm
|
12
|
+
@ra = ra
|
13
|
+
@sf = sf
|
14
|
+
end
|
15
|
+
|
16
|
+
def encode
|
17
|
+
self.MADD(@sf, @rm.to_i, @ra.to_i, @rn.to_i, @rd.to_i)
|
18
|
+
end
|
19
|
+
|
20
|
+
private
|
21
|
+
|
22
|
+
def MADD sf, rm, ra, rn, rd
|
23
|
+
insn = 0b0_00_11011_000_00000_0_00000_00000_00000
|
24
|
+
insn |= ((sf & 0x1) << 31)
|
25
|
+
insn |= ((rm & 0x1f) << 16)
|
26
|
+
insn |= ((ra & 0x1f) << 10)
|
27
|
+
insn |= ((rn & 0x1f) << 5)
|
28
|
+
insn |= (rd & 0x1f)
|
29
|
+
insn
|
30
|
+
end
|
31
|
+
end
|
32
|
+
end
|
33
|
+
end
|
@@ -0,0 +1,31 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# MOVK -- A64
|
4
|
+
# Move wide with keep
|
5
|
+
# MOVK <Wd>, #<imm>{, LSL #<shift>}
|
6
|
+
# MOVK <Xd>, #<imm>{, LSL #<shift>}
|
7
|
+
class MOVK
|
8
|
+
def initialize reg, imm, shift, sf
|
9
|
+
@reg = reg
|
10
|
+
@imm = imm
|
11
|
+
@shift = shift
|
12
|
+
@sf = sf
|
13
|
+
end
|
14
|
+
|
15
|
+
def encode
|
16
|
+
MOVK(@sf, @shift, @imm, @reg.to_i)
|
17
|
+
end
|
18
|
+
|
19
|
+
private
|
20
|
+
|
21
|
+
def MOVK sf, hw, imm16, rd
|
22
|
+
insn = 0b0_11_100101_00_0000000000000000_00000
|
23
|
+
insn |= ((sf & 0x1) << 31)
|
24
|
+
insn |= ((hw & 0x3) << 21)
|
25
|
+
insn |= ((imm16 & 0xffff) << 5)
|
26
|
+
insn |= (rd & 0x1f)
|
27
|
+
insn
|
28
|
+
end
|
29
|
+
end
|
30
|
+
end
|
31
|
+
end
|
@@ -0,0 +1,31 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# MOVN -- A64
|
4
|
+
# Move wide with NOT
|
5
|
+
# MOVN <Wd>, #<imm>{, LSL #<shift>}
|
6
|
+
# MOVN <Xd>, #<imm>{, LSL #<shift>}
|
7
|
+
class MOVN
|
8
|
+
def initialize rd, imm16, hw, sf
|
9
|
+
@rd = rd
|
10
|
+
@imm16 = imm16
|
11
|
+
@hw = hw
|
12
|
+
@sf = sf
|
13
|
+
end
|
14
|
+
|
15
|
+
def encode
|
16
|
+
self.MOVN(@sf, @hw, @imm16, @rd.to_i)
|
17
|
+
end
|
18
|
+
|
19
|
+
private
|
20
|
+
|
21
|
+
def MOVN sf, hw, imm16, rd
|
22
|
+
insn = 0b0_00_100101_00_0000000000000000_00000
|
23
|
+
insn |= ((sf & 0x1) << 31)
|
24
|
+
insn |= ((hw & 0x3) << 21)
|
25
|
+
insn |= ((imm16 & 0xffff) << 5)
|
26
|
+
insn |= (rd & 0x1f)
|
27
|
+
insn
|
28
|
+
end
|
29
|
+
end
|
30
|
+
end
|
31
|
+
end
|
@@ -0,0 +1,31 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# MOVZ -- A64
|
4
|
+
# Move wide with zero
|
5
|
+
# MOVZ <Wd>, #<imm>{, LSL #<shift>}
|
6
|
+
# MOVZ <Xd>, #<imm>{, LSL #<shift>}
|
7
|
+
class MOVZ
|
8
|
+
def initialize reg, imm, shift, sf
|
9
|
+
@reg = reg
|
10
|
+
@imm = imm
|
11
|
+
@shift = shift
|
12
|
+
@sf = sf
|
13
|
+
end
|
14
|
+
|
15
|
+
def encode
|
16
|
+
MOVZ(@sf, @shift, @imm, @reg.to_i)
|
17
|
+
end
|
18
|
+
|
19
|
+
private
|
20
|
+
|
21
|
+
def MOVZ sf, hw, imm16, rd
|
22
|
+
insn = 0b0_10_100101_00_0000000000000000_00000
|
23
|
+
insn |= ((sf & 0x1) << 31)
|
24
|
+
insn |= ((hw & 0x3) << 21)
|
25
|
+
insn |= ((imm16 & 0xffff) << 5)
|
26
|
+
insn |= (rd & 0x1f)
|
27
|
+
insn
|
28
|
+
end
|
29
|
+
end
|
30
|
+
end
|
31
|
+
end
|
@@ -0,0 +1,34 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# MRS -- A64
|
4
|
+
# Move System Register
|
5
|
+
# MRS <Xt>, (<systemreg>|S<op0>_<op1>_<Cn>_<Cm>_<op2>)
|
6
|
+
class MRS
|
7
|
+
def initialize o0, op1, crn, crm, op2, rt
|
8
|
+
@o0 = o0
|
9
|
+
@op1 = op1
|
10
|
+
@crn = crn
|
11
|
+
@crm = crm
|
12
|
+
@op2 = op2
|
13
|
+
@rt = rt
|
14
|
+
end
|
15
|
+
|
16
|
+
def encode
|
17
|
+
self.MRS(@o0, @op1, @crn, @crm, @op2, @rt.to_i)
|
18
|
+
end
|
19
|
+
|
20
|
+
private
|
21
|
+
|
22
|
+
def MRS o0, op1, crn, crm, op2, rt
|
23
|
+
insn = 0b1101010100_1_1_0_000_0000_0000_000_00000
|
24
|
+
insn |= ((o0 & 0x1) << 19)
|
25
|
+
insn |= ((op1 & 0x7) << 16)
|
26
|
+
insn |= ((crn & 0xf) << 12)
|
27
|
+
insn |= ((crm & 0xf) << 8)
|
28
|
+
insn |= ((op2 & 0x7) << 5)
|
29
|
+
insn |= (rt & 0x1f)
|
30
|
+
insn
|
31
|
+
end
|
32
|
+
end
|
33
|
+
end
|
34
|
+
end
|
@@ -0,0 +1,28 @@
|
|
1
|
+
module AArch64
|
2
|
+
module Instructions
|
3
|
+
# MSR (immediate) -- A64
|
4
|
+
# Move immediate value to Special Register
|
5
|
+
# MSR <pstatefield>, #<imm>
|
6
|
+
class MSR_imm
|
7
|
+
def initialize op1, crm, op2
|
8
|
+
@op1 = op1
|
9
|
+
@crm = crm
|
10
|
+
@op2 = op2
|
11
|
+
end
|
12
|
+
|
13
|
+
def encode
|
14
|
+
self.MSR_imm(@op1, @crm, @op2)
|
15
|
+
end
|
16
|
+
|
17
|
+
private
|
18
|
+
|
19
|
+
def MSR_imm op1, crm, op2
|
20
|
+
insn = 0b1101010100_0_00_000_0100_0000_000_11111
|
21
|
+
insn |= ((op1 & 0x7) << 16)
|
22
|
+
insn |= ((crm & 0xf) << 8)
|
23
|
+
insn |= ((op2 & 0x7) << 5)
|
24
|
+
insn
|
25
|
+
end
|
26
|
+
end
|
27
|
+
end
|
28
|
+
end
|