aarch64 1.0.0

data/lib/aarch64/instructions/ldumax.rb

@@ -0,0 +1,41 @@
+module AArch64
+  module Instructions
+    # LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL -- A64
+    # Atomic unsigned maximum on word or doubleword in memory
+    # LDUMAX  <Ws>, <Wt>, [<Xn|SP>]
+    # LDUMAXA  <Ws>, <Wt>, [<Xn|SP>]
+    # LDUMAXAL  <Ws>, <Wt>, [<Xn|SP>]
+    # LDUMAXL  <Ws>, <Wt>, [<Xn|SP>]
+    # LDUMAX  <Xs>, <Xt>, [<Xn|SP>]
+    # LDUMAXA  <Xs>, <Xt>, [<Xn|SP>]
+    # LDUMAXAL  <Xs>, <Xt>, [<Xn|SP>]
+    # LDUMAXL  <Xs>, <Xt>, [<Xn|SP>]
+    class LDUMAX
+      def initialize rs, rt, rn, size, a, r
+        @rs   = rs
+        @rt   = rt
+        @rn   = rn
+        @size = size
+        @a    = a
+        @r    = r
+      end
+
+      def encode
+        self.LDUMAX(@size, @a, @r.to_i, @rs.to_i, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def LDUMAX size, a, r, rs, rn, rt
+        insn = 0b00_111_0_00_0_0_1_00000_0_110_00_00000_00000
+        insn |= ((size & 0x3) << 30)
+        insn |= ((a & 0x1) << 23)
+        insn |= ((r & 0x1) << 22)
+        insn |= ((rs & 0x1f) << 16)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/ldumaxb.rb

@@ -0,0 +1,35 @@
+module AArch64
+  module Instructions
+    # LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLB -- A64
+    # Atomic unsigned maximum on byte in memory
+    # LDUMAXAB  <Ws>, <Wt>, [<Xn|SP>]
+    # LDUMAXALB  <Ws>, <Wt>, [<Xn|SP>]
+    # LDUMAXB  <Ws>, <Wt>, [<Xn|SP>]
+    # LDUMAXLB  <Ws>, <Wt>, [<Xn|SP>]
+    class LDUMAXB
+      def initialize rs, rt, rn, a, r
+        @rs = rs
+        @rt = rt
+        @rn = rn
+        @a  = a
+        @r  = r
+      end
+
+      def encode
+        self.LDUMAXB(@a, @r.to_i, @rs.to_i, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def LDUMAXB a, r, rs, rn, rt
+        insn = 0b00_111_0_00_0_0_1_00000_0_110_00_00000_00000
+        insn |= ((a & 0x1) << 23)
+        insn |= ((r & 0x1) << 22)
+        insn |= ((rs & 0x1f) << 16)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/ldumaxh.rb

@@ -0,0 +1,35 @@
+module AArch64
+  module Instructions
+    # LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLH -- A64
+    # Atomic unsigned maximum on halfword in memory
+    # LDUMAXAH  <Ws>, <Wt>, [<Xn|SP>]
+    # LDUMAXALH  <Ws>, <Wt>, [<Xn|SP>]
+    # LDUMAXH  <Ws>, <Wt>, [<Xn|SP>]
+    # LDUMAXLH  <Ws>, <Wt>, [<Xn|SP>]
+    class LDUMAXH
+      def initialize rs, rt, rn, a, r
+        @rs = rs
+        @rt = rt
+        @rn = rn
+        @a  = a
+        @r  = r
+      end
+
+      def encode
+        self.LDUMAXH(@a, @r.to_i, @rs.to_i, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def LDUMAXH a, r, rs, rn, rt
+        insn = 0b01_111_0_00_0_0_1_00000_0_110_00_00000_00000
+        insn |= ((a & 0x1) << 23)
+        insn |= ((r & 0x1) << 22)
+        insn |= ((rs & 0x1f) << 16)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/ldumin.rb

@@ -0,0 +1,41 @@
+module AArch64
+  module Instructions
+    # LDUMIN, LDUMINA, LDUMINAL, LDUMINL -- A64
+    # Atomic unsigned minimum on word or doubleword in memory
+    # LDUMIN  <Ws>, <Wt>, [<Xn|SP>]
+    # LDUMINA  <Ws>, <Wt>, [<Xn|SP>]
+    # LDUMINAL  <Ws>, <Wt>, [<Xn|SP>]
+    # LDUMINL  <Ws>, <Wt>, [<Xn|SP>]
+    # LDUMIN  <Xs>, <Xt>, [<Xn|SP>]
+    # LDUMINA  <Xs>, <Xt>, [<Xn|SP>]
+    # LDUMINAL  <Xs>, <Xt>, [<Xn|SP>]
+    # LDUMINL  <Xs>, <Xt>, [<Xn|SP>]
+    class LDUMIN
+      def initialize rs, rt, rn, size, a, r
+        @rs   = rs
+        @rt   = rt
+        @rn   = rn
+        @size = size
+        @a    = a
+        @r    = r
+      end
+
+      def encode
+        self.LDUMIN(@size, @a, @r.to_i, @rs.to_i, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def LDUMIN size, a, r, rs, rn, rt
+        insn = 0b00_111_0_00_0_0_1_00000_0_111_00_00000_00000
+        insn |= ((size & 0x3) << 30)
+        insn |= ((a & 0x1) << 23)
+        insn |= ((r & 0x1) << 22)
+        insn |= ((rs & 0x1f) << 16)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/lduminb.rb

@@ -0,0 +1,35 @@
+module AArch64
+  module Instructions
+    # LDUMINB, LDUMINAB, LDUMINALB, LDUMINLB -- A64
+    # Atomic unsigned minimum on byte in memory
+    # LDUMINAB  <Ws>, <Wt>, [<Xn|SP>]
+    # LDUMINALB  <Ws>, <Wt>, [<Xn|SP>]
+    # LDUMINB  <Ws>, <Wt>, [<Xn|SP>]
+    # LDUMINLB  <Ws>, <Wt>, [<Xn|SP>]
+    class LDUMINB
+      def initialize rs, rt, rn, a, r
+        @rs = rs
+        @rt = rt
+        @rn = rn
+        @a  = a
+        @r  = r
+      end
+
+      def encode
+        self.LDUMINB(@a, @r.to_i, @rs.to_i, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def LDUMINB a, r, rs, rn, rt
+        insn = 0b00_111_0_00_0_0_1_00000_0_111_00_00000_00000
+        insn |= ((a & 0x1) << 23)
+        insn |= ((r & 0x1) << 22)
+        insn |= ((rs & 0x1f) << 16)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/lduminh.rb

@@ -0,0 +1,35 @@
+module AArch64
+  module Instructions
+    # LDUMINH, LDUMINAH, LDUMINALH, LDUMINLH -- A64
+    # Atomic unsigned minimum on halfword in memory
+    # LDUMINAH  <Ws>, <Wt>, [<Xn|SP>]
+    # LDUMINALH  <Ws>, <Wt>, [<Xn|SP>]
+    # LDUMINH  <Ws>, <Wt>, [<Xn|SP>]
+    # LDUMINLH  <Ws>, <Wt>, [<Xn|SP>]
+    class LDUMINH
+      def initialize rs, rt, rn, a, r
+        @rs = rs
+        @rt = rt
+        @rn = rn
+        @a  = a
+        @r  = r
+      end
+
+      def encode
+        self.LDUMINH(@a, @r.to_i, @rs.to_i, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def LDUMINH a, r, rs, rn, rt
+        insn = 0b01_111_0_00_0_0_1_00000_0_111_00_00000_00000
+        insn |= ((a & 0x1) << 23)
+        insn |= ((r & 0x1) << 22)
+        insn |= ((rs & 0x1f) << 16)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/ldur_gen.rb

@@ -0,0 +1,31 @@
+module AArch64
+  module Instructions
+    # LDUR -- A64
+    # Load Register (unscaled)
+    # LDUR  <Wt>, [<Xn|SP>{, #<simm>}]
+    # LDUR  <Xt>, [<Xn|SP>{, #<simm>}]
+    class LDUR_gen
+      def initialize rt, rn, imm9, size
+        @rt   = rt
+        @rn   = rn
+        @imm9 = imm9
+        @size = size
+      end
+
+      def encode
+        self.LDUR_gen(@size, @imm9, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def LDUR_gen size, imm9, rn, rt
+        insn = 0b00_111_0_00_01_0_000000000_00_00000_00000
+        insn |= ((size & 0x3) << 30)
+        insn |= ((imm9 & 0x1ff) << 12)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/ldursb.rb

@@ -0,0 +1,31 @@
+module AArch64
+  module Instructions
+    # LDURSB -- A64
+    # Load Register Signed Byte (unscaled)
+    # LDURSB  <Wt>, [<Xn|SP>{, #<simm>}]
+    # LDURSB  <Xt>, [<Xn|SP>{, #<simm>}]
+    class LDURSB
+      def initialize rt, rn, imm9, opc
+        @rt   = rt
+        @rn   = rn
+        @imm9 = imm9
+        @opc  = opc
+      end
+
+      def encode
+        self.LDURSB(@opc, @imm9, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def LDURSB opc, imm9, rn, rt
+        insn = 0b00_111_0_00_00_0_000000000_00_00000_00000
+        insn |= ((opc & 0x3) << 22)
+        insn |= ((imm9 & 0x1ff) << 12)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/ldursh.rb

@@ -0,0 +1,31 @@
+module AArch64
+  module Instructions
+    # LDURSH -- A64
+    # Load Register Signed Halfword (unscaled)
+    # LDURSH  <Wt>, [<Xn|SP>{, #<simm>}]
+    # LDURSH  <Xt>, [<Xn|SP>{, #<simm>}]
+    class LDURSH
+      def initialize rt, rn, imm9, opc
+        @rt   = rt
+        @rn   = rn
+        @imm9 = imm9
+        @opc  = opc
+      end
+
+      def encode
+        self.LDURSH(@opc, @imm9, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def LDURSH opc, imm9, rn, rt
+        insn = 0b01_111_0_00_00_0_000000000_00_00000_00000
+        insn |= ((opc & 0x3) << 22)
+        insn |= ((imm9 & 0x1ff) << 12)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/ldursw.rb

@@ -0,0 +1,28 @@
+module AArch64
+  module Instructions
+    # LDURSW -- A64
+    # Load Register Signed Word (unscaled)
+    # LDURSW  <Xt>, [<Xn|SP>{, #<simm>}]
+    class LDURSW
+      def initialize rt, rn, imm9
+        @rt   = rt
+        @rn   = rn
+        @imm9 = imm9
+      end
+
+      def encode
+        self.LDURSW(@imm9, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def LDURSW imm9, rn, rt
+        insn = 0b10_111_0_00_10_0_000000000_00_00000_00000
+        insn |= ((imm9 & 0x1ff) << 12)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/ldxp.rb

@@ -0,0 +1,31 @@
+module AArch64
+  module Instructions
+    # LDXP -- A64
+    # Load Exclusive Pair of Registers
+    # LDXP  <Wt1>, <Wt2>, [<Xn|SP>{,#0}]
+    # LDXP  <Xt1>, <Xt2>, [<Xn|SP>{,#0}]
+    class LDXP
+      def initialize rt, rt2, rn, sz
+        @rt  = rt
+        @rt2 = rt2
+        @rn  = rn
+        @sz  = sz
+      end
+
+      def encode
+        self.LDXP(@sz, @rt2.to_i, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def LDXP sz, rt2, rn, rt
+        insn = 0b1_0_001000_0_1_1_11111_0_00000_00000_00000
+        insn |= ((sz & 0x1) << 30)
+        insn |= ((rt2 & 0x1f) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/ldxr.rb

@@ -0,0 +1,29 @@
+module AArch64
+  module Instructions
+    # LDXR -- A64
+    # Load Exclusive Register
+    # LDXR  <Wt>, [<Xn|SP>{,#0}]
+    # LDXR  <Xt>, [<Xn|SP>{,#0}]
+    class LDXR
+      def initialize rt, rn, size
+        @rt   = rt
+        @rn   = rn
+        @size = size
+      end
+
+      def encode
+        self.LDXR(@size, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def LDXR size, rn, rt
+        insn = 0b00_001000_0_1_0_11111_0_11111_00000_00000
+        insn |= ((size & 0x3) << 30)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/lslv.rb

@@ -0,0 +1,31 @@
+module AArch64
+  module Instructions
+    # LSLV -- A64
+    # Logical Shift Left Variable
+    # LSLV  <Wd>, <Wn>, <Wm>
+    # LSLV  <Xd>, <Xn>, <Xm>
+    class LSLV
+      def initialize rd, rn, rm, sf
+        @rd = rd
+        @rn = rn
+        @rm = rm
+        @sf = sf
+      end
+
+      def encode
+        self.LSLV(@sf, @rm.to_i, @rn.to_i, @rd.to_i)
+      end
+
+      private
+
+      def LSLV sf, rm, rn, rd
+        insn = 0b0_0_0_11010110_00000_0010_00_00000_00000
+        insn |= ((sf & 0x1) << 31)
+        insn |= ((rm & 0x1f) << 16)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/lsrv.rb

@@ -0,0 +1,31 @@
+module AArch64
+  module Instructions
+    # LSRV -- A64
+    # Logical Shift Right Variable
+    # LSRV  <Wd>, <Wn>, <Wm>
+    # LSRV  <Xd>, <Xn>, <Xm>
+    class LSRV
+      def initialize rd, rn, rm, sf
+        @rd = rd
+        @rn = rn
+        @rm = rm
+        @sf = sf
+      end
+
+      def encode
+        self.LSRV(@sf, @rm.to_i, @rn.to_i, @rd.to_i)
+      end
+
+      private
+
+      def LSRV sf, rm, rn, rd
+        insn = 0b0_0_0_11010110_00000_0010_01_00000_00000
+        insn |= ((sf & 0x1) << 31)
+        insn |= ((rm & 0x1f) << 16)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/madd.rb

@@ -0,0 +1,33 @@
+module AArch64
+  module Instructions
+    # MADD -- A64
+    # Multiply-Add
+    # MADD  <Wd>, <Wn>, <Wm>, <Wa>
+    # MADD  <Xd>, <Xn>, <Xm>, <Xa>
+    class MADD
+      def initialize rd, rn, rm, ra, sf
+        @rd = rd
+        @rn = rn
+        @rm = rm
+        @ra = ra
+        @sf = sf
+      end
+
+      def encode
+        self.MADD(@sf, @rm.to_i, @ra.to_i, @rn.to_i, @rd.to_i)
+      end
+
+      private
+
+      def MADD sf, rm, ra, rn, rd
+        insn = 0b0_00_11011_000_00000_0_00000_00000_00000
+        insn |= ((sf & 0x1) << 31)
+        insn |= ((rm & 0x1f) << 16)
+        insn |= ((ra & 0x1f) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/movk.rb

@@ -0,0 +1,31 @@
+module AArch64
+  module Instructions
+    # MOVK -- A64
+    # Move wide with keep
+    # MOVK  <Wd>, #<imm>{, LSL #<shift>}
+    # MOVK  <Xd>, #<imm>{, LSL #<shift>}
+    class MOVK
+      def initialize reg, imm, shift, sf
+        @reg   = reg
+        @imm   = imm
+        @shift = shift
+        @sf    = sf
+      end
+
+      def encode
+        MOVK(@sf, @shift, @imm, @reg.to_i)
+      end
+
+      private
+
+      def MOVK sf, hw, imm16, rd
+        insn = 0b0_11_100101_00_0000000000000000_00000
+        insn |= ((sf & 0x1) << 31)
+        insn |= ((hw & 0x3) << 21)
+        insn |= ((imm16 & 0xffff) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/movn.rb

@@ -0,0 +1,31 @@
+module AArch64
+  module Instructions
+    # MOVN -- A64
+    # Move wide with NOT
+    # MOVN  <Wd>, #<imm>{, LSL #<shift>}
+    # MOVN  <Xd>, #<imm>{, LSL #<shift>}
+    class MOVN
+      def initialize rd, imm16, hw, sf
+        @rd    = rd
+        @imm16 = imm16
+        @hw    = hw
+        @sf    = sf
+      end
+
+      def encode
+        self.MOVN(@sf, @hw, @imm16, @rd.to_i)
+      end
+
+      private
+
+      def MOVN sf, hw, imm16, rd
+        insn = 0b0_00_100101_00_0000000000000000_00000
+        insn |= ((sf & 0x1) << 31)
+        insn |= ((hw & 0x3) << 21)
+        insn |= ((imm16 & 0xffff) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/movz.rb

@@ -0,0 +1,31 @@
+module AArch64
+  module Instructions
+    # MOVZ -- A64
+    # Move wide with zero
+    # MOVZ  <Wd>, #<imm>{, LSL #<shift>}
+    # MOVZ  <Xd>, #<imm>{, LSL #<shift>}
+    class MOVZ
+      def initialize reg, imm, shift, sf
+        @reg   = reg
+        @imm   = imm
+        @shift = shift
+        @sf    = sf
+      end
+
+      def encode
+        MOVZ(@sf, @shift, @imm, @reg.to_i)
+      end
+
+      private
+
+      def MOVZ sf, hw, imm16, rd
+        insn = 0b0_10_100101_00_0000000000000000_00000
+        insn |= ((sf & 0x1) << 31)
+        insn |= ((hw & 0x3) << 21)
+        insn |= ((imm16 & 0xffff) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/mrs.rb

@@ -0,0 +1,34 @@
+module AArch64
+  module Instructions
+    # MRS -- A64
+    # Move System Register
+    # MRS  <Xt>, (<systemreg>|S<op0>_<op1>_<Cn>_<Cm>_<op2>)
+    class MRS
+      def initialize o0, op1, crn, crm, op2, rt
+        @o0  = o0
+        @op1 = op1
+        @crn = crn
+        @crm = crm
+        @op2 = op2
+        @rt  = rt
+      end
+
+      def encode
+        self.MRS(@o0, @op1, @crn, @crm, @op2, @rt.to_i)
+      end
+
+      private
+
+      def MRS o0, op1, crn, crm, op2, rt
+        insn = 0b1101010100_1_1_0_000_0000_0000_000_00000
+        insn |= ((o0 & 0x1) << 19)
+        insn |= ((op1 & 0x7) << 16)
+        insn |= ((crn & 0xf) << 12)
+        insn |= ((crm & 0xf) << 8)
+        insn |= ((op2 & 0x7) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/msr_imm.rb

@@ -0,0 +1,28 @@
+module AArch64
+  module Instructions
+    # MSR (immediate) -- A64
+    # Move immediate value to Special Register
+    # MSR  <pstatefield>, #<imm>
+    class MSR_imm
+      def initialize op1, crm, op2
+        @op1 = op1
+        @crm = crm
+        @op2 = op2
+      end
+
+      def encode
+        self.MSR_imm(@op1, @crm, @op2)
+      end
+
+      private
+
+      def MSR_imm op1, crm, op2
+        insn = 0b1101010100_0_00_000_0100_0000_000_11111
+        insn |= ((op1 & 0x7) << 16)
+        insn |= ((crm & 0xf) << 8)
+        insn |= ((op2 & 0x7) << 5)
+        insn
+      end
+    end
+  end
+end