aarch64 1.0.0

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Files changed (281) hide show
  1. checksums.yaml +7 -0
  2. data/CODE_OF_CONDUCT.md +77 -0
  3. data/Gemfile +3 -0
  4. data/LICENSE +201 -0
  5. data/README.md +77 -0
  6. data/Rakefile +168 -0
  7. data/aarch64.gemspec +21 -0
  8. data/bin/build_instructions.rb +102 -0
  9. data/lib/aarch64/instructions/adc.rb +31 -0
  10. data/lib/aarch64/instructions/adcs.rb +30 -0
  11. data/lib/aarch64/instructions/add_addsub_ext.rb +35 -0
  12. data/lib/aarch64/instructions/add_addsub_imm.rb +32 -0
  13. data/lib/aarch64/instructions/add_addsub_shift.rb +35 -0
  14. data/lib/aarch64/instructions/addg.rb +30 -0
  15. data/lib/aarch64/instructions/adds_addsub_ext.rb +35 -0
  16. data/lib/aarch64/instructions/adds_addsub_imm.rb +33 -0
  17. data/lib/aarch64/instructions/adds_addsub_shift.rb +35 -0
  18. data/lib/aarch64/instructions/adr.rb +28 -0
  19. data/lib/aarch64/instructions/adrp.rb +28 -0
  20. data/lib/aarch64/instructions/and_log_imm.rb +35 -0
  21. data/lib/aarch64/instructions/and_log_shift.rb +35 -0
  22. data/lib/aarch64/instructions/ands_log_imm.rb +35 -0
  23. data/lib/aarch64/instructions/ands_log_shift.rb +35 -0
  24. data/lib/aarch64/instructions/asrv.rb +31 -0
  25. data/lib/aarch64/instructions/autda.rb +32 -0
  26. data/lib/aarch64/instructions/autdb.rb +32 -0
  27. data/lib/aarch64/instructions/autia.rb +35 -0
  28. data/lib/aarch64/instructions/autib.rb +35 -0
  29. data/lib/aarch64/instructions/axflag.rb +18 -0
  30. data/lib/aarch64/instructions/b_cond.rb +26 -0
  31. data/lib/aarch64/instructions/b_uncond.rb +24 -0
  32. data/lib/aarch64/instructions/bc_cond.rb +26 -0
  33. data/lib/aarch64/instructions/bfm.rb +34 -0
  34. data/lib/aarch64/instructions/bic_log_shift.rb +35 -0
  35. data/lib/aarch64/instructions/bics.rb +35 -0
  36. data/lib/aarch64/instructions/bl.rb +24 -0
  37. data/lib/aarch64/instructions/blr.rb +24 -0
  38. data/lib/aarch64/instructions/blra.rb +33 -0
  39. data/lib/aarch64/instructions/br.rb +24 -0
  40. data/lib/aarch64/instructions/bra.rb +33 -0
  41. data/lib/aarch64/instructions/brk.rb +24 -0
  42. data/lib/aarch64/instructions/bti.rb +24 -0
  43. data/lib/aarch64/instructions/cas.rb +41 -0
  44. data/lib/aarch64/instructions/casb.rb +35 -0
  45. data/lib/aarch64/instructions/cash.rb +35 -0
  46. data/lib/aarch64/instructions/casp.rb +41 -0
  47. data/lib/aarch64/instructions/cbnz.rb +29 -0
  48. data/lib/aarch64/instructions/cbz.rb +29 -0
  49. data/lib/aarch64/instructions/ccmn_imm.rb +33 -0
  50. data/lib/aarch64/instructions/ccmn_reg.rb +33 -0
  51. data/lib/aarch64/instructions/ccmp_imm.rb +33 -0
  52. data/lib/aarch64/instructions/ccmp_reg.rb +33 -0
  53. data/lib/aarch64/instructions/cfinv.rb +19 -0
  54. data/lib/aarch64/instructions/clrex.rb +24 -0
  55. data/lib/aarch64/instructions/cls_int.rb +29 -0
  56. data/lib/aarch64/instructions/clz_int.rb +29 -0
  57. data/lib/aarch64/instructions/crc32.rb +35 -0
  58. data/lib/aarch64/instructions/crc32c.rb +35 -0
  59. data/lib/aarch64/instructions/csdb.rb +19 -0
  60. data/lib/aarch64/instructions/csel.rb +33 -0
  61. data/lib/aarch64/instructions/csinc.rb +33 -0
  62. data/lib/aarch64/instructions/csinv.rb +33 -0
  63. data/lib/aarch64/instructions/csneg.rb +33 -0
  64. data/lib/aarch64/instructions/dcps.rb +26 -0
  65. data/lib/aarch64/instructions/dgh.rb +19 -0
  66. data/lib/aarch64/instructions/dmb.rb +24 -0
  67. data/lib/aarch64/instructions/drps.rb +19 -0
  68. data/lib/aarch64/instructions/dsb.rb +25 -0
  69. data/lib/aarch64/instructions/eon.rb +35 -0
  70. data/lib/aarch64/instructions/eor_log_imm.rb +35 -0
  71. data/lib/aarch64/instructions/eor_log_shift.rb +35 -0
  72. data/lib/aarch64/instructions/eret.rb +19 -0
  73. data/lib/aarch64/instructions/ereta.rb +25 -0
  74. data/lib/aarch64/instructions/esb.rb +19 -0
  75. data/lib/aarch64/instructions/extr.rb +34 -0
  76. data/lib/aarch64/instructions/gmi.rb +28 -0
  77. data/lib/aarch64/instructions/hint.rb +26 -0
  78. data/lib/aarch64/instructions/hlt.rb +24 -0
  79. data/lib/aarch64/instructions/hvc.rb +24 -0
  80. data/lib/aarch64/instructions/irg.rb +28 -0
  81. data/lib/aarch64/instructions/isb.rb +24 -0
  82. data/lib/aarch64/instructions/ld64b.rb +26 -0
  83. data/lib/aarch64/instructions/ldadd.rb +41 -0
  84. data/lib/aarch64/instructions/ldaddb.rb +35 -0
  85. data/lib/aarch64/instructions/ldaddh.rb +35 -0
  86. data/lib/aarch64/instructions/ldapr.rb +29 -0
  87. data/lib/aarch64/instructions/ldaprb.rb +26 -0
  88. data/lib/aarch64/instructions/ldaprh.rb +26 -0
  89. data/lib/aarch64/instructions/ldapur_gen.rb +33 -0
  90. data/lib/aarch64/instructions/ldar.rb +29 -0
  91. data/lib/aarch64/instructions/ldaxp.rb +31 -0
  92. data/lib/aarch64/instructions/ldaxr.rb +29 -0
  93. data/lib/aarch64/instructions/ldclr.rb +41 -0
  94. data/lib/aarch64/instructions/ldclrb.rb +37 -0
  95. data/lib/aarch64/instructions/ldeor.rb +41 -0
  96. data/lib/aarch64/instructions/ldg.rb +28 -0
  97. data/lib/aarch64/instructions/ldgm.rb +26 -0
  98. data/lib/aarch64/instructions/ldlar.rb +29 -0
  99. data/lib/aarch64/instructions/ldnp_gen.rb +33 -0
  100. data/lib/aarch64/instructions/ldp_gen.rb +39 -0
  101. data/lib/aarch64/instructions/ldpsw.rb +34 -0
  102. data/lib/aarch64/instructions/ldr_imm_gen.rb +35 -0
  103. data/lib/aarch64/instructions/ldr_imm_unsigned.rb +31 -0
  104. data/lib/aarch64/instructions/ldr_lit_gen.rb +29 -0
  105. data/lib/aarch64/instructions/ldr_reg_gen.rb +35 -0
  106. data/lib/aarch64/instructions/ldra.rb +37 -0
  107. data/lib/aarch64/instructions/ldrb_imm.rb +32 -0
  108. data/lib/aarch64/instructions/ldrb_reg.rb +33 -0
  109. data/lib/aarch64/instructions/ldrb_unsigned.rb +28 -0
  110. data/lib/aarch64/instructions/ldrh_imm.rb +32 -0
  111. data/lib/aarch64/instructions/ldrh_reg.rb +32 -0
  112. data/lib/aarch64/instructions/ldrh_unsigned.rb +28 -0
  113. data/lib/aarch64/instructions/ldrsb_imm.rb +37 -0
  114. data/lib/aarch64/instructions/ldrsb_reg.rb +37 -0
  115. data/lib/aarch64/instructions/ldrsb_unsigned.rb +35 -0
  116. data/lib/aarch64/instructions/ldrsh_imm.rb +37 -0
  117. data/lib/aarch64/instructions/ldrsh_reg.rb +35 -0
  118. data/lib/aarch64/instructions/ldrsh_unsigned.rb +31 -0
  119. data/lib/aarch64/instructions/ldrsw_imm.rb +32 -0
  120. data/lib/aarch64/instructions/ldrsw_lit.rb +26 -0
  121. data/lib/aarch64/instructions/ldrsw_reg.rb +32 -0
  122. data/lib/aarch64/instructions/ldrsw_unsigned.rb +30 -0
  123. data/lib/aarch64/instructions/ldset.rb +41 -0
  124. data/lib/aarch64/instructions/ldsetb.rb +35 -0
  125. data/lib/aarch64/instructions/ldseth.rb +35 -0
  126. data/lib/aarch64/instructions/ldsmax.rb +41 -0
  127. data/lib/aarch64/instructions/ldsmaxb.rb +35 -0
  128. data/lib/aarch64/instructions/ldsmaxh.rb +35 -0
  129. data/lib/aarch64/instructions/ldsmin.rb +41 -0
  130. data/lib/aarch64/instructions/ldsminb.rb +35 -0
  131. data/lib/aarch64/instructions/ldsminh.rb +35 -0
  132. data/lib/aarch64/instructions/ldtr.rb +31 -0
  133. data/lib/aarch64/instructions/ldtrb.rb +28 -0
  134. data/lib/aarch64/instructions/ldtrh.rb +28 -0
  135. data/lib/aarch64/instructions/ldtrsb.rb +31 -0
  136. data/lib/aarch64/instructions/ldtrsh.rb +31 -0
  137. data/lib/aarch64/instructions/ldtrsw.rb +28 -0
  138. data/lib/aarch64/instructions/ldumax.rb +41 -0
  139. data/lib/aarch64/instructions/ldumaxb.rb +35 -0
  140. data/lib/aarch64/instructions/ldumaxh.rb +35 -0
  141. data/lib/aarch64/instructions/ldumin.rb +41 -0
  142. data/lib/aarch64/instructions/lduminb.rb +35 -0
  143. data/lib/aarch64/instructions/lduminh.rb +35 -0
  144. data/lib/aarch64/instructions/ldur_gen.rb +31 -0
  145. data/lib/aarch64/instructions/ldursb.rb +31 -0
  146. data/lib/aarch64/instructions/ldursh.rb +31 -0
  147. data/lib/aarch64/instructions/ldursw.rb +28 -0
  148. data/lib/aarch64/instructions/ldxp.rb +31 -0
  149. data/lib/aarch64/instructions/ldxr.rb +29 -0
  150. data/lib/aarch64/instructions/lslv.rb +31 -0
  151. data/lib/aarch64/instructions/lsrv.rb +31 -0
  152. data/lib/aarch64/instructions/madd.rb +33 -0
  153. data/lib/aarch64/instructions/movk.rb +31 -0
  154. data/lib/aarch64/instructions/movn.rb +31 -0
  155. data/lib/aarch64/instructions/movz.rb +31 -0
  156. data/lib/aarch64/instructions/mrs.rb +34 -0
  157. data/lib/aarch64/instructions/msr_imm.rb +28 -0
  158. data/lib/aarch64/instructions/msr_reg.rb +34 -0
  159. data/lib/aarch64/instructions/msub.rb +33 -0
  160. data/lib/aarch64/instructions/nop.rb +19 -0
  161. data/lib/aarch64/instructions/orn_log_shift.rb +35 -0
  162. data/lib/aarch64/instructions/orr_log_imm.rb +35 -0
  163. data/lib/aarch64/instructions/orr_log_shift.rb +35 -0
  164. data/lib/aarch64/instructions/pacda.rb +29 -0
  165. data/lib/aarch64/instructions/pacdb.rb +29 -0
  166. data/lib/aarch64/instructions/pacga.rb +28 -0
  167. data/lib/aarch64/instructions/pacia.rb +32 -0
  168. data/lib/aarch64/instructions/pacia2.rb +28 -0
  169. data/lib/aarch64/instructions/pacib.rb +32 -0
  170. data/lib/aarch64/instructions/prfm_imm.rb +28 -0
  171. data/lib/aarch64/instructions/prfm_lit.rb +26 -0
  172. data/lib/aarch64/instructions/prfm_reg.rb +32 -0
  173. data/lib/aarch64/instructions/prfum.rb +28 -0
  174. data/lib/aarch64/instructions/psb.rb +19 -0
  175. data/lib/aarch64/instructions/rbit_int.rb +29 -0
  176. data/lib/aarch64/instructions/ret.rb +24 -0
  177. data/lib/aarch64/instructions/reta.rb +25 -0
  178. data/lib/aarch64/instructions/rev.rb +31 -0
  179. data/lib/aarch64/instructions/rmif.rb +28 -0
  180. data/lib/aarch64/instructions/rorv.rb +31 -0
  181. data/lib/aarch64/instructions/sb.rb +19 -0
  182. data/lib/aarch64/instructions/sbc.rb +31 -0
  183. data/lib/aarch64/instructions/sbcs.rb +31 -0
  184. data/lib/aarch64/instructions/sbfm.rb +34 -0
  185. data/lib/aarch64/instructions/sdiv.rb +31 -0
  186. data/lib/aarch64/instructions/setf.rb +27 -0
  187. data/lib/aarch64/instructions/setgp.rb +25 -0
  188. data/lib/aarch64/instructions/setgpn.rb +25 -0
  189. data/lib/aarch64/instructions/setgpt.rb +25 -0
  190. data/lib/aarch64/instructions/setgptn.rb +25 -0
  191. data/lib/aarch64/instructions/setp.rb +25 -0
  192. data/lib/aarch64/instructions/setpn.rb +25 -0
  193. data/lib/aarch64/instructions/setpt.rb +25 -0
  194. data/lib/aarch64/instructions/setptn.rb +25 -0
  195. data/lib/aarch64/instructions/sev.rb +18 -0
  196. data/lib/aarch64/instructions/sevl.rb +18 -0
  197. data/lib/aarch64/instructions/smaddl.rb +30 -0
  198. data/lib/aarch64/instructions/smc.rb +24 -0
  199. data/lib/aarch64/instructions/smsubl.rb +30 -0
  200. data/lib/aarch64/instructions/smulh.rb +28 -0
  201. data/lib/aarch64/instructions/st2g.rb +32 -0
  202. data/lib/aarch64/instructions/st64b.rb +26 -0
  203. data/lib/aarch64/instructions/st64bv.rb +28 -0
  204. data/lib/aarch64/instructions/st64bv0.rb +28 -0
  205. data/lib/aarch64/instructions/stg.rb +32 -0
  206. data/lib/aarch64/instructions/stgm.rb +26 -0
  207. data/lib/aarch64/instructions/stgp.rb +34 -0
  208. data/lib/aarch64/instructions/stllr.rb +29 -0
  209. data/lib/aarch64/instructions/stllrb.rb +26 -0
  210. data/lib/aarch64/instructions/stllrh.rb +26 -0
  211. data/lib/aarch64/instructions/stlr.rb +29 -0
  212. data/lib/aarch64/instructions/stlrb.rb +26 -0
  213. data/lib/aarch64/instructions/stlrh.rb +26 -0
  214. data/lib/aarch64/instructions/stlur_gen.rb +31 -0
  215. data/lib/aarch64/instructions/stlxp.rb +33 -0
  216. data/lib/aarch64/instructions/stlxr.rb +31 -0
  217. data/lib/aarch64/instructions/stlxrb.rb +28 -0
  218. data/lib/aarch64/instructions/stlxrh.rb +28 -0
  219. data/lib/aarch64/instructions/stnp_gen.rb +33 -0
  220. data/lib/aarch64/instructions/stp_gen.rb +39 -0
  221. data/lib/aarch64/instructions/str_imm_gen.rb +37 -0
  222. data/lib/aarch64/instructions/str_imm_unsigned.rb +31 -0
  223. data/lib/aarch64/instructions/str_reg_gen.rb +35 -0
  224. data/lib/aarch64/instructions/strb_imm.rb +32 -0
  225. data/lib/aarch64/instructions/strb_imm_unsigned.rb +28 -0
  226. data/lib/aarch64/instructions/strb_reg.rb +33 -0
  227. data/lib/aarch64/instructions/strh_imm.rb +32 -0
  228. data/lib/aarch64/instructions/strh_imm_unsigned.rb +28 -0
  229. data/lib/aarch64/instructions/strh_reg.rb +32 -0
  230. data/lib/aarch64/instructions/sttr.rb +31 -0
  231. data/lib/aarch64/instructions/stur_gen.rb +31 -0
  232. data/lib/aarch64/instructions/stxp.rb +33 -0
  233. data/lib/aarch64/instructions/stxr.rb +31 -0
  234. data/lib/aarch64/instructions/stxrb.rb +28 -0
  235. data/lib/aarch64/instructions/stxrh.rb +28 -0
  236. data/lib/aarch64/instructions/stz2g.rb +32 -0
  237. data/lib/aarch64/instructions/stzg.rb +32 -0
  238. data/lib/aarch64/instructions/stzgm.rb +26 -0
  239. data/lib/aarch64/instructions/sub_addsub_ext.rb +35 -0
  240. data/lib/aarch64/instructions/sub_addsub_imm.rb +33 -0
  241. data/lib/aarch64/instructions/sub_addsub_shift.rb +35 -0
  242. data/lib/aarch64/instructions/subg.rb +30 -0
  243. data/lib/aarch64/instructions/subp.rb +28 -0
  244. data/lib/aarch64/instructions/subps.rb +28 -0
  245. data/lib/aarch64/instructions/subs_addsub_ext.rb +35 -0
  246. data/lib/aarch64/instructions/subs_addsub_imm.rb +33 -0
  247. data/lib/aarch64/instructions/subs_addsub_shift.rb +35 -0
  248. data/lib/aarch64/instructions/svc.rb +24 -0
  249. data/lib/aarch64/instructions/swp.rb +41 -0
  250. data/lib/aarch64/instructions/swpb.rb +35 -0
  251. data/lib/aarch64/instructions/swph.rb +35 -0
  252. data/lib/aarch64/instructions/sys.rb +32 -0
  253. data/lib/aarch64/instructions/sysl.rb +32 -0
  254. data/lib/aarch64/instructions/tbnz.rb +30 -0
  255. data/lib/aarch64/instructions/tbz.rb +30 -0
  256. data/lib/aarch64/instructions/tsb.rb +18 -0
  257. data/lib/aarch64/instructions/ubfm.rb +34 -0
  258. data/lib/aarch64/instructions/udf_perm_undef.rb +24 -0
  259. data/lib/aarch64/instructions/udiv.rb +31 -0
  260. data/lib/aarch64/instructions/umaddl.rb +30 -0
  261. data/lib/aarch64/instructions/umsubl.rb +30 -0
  262. data/lib/aarch64/instructions/umulh.rb +28 -0
  263. data/lib/aarch64/instructions/wfe.rb +19 -0
  264. data/lib/aarch64/instructions/wfet.rb +24 -0
  265. data/lib/aarch64/instructions/wfi.rb +19 -0
  266. data/lib/aarch64/instructions/wfit.rb +24 -0
  267. data/lib/aarch64/instructions/xaflag.rb +19 -0
  268. data/lib/aarch64/instructions/xpac.rb +28 -0
  269. data/lib/aarch64/instructions/xpaclri.rb +18 -0
  270. data/lib/aarch64/instructions/yield.rb +19 -0
  271. data/lib/aarch64/instructions.rb +266 -0
  272. data/lib/aarch64/system_registers/mrs_msr_64.rb +395 -0
  273. data/lib/aarch64/utils.rb +325 -0
  274. data/lib/aarch64/version.rb +3 -0
  275. data/lib/aarch64.rb +2857 -0
  276. data/test/all_adds_test.rb +129 -0
  277. data/test/base_instructions_test.rb +9263 -0
  278. data/test/dsl_test.rb +11 -0
  279. data/test/helper.rb +51 -0
  280. data/test/not_supported_yet_test.rb +55 -0
  281. metadata +382 -0
@@ -0,0 +1,41 @@
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+ module AArch64
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+ module Instructions
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+ # SWP, SWPA, SWPAL, SWPL -- A64
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+ # Swap word or doubleword in memory
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+ # SWP <Ws>, <Wt>, [<Xn|SP>]
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+ # SWPA <Ws>, <Wt>, [<Xn|SP>]
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+ # SWPAL <Ws>, <Wt>, [<Xn|SP>]
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+ # SWPL <Ws>, <Wt>, [<Xn|SP>]
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+ # SWP <Xs>, <Xt>, [<Xn|SP>]
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+ # SWPA <Xs>, <Xt>, [<Xn|SP>]
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+ # SWPAL <Xs>, <Xt>, [<Xn|SP>]
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+ # SWPL <Xs>, <Xt>, [<Xn|SP>]
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+ class SWP
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+ def initialize rs, rt, rn, size, a, r
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+ @rs = rs
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+ @rt = rt
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+ @rn = rn
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+ @size = size
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+ @a = a
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+ @r = r
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+ end
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+
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+ def encode
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+ self.SWP(@size, @a, @r, @rs.to_i, @rn.to_i, @rt.to_i)
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+ end
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+
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+ private
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+
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+ def SWP size, a, r, rs, rn, rt
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+ insn = 0b00_111_0_00_0_0_1_00000_1_000_00_00000_00000
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+ insn |= ((size & 0x3) << 30)
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+ insn |= ((a & 0x1) << 23)
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+ insn |= ((r & 0x1) << 22)
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+ insn |= ((rs & 0x1f) << 16)
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+ insn |= ((rn & 0x1f) << 5)
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+ insn |= (rt & 0x1f)
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+ insn
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+ end
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+ end
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+ end
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+ end
@@ -0,0 +1,35 @@
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+ module AArch64
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+ module Instructions
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+ # SWPB, SWPAB, SWPALB, SWPLB -- A64
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+ # Swap byte in memory
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+ # SWPAB <Ws>, <Wt>, [<Xn|SP>]
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+ # SWPALB <Ws>, <Wt>, [<Xn|SP>]
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+ # SWPB <Ws>, <Wt>, [<Xn|SP>]
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+ # SWPLB <Ws>, <Wt>, [<Xn|SP>]
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+ class SWPB
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+ def initialize rs, rt, rn, a, r
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+ @rs = rs
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+ @rt = rt
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+ @rn = rn
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+ @a = a
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+ @r = r
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+ end
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+
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+ def encode
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+ self.SWPB(@a, @r, @rs.to_i, @rn.to_i, @rt.to_i)
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+ end
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+
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+ private
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+
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+ def SWPB a, r, rs, rn, rt
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+ insn = 0b00_111_0_00_0_0_1_00000_1_000_00_00000_00000
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+ insn |= ((a & 0x1) << 23)
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+ insn |= ((r & 0x1) << 22)
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+ insn |= ((rs & 0x1f) << 16)
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+ insn |= ((rn & 0x1f) << 5)
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+ insn |= (rt & 0x1f)
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+ insn
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+ end
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+ end
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+ end
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+ end
@@ -0,0 +1,35 @@
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+ module AArch64
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+ module Instructions
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+ # SWPH, SWPAH, SWPALH, SWPLH -- A64
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+ # Swap halfword in memory
5
+ # SWPAH <Ws>, <Wt>, [<Xn|SP>]
6
+ # SWPALH <Ws>, <Wt>, [<Xn|SP>]
7
+ # SWPH <Ws>, <Wt>, [<Xn|SP>]
8
+ # SWPLH <Ws>, <Wt>, [<Xn|SP>]
9
+ class SWPH
10
+ def initialize rs, rt, rn, a, r
11
+ @rs = rs
12
+ @rt = rt
13
+ @rn = rn
14
+ @a = a
15
+ @r = r
16
+ end
17
+
18
+ def encode
19
+ self.SWPH(@a, @r, @rs.to_i, @rn.to_i, @rt.to_i)
20
+ end
21
+
22
+ private
23
+
24
+ def SWPH a, r, rs, rn, rt
25
+ insn = 0b01_111_0_00_0_0_1_00000_1_000_00_00000_00000
26
+ insn |= ((a & 0x1) << 23)
27
+ insn |= ((r & 0x1) << 22)
28
+ insn |= ((rs & 0x1f) << 16)
29
+ insn |= ((rn & 0x1f) << 5)
30
+ insn |= (rt & 0x1f)
31
+ insn
32
+ end
33
+ end
34
+ end
35
+ end
@@ -0,0 +1,32 @@
1
+ module AArch64
2
+ module Instructions
3
+ # SYS -- A64
4
+ # System instruction
5
+ # SYS #<op1>, <Cn>, <Cm>, #<op2>{, <Xt>}
6
+ class SYS
7
+ def initialize op1, cn, cm, op2, xt
8
+ @op1 = op1
9
+ @cn = cn
10
+ @cm = cm
11
+ @op2 = op2
12
+ @xt = xt
13
+ end
14
+
15
+ def encode
16
+ self.SYS(@op1, @cn, @cm, @op2, @xt.to_i)
17
+ end
18
+
19
+ private
20
+
21
+ def SYS op1, crn, crm, op2, rt
22
+ insn = 0b1101010100_0_01_000_0000_0000_000_00000
23
+ insn |= ((op1 & 0x7) << 16)
24
+ insn |= ((crn & 0xf) << 12)
25
+ insn |= ((crm & 0xf) << 8)
26
+ insn |= ((op2 & 0x7) << 5)
27
+ insn |= (rt & 0x1f)
28
+ insn
29
+ end
30
+ end
31
+ end
32
+ end
@@ -0,0 +1,32 @@
1
+ module AArch64
2
+ module Instructions
3
+ # SYSL -- A64
4
+ # System instruction with result
5
+ # SYSL <Xt>, #<op1>, <Cn>, <Cm>, #<op2>
6
+ class SYSL
7
+ def initialize xt, op1, cn, cm, op2
8
+ @xt = xt
9
+ @op1 = op1
10
+ @cn = cn
11
+ @cm = cm
12
+ @op2 = op2
13
+ end
14
+
15
+ def encode
16
+ self.SYSL(@op1, @cn.to_i, @cm.to_i, @op2, @xt.to_i)
17
+ end
18
+
19
+ private
20
+
21
+ def SYSL op1, crn, crm, op2, rt
22
+ insn = 0b1101010100_1_01_000_0000_0000_000_00000
23
+ insn |= ((op1 & 0x7) << 16)
24
+ insn |= ((crn & 0xf) << 12)
25
+ insn |= ((crm & 0xf) << 8)
26
+ insn |= ((op2 & 0x7) << 5)
27
+ insn |= (rt & 0x1f)
28
+ insn
29
+ end
30
+ end
31
+ end
32
+ end
@@ -0,0 +1,30 @@
1
+ module AArch64
2
+ module Instructions
3
+ # TBNZ -- A64
4
+ # Test bit and Branch if Nonzero
5
+ # TBNZ <R><t>, #<imm>, <label>
6
+ class TBNZ
7
+ def initialize rt, imm, label, sf
8
+ @rt = rt
9
+ @imm = imm
10
+ @label = label
11
+ @sf = sf
12
+ end
13
+
14
+ def encode
15
+ self.TBNZ(@sf, @imm, @label.to_i / 4, @rt.to_i)
16
+ end
17
+
18
+ private
19
+
20
+ def TBNZ b5, b40, imm14, rt
21
+ insn = 0b0_011011_1_00000_00000000000000_00000
22
+ insn |= ((b5 & 0x1) << 31)
23
+ insn |= ((b40 & 0x1f) << 19)
24
+ insn |= ((imm14 & 0x3fff) << 5)
25
+ insn |= (rt & 0x1f)
26
+ insn
27
+ end
28
+ end
29
+ end
30
+ end
@@ -0,0 +1,30 @@
1
+ module AArch64
2
+ module Instructions
3
+ # TBZ -- A64
4
+ # Test bit and Branch if Zero
5
+ # TBZ <R><t>, #<imm>, <label>
6
+ class TBZ
7
+ def initialize rt, imm, label, sf
8
+ @rt = rt
9
+ @imm = imm
10
+ @label = label
11
+ @sf = sf
12
+ end
13
+
14
+ def encode
15
+ self.TBZ(@sf, @imm, @label.to_i / 4, @rt.to_i)
16
+ end
17
+
18
+ private
19
+
20
+ def TBZ b5, b40, imm14, rt
21
+ insn = 0b0_011011_0_00000_00000000000000_00000
22
+ insn |= ((b5 & 0x1) << 31)
23
+ insn |= ((b40 & 0x1f) << 19)
24
+ insn |= ((imm14 & 0x3fff) << 5)
25
+ insn |= (rt & 0x1f)
26
+ insn
27
+ end
28
+ end
29
+ end
30
+ end
@@ -0,0 +1,18 @@
1
+ module AArch64
2
+ module Instructions
3
+ # TSB CSYNC -- A64
4
+ # Trace Synchronization Barrier
5
+ # TSB CSYNC
6
+ class TSB
7
+ def encode
8
+ self.TSB
9
+ end
10
+
11
+ private
12
+
13
+ def TSB
14
+ 0b1101010100_0_00_011_0010_0010_010_11111
15
+ end
16
+ end
17
+ end
18
+ end
@@ -0,0 +1,34 @@
1
+ module AArch64
2
+ module Instructions
3
+ # UBFM -- A64
4
+ # Unsigned Bitfield Move
5
+ # UBFM <Wd>, <Wn>, #<immr>, #<imms>
6
+ # UBFM <Xd>, <Xn>, #<immr>, #<imms>
7
+ class UBFM
8
+ def initialize rd, rn, immr, imms, sf
9
+ @rd = rd
10
+ @rn = rn
11
+ @immr = immr
12
+ @imms = imms
13
+ @sf = sf
14
+ end
15
+
16
+ def encode
17
+ self.UBFM(@sf, @sf, @immr, @imms, @rn.to_i, @rd.to_i)
18
+ end
19
+
20
+ private
21
+
22
+ def UBFM sf, n, immr, imms, rn, rd
23
+ insn = 0b0_10_100110_0_000000_000000_00000_00000
24
+ insn |= ((sf & 0x1) << 31)
25
+ insn |= ((n & 0x1) << 22)
26
+ insn |= ((immr & 0x3f) << 16)
27
+ insn |= ((imms & 0x3f) << 10)
28
+ insn |= ((rn & 0x1f) << 5)
29
+ insn |= (rd & 0x1f)
30
+ insn
31
+ end
32
+ end
33
+ end
34
+ end
@@ -0,0 +1,24 @@
1
+ module AArch64
2
+ module Instructions
3
+ # UDF -- A64
4
+ # Permanently Undefined
5
+ # UDF #<imm>
6
+ class UDF_perm_undef
7
+ def initialize imm
8
+ @imm = imm
9
+ end
10
+
11
+ def encode
12
+ self.UDF_perm_undef(@imm)
13
+ end
14
+
15
+ private
16
+
17
+ def UDF_perm_undef imm16
18
+ insn = 0b0000000000000000_0000000000000000
19
+ insn |= (imm16 & 0xffff)
20
+ insn
21
+ end
22
+ end
23
+ end
24
+ end
@@ -0,0 +1,31 @@
1
+ module AArch64
2
+ module Instructions
3
+ # UDIV -- A64
4
+ # Unsigned Divide
5
+ # UDIV <Wd>, <Wn>, <Wm>
6
+ # UDIV <Xd>, <Xn>, <Xm>
7
+ class UDIV
8
+ def initialize rd, rn, rm, sf
9
+ @rd = rd
10
+ @rn = rn
11
+ @rm = rm
12
+ @sf = sf
13
+ end
14
+
15
+ def encode
16
+ self.UDIV(@sf, @rm.to_i, @rn.to_i, @rd.to_i)
17
+ end
18
+
19
+ private
20
+
21
+ def UDIV sf, rm, rn, rd
22
+ insn = 0b0_0_0_11010110_00000_00001_0_00000_00000
23
+ insn |= ((sf & 0x1) << 31)
24
+ insn |= ((rm & 0x1f) << 16)
25
+ insn |= ((rn & 0x1f) << 5)
26
+ insn |= (rd & 0x1f)
27
+ insn
28
+ end
29
+ end
30
+ end
31
+ end
@@ -0,0 +1,30 @@
1
+ module AArch64
2
+ module Instructions
3
+ # UMADDL -- A64
4
+ # Unsigned Multiply-Add Long
5
+ # UMADDL <Xd>, <Wn>, <Wm>, <Xa>
6
+ class UMADDL
7
+ def initialize xd, wn, wm, xa
8
+ @xd = xd
9
+ @wn = wn
10
+ @wm = wm
11
+ @xa = xa
12
+ end
13
+
14
+ def encode
15
+ self.UMADDL(@wm.to_i, @xa.to_i, @wn.to_i, @xd.to_i)
16
+ end
17
+
18
+ private
19
+
20
+ def UMADDL rm, ra, rn, rd
21
+ insn = 0b1_00_11011_1_01_00000_0_00000_00000_00000
22
+ insn |= ((rm & 0x1f) << 16)
23
+ insn |= ((ra & 0x1f) << 10)
24
+ insn |= ((rn & 0x1f) << 5)
25
+ insn |= (rd & 0x1f)
26
+ insn
27
+ end
28
+ end
29
+ end
30
+ end
@@ -0,0 +1,30 @@
1
+ module AArch64
2
+ module Instructions
3
+ # UMSUBL -- A64
4
+ # Unsigned Multiply-Subtract Long
5
+ # UMSUBL <Xd>, <Wn>, <Wm>, <Xa>
6
+ class UMSUBL
7
+ def initialize xd, wn, wm, xa
8
+ @xd = xd
9
+ @wn = wn
10
+ @wm = wm
11
+ @xa = xa
12
+ end
13
+
14
+ def encode
15
+ self.UMSUBL(@wm.to_i, @xa.to_i, @wn.to_i, @xd.to_i)
16
+ end
17
+
18
+ private
19
+
20
+ def UMSUBL rm, ra, rn, rd
21
+ insn = 0b1_00_11011_1_01_00000_1_00000_00000_00000
22
+ insn |= ((rm & 0x1f) << 16)
23
+ insn |= ((ra & 0x1f) << 10)
24
+ insn |= ((rn & 0x1f) << 5)
25
+ insn |= (rd & 0x1f)
26
+ insn
27
+ end
28
+ end
29
+ end
30
+ end
@@ -0,0 +1,28 @@
1
+ module AArch64
2
+ module Instructions
3
+ # UMULH -- A64
4
+ # Unsigned Multiply High
5
+ # UMULH <Xd>, <Xn>, <Xm>
6
+ class UMULH
7
+ def initialize rd, rn, rm
8
+ @rd = rd
9
+ @rn = rn
10
+ @rm = rm
11
+ end
12
+
13
+ def encode
14
+ self.UMULH(@rm.to_i, @rn.to_i, @rd.to_i)
15
+ end
16
+
17
+ private
18
+
19
+ def UMULH rm, rn, rd
20
+ insn = 0b1_00_11011_1_10_00000_0_11111_00000_00000
21
+ insn |= ((rm & 0x1f) << 16)
22
+ insn |= ((rn & 0x1f) << 5)
23
+ insn |= (rd & 0x1f)
24
+ insn
25
+ end
26
+ end
27
+ end
28
+ end
@@ -0,0 +1,19 @@
1
+ module AArch64
2
+ module Instructions
3
+ # WFE -- A64
4
+ # Wait For Event
5
+ # WFE
6
+ class WFE
7
+ def encode
8
+ self.WFE
9
+ end
10
+
11
+ private
12
+
13
+ def WFE
14
+ insn = 0b1101010100_0_00_011_0010_0000_010_11111
15
+ insn
16
+ end
17
+ end
18
+ end
19
+ end
@@ -0,0 +1,24 @@
1
+ module AArch64
2
+ module Instructions
3
+ # WFET -- A64
4
+ # Wait For Event with Timeout
5
+ # WFET <Xt>
6
+ class WFET
7
+ def initialize rd
8
+ @rd = rd
9
+ end
10
+
11
+ def encode
12
+ self.WFET(@rd.to_i)
13
+ end
14
+
15
+ private
16
+
17
+ def WFET rd
18
+ insn = 0b11010101000000110001_0000_000_00000
19
+ insn |= (rd & 0x1f)
20
+ insn
21
+ end
22
+ end
23
+ end
24
+ end
@@ -0,0 +1,19 @@
1
+ module AArch64
2
+ module Instructions
3
+ # WFI -- A64
4
+ # Wait For Interrupt
5
+ # WFI
6
+ class WFI
7
+ def encode
8
+ self.WFI
9
+ end
10
+
11
+ private
12
+
13
+ def WFI
14
+ insn = 0b1101010100_0_00_011_0010_0000_011_11111
15
+ insn
16
+ end
17
+ end
18
+ end
19
+ end
@@ -0,0 +1,24 @@
1
+ module AArch64
2
+ module Instructions
3
+ # WFIT -- A64
4
+ # Wait For Interrupt with Timeout
5
+ # WFIT <Xt>
6
+ class WFIT
7
+ def initialize rd
8
+ @rd = rd
9
+ end
10
+
11
+ def encode
12
+ self.WFIT(@rd.to_i)
13
+ end
14
+
15
+ private
16
+
17
+ def WFIT rd
18
+ insn = 0b11010101000000110001_0000_001_00000
19
+ insn |= (rd & 0x1f)
20
+ insn
21
+ end
22
+ end
23
+ end
24
+ end
@@ -0,0 +1,19 @@
1
+ module AArch64
2
+ module Instructions
3
+ # XAFLAG -- A64
4
+ # Convert floating-point condition flags from external format to Arm format
5
+ # XAFLAG
6
+ class XAFLAG
7
+ def encode
8
+ self.XAFLAG
9
+ end
10
+
11
+ private
12
+
13
+ def XAFLAG
14
+ insn = 0b1101010100_0_00_000_0100_0000_001_11111
15
+ insn
16
+ end
17
+ end
18
+ end
19
+ end
@@ -0,0 +1,28 @@
1
+ module AArch64
2
+ module Instructions
3
+ # XPACD, XPACI, XPACLRI -- A64
4
+ # Strip Pointer Authentication Code
5
+ # XPACD <Xd>
6
+ # XPACI <Xd>
7
+ # XPACLRI
8
+ class XPAC
9
+ def initialize rd, d
10
+ @rd = rd
11
+ @d = d
12
+ end
13
+
14
+ def encode
15
+ self.XPAC(@d, @rd.to_i)
16
+ end
17
+
18
+ private
19
+
20
+ def XPAC d, rd
21
+ insn = 0b1_1_0_11010110_00001_0_1_000_0_11111_00000
22
+ insn |= ((d & 0x1) << 10)
23
+ insn |= (rd & 0x1f)
24
+ insn
25
+ end
26
+ end
27
+ end
28
+ end
@@ -0,0 +1,18 @@
1
+ module AArch64
2
+ module Instructions
3
+ # XPACLRI -- A64
4
+ # Strip Pointer Authentication Code
5
+ # XPACLRI
6
+ class XPACLRI
7
+ def encode
8
+ self.XPACLRI
9
+ end
10
+
11
+ private
12
+
13
+ def XPACLRI
14
+ 0b11010101000000110010000011111111
15
+ end
16
+ end
17
+ end
18
+ end
@@ -0,0 +1,19 @@
1
+ module AArch64
2
+ module Instructions
3
+ # YIELD -- A64
4
+ # YIELD
5
+ # YIELD
6
+ class YIELD
7
+ def encode
8
+ self.YIELD
9
+ end
10
+
11
+ private
12
+
13
+ def YIELD
14
+ insn = 0b1101010100_0_00_011_0010_0000_001_11111
15
+ insn
16
+ end
17
+ end
18
+ end
19
+ end