aarch64 1.0.0

data/lib/aarch64/instructions/swp.rb

@@ -0,0 +1,41 @@
+module AArch64
+  module Instructions
+    # SWP, SWPA, SWPAL, SWPL -- A64
+    # Swap word or doubleword in memory
+    # SWP  <Ws>, <Wt>, [<Xn|SP>]
+    # SWPA  <Ws>, <Wt>, [<Xn|SP>]
+    # SWPAL  <Ws>, <Wt>, [<Xn|SP>]
+    # SWPL  <Ws>, <Wt>, [<Xn|SP>]
+    # SWP  <Xs>, <Xt>, [<Xn|SP>]
+    # SWPA  <Xs>, <Xt>, [<Xn|SP>]
+    # SWPAL  <Xs>, <Xt>, [<Xn|SP>]
+    # SWPL  <Xs>, <Xt>, [<Xn|SP>]
+    class SWP
+      def initialize rs, rt, rn, size, a, r
+        @rs   = rs
+        @rt   = rt
+        @rn   = rn
+        @size = size
+        @a    = a
+        @r    = r
+      end
+
+      def encode
+        self.SWP(@size, @a, @r, @rs.to_i, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def SWP size, a, r, rs, rn, rt
+        insn = 0b00_111_0_00_0_0_1_00000_1_000_00_00000_00000
+        insn |= ((size & 0x3) << 30)
+        insn |= ((a & 0x1) << 23)
+        insn |= ((r & 0x1) << 22)
+        insn |= ((rs & 0x1f) << 16)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/swpb.rb

@@ -0,0 +1,35 @@
+module AArch64
+  module Instructions
+    # SWPB, SWPAB, SWPALB, SWPLB -- A64
+    # Swap byte in memory
+    # SWPAB  <Ws>, <Wt>, [<Xn|SP>]
+    # SWPALB  <Ws>, <Wt>, [<Xn|SP>]
+    # SWPB  <Ws>, <Wt>, [<Xn|SP>]
+    # SWPLB  <Ws>, <Wt>, [<Xn|SP>]
+    class SWPB
+      def initialize rs, rt, rn, a, r
+        @rs = rs
+        @rt = rt
+        @rn = rn
+        @a  = a
+        @r  = r
+      end
+
+      def encode
+        self.SWPB(@a, @r, @rs.to_i, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def SWPB a, r, rs, rn, rt
+        insn = 0b00_111_0_00_0_0_1_00000_1_000_00_00000_00000
+        insn |= ((a & 0x1) << 23)
+        insn |= ((r & 0x1) << 22)
+        insn |= ((rs & 0x1f) << 16)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/swph.rb

@@ -0,0 +1,35 @@
+module AArch64
+  module Instructions
+    # SWPH, SWPAH, SWPALH, SWPLH -- A64
+    # Swap halfword in memory
+    # SWPAH  <Ws>, <Wt>, [<Xn|SP>]
+    # SWPALH  <Ws>, <Wt>, [<Xn|SP>]
+    # SWPH  <Ws>, <Wt>, [<Xn|SP>]
+    # SWPLH  <Ws>, <Wt>, [<Xn|SP>]
+    class SWPH
+      def initialize rs, rt, rn, a, r
+        @rs = rs
+        @rt = rt
+        @rn = rn
+        @a  = a
+        @r  = r
+      end
+
+      def encode
+        self.SWPH(@a, @r, @rs.to_i, @rn.to_i, @rt.to_i)
+      end
+
+      private
+
+      def SWPH a, r, rs, rn, rt
+        insn = 0b01_111_0_00_0_0_1_00000_1_000_00_00000_00000
+        insn |= ((a & 0x1) << 23)
+        insn |= ((r & 0x1) << 22)
+        insn |= ((rs & 0x1f) << 16)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/sys.rb

@@ -0,0 +1,32 @@
+module AArch64
+  module Instructions
+    # SYS -- A64
+    # System instruction
+    # SYS  #<op1>, <Cn>, <Cm>, #<op2>{, <Xt>}
+    class SYS
+      def initialize op1, cn, cm, op2, xt
+        @op1 = op1
+        @cn  = cn
+        @cm  = cm
+        @op2 = op2
+        @xt  = xt
+      end
+
+      def encode
+        self.SYS(@op1, @cn, @cm, @op2, @xt.to_i)
+      end
+
+      private
+
+      def SYS op1, crn, crm, op2, rt
+        insn = 0b1101010100_0_01_000_0000_0000_000_00000
+        insn |= ((op1 & 0x7) << 16)
+        insn |= ((crn & 0xf) << 12)
+        insn |= ((crm & 0xf) << 8)
+        insn |= ((op2 & 0x7) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/sysl.rb

@@ -0,0 +1,32 @@
+module AArch64
+  module Instructions
+    # SYSL -- A64
+    # System instruction with result
+    # SYSL  <Xt>, #<op1>, <Cn>, <Cm>, #<op2>
+    class SYSL
+      def initialize xt, op1, cn, cm, op2
+        @xt  = xt
+        @op1 = op1
+        @cn  = cn
+        @cm  = cm
+        @op2 = op2
+      end
+
+      def encode
+        self.SYSL(@op1, @cn.to_i, @cm.to_i, @op2, @xt.to_i)
+      end
+
+      private
+
+      def SYSL op1, crn, crm, op2, rt
+        insn = 0b1101010100_1_01_000_0000_0000_000_00000
+        insn |= ((op1 & 0x7) << 16)
+        insn |= ((crn & 0xf) << 12)
+        insn |= ((crm & 0xf) << 8)
+        insn |= ((op2 & 0x7) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/tbnz.rb

@@ -0,0 +1,30 @@
+module AArch64
+  module Instructions
+    # TBNZ -- A64
+    # Test bit and Branch if Nonzero
+    # TBNZ  <R><t>, #<imm>, <label>
+    class TBNZ
+      def initialize rt, imm, label, sf
+        @rt    = rt
+        @imm   = imm
+        @label = label
+        @sf    = sf
+      end
+
+      def encode
+        self.TBNZ(@sf, @imm, @label.to_i / 4, @rt.to_i)
+      end
+
+      private
+
+      def TBNZ b5, b40, imm14, rt
+        insn = 0b0_011011_1_00000_00000000000000_00000
+        insn |= ((b5 & 0x1) << 31)
+        insn |= ((b40 & 0x1f) << 19)
+        insn |= ((imm14 & 0x3fff) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/tbz.rb

@@ -0,0 +1,30 @@
+module AArch64
+  module Instructions
+    # TBZ -- A64
+    # Test bit and Branch if Zero
+    # TBZ  <R><t>, #<imm>, <label>
+    class TBZ
+      def initialize rt, imm, label, sf
+        @rt    = rt
+        @imm   = imm
+        @label = label
+        @sf    = sf
+      end
+
+      def encode
+        self.TBZ(@sf, @imm, @label.to_i / 4, @rt.to_i)
+      end
+
+      private
+
+      def TBZ b5, b40, imm14, rt
+        insn = 0b0_011011_0_00000_00000000000000_00000
+        insn |= ((b5 & 0x1) << 31)
+        insn |= ((b40 & 0x1f) << 19)
+        insn |= ((imm14 & 0x3fff) << 5)
+        insn |= (rt & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/tsb.rb

@@ -0,0 +1,18 @@
+module AArch64
+  module Instructions
+    # TSB CSYNC -- A64
+    # Trace Synchronization Barrier
+    # TSB CSYNC
+    class TSB
+      def encode
+        self.TSB
+      end
+
+      private
+
+      def TSB
+        0b1101010100_0_00_011_0010_0010_010_11111
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/ubfm.rb

@@ -0,0 +1,34 @@
+module AArch64
+  module Instructions
+    # UBFM -- A64
+    # Unsigned Bitfield Move
+    # UBFM  <Wd>, <Wn>, #<immr>, #<imms>
+    # UBFM  <Xd>, <Xn>, #<immr>, #<imms>
+    class UBFM
+      def initialize rd, rn, immr, imms, sf
+        @rd   = rd
+        @rn   = rn
+        @immr = immr
+        @imms = imms
+        @sf   = sf
+      end
+
+      def encode
+        self.UBFM(@sf, @sf, @immr, @imms, @rn.to_i, @rd.to_i)
+      end
+
+      private
+
+      def UBFM sf, n, immr, imms, rn, rd
+        insn = 0b0_10_100110_0_000000_000000_00000_00000
+        insn |= ((sf & 0x1) << 31)
+        insn |= ((n & 0x1) << 22)
+        insn |= ((immr & 0x3f) << 16)
+        insn |= ((imms & 0x3f) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/udf_perm_undef.rb

@@ -0,0 +1,24 @@
+module AArch64
+  module Instructions
+    # UDF -- A64
+    # Permanently Undefined
+    # UDF  #<imm>
+    class UDF_perm_undef
+      def initialize imm
+        @imm = imm
+      end
+
+      def encode
+        self.UDF_perm_undef(@imm)
+      end
+
+      private
+
+      def UDF_perm_undef imm16
+        insn = 0b0000000000000000_0000000000000000
+        insn |= (imm16 & 0xffff)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/udiv.rb

@@ -0,0 +1,31 @@
+module AArch64
+  module Instructions
+    # UDIV -- A64
+    # Unsigned Divide
+    # UDIV  <Wd>, <Wn>, <Wm>
+    # UDIV  <Xd>, <Xn>, <Xm>
+    class UDIV
+      def initialize rd, rn, rm, sf
+        @rd = rd
+        @rn = rn
+        @rm = rm
+        @sf = sf
+      end
+
+      def encode
+        self.UDIV(@sf, @rm.to_i, @rn.to_i, @rd.to_i)
+      end
+
+      private
+
+      def UDIV sf, rm, rn, rd
+        insn = 0b0_0_0_11010110_00000_00001_0_00000_00000
+        insn |= ((sf & 0x1) << 31)
+        insn |= ((rm & 0x1f) << 16)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/umaddl.rb

@@ -0,0 +1,30 @@
+module AArch64
+  module Instructions
+    # UMADDL -- A64
+    # Unsigned Multiply-Add Long
+    # UMADDL  <Xd>, <Wn>, <Wm>, <Xa>
+    class UMADDL
+      def initialize xd, wn, wm, xa
+        @xd = xd
+        @wn = wn
+        @wm = wm
+        @xa = xa
+      end
+
+      def encode
+        self.UMADDL(@wm.to_i, @xa.to_i, @wn.to_i, @xd.to_i)
+      end
+
+      private
+
+      def UMADDL rm, ra, rn, rd
+        insn = 0b1_00_11011_1_01_00000_0_00000_00000_00000
+        insn |= ((rm & 0x1f) << 16)
+        insn |= ((ra & 0x1f) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/umsubl.rb

@@ -0,0 +1,30 @@
+module AArch64
+  module Instructions
+    # UMSUBL -- A64
+    # Unsigned Multiply-Subtract Long
+    # UMSUBL  <Xd>, <Wn>, <Wm>, <Xa>
+    class UMSUBL
+      def initialize xd, wn, wm, xa
+        @xd = xd
+        @wn = wn
+        @wm = wm
+        @xa = xa
+      end
+
+      def encode
+        self.UMSUBL(@wm.to_i, @xa.to_i, @wn.to_i, @xd.to_i)
+      end
+
+      private
+
+      def UMSUBL rm, ra, rn, rd
+        insn = 0b1_00_11011_1_01_00000_1_00000_00000_00000
+        insn |= ((rm & 0x1f) << 16)
+        insn |= ((ra & 0x1f) << 10)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/umulh.rb

@@ -0,0 +1,28 @@
+module AArch64
+  module Instructions
+    # UMULH -- A64
+    # Unsigned Multiply High
+    # UMULH  <Xd>, <Xn>, <Xm>
+    class UMULH
+      def initialize rd, rn, rm
+        @rd = rd
+        @rn = rn
+        @rm = rm
+      end
+
+      def encode
+        self.UMULH(@rm.to_i, @rn.to_i, @rd.to_i)
+      end
+
+      private
+
+      def UMULH rm, rn, rd
+        insn = 0b1_00_11011_1_10_00000_0_11111_00000_00000
+        insn |= ((rm & 0x1f) << 16)
+        insn |= ((rn & 0x1f) << 5)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/wfe.rb

@@ -0,0 +1,19 @@
+module AArch64
+  module Instructions
+    # WFE -- A64
+    # Wait For Event
+    # WFE
+    class WFE
+      def encode
+        self.WFE
+      end
+
+      private
+
+      def WFE
+        insn = 0b1101010100_0_00_011_0010_0000_010_11111
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/wfet.rb

@@ -0,0 +1,24 @@
+module AArch64
+  module Instructions
+    # WFET -- A64
+    # Wait For Event with Timeout
+    # WFET  <Xt>
+    class WFET
+      def initialize rd
+        @rd = rd
+      end
+
+      def encode
+        self.WFET(@rd.to_i)
+      end
+
+      private
+
+      def WFET rd
+        insn = 0b11010101000000110001_0000_000_00000
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/wfi.rb

@@ -0,0 +1,19 @@
+module AArch64
+  module Instructions
+    # WFI -- A64
+    # Wait For Interrupt
+    # WFI
+    class WFI
+      def encode
+        self.WFI
+      end
+
+      private
+
+      def WFI
+        insn = 0b1101010100_0_00_011_0010_0000_011_11111
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/wfit.rb

@@ -0,0 +1,24 @@
+module AArch64
+  module Instructions
+    # WFIT -- A64
+    # Wait For Interrupt with Timeout
+    # WFIT  <Xt>
+    class WFIT
+      def initialize rd
+        @rd = rd
+      end
+
+      def encode
+        self.WFIT(@rd.to_i)
+      end
+
+      private
+
+      def WFIT rd
+        insn = 0b11010101000000110001_0000_001_00000
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/xaflag.rb

@@ -0,0 +1,19 @@
+module AArch64
+  module Instructions
+    # XAFLAG -- A64
+    # Convert floating-point condition flags from external format to Arm format
+    # XAFLAG
+    class XAFLAG
+      def encode
+        self.XAFLAG
+      end
+
+      private
+
+      def XAFLAG
+        insn = 0b1101010100_0_00_000_0100_0000_001_11111
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/xpac.rb

@@ -0,0 +1,28 @@
+module AArch64
+  module Instructions
+    # XPACD, XPACI, XPACLRI -- A64
+    # Strip Pointer Authentication Code
+    # XPACD  <Xd>
+    # XPACI  <Xd>
+    # XPACLRI
+    class XPAC
+      def initialize rd, d
+        @rd = rd
+        @d  = d
+      end
+
+      def encode
+        self.XPAC(@d, @rd.to_i)
+      end
+
+      private
+
+      def XPAC d, rd
+        insn = 0b1_1_0_11010110_00001_0_1_000_0_11111_00000
+        insn |= ((d & 0x1) << 10)
+        insn |= (rd & 0x1f)
+        insn
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/xpaclri.rb

@@ -0,0 +1,18 @@
+module AArch64
+  module Instructions
+    # XPACLRI -- A64
+    # Strip Pointer Authentication Code
+    # XPACLRI
+    class XPACLRI
+      def encode
+        self.XPACLRI
+      end
+
+      private
+
+      def XPACLRI
+        0b11010101000000110010000011111111
+      end
+    end
+  end
+end

data/lib/aarch64/instructions/yield.rb

@@ -0,0 +1,19 @@
+module AArch64
+  module Instructions
+    # YIELD -- A64
+    # YIELD
+    # YIELD
+    class YIELD
+      def encode
+        self.YIELD
+      end
+
+      private
+
+      def YIELD
+        insn = 0b1101010100_0_00_011_0010_0000_001_11111
+        insn
+      end
+    end
+  end
+end