aarch64 1.0.0
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- checksums.yaml +7 -0
- data/CODE_OF_CONDUCT.md +77 -0
- data/Gemfile +3 -0
- data/LICENSE +201 -0
- data/README.md +77 -0
- data/Rakefile +168 -0
- data/aarch64.gemspec +21 -0
- data/bin/build_instructions.rb +102 -0
- data/lib/aarch64/instructions/adc.rb +31 -0
- data/lib/aarch64/instructions/adcs.rb +30 -0
- data/lib/aarch64/instructions/add_addsub_ext.rb +35 -0
- data/lib/aarch64/instructions/add_addsub_imm.rb +32 -0
- data/lib/aarch64/instructions/add_addsub_shift.rb +35 -0
- data/lib/aarch64/instructions/addg.rb +30 -0
- data/lib/aarch64/instructions/adds_addsub_ext.rb +35 -0
- data/lib/aarch64/instructions/adds_addsub_imm.rb +33 -0
- data/lib/aarch64/instructions/adds_addsub_shift.rb +35 -0
- data/lib/aarch64/instructions/adr.rb +28 -0
- data/lib/aarch64/instructions/adrp.rb +28 -0
- data/lib/aarch64/instructions/and_log_imm.rb +35 -0
- data/lib/aarch64/instructions/and_log_shift.rb +35 -0
- data/lib/aarch64/instructions/ands_log_imm.rb +35 -0
- data/lib/aarch64/instructions/ands_log_shift.rb +35 -0
- data/lib/aarch64/instructions/asrv.rb +31 -0
- data/lib/aarch64/instructions/autda.rb +32 -0
- data/lib/aarch64/instructions/autdb.rb +32 -0
- data/lib/aarch64/instructions/autia.rb +35 -0
- data/lib/aarch64/instructions/autib.rb +35 -0
- data/lib/aarch64/instructions/axflag.rb +18 -0
- data/lib/aarch64/instructions/b_cond.rb +26 -0
- data/lib/aarch64/instructions/b_uncond.rb +24 -0
- data/lib/aarch64/instructions/bc_cond.rb +26 -0
- data/lib/aarch64/instructions/bfm.rb +34 -0
- data/lib/aarch64/instructions/bic_log_shift.rb +35 -0
- data/lib/aarch64/instructions/bics.rb +35 -0
- data/lib/aarch64/instructions/bl.rb +24 -0
- data/lib/aarch64/instructions/blr.rb +24 -0
- data/lib/aarch64/instructions/blra.rb +33 -0
- data/lib/aarch64/instructions/br.rb +24 -0
- data/lib/aarch64/instructions/bra.rb +33 -0
- data/lib/aarch64/instructions/brk.rb +24 -0
- data/lib/aarch64/instructions/bti.rb +24 -0
- data/lib/aarch64/instructions/cas.rb +41 -0
- data/lib/aarch64/instructions/casb.rb +35 -0
- data/lib/aarch64/instructions/cash.rb +35 -0
- data/lib/aarch64/instructions/casp.rb +41 -0
- data/lib/aarch64/instructions/cbnz.rb +29 -0
- data/lib/aarch64/instructions/cbz.rb +29 -0
- data/lib/aarch64/instructions/ccmn_imm.rb +33 -0
- data/lib/aarch64/instructions/ccmn_reg.rb +33 -0
- data/lib/aarch64/instructions/ccmp_imm.rb +33 -0
- data/lib/aarch64/instructions/ccmp_reg.rb +33 -0
- data/lib/aarch64/instructions/cfinv.rb +19 -0
- data/lib/aarch64/instructions/clrex.rb +24 -0
- data/lib/aarch64/instructions/cls_int.rb +29 -0
- data/lib/aarch64/instructions/clz_int.rb +29 -0
- data/lib/aarch64/instructions/crc32.rb +35 -0
- data/lib/aarch64/instructions/crc32c.rb +35 -0
- data/lib/aarch64/instructions/csdb.rb +19 -0
- data/lib/aarch64/instructions/csel.rb +33 -0
- data/lib/aarch64/instructions/csinc.rb +33 -0
- data/lib/aarch64/instructions/csinv.rb +33 -0
- data/lib/aarch64/instructions/csneg.rb +33 -0
- data/lib/aarch64/instructions/dcps.rb +26 -0
- data/lib/aarch64/instructions/dgh.rb +19 -0
- data/lib/aarch64/instructions/dmb.rb +24 -0
- data/lib/aarch64/instructions/drps.rb +19 -0
- data/lib/aarch64/instructions/dsb.rb +25 -0
- data/lib/aarch64/instructions/eon.rb +35 -0
- data/lib/aarch64/instructions/eor_log_imm.rb +35 -0
- data/lib/aarch64/instructions/eor_log_shift.rb +35 -0
- data/lib/aarch64/instructions/eret.rb +19 -0
- data/lib/aarch64/instructions/ereta.rb +25 -0
- data/lib/aarch64/instructions/esb.rb +19 -0
- data/lib/aarch64/instructions/extr.rb +34 -0
- data/lib/aarch64/instructions/gmi.rb +28 -0
- data/lib/aarch64/instructions/hint.rb +26 -0
- data/lib/aarch64/instructions/hlt.rb +24 -0
- data/lib/aarch64/instructions/hvc.rb +24 -0
- data/lib/aarch64/instructions/irg.rb +28 -0
- data/lib/aarch64/instructions/isb.rb +24 -0
- data/lib/aarch64/instructions/ld64b.rb +26 -0
- data/lib/aarch64/instructions/ldadd.rb +41 -0
- data/lib/aarch64/instructions/ldaddb.rb +35 -0
- data/lib/aarch64/instructions/ldaddh.rb +35 -0
- data/lib/aarch64/instructions/ldapr.rb +29 -0
- data/lib/aarch64/instructions/ldaprb.rb +26 -0
- data/lib/aarch64/instructions/ldaprh.rb +26 -0
- data/lib/aarch64/instructions/ldapur_gen.rb +33 -0
- data/lib/aarch64/instructions/ldar.rb +29 -0
- data/lib/aarch64/instructions/ldaxp.rb +31 -0
- data/lib/aarch64/instructions/ldaxr.rb +29 -0
- data/lib/aarch64/instructions/ldclr.rb +41 -0
- data/lib/aarch64/instructions/ldclrb.rb +37 -0
- data/lib/aarch64/instructions/ldeor.rb +41 -0
- data/lib/aarch64/instructions/ldg.rb +28 -0
- data/lib/aarch64/instructions/ldgm.rb +26 -0
- data/lib/aarch64/instructions/ldlar.rb +29 -0
- data/lib/aarch64/instructions/ldnp_gen.rb +33 -0
- data/lib/aarch64/instructions/ldp_gen.rb +39 -0
- data/lib/aarch64/instructions/ldpsw.rb +34 -0
- data/lib/aarch64/instructions/ldr_imm_gen.rb +35 -0
- data/lib/aarch64/instructions/ldr_imm_unsigned.rb +31 -0
- data/lib/aarch64/instructions/ldr_lit_gen.rb +29 -0
- data/lib/aarch64/instructions/ldr_reg_gen.rb +35 -0
- data/lib/aarch64/instructions/ldra.rb +37 -0
- data/lib/aarch64/instructions/ldrb_imm.rb +32 -0
- data/lib/aarch64/instructions/ldrb_reg.rb +33 -0
- data/lib/aarch64/instructions/ldrb_unsigned.rb +28 -0
- data/lib/aarch64/instructions/ldrh_imm.rb +32 -0
- data/lib/aarch64/instructions/ldrh_reg.rb +32 -0
- data/lib/aarch64/instructions/ldrh_unsigned.rb +28 -0
- data/lib/aarch64/instructions/ldrsb_imm.rb +37 -0
- data/lib/aarch64/instructions/ldrsb_reg.rb +37 -0
- data/lib/aarch64/instructions/ldrsb_unsigned.rb +35 -0
- data/lib/aarch64/instructions/ldrsh_imm.rb +37 -0
- data/lib/aarch64/instructions/ldrsh_reg.rb +35 -0
- data/lib/aarch64/instructions/ldrsh_unsigned.rb +31 -0
- data/lib/aarch64/instructions/ldrsw_imm.rb +32 -0
- data/lib/aarch64/instructions/ldrsw_lit.rb +26 -0
- data/lib/aarch64/instructions/ldrsw_reg.rb +32 -0
- data/lib/aarch64/instructions/ldrsw_unsigned.rb +30 -0
- data/lib/aarch64/instructions/ldset.rb +41 -0
- data/lib/aarch64/instructions/ldsetb.rb +35 -0
- data/lib/aarch64/instructions/ldseth.rb +35 -0
- data/lib/aarch64/instructions/ldsmax.rb +41 -0
- data/lib/aarch64/instructions/ldsmaxb.rb +35 -0
- data/lib/aarch64/instructions/ldsmaxh.rb +35 -0
- data/lib/aarch64/instructions/ldsmin.rb +41 -0
- data/lib/aarch64/instructions/ldsminb.rb +35 -0
- data/lib/aarch64/instructions/ldsminh.rb +35 -0
- data/lib/aarch64/instructions/ldtr.rb +31 -0
- data/lib/aarch64/instructions/ldtrb.rb +28 -0
- data/lib/aarch64/instructions/ldtrh.rb +28 -0
- data/lib/aarch64/instructions/ldtrsb.rb +31 -0
- data/lib/aarch64/instructions/ldtrsh.rb +31 -0
- data/lib/aarch64/instructions/ldtrsw.rb +28 -0
- data/lib/aarch64/instructions/ldumax.rb +41 -0
- data/lib/aarch64/instructions/ldumaxb.rb +35 -0
- data/lib/aarch64/instructions/ldumaxh.rb +35 -0
- data/lib/aarch64/instructions/ldumin.rb +41 -0
- data/lib/aarch64/instructions/lduminb.rb +35 -0
- data/lib/aarch64/instructions/lduminh.rb +35 -0
- data/lib/aarch64/instructions/ldur_gen.rb +31 -0
- data/lib/aarch64/instructions/ldursb.rb +31 -0
- data/lib/aarch64/instructions/ldursh.rb +31 -0
- data/lib/aarch64/instructions/ldursw.rb +28 -0
- data/lib/aarch64/instructions/ldxp.rb +31 -0
- data/lib/aarch64/instructions/ldxr.rb +29 -0
- data/lib/aarch64/instructions/lslv.rb +31 -0
- data/lib/aarch64/instructions/lsrv.rb +31 -0
- data/lib/aarch64/instructions/madd.rb +33 -0
- data/lib/aarch64/instructions/movk.rb +31 -0
- data/lib/aarch64/instructions/movn.rb +31 -0
- data/lib/aarch64/instructions/movz.rb +31 -0
- data/lib/aarch64/instructions/mrs.rb +34 -0
- data/lib/aarch64/instructions/msr_imm.rb +28 -0
- data/lib/aarch64/instructions/msr_reg.rb +34 -0
- data/lib/aarch64/instructions/msub.rb +33 -0
- data/lib/aarch64/instructions/nop.rb +19 -0
- data/lib/aarch64/instructions/orn_log_shift.rb +35 -0
- data/lib/aarch64/instructions/orr_log_imm.rb +35 -0
- data/lib/aarch64/instructions/orr_log_shift.rb +35 -0
- data/lib/aarch64/instructions/pacda.rb +29 -0
- data/lib/aarch64/instructions/pacdb.rb +29 -0
- data/lib/aarch64/instructions/pacga.rb +28 -0
- data/lib/aarch64/instructions/pacia.rb +32 -0
- data/lib/aarch64/instructions/pacia2.rb +28 -0
- data/lib/aarch64/instructions/pacib.rb +32 -0
- data/lib/aarch64/instructions/prfm_imm.rb +28 -0
- data/lib/aarch64/instructions/prfm_lit.rb +26 -0
- data/lib/aarch64/instructions/prfm_reg.rb +32 -0
- data/lib/aarch64/instructions/prfum.rb +28 -0
- data/lib/aarch64/instructions/psb.rb +19 -0
- data/lib/aarch64/instructions/rbit_int.rb +29 -0
- data/lib/aarch64/instructions/ret.rb +24 -0
- data/lib/aarch64/instructions/reta.rb +25 -0
- data/lib/aarch64/instructions/rev.rb +31 -0
- data/lib/aarch64/instructions/rmif.rb +28 -0
- data/lib/aarch64/instructions/rorv.rb +31 -0
- data/lib/aarch64/instructions/sb.rb +19 -0
- data/lib/aarch64/instructions/sbc.rb +31 -0
- data/lib/aarch64/instructions/sbcs.rb +31 -0
- data/lib/aarch64/instructions/sbfm.rb +34 -0
- data/lib/aarch64/instructions/sdiv.rb +31 -0
- data/lib/aarch64/instructions/setf.rb +27 -0
- data/lib/aarch64/instructions/setgp.rb +25 -0
- data/lib/aarch64/instructions/setgpn.rb +25 -0
- data/lib/aarch64/instructions/setgpt.rb +25 -0
- data/lib/aarch64/instructions/setgptn.rb +25 -0
- data/lib/aarch64/instructions/setp.rb +25 -0
- data/lib/aarch64/instructions/setpn.rb +25 -0
- data/lib/aarch64/instructions/setpt.rb +25 -0
- data/lib/aarch64/instructions/setptn.rb +25 -0
- data/lib/aarch64/instructions/sev.rb +18 -0
- data/lib/aarch64/instructions/sevl.rb +18 -0
- data/lib/aarch64/instructions/smaddl.rb +30 -0
- data/lib/aarch64/instructions/smc.rb +24 -0
- data/lib/aarch64/instructions/smsubl.rb +30 -0
- data/lib/aarch64/instructions/smulh.rb +28 -0
- data/lib/aarch64/instructions/st2g.rb +32 -0
- data/lib/aarch64/instructions/st64b.rb +26 -0
- data/lib/aarch64/instructions/st64bv.rb +28 -0
- data/lib/aarch64/instructions/st64bv0.rb +28 -0
- data/lib/aarch64/instructions/stg.rb +32 -0
- data/lib/aarch64/instructions/stgm.rb +26 -0
- data/lib/aarch64/instructions/stgp.rb +34 -0
- data/lib/aarch64/instructions/stllr.rb +29 -0
- data/lib/aarch64/instructions/stllrb.rb +26 -0
- data/lib/aarch64/instructions/stllrh.rb +26 -0
- data/lib/aarch64/instructions/stlr.rb +29 -0
- data/lib/aarch64/instructions/stlrb.rb +26 -0
- data/lib/aarch64/instructions/stlrh.rb +26 -0
- data/lib/aarch64/instructions/stlur_gen.rb +31 -0
- data/lib/aarch64/instructions/stlxp.rb +33 -0
- data/lib/aarch64/instructions/stlxr.rb +31 -0
- data/lib/aarch64/instructions/stlxrb.rb +28 -0
- data/lib/aarch64/instructions/stlxrh.rb +28 -0
- data/lib/aarch64/instructions/stnp_gen.rb +33 -0
- data/lib/aarch64/instructions/stp_gen.rb +39 -0
- data/lib/aarch64/instructions/str_imm_gen.rb +37 -0
- data/lib/aarch64/instructions/str_imm_unsigned.rb +31 -0
- data/lib/aarch64/instructions/str_reg_gen.rb +35 -0
- data/lib/aarch64/instructions/strb_imm.rb +32 -0
- data/lib/aarch64/instructions/strb_imm_unsigned.rb +28 -0
- data/lib/aarch64/instructions/strb_reg.rb +33 -0
- data/lib/aarch64/instructions/strh_imm.rb +32 -0
- data/lib/aarch64/instructions/strh_imm_unsigned.rb +28 -0
- data/lib/aarch64/instructions/strh_reg.rb +32 -0
- data/lib/aarch64/instructions/sttr.rb +31 -0
- data/lib/aarch64/instructions/stur_gen.rb +31 -0
- data/lib/aarch64/instructions/stxp.rb +33 -0
- data/lib/aarch64/instructions/stxr.rb +31 -0
- data/lib/aarch64/instructions/stxrb.rb +28 -0
- data/lib/aarch64/instructions/stxrh.rb +28 -0
- data/lib/aarch64/instructions/stz2g.rb +32 -0
- data/lib/aarch64/instructions/stzg.rb +32 -0
- data/lib/aarch64/instructions/stzgm.rb +26 -0
- data/lib/aarch64/instructions/sub_addsub_ext.rb +35 -0
- data/lib/aarch64/instructions/sub_addsub_imm.rb +33 -0
- data/lib/aarch64/instructions/sub_addsub_shift.rb +35 -0
- data/lib/aarch64/instructions/subg.rb +30 -0
- data/lib/aarch64/instructions/subp.rb +28 -0
- data/lib/aarch64/instructions/subps.rb +28 -0
- data/lib/aarch64/instructions/subs_addsub_ext.rb +35 -0
- data/lib/aarch64/instructions/subs_addsub_imm.rb +33 -0
- data/lib/aarch64/instructions/subs_addsub_shift.rb +35 -0
- data/lib/aarch64/instructions/svc.rb +24 -0
- data/lib/aarch64/instructions/swp.rb +41 -0
- data/lib/aarch64/instructions/swpb.rb +35 -0
- data/lib/aarch64/instructions/swph.rb +35 -0
- data/lib/aarch64/instructions/sys.rb +32 -0
- data/lib/aarch64/instructions/sysl.rb +32 -0
- data/lib/aarch64/instructions/tbnz.rb +30 -0
- data/lib/aarch64/instructions/tbz.rb +30 -0
- data/lib/aarch64/instructions/tsb.rb +18 -0
- data/lib/aarch64/instructions/ubfm.rb +34 -0
- data/lib/aarch64/instructions/udf_perm_undef.rb +24 -0
- data/lib/aarch64/instructions/udiv.rb +31 -0
- data/lib/aarch64/instructions/umaddl.rb +30 -0
- data/lib/aarch64/instructions/umsubl.rb +30 -0
- data/lib/aarch64/instructions/umulh.rb +28 -0
- data/lib/aarch64/instructions/wfe.rb +19 -0
- data/lib/aarch64/instructions/wfet.rb +24 -0
- data/lib/aarch64/instructions/wfi.rb +19 -0
- data/lib/aarch64/instructions/wfit.rb +24 -0
- data/lib/aarch64/instructions/xaflag.rb +19 -0
- data/lib/aarch64/instructions/xpac.rb +28 -0
- data/lib/aarch64/instructions/xpaclri.rb +18 -0
- data/lib/aarch64/instructions/yield.rb +19 -0
- data/lib/aarch64/instructions.rb +266 -0
- data/lib/aarch64/system_registers/mrs_msr_64.rb +395 -0
- data/lib/aarch64/utils.rb +325 -0
- data/lib/aarch64/version.rb +3 -0
- data/lib/aarch64.rb +2857 -0
- data/test/all_adds_test.rb +129 -0
- data/test/base_instructions_test.rb +9263 -0
- data/test/dsl_test.rb +11 -0
- data/test/helper.rb +51 -0
- data/test/not_supported_yet_test.rb +55 -0
- metadata +382 -0
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# frozen_string_literal: true
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module AArch64
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module Utils
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EncodedMask = Struct.new(:n, :immr, :imms)
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MAX_INT_64 = 0xFFFFFFFFFFFFFFFF
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COND_TABLE = {
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"EQ" => 0b0000,
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"NE" => 0b0001,
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"CS" => 0b0010,
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"HS" => 0b0010,
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"CC" => 0b0011,
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"LO" => 0b0011,
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"MI" => 0b0100,
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"PL" => 0b0101,
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"VS" => 0b0110,
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"VC" => 0b0111,
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"HI" => 0b1000,
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"LS" => 0b1001,
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"GE" => 0b1010,
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"LT" => 0b1011,
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"GT" => 0b1100,
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"LE" => 0b1101,
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"AL" => 0b1110,
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"NVb" => 0b1111,
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}
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def cond2bin cond
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COND_TABLE.fetch(cond.to_s.upcase)
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end
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module_function :cond2bin
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def mask? num
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((num + 1) & num) == 0
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end
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module_function :mask?
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def shifted_mask? num
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mask?((num - 1) | num)
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end
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module_function :shifted_mask?
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def count_trailing_zeros num
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count = 0
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loop do
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break if num & 1 == 1
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count += 1
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num >>= 1
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end
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count
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end
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module_function :count_trailing_zeros
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def count_trailing_ones num
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count = 0
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loop do
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break if num & 1 == 0
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count += 1
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num >>= 1
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end
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count
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end
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module_function :count_trailing_ones
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def count_leading_ones num
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count = 0
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top_bit = 1 << 63
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loop do
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break if num & top_bit != top_bit
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count += 1
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(num <<= 1) & MAX_INT_64
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end
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count
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end
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module_function :count_leading_ones
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def encode_mask imm, regsize
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size = regsize
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loop do
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size >>= 1
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mask = (1 << size) - 1
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if (imm & mask) != ((imm >> size) & mask)
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size <<= 1
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break
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end
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break unless size > 2
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end
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mask = (-1 & MAX_INT_64) >> (64 - size)
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+
imm &= mask
|
96
|
+
|
97
|
+
if shifted_mask?(imm)
|
98
|
+
i = count_trailing_zeros imm
|
99
|
+
cto = count_trailing_ones(imm >> i)
|
100
|
+
else
|
101
|
+
imm |= ((~mask) & MAX_INT_64)
|
102
|
+
unless shifted_mask?((~imm) & MAX_INT_64)
|
103
|
+
return nil
|
104
|
+
end
|
105
|
+
|
106
|
+
clo = count_leading_ones(imm & MAX_INT_64)
|
107
|
+
i = 64 - clo
|
108
|
+
cto = clo + count_trailing_ones(imm) - (64 - size)
|
109
|
+
end
|
110
|
+
|
111
|
+
immr = (size - i) & (size - 1)
|
112
|
+
imms = (~(size - 1) << 1) | (cto - 1)
|
113
|
+
n = ((imms >> 6) & 1) ^ 1
|
114
|
+
|
115
|
+
EncodedMask.new(n, immr & 0x3F, imms & 0x3F)
|
116
|
+
end
|
117
|
+
module_function :encode_mask
|
118
|
+
|
119
|
+
DC_OP = {
|
120
|
+
# dc_op op1, CRm, op2
|
121
|
+
"IVAC" => [0b0000, 0b0110, 0b0001],
|
122
|
+
"ISW" => [0b0000, 0b0110, 0b0010],
|
123
|
+
"IGVAC" => [0b0000, 0b0110, 0b0011],
|
124
|
+
"IGSW" => [0b0000, 0b0110, 0b0100],
|
125
|
+
"IGDVAC" => [0b0000, 0b0110, 0b0101],
|
126
|
+
"IGDSW" => [0b0000, 0b0110, 0b0110],
|
127
|
+
"CSW" => [0b0000, 0b1010, 0b0010],
|
128
|
+
"CGSW" => [0b0000, 0b1010, 0b0100],
|
129
|
+
"CGDSW" => [0b0000, 0b1010, 0b0110],
|
130
|
+
"CISW" => [0b0000, 0b1110, 0b0010],
|
131
|
+
"CIGSW" => [0b0000, 0b1110, 0b0100],
|
132
|
+
"CIGDSW" => [0b0000, 0b1110, 0b0110],
|
133
|
+
"ZVA" => [0b0011, 0b0100, 0b0001],
|
134
|
+
"GVA" => [0b0011, 0b0100, 0b0011],
|
135
|
+
"GZVA" => [0b0011, 0b0100, 0b0100],
|
136
|
+
"CVAC" => [0b0011, 0b1010, 0b0001],
|
137
|
+
"CGVAC" => [0b0011, 0b1010, 0b0011],
|
138
|
+
"CGDVAC" => [0b0011, 0b1010, 0b0101],
|
139
|
+
"CVAU" => [0b0011, 0b1011, 0b0001],
|
140
|
+
"CVAP" => [0b0011, 0b1100, 0b0001],
|
141
|
+
"CGVAP" => [0b0011, 0b1100, 0b0011],
|
142
|
+
"CGDVAP" => [0b0011, 0b1100, 0b0101],
|
143
|
+
"CVADP" => [0b0011, 0b1101, 0b0001],
|
144
|
+
"CGVADP" => [0b0011, 0b1101, 0b0011],
|
145
|
+
"CGDVADP" => [0b0011, 0b1101, 0b0101],
|
146
|
+
"CIVAC" => [0b0011, 0b1110, 0b0001],
|
147
|
+
"CIGVAC" => [0b0011, 0b1110, 0b0011],
|
148
|
+
"CIGDVAC" => [0b0011, 0b1110, 0b0101],
|
149
|
+
}
|
150
|
+
|
151
|
+
def dc_op v
|
152
|
+
DC_OP.fetch(v.to_s.upcase)
|
153
|
+
end
|
154
|
+
module_function :dc_op
|
155
|
+
|
156
|
+
DMB_OPTIONS = {
|
157
|
+
"oshld" => 0b0001,
|
158
|
+
"oshst" => 0b0010,
|
159
|
+
"osh" => 0b0011,
|
160
|
+
"nshld" => 0b0101,
|
161
|
+
"nshst" => 0b0110,
|
162
|
+
"nsh" => 0b0111,
|
163
|
+
"ishld" => 0b1001,
|
164
|
+
"ishst" => 0b1010,
|
165
|
+
"ish" => 0b1011,
|
166
|
+
"ld" => 0b1101,
|
167
|
+
"st" => 0b1110,
|
168
|
+
"sy" => 0b1111,
|
169
|
+
}
|
170
|
+
|
171
|
+
def dmb2imm option
|
172
|
+
DMB_OPTIONS.fetch(option.to_s.downcase)
|
173
|
+
end
|
174
|
+
module_function :dmb2imm
|
175
|
+
|
176
|
+
IC_OPTIONS = {
|
177
|
+
# op1, CRm, op2
|
178
|
+
"ialluis" => [0b000, 0b0001, 0b00],
|
179
|
+
"iallu" => [0b000, 0b0101, 0b00],
|
180
|
+
"ivau" => [0b011, 0b0101, 0b01],
|
181
|
+
}
|
182
|
+
|
183
|
+
def ic_op name
|
184
|
+
IC_OPTIONS.fetch(name.to_s.downcase)
|
185
|
+
end
|
186
|
+
module_function :ic_op
|
187
|
+
|
188
|
+
TLBI_OPTIONS = {
|
189
|
+
# op1, CRm, op2,
|
190
|
+
"VMALLE1OS" => [0b0000, 0b0001, 0b0000],
|
191
|
+
"VAE1OS" => [0b0000, 0b0001, 0b0001],
|
192
|
+
"ASIDE1OS" => [0b0000, 0b0001, 0b0010],
|
193
|
+
"VAAE1OS" => [0b0000, 0b0001, 0b0011],
|
194
|
+
"VALE1OS" => [0b0000, 0b0001, 0b0101],
|
195
|
+
"VAALE1OS" => [0b0000, 0b0001, 0b0111],
|
196
|
+
"RVAE1IS" => [0b0000, 0b0010, 0b0001],
|
197
|
+
"RVAAE1IS" => [0b0000, 0b0010, 0b0011],
|
198
|
+
"RVALE1IS" => [0b0000, 0b0010, 0b0101],
|
199
|
+
"RVAALE1IS" => [0b0000, 0b0010, 0b0111],
|
200
|
+
"VMALLE1IS" => [0b0000, 0b0011, 0b0000],
|
201
|
+
"VAE1IS" => [0b0000, 0b0011, 0b0001],
|
202
|
+
"ASIDE1IS" => [0b0000, 0b0011, 0b0010],
|
203
|
+
"VAAE1IS" => [0b0000, 0b0011, 0b0011],
|
204
|
+
"VALE1IS" => [0b0000, 0b0011, 0b0101],
|
205
|
+
"VAALE1IS" => [0b0000, 0b0011, 0b0111],
|
206
|
+
"RVAE1OS" => [0b0000, 0b0101, 0b0001],
|
207
|
+
"RVAAE1OS" => [0b0000, 0b0101, 0b0011],
|
208
|
+
"RVALE1OS" => [0b0000, 0b0101, 0b0101],
|
209
|
+
"RVAALE1OS" => [0b0000, 0b0101, 0b0111],
|
210
|
+
"RVAE1" => [0b0000, 0b0110, 0b0001],
|
211
|
+
"RVAAE1" => [0b0000, 0b0110, 0b0011],
|
212
|
+
"RVALE1" => [0b0000, 0b0110, 0b0101],
|
213
|
+
"RVAALE1" => [0b0000, 0b0110, 0b0111],
|
214
|
+
"VMALLE1" => [0b0000, 0b0111, 0b0000],
|
215
|
+
"VAE1" => [0b0000, 0b0111, 0b0001],
|
216
|
+
"ASIDE1" => [0b0000, 0b0111, 0b0010],
|
217
|
+
"VAAE1" => [0b0000, 0b0111, 0b0011],
|
218
|
+
"VALE1" => [0b0000, 0b0111, 0b0101],
|
219
|
+
"VAALE1" => [0b0000, 0b0111, 0b0111],
|
220
|
+
"IPAS2E1IS" => [0b0100, 0b0000, 0b0001],
|
221
|
+
"RIPAS2E1IS" => [0b0100, 0b0000, 0b0010],
|
222
|
+
"IPAS2LE1IS" => [0b0100, 0b0000, 0b0101],
|
223
|
+
"RIPAS2LE1IS" => [0b0100, 0b0000, 0b0110],
|
224
|
+
"ALLE2OS" => [0b0100, 0b0001, 0b0000],
|
225
|
+
"VAE2OS" => [0b0100, 0b0001, 0b0001],
|
226
|
+
"ALLE1OS" => [0b0100, 0b0001, 0b0100],
|
227
|
+
"VALE2OS" => [0b0100, 0b0001, 0b0101],
|
228
|
+
"VMALLS12E1OS" => [0b0100, 0b0001, 0b0110],
|
229
|
+
"RVAE2IS" => [0b0100, 0b0010, 0b0001],
|
230
|
+
"RVALE2IS" => [0b0100, 0b0010, 0b0101],
|
231
|
+
"ALLE2IS" => [0b0100, 0b0011, 0b0000],
|
232
|
+
"VAE2IS" => [0b0100, 0b0011, 0b0001],
|
233
|
+
"ALLE1IS" => [0b0100, 0b0011, 0b0100],
|
234
|
+
"VALE2IS" => [0b0100, 0b0011, 0b0101],
|
235
|
+
"VMALLS12E1IS" => [0b0100, 0b0011, 0b0110],
|
236
|
+
"IPAS2E1OS" => [0b0100, 0b0100, 0b0000],
|
237
|
+
"IPAS2E1" => [0b0100, 0b0100, 0b0001],
|
238
|
+
"RIPAS2E1" => [0b0100, 0b0100, 0b0010],
|
239
|
+
"RIPAS2E1OS" => [0b0100, 0b0100, 0b0011],
|
240
|
+
"IPAS2LE1OS" => [0b0100, 0b0100, 0b0100],
|
241
|
+
"IPAS2LE1" => [0b0100, 0b0100, 0b0101],
|
242
|
+
"RIPAS2LE1" => [0b0100, 0b0100, 0b0110],
|
243
|
+
"RIPAS2LE1OS" => [0b0100, 0b0100, 0b0111],
|
244
|
+
"RVAE2OS" => [0b0100, 0b0101, 0b0001],
|
245
|
+
"RVALE2OS" => [0b0100, 0b0101, 0b0101],
|
246
|
+
"RVAE2" => [0b0100, 0b0110, 0b0001],
|
247
|
+
"RVALE2" => [0b0100, 0b0110, 0b0101],
|
248
|
+
"ALLE2" => [0b0100, 0b0111, 0b0000],
|
249
|
+
"VAE2" => [0b0100, 0b0111, 0b0001],
|
250
|
+
"ALLE1" => [0b0100, 0b0111, 0b0100],
|
251
|
+
"VALE2" => [0b0100, 0b0111, 0b0101],
|
252
|
+
"VMALLS12E1" => [0b0100, 0b0111, 0b0110],
|
253
|
+
"ALLE3OS" => [0b0110, 0b0001, 0b0000],
|
254
|
+
"VAE3OS" => [0b0110, 0b0001, 0b0001],
|
255
|
+
"VALE3OS" => [0b0110, 0b0001, 0b0101],
|
256
|
+
"RVAE3IS" => [0b0110, 0b0010, 0b0001],
|
257
|
+
"RVALE3IS" => [0b0110, 0b0010, 0b0101],
|
258
|
+
"ALLE3IS" => [0b0110, 0b0011, 0b0000],
|
259
|
+
"VAE3IS" => [0b0110, 0b0011, 0b0001],
|
260
|
+
"VALE3IS" => [0b0110, 0b0011, 0b0101],
|
261
|
+
"RVAE3OS" => [0b0110, 0b0101, 0b0001],
|
262
|
+
"RVALE3OS" => [0b0110, 0b0101, 0b0101],
|
263
|
+
"RVAE3" => [0b0110, 0b0110, 0b0001],
|
264
|
+
"RVALE3" => [0b0110, 0b0110, 0b0101],
|
265
|
+
"ALLE3" => [0b0110, 0b0111, 0b0000],
|
266
|
+
"VAE3" => [0b0110, 0b0111, 0b0001],
|
267
|
+
"VALE3" => [0b0110, 0b0111, 0b0101],
|
268
|
+
}
|
269
|
+
def tlbi_op name
|
270
|
+
TLBI_OPTIONS.fetch(name.to_s.upcase)
|
271
|
+
end
|
272
|
+
module_function :tlbi_op
|
273
|
+
|
274
|
+
def prfop sym
|
275
|
+
if sym.to_s =~ /^(\w{3})(\w\w)(\w{4})$/
|
276
|
+
x = case $1
|
277
|
+
when "pld" then (0b00 << 3)
|
278
|
+
when "pli" then (0b01 << 3)
|
279
|
+
when "pst" then (0b10 << 3)
|
280
|
+
else
|
281
|
+
raise "unknown key #{$1}"
|
282
|
+
end
|
283
|
+
y = case $2
|
284
|
+
when "l1" then (0b00 << 1)
|
285
|
+
when "l2" then (0b01 << 1)
|
286
|
+
when "l3" then (0b10 << 1)
|
287
|
+
else
|
288
|
+
raise "unknown key #{$2}"
|
289
|
+
end
|
290
|
+
z = case $3
|
291
|
+
when "keep" then 0b0
|
292
|
+
when "strm" then 0b1
|
293
|
+
else
|
294
|
+
raise "unknown key #{$3}"
|
295
|
+
end
|
296
|
+
x | y | z
|
297
|
+
else
|
298
|
+
raise ArgumentError, sym.to_s
|
299
|
+
end
|
300
|
+
end
|
301
|
+
module_function :prfop
|
302
|
+
|
303
|
+
AT_TABLE = {
|
304
|
+
:s1e1r => { :op1 => 0b000, :crm => 0b1000, :op2 => 0b000 },
|
305
|
+
:s1e1w => { :op1 => 0b000, :crm => 0b1000, :op2 => 0b001 },
|
306
|
+
:s1e0r => { :op1 => 0b000, :crm => 0b1000, :op2 => 0b010 },
|
307
|
+
:s1e0w => { :op1 => 0b000, :crm => 0b1000, :op2 => 0b011 },
|
308
|
+
:s1e1rp => { :op1 => 0b000, :crm => 0b1001, :op2 => 0b000 },
|
309
|
+
:s1e1wp => { :op1 => 0b000, :crm => 0b1001, :op2 => 0b001 },
|
310
|
+
:s1e2r => { :op1 => 0b100, :crm => 0b1000, :op2 => 0b000 },
|
311
|
+
:s1e2w => { :op1 => 0b100, :crm => 0b1000, :op2 => 0b001 },
|
312
|
+
:s12e1r => { :op1 => 0b100, :crm => 0b1000, :op2 => 0b100 },
|
313
|
+
:s12e1w => { :op1 => 0b100, :crm => 0b1000, :op2 => 0b101 },
|
314
|
+
:s12e0r => { :op1 => 0b100, :crm => 0b1000, :op2 => 0b110 },
|
315
|
+
:s12e0w => { :op1 => 0b100, :crm => 0b1000, :op2 => 0b111 },
|
316
|
+
:s1e3r => { :op1 => 0b110, :crm => 0b1000, :op2 => 0b000 },
|
317
|
+
:s1e3w => { :op1 => 0b110, :crm => 0b1000, :op2 => 0b001 },
|
318
|
+
}
|
319
|
+
|
320
|
+
def at_op at_op
|
321
|
+
AT_TABLE.fetch at_op
|
322
|
+
end
|
323
|
+
module_function :at_op
|
324
|
+
end
|
325
|
+
end
|