ceedling 0.29.1 → 0.30.0

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Files changed (1267) hide show
  1. checksums.yaml +5 -5
  2. data/Gemfile +15 -16
  3. data/Gemfile.lock +1 -1
  4. data/README.md +108 -107
  5. data/Rakefile +11 -11
  6. data/assets/ceedling +3 -3
  7. data/assets/ceedling.cmd +0 -0
  8. data/assets/default_gitignore +5 -5
  9. data/assets/example_file.c +5 -5
  10. data/assets/example_file.h +6 -6
  11. data/assets/project_as_gem.yml +101 -97
  12. data/assets/project_with_guts.yml +102 -98
  13. data/assets/project_with_guts_gcov.yml +102 -98
  14. data/assets/project_with_guts_gcov_abortonuncovered.yml +93 -0
  15. data/assets/test_example_file.c +13 -13
  16. data/assets/test_example_file_boom.c +13 -13
  17. data/assets/test_example_file_success.c +14 -14
  18. data/assets/test_example_file_verbose.c +12 -12
  19. data/assets/uncovered_example_file.c +5 -0
  20. data/bin/ceedling +351 -339
  21. data/ceedling.gemspec +52 -36
  22. data/config/test_environment.rb +11 -11
  23. data/docs/Ceedling Basic Porting.pdf +0 -0
  24. data/docs/Ceedling Managing Release Code.pdf +0 -0
  25. data/docs/Ceedling Powerful Plugins.pdf +0 -0
  26. data/docs/Ceedling Working with IDEs.pdf +0 -0
  27. data/docs/CeedlingPacket.md +2213 -2134
  28. data/docs/CeedlingUpgrade.md +83 -83
  29. data/docs/ThrowTheSwitchCodingStandard.md +207 -207
  30. data/examples/blinky/project.yml +99 -99
  31. data/examples/blinky/rakefile.rb +31 -31
  32. data/examples/blinky/src/BlinkTask.c +21 -21
  33. data/examples/blinky/src/BlinkTask.h +6 -6
  34. data/examples/blinky/src/Configure.c +36 -36
  35. data/examples/blinky/src/Configure.h +6 -6
  36. data/examples/blinky/src/main.c +51 -51
  37. data/examples/blinky/src/main.h +9 -9
  38. data/examples/blinky/test/support/stub_interrupt.h +347 -347
  39. data/examples/blinky/test/support/stub_io.h +421 -421
  40. data/examples/blinky/test/support/stub_iom328p.h +883 -883
  41. data/examples/blinky/test/support/stub_sfr_defs.h +269 -269
  42. data/examples/blinky/test/test_BlinkTask.c +42 -42
  43. data/examples/blinky/test/test_Configure.c +29 -29
  44. data/examples/blinky/test/test_main.c +60 -60
  45. data/examples/temp_sensor/project.yml +66 -76
  46. data/examples/temp_sensor/rakefile.rb +6 -6
  47. data/examples/temp_sensor/src/AdcConductor.c +42 -42
  48. data/examples/temp_sensor/src/AdcConductor.h +13 -13
  49. data/examples/temp_sensor/src/AdcHardware.c +27 -27
  50. data/examples/temp_sensor/src/AdcHardware.h +11 -11
  51. data/examples/temp_sensor/src/AdcHardwareConfigurator.c +18 -18
  52. data/examples/temp_sensor/src/AdcHardwareConfigurator.h +10 -10
  53. data/examples/temp_sensor/src/AdcModel.c +33 -33
  54. data/examples/temp_sensor/src/AdcModel.h +13 -13
  55. data/examples/temp_sensor/src/AdcTemperatureSensor.c +51 -51
  56. data/examples/temp_sensor/src/AdcTemperatureSensor.h +10 -10
  57. data/examples/temp_sensor/src/Executor.c +25 -25
  58. data/examples/temp_sensor/src/Executor.h +9 -9
  59. data/examples/temp_sensor/src/IntrinsicsWrapper.c +18 -18
  60. data/examples/temp_sensor/src/IntrinsicsWrapper.h +7 -7
  61. data/examples/temp_sensor/src/Main.c +46 -46
  62. data/examples/temp_sensor/src/Main.h +7 -7
  63. data/examples/temp_sensor/src/Model.c +10 -10
  64. data/examples/temp_sensor/src/Model.h +8 -8
  65. data/examples/temp_sensor/src/ModelConfig.h +7 -7
  66. data/examples/temp_sensor/src/TaskScheduler.c +72 -72
  67. data/examples/temp_sensor/src/TaskScheduler.h +11 -11
  68. data/examples/temp_sensor/src/TemperatureCalculator.c +27 -27
  69. data/examples/temp_sensor/src/TemperatureCalculator.h +8 -8
  70. data/examples/temp_sensor/src/TemperatureFilter.c +38 -38
  71. data/examples/temp_sensor/src/TemperatureFilter.h +10 -10
  72. data/examples/temp_sensor/src/TimerConductor.c +15 -15
  73. data/examples/temp_sensor/src/TimerConductor.h +9 -9
  74. data/examples/temp_sensor/src/TimerConfigurator.c +51 -51
  75. data/examples/temp_sensor/src/TimerConfigurator.h +15 -15
  76. data/examples/temp_sensor/src/TimerHardware.c +15 -15
  77. data/examples/temp_sensor/src/TimerHardware.h +8 -8
  78. data/examples/temp_sensor/src/TimerInterruptConfigurator.c +55 -55
  79. data/examples/temp_sensor/src/TimerInterruptConfigurator.h +13 -13
  80. data/examples/temp_sensor/src/TimerInterruptHandler.c +25 -25
  81. data/examples/temp_sensor/src/TimerInterruptHandler.h +10 -10
  82. data/examples/temp_sensor/src/TimerModel.c +9 -9
  83. data/examples/temp_sensor/src/TimerModel.h +8 -8
  84. data/examples/temp_sensor/src/Types.h +90 -90
  85. data/examples/temp_sensor/src/UsartBaudRateRegisterCalculator.c +18 -18
  86. data/examples/temp_sensor/src/UsartBaudRateRegisterCalculator.h +8 -8
  87. data/examples/temp_sensor/src/UsartConductor.c +21 -21
  88. data/examples/temp_sensor/src/UsartConductor.h +7 -7
  89. data/examples/temp_sensor/src/UsartConfigurator.c +39 -39
  90. data/examples/temp_sensor/src/UsartConfigurator.h +13 -13
  91. data/examples/temp_sensor/src/UsartHardware.c +22 -22
  92. data/examples/temp_sensor/src/UsartHardware.h +9 -9
  93. data/examples/temp_sensor/src/UsartModel.c +34 -34
  94. data/examples/temp_sensor/src/UsartModel.h +10 -10
  95. data/examples/temp_sensor/src/UsartPutChar.c +16 -16
  96. data/examples/temp_sensor/src/UsartPutChar.h +8 -8
  97. data/examples/temp_sensor/src/UsartTransmitBufferStatus.c +7 -7
  98. data/examples/temp_sensor/src/UsartTransmitBufferStatus.h +8 -8
  99. data/examples/temp_sensor/test/TestAdcConductor.c +121 -121
  100. data/examples/temp_sensor/test/TestAdcHardware.c +44 -44
  101. data/examples/temp_sensor/test/TestAdcModel.c +33 -33
  102. data/examples/temp_sensor/test/TestExecutor.c +36 -36
  103. data/examples/temp_sensor/test/TestMain.c +24 -24
  104. data/examples/temp_sensor/test/TestModel.c +20 -20
  105. data/examples/temp_sensor/test/TestTaskScheduler.c +104 -104
  106. data/examples/temp_sensor/test/TestTemperatureCalculator.c +36 -36
  107. data/examples/temp_sensor/test/TestTemperatureFilter.c +79 -79
  108. data/examples/temp_sensor/test/TestTimerConductor.c +32 -32
  109. data/examples/temp_sensor/test/TestTimerHardware.c +26 -26
  110. data/examples/temp_sensor/test/TestTimerModel.c +18 -18
  111. data/examples/temp_sensor/test/TestUsartBaudRateRegisterCalculator.c +21 -21
  112. data/examples/temp_sensor/test/TestUsartConductor.c +40 -40
  113. data/examples/temp_sensor/test/TestUsartHardware.c +36 -36
  114. data/examples/temp_sensor/test/TestUsartModel.c +40 -40
  115. data/examples/temp_sensor/test/support/UnityHelper.c +12 -12
  116. data/examples/temp_sensor/test/support/UnityHelper.h +12 -12
  117. data/lib/ceedling.rb +99 -99
  118. data/lib/ceedling/build_invoker_utils.rb +39 -39
  119. data/lib/ceedling/cacheinator.rb +47 -47
  120. data/lib/ceedling/cacheinator_helper.rb +35 -31
  121. data/lib/ceedling/cmock_builder.rb +15 -15
  122. data/lib/ceedling/configurator.rb +372 -363
  123. data/lib/ceedling/configurator_builder.rb +463 -458
  124. data/lib/ceedling/configurator_plugins.rb +111 -111
  125. data/lib/ceedling/configurator_setup.rb +127 -127
  126. data/lib/ceedling/configurator_validator.rb +193 -193
  127. data/lib/ceedling/constants.rb +99 -97
  128. data/lib/ceedling/defaults.rb +447 -418
  129. data/lib/ceedling/dependinator.rb +97 -98
  130. data/lib/ceedling/erb_wrapper.rb +8 -8
  131. data/lib/ceedling/file_finder.rb +149 -149
  132. data/lib/ceedling/file_finder_helper.rb +56 -54
  133. data/lib/ceedling/file_path_utils.rb +202 -200
  134. data/lib/ceedling/file_system_utils.rb +69 -69
  135. data/lib/ceedling/file_system_wrapper.rb +9 -9
  136. data/lib/ceedling/file_wrapper.rb +83 -83
  137. data/lib/ceedling/flaginator.rb +74 -74
  138. data/lib/ceedling/generator.rb +186 -183
  139. data/lib/ceedling/generator_helper.rb +40 -40
  140. data/lib/ceedling/generator_test_results.rb +100 -100
  141. data/lib/ceedling/generator_test_results_sanity_checker.rb +65 -65
  142. data/lib/ceedling/generator_test_runner.rb +58 -56
  143. data/lib/ceedling/loginator.rb +31 -31
  144. data/lib/ceedling/makefile.rb +46 -46
  145. data/lib/ceedling/objects.yml +311 -310
  146. data/lib/ceedling/par_map.rb +19 -19
  147. data/lib/ceedling/plugin.rb +80 -80
  148. data/lib/ceedling/plugin_builder.rb +52 -52
  149. data/lib/ceedling/plugin_manager.rb +107 -107
  150. data/lib/ceedling/plugin_manager_helper.rb +19 -19
  151. data/lib/ceedling/plugin_reportinator.rb +76 -76
  152. data/lib/ceedling/plugin_reportinator_helper.rb +51 -51
  153. data/lib/ceedling/preprocessinator.rb +47 -42
  154. data/lib/ceedling/preprocessinator_extractor.rb +30 -30
  155. data/lib/ceedling/preprocessinator_file_handler.rb +21 -21
  156. data/lib/ceedling/preprocessinator_helper.rb +50 -46
  157. data/lib/ceedling/preprocessinator_includes_handler.rb +181 -181
  158. data/lib/ceedling/project_config_manager.rb +52 -46
  159. data/lib/ceedling/project_file_loader.rb +99 -99
  160. data/lib/ceedling/rake_utils.rb +17 -17
  161. data/lib/ceedling/rake_wrapper.rb +33 -33
  162. data/lib/ceedling/rakefile.rb +86 -86
  163. data/lib/ceedling/release_invoker.rb +98 -73
  164. data/lib/ceedling/release_invoker_helper.rb +19 -19
  165. data/lib/ceedling/reportinator.rb +26 -26
  166. data/lib/ceedling/rules_cmock.rake +9 -9
  167. data/lib/ceedling/rules_preprocess.rake +26 -26
  168. data/lib/ceedling/rules_release.rake +99 -86
  169. data/lib/ceedling/rules_release_deep_dependencies.rake +15 -15
  170. data/lib/ceedling/rules_tests.rake +73 -74
  171. data/lib/ceedling/rules_tests_deep_dependencies.rake +15 -15
  172. data/lib/ceedling/setupinator.rb +53 -53
  173. data/lib/ceedling/stream_wrapper.rb +28 -28
  174. data/lib/ceedling/streaminator.rb +40 -40
  175. data/lib/ceedling/streaminator_helper.rb +15 -15
  176. data/lib/ceedling/system_utils.rb +37 -37
  177. data/lib/ceedling/system_wrapper.rb +80 -80
  178. data/lib/ceedling/target_loader.rb +38 -38
  179. data/lib/ceedling/task_invoker.rb +122 -117
  180. data/lib/ceedling/tasks_base.rake +116 -105
  181. data/lib/ceedling/tasks_filesystem.rake +113 -112
  182. data/lib/ceedling/tasks_release.rake +30 -30
  183. data/lib/ceedling/tasks_release_deep_dependencies.rake +9 -9
  184. data/lib/ceedling/tasks_tests.rake +60 -60
  185. data/lib/ceedling/tasks_tests_deep_dependencies.rake +9 -9
  186. data/lib/ceedling/tasks_vendor.rake +35 -35
  187. data/lib/ceedling/test_includes_extractor.rb +111 -85
  188. data/lib/ceedling/test_invoker.rb +164 -188
  189. data/lib/ceedling/test_invoker_helper.rb +32 -32
  190. data/lib/ceedling/tool_executor.rb +229 -229
  191. data/lib/ceedling/tool_executor_helper.rb +164 -164
  192. data/lib/ceedling/verbosinator.rb +10 -10
  193. data/lib/ceedling/version.rb +50 -50
  194. data/lib/ceedling/yaml_wrapper.rb +17 -17
  195. data/license.txt +31 -31
  196. data/plugins/beep/README.md +22 -22
  197. data/plugins/beep/lib/beep.rb +40 -40
  198. data/plugins/bullseye/README.md +76 -0
  199. data/plugins/bullseye/assets/template.erb +15 -15
  200. data/plugins/bullseye/bullseye.rake +173 -169
  201. data/plugins/bullseye/config/defaults.yml +57 -57
  202. data/plugins/bullseye/lib/bullseye.rb +194 -194
  203. data/plugins/colour_report/README.md +20 -0
  204. data/plugins/colour_report/lib/colour_report.rb +16 -16
  205. data/plugins/command_hooks/README.md +53 -53
  206. data/plugins/command_hooks/lib/command_hooks.rb +92 -92
  207. data/plugins/compile_commands_json/README.md +29 -0
  208. data/plugins/compile_commands_json/lib/compile_commands_json.rb +35 -0
  209. data/plugins/dependencies/README.md +254 -0
  210. data/plugins/dependencies/config/defaults.yml +5 -0
  211. data/plugins/dependencies/dependencies.rake +144 -0
  212. data/plugins/dependencies/lib/dependencies.rb +231 -0
  213. data/plugins/fake_function_framework/README.md +250 -250
  214. data/plugins/fake_function_framework/Rakefile +18 -18
  215. data/plugins/fake_function_framework/examples/fff_example/project.yml +71 -71
  216. data/plugins/fake_function_framework/examples/fff_example/rakefile.rb +7 -7
  217. data/plugins/fake_function_framework/examples/fff_example/src/bar.c +1 -1
  218. data/plugins/fake_function_framework/examples/fff_example/src/bar.h +14 -14
  219. data/plugins/fake_function_framework/examples/fff_example/src/custom_types.h +6 -6
  220. data/plugins/fake_function_framework/examples/fff_example/src/display.c +6 -6
  221. data/plugins/fake_function_framework/examples/fff_example/src/display.h +16 -16
  222. data/plugins/fake_function_framework/examples/fff_example/src/event_processor.c +93 -93
  223. data/plugins/fake_function_framework/examples/fff_example/src/event_processor.h +11 -11
  224. data/plugins/fake_function_framework/examples/fff_example/src/foo.c +16 -16
  225. data/plugins/fake_function_framework/examples/fff_example/src/foo.h +8 -8
  226. data/plugins/fake_function_framework/examples/fff_example/src/subfolder/zzz.c +1 -1
  227. data/plugins/fake_function_framework/examples/fff_example/src/subfolder/zzz.h +6 -6
  228. data/plugins/fake_function_framework/examples/fff_example/test/test_event_processor.c +155 -155
  229. data/plugins/fake_function_framework/examples/fff_example/test/test_foo.c +47 -47
  230. data/plugins/fake_function_framework/lib/fake_function_framework.rb +87 -87
  231. data/plugins/fake_function_framework/lib/fff_mock_generator.rb +163 -163
  232. data/plugins/fake_function_framework/spec/fff_mock_header_generator_spec.rb +304 -304
  233. data/plugins/fake_function_framework/spec/fff_mock_source_generator_spec.rb +148 -148
  234. data/plugins/fake_function_framework/spec/header_generator.rb +50 -50
  235. data/plugins/fake_function_framework/spec/spec_helper.rb +96 -96
  236. data/plugins/fake_function_framework/src/fff_unity_helper.h +32 -32
  237. data/plugins/gcov/README.md +412 -101
  238. data/plugins/gcov/assets/template.erb +15 -15
  239. data/plugins/gcov/config/defaults.yml +51 -73
  240. data/plugins/gcov/gcov.rake +209 -220
  241. data/plugins/gcov/lib/gcov.rb +133 -113
  242. data/plugins/gcov/lib/gcov_constants.rb +48 -19
  243. data/plugins/gcov/lib/gcovr_reportinator.rb +331 -0
  244. data/plugins/gcov/lib/reportgenerator_reportinator.rb +153 -0
  245. data/plugins/gcov/lib/reportinator_helper.rb +15 -0
  246. data/plugins/json_tests_report/README.md +36 -0
  247. data/plugins/json_tests_report/lib/json_tests_report.rb +83 -0
  248. data/plugins/junit_tests_report/README.md +36 -36
  249. data/plugins/junit_tests_report/lib/junit_tests_report.rb +134 -130
  250. data/plugins/module_generator/README.md +105 -0
  251. data/plugins/module_generator/config/module_generator.yml +3 -3
  252. data/plugins/module_generator/lib/module_generator.rb +79 -70
  253. data/plugins/module_generator/module_generator.rake +62 -47
  254. data/plugins/raw_output_report/README.md +19 -0
  255. data/plugins/raw_output_report/lib/raw_output_report.rb +41 -41
  256. data/plugins/stdout_gtestlike_tests_report/README.md +19 -0
  257. data/plugins/stdout_gtestlike_tests_report/assets/template.erb +84 -84
  258. data/plugins/stdout_gtestlike_tests_report/assets/template.erb copy +59 -59
  259. data/plugins/stdout_gtestlike_tests_report/config/stdout_gtestlike_tests_report.yml +4 -4
  260. data/plugins/stdout_gtestlike_tests_report/lib/stdout_gtestlike_tests_report.rb +43 -43
  261. data/plugins/stdout_ide_tests_report/README.md +18 -0
  262. data/plugins/stdout_ide_tests_report/config/stdout_ide_tests_report.yml +4 -4
  263. data/plugins/stdout_ide_tests_report/lib/stdout_ide_tests_report.rb +44 -44
  264. data/plugins/stdout_pretty_tests_report/README.md +20 -0
  265. data/plugins/stdout_pretty_tests_report/assets/template.erb +59 -59
  266. data/plugins/stdout_pretty_tests_report/config/stdout_pretty_tests_report.yml +4 -4
  267. data/plugins/stdout_pretty_tests_report/lib/stdout_pretty_tests_report.rb +47 -47
  268. data/plugins/subprojects/README.md +63 -63
  269. data/plugins/subprojects/config/defaults.yml +33 -33
  270. data/plugins/subprojects/lib/subprojects.rb +92 -92
  271. data/plugins/subprojects/subprojects.rake +78 -78
  272. data/plugins/teamcity_tests_report/README.md +18 -0
  273. data/plugins/teamcity_tests_report/config/teamcity_tests_report.yml +4 -4
  274. data/plugins/teamcity_tests_report/lib/teamcity_tests_report.rb +57 -57
  275. data/plugins/warnings_report/README.md +19 -0
  276. data/plugins/warnings_report/lib/warnings_report.rb +69 -69
  277. data/plugins/xml_tests_report/README.md +36 -36
  278. data/plugins/xml_tests_report/lib/xml_tests_report.rb +110 -110
  279. data/spec/build_invoker_utils_spec.rb +54 -54
  280. data/spec/ceedling_spec.rb +154 -154
  281. data/spec/configurator_builder_spec.rb +6 -6
  282. data/spec/configurator_helper_spec.rb +4 -4
  283. data/spec/configurator_spec.rb +9 -9
  284. data/spec/file_finder_helper_spec.rb +53 -53
  285. data/spec/gcov/gcov_deployment_spec.rb +72 -70
  286. data/spec/gcov/gcov_test_cases_spec.rb +128 -91
  287. data/spec/generator_test_results_sanity_checker_spec.rb +88 -88
  288. data/spec/generator_test_results_spec.rb +107 -107
  289. data/spec/par_map_spec.rb +57 -57
  290. data/spec/preprocessinator_extractor_spec.rb +45 -45
  291. data/spec/preprocessinator_includes_handler_spec.rb +202 -202
  292. data/spec/reportinator_spec.rb +19 -19
  293. data/spec/spec_helper.rb +27 -27
  294. data/spec/spec_system_helper.rb +616 -615
  295. data/spec/support/test_example.fail +24 -24
  296. data/spec/support/test_example.pass +24 -24
  297. data/spec/support/test_example_empty.pass +14 -14
  298. data/spec/support/test_example_ignore.pass +24 -24
  299. data/spec/support/test_example_mangled.pass +21 -21
  300. data/spec/support/test_example_with_time.pass +24 -24
  301. data/spec/system/deployment_spec.rb +225 -225
  302. data/spec/system_utils_spec.rb +56 -56
  303. data/spec/target_loader_spec.rb +30 -30
  304. data/spec/tool_executor_helper_spec.rb +310 -310
  305. data/spec/uncatagorized_specs_spec.rb +8 -8
  306. data/vendor/behaviors/Manifest.txt +9 -9
  307. data/vendor/behaviors/Rakefile +19 -19
  308. data/vendor/behaviors/lib/behaviors.rb +76 -76
  309. data/vendor/behaviors/lib/behaviors/reporttask.rb +158 -158
  310. data/vendor/behaviors/test/behaviors_tasks_test.rb +73 -73
  311. data/vendor/behaviors/test/behaviors_test.rb +50 -50
  312. data/vendor/behaviors/test/tasks_test/Rakefile +19 -19
  313. data/vendor/behaviors/test/tasks_test/lib/user.rb +2 -2
  314. data/vendor/behaviors/test/tasks_test/test/user_test.rb +17 -17
  315. data/vendor/c_exception/Gemfile +4 -4
  316. data/vendor/c_exception/Gemfile.lock +12 -12
  317. data/vendor/c_exception/README.md +249 -162
  318. data/vendor/c_exception/docs/CException.md +332 -292
  319. data/vendor/c_exception/docs/ThrowTheSwitchCodingStandard.md +207 -207
  320. data/vendor/c_exception/lib/CException.c +46 -46
  321. data/vendor/c_exception/lib/CException.h +115 -115
  322. data/vendor/c_exception/lib/meson.build +11 -0
  323. data/vendor/c_exception/meson.build +48 -0
  324. data/vendor/c_exception/project.yml +37 -0
  325. data/vendor/c_exception/test/TestException.c +391 -391
  326. data/vendor/{cmock/vendor/c_exception/test → c_exception/test/support}/CExceptionConfig.h +46 -46
  327. data/vendor/c_exception/vendor/unity/README.md +220 -220
  328. data/vendor/c_exception/vendor/unity/auto/colour_prompt.rb +118 -118
  329. data/vendor/c_exception/vendor/unity/auto/colour_reporter.rb +39 -39
  330. data/vendor/c_exception/vendor/unity/auto/generate_config.yml +36 -36
  331. data/vendor/c_exception/vendor/unity/auto/generate_module.rb +308 -308
  332. data/vendor/c_exception/vendor/unity/auto/generate_test_runner.rb +437 -437
  333. data/vendor/c_exception/vendor/unity/auto/parse_output.rb +220 -220
  334. data/vendor/c_exception/vendor/unity/auto/stylize_as_junit.rb +252 -252
  335. data/vendor/c_exception/vendor/unity/auto/test_file_filter.rb +25 -25
  336. data/vendor/c_exception/vendor/unity/auto/type_sanitizer.rb +6 -6
  337. data/vendor/c_exception/vendor/unity/auto/unity_test_summary.py +139 -139
  338. data/vendor/c_exception/vendor/unity/auto/unity_test_summary.rb +136 -136
  339. data/vendor/c_exception/vendor/unity/auto/unity_to_junit.py +146 -146
  340. data/vendor/c_exception/vendor/unity/docs/ThrowTheSwitchCodingStandard.md +207 -207
  341. data/vendor/c_exception/vendor/unity/docs/UnityAssertionsReference.md +716 -716
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data/examples/blinky/test/support/stub_iom328p.h CHANGED
@@ -1,883 +1,883 @@
1
- /* Copyright (c) 2007 Atmel Corporation
2
- All rights reserved.
3
-
4
- Redistribution and use in source and binary forms, with or without
5
- modification, are permitted provided that the following conditions are met:
6
-
7
- * Redistributions of source code must retain the above copyright
8
- notice, this list of conditions and the following disclaimer.
9
-
10
- * Redistributions in binary form must reproduce the above copyright
11
- notice, this list of conditions and the following disclaimer in
12
- the documentation and/or other materials provided with the
13
- distribution.
14
-
15
- * Neither the name of the copyright holders nor the names of
16
- contributors may be used to endorse or promote products derived
17
- from this software without specific prior written permission.
18
-
19
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22
- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29
- POSSIBILITY OF SUCH DAMAGE.
30
- */
31
-
32
- /* $Id: iom328p.h,v 1.3.2.14 2009/02/11 18:05:28 arcanum Exp $ */
33
-
34
- /* avr/iom328p.h - definitions for ATmega328P. */
35
-
36
- /* This file should only be included from <avr/io.h>, never directly. */
37
-
38
- // #ifndef _AVR_IO_H_
39
- // # error "Include <avr/io.h> instead of this file."
40
- // #endif
41
-
42
- // #ifndef _AVR_IOXXX_H_
43
- // # define _AVR_IOXXX_H_ "iom328p.h"
44
- // #else
45
- // # error "Attempt to include more than one <avr/ioXXX.h> file."
46
- // #endif
47
-
48
-
49
- #ifndef _AVR_IOM328P_H_
50
- #define _AVR_IOM328P_H_ 1
51
-
52
- /* Registers and associated bit numbers */
53
-
54
- // #define PINB _SFR_IO8(0x03)
55
- // #define PINB0 0
56
- // #define PINB1 1
57
- // #define PINB2 2
58
- // #define PINB3 3
59
- // #define PINB4 4
60
- // #define PINB5 5
61
- // #define PINB6 6
62
- // #define PINB7 7
63
-
64
- // #define DDRB _SFR_IO8(0x04)
65
- char DDRB;
66
- #define DDB0 0
67
- #define DDB1 1
68
- #define DDB2 2
69
- #define DDB3 3
70
- #define DDB4 4
71
- #define DDB5 5
72
- #define DDB6 6
73
- #define DDB7 7
74
-
75
- // #define PORTB _SFR_IO8(0x05)
76
- char PORTB;
77
- #define PORTB0 0
78
- #define PORTB1 1
79
- #define PORTB2 2
80
- #define PORTB3 3
81
- #define PORTB4 4
82
- #define PORTB5 5
83
- #define PORTB6 6
84
- #define PORTB7 7
85
-
86
- // #define PINC _SFR_IO8(0x06)
87
- // #define PINC0 0
88
- // #define PINC1 1
89
- // #define PINC2 2
90
- // #define PINC3 3
91
- // #define PINC4 4
92
- // #define PINC5 5
93
- // #define PINC6 6
94
-
95
- // #define DDRC _SFR_IO8(0x07)
96
- // #define DDC0 0
97
- // #define DDC1 1
98
- // #define DDC2 2
99
- // #define DDC3 3
100
- // #define DDC4 4
101
- // #define DDC5 5
102
- // #define DDC6 6
103
-
104
- // #define PORTC _SFR_IO8(0x08)
105
- // #define PORTC0 0
106
- // #define PORTC1 1
107
- // #define PORTC2 2
108
- // #define PORTC3 3
109
- // #define PORTC4 4
110
- // #define PORTC5 5
111
- // #define PORTC6 6
112
-
113
- // #define PIND _SFR_IO8(0x09)
114
- char PIND;
115
- #define PIND0 0
116
- #define PIND1 1
117
- #define PIND2 2
118
- #define PIND3 3
119
- #define PIND4 4
120
- #define PIND5 5
121
- #define PIND6 6
122
- #define PIND7 7
123
-
124
- // #define DDRD _SFR_IO8(0x0A)
125
- char DDRD;
126
- #define DDD0 0
127
- #define DDD1 1
128
- #define DDD2 2
129
- #define DDD3 3
130
- #define DDD4 4
131
- #define DDD5 5
132
- #define DDD6 6
133
- #define DDD7 7
134
-
135
- // #define PORTD _SFR_IO8(0x0B)
136
- char PORTD;
137
- #define PORTD0 0
138
- #define PORTD1 1
139
- #define PORTD2 2
140
- #define PORTD3 3
141
- #define PORTD4 4
142
- #define PORTD5 5
143
- #define PORTD6 6
144
- #define PORTD7 7
145
-
146
- // #define TIFR0 _SFR_IO8(0x15)
147
- // #define TOV0 0
148
- // #define OCF0A 1
149
- // #define OCF0B 2
150
-
151
- // #define TIFR1 _SFR_IO8(0x16)
152
- // #define TOV1 0
153
- // #define OCF1A 1
154
- // #define OCF1B 2
155
- // #define ICF1 5
156
-
157
- // #define TIFR2 _SFR_IO8(0x17)
158
- // #define TOV2 0
159
- // #define OCF2A 1
160
- // #define OCF2B 2
161
-
162
- // #define PCIFR _SFR_IO8(0x1B)
163
- // #define PCIF0 0
164
- // #define PCIF1 1
165
- // #define PCIF2 2
166
-
167
- // #define EIFR _SFR_IO8(0x1C)
168
- // #define INTF0 0
169
- // #define INTF1 1
170
-
171
- // #define EIMSK _SFR_IO8(0x1D)
172
- // #define INT0 0
173
- // #define INT1 1
174
-
175
- // #define GPIOR0 _SFR_IO8(0x1E)
176
- // #define GPIOR00 0
177
- // #define GPIOR01 1
178
- // #define GPIOR02 2
179
- // #define GPIOR03 3
180
- // #define GPIOR04 4
181
- // #define GPIOR05 5
182
- // #define GPIOR06 6
183
- // #define GPIOR07 7
184
-
185
- // #define EECR _SFR_IO8(0x1F)
186
- // #define EERE 0
187
- // #define EEPE 1
188
- // #define EEMPE 2
189
- // #define EERIE 3
190
- // #define EEPM0 4
191
- // #define EEPM1 5
192
-
193
- // #define EEDR _SFR_IO8(0x20)
194
- // #define EEDR0 0
195
- // #define EEDR1 1
196
- // #define EEDR2 2
197
- // #define EEDR3 3
198
- // #define EEDR4 4
199
- // #define EEDR5 5
200
- // #define EEDR6 6
201
- // #define EEDR7 7
202
-
203
- // #define EEAR _SFR_IO16(0x21)
204
-
205
- // #define EEARL _SFR_IO8(0x21)
206
- // #define EEAR0 0
207
- // #define EEAR1 1
208
- // #define EEAR2 2
209
- // #define EEAR3 3
210
- // #define EEAR4 4
211
- // #define EEAR5 5
212
- // #define EEAR6 6
213
- // #define EEAR7 7
214
-
215
- // #define EEARH _SFR_IO8(0x22)
216
- // #define EEAR8 0
217
- // #define EEAR9 1
218
-
219
- // #define _EEPROM_REG_LOCATIONS_ 1F2021
220
-
221
- // #define GTCCR _SFR_IO8(0x23)
222
- // #define PSRSYNC 0
223
- // #define PSRASY 1
224
- // #define TSM 7
225
-
226
- // #define TCCR0A _SFR_IO8(0x24)
227
- // #define WGM00 0
228
- // #define WGM01 1
229
- // #define COM0B0 4
230
- // #define COM0B1 5
231
- // #define COM0A0 6
232
- // #define COM0A1 7
233
-
234
- // #define TCCR0B _SFR_IO8(0x25)
235
- char TCCR0B;
236
- #define CS00 0
237
- #define CS01 1
238
- #define CS02 2
239
- #define WGM02 3
240
- #define FOC0B 6
241
- #define FOC0A 7
242
-
243
- // #define TCNT0 _SFR_IO8(0x26)
244
- char TCNT0;
245
- #define TCNT0_0 0
246
- #define TCNT0_1 1
247
- #define TCNT0_2 2
248
- #define TCNT0_3 3
249
- #define TCNT0_4 4
250
- #define TCNT0_5 5
251
- #define TCNT0_6 6
252
- #define TCNT0_7 7
253
-
254
- // #define OCR0A _SFR_IO8(0x27)
255
- // #define OCR0A_0 0
256
- // #define OCR0A_1 1
257
- // #define OCR0A_2 2
258
- // #define OCR0A_3 3
259
- // #define OCR0A_4 4
260
- // #define OCR0A_5 5
261
- // #define OCR0A_6 6
262
- // #define OCR0A_7 7
263
-
264
- // #define OCR0B _SFR_IO8(0x28)
265
- // #define OCR0B_0 0
266
- // #define OCR0B_1 1
267
- // #define OCR0B_2 2
268
- // #define OCR0B_3 3
269
- // #define OCR0B_4 4
270
- // #define OCR0B_5 5
271
- // #define OCR0B_6 6
272
- // #define OCR0B_7 7
273
-
274
- // #define GPIOR1 _SFR_IO8(0x2A)
275
- // #define GPIOR10 0
276
- // #define GPIOR11 1
277
- // #define GPIOR12 2
278
- // #define GPIOR13 3
279
- // #define GPIOR14 4
280
- // #define GPIOR15 5
281
- // #define GPIOR16 6
282
- // #define GPIOR17 7
283
-
284
- // #define GPIOR2 _SFR_IO8(0x2B)
285
- // #define GPIOR20 0
286
- // #define GPIOR21 1
287
- // #define GPIOR22 2
288
- // #define GPIOR23 3
289
- // #define GPIOR24 4
290
- // #define GPIOR25 5
291
- // #define GPIOR26 6
292
- // #define GPIOR27 7
293
-
294
- // #define SPCR _SFR_IO8(0x2C)
295
- // #define SPR0 0
296
- // #define SPR1 1
297
- // #define CPHA 2
298
- // #define CPOL 3
299
- // #define MSTR 4
300
- // #define DORD 5
301
- // #define SPE 6
302
- // #define SPIE 7
303
-
304
- // #define SPSR _SFR_IO8(0x2D)
305
- // #define SPI2X 0
306
- // #define WCOL 6
307
- // #define SPIF 7
308
-
309
- // #define SPDR _SFR_IO8(0x2E)
310
- // #define SPDR0 0
311
- // #define SPDR1 1
312
- // #define SPDR2 2
313
- // #define SPDR3 3
314
- // #define SPDR4 4
315
- // #define SPDR5 5
316
- // #define SPDR6 6
317
- // #define SPDR7 7
318
-
319
- // #define ACSR _SFR_IO8(0x30)
320
- // #define ACIS0 0
321
- // #define ACIS1 1
322
- // #define ACIC 2
323
- // #define ACIE 3
324
- // #define ACI 4
325
- // #define ACO 5
326
- // #define ACBG 6
327
- // #define ACD 7
328
-
329
- // #define SMCR _SFR_IO8(0x33)
330
- // #define SE 0
331
- // #define SM0 1
332
- // #define SM1 2
333
- // #define SM2 3
334
-
335
- // #define MCUSR _SFR_IO8(0x34)
336
- // #define PORF 0
337
- // #define EXTRF 1
338
- // #define BORF 2
339
- // #define WDRF 3
340
-
341
- // #define MCUCR _SFR_IO8(0x35)
342
- // #define IVCE 0
343
- // #define IVSEL 1
344
- // #define PUD 4
345
- // #define BODSE 5
346
- // #define BODS 6
347
-
348
- // #define SPMCSR _SFR_IO8(0x37)
349
- // #define SELFPRGEN 0
350
- // #define PGERS 1
351
- // #define PGWRT 2
352
- // #define BLBSET 3
353
- // #define RWWSRE 4
354
- // #define RWWSB 6
355
- // #define SPMIE 7
356
-
357
- // #define WDTCSR _SFR_MEM8(0x60)
358
- // #define WDP0 0
359
- // #define WDP1 1
360
- // #define WDP2 2
361
- // #define WDE 3
362
- // #define WDCE 4
363
- // #define WDP3 5
364
- // #define WDIE 6
365
- // #define WDIF 7
366
-
367
- // #define CLKPR _SFR_MEM8(0x61)
368
- // #define CLKPS0 0
369
- // #define CLKPS1 1
370
- // #define CLKPS2 2
371
- // #define CLKPS3 3
372
- // #define CLKPCE 7
373
-
374
- // #define PRR _SFR_MEM8(0x64)
375
- // #define PRADC 0
376
- // #define PRUSART0 1
377
- // #define PRSPI 2
378
- // #define PRTIM1 3
379
- // #define PRTIM0 5
380
- // #define PRTIM2 6
381
- // #define PRTWI 7
382
-
383
- // #define OSCCAL _SFR_MEM8(0x66)
384
- // #define CAL0 0
385
- // #define CAL1 1
386
- // #define CAL2 2
387
- // #define CAL3 3
388
- // #define CAL4 4
389
- // #define CAL5 5
390
- // #define CAL6 6
391
- // #define CAL7 7
392
-
393
- // #define PCICR _SFR_MEM8(0x68)
394
- // #define PCIE0 0
395
- // #define PCIE1 1
396
- // #define PCIE2 2
397
-
398
- // #define EICRA _SFR_MEM8(0x69)
399
- // #define ISC00 0
400
- // #define ISC01 1
401
- // #define ISC10 2
402
- // #define ISC11 3
403
-
404
- // #define PCMSK0 _SFR_MEM8(0x6B)
405
- // #define PCINT0 0
406
- // #define PCINT1 1
407
- // #define PCINT2 2
408
- // #define PCINT3 3
409
- // #define PCINT4 4
410
- // #define PCINT5 5
411
- // #define PCINT6 6
412
- // #define PCINT7 7
413
-
414
- // #define PCMSK1 _SFR_MEM8(0x6C)
415
- // #define PCINT8 0
416
- // #define PCINT9 1
417
- // #define PCINT10 2
418
- // #define PCINT11 3
419
- // #define PCINT12 4
420
- // #define PCINT13 5
421
- // #define PCINT14 6
422
-
423
- // #define PCMSK2 _SFR_MEM8(0x6D)
424
- // #define PCINT16 0
425
- // #define PCINT17 1
426
- // #define PCINT18 2
427
- // #define PCINT19 3
428
- // #define PCINT20 4
429
- // #define PCINT21 5
430
- // #define PCINT22 6
431
- // #define PCINT23 7
432
-
433
- // #define TIMSK0 _SFR_MEM8(0x6E)
434
- char TIMSK0;
435
- #define TOIE0 0
436
- #define OCIE0A 1
437
- #define OCIE0B 2
438
-
439
- // #define TIMSK1 _SFR_MEM8(0x6F)
440
- // #define TOIE1 0
441
- // #define OCIE1A 1
442
- // #define OCIE1B 2
443
- // #define ICIE1 5
444
-
445
- // #define TIMSK2 _SFR_MEM8(0x70)
446
- // #define TOIE2 0
447
- // #define OCIE2A 1
448
- // #define OCIE2B 2
449
-
450
- // #ifndef __ASSEMBLER__
451
- // #define ADC _SFR_MEM16(0x78)
452
- // #endif
453
- // #define ADCW _SFR_MEM16(0x78)
454
-
455
- // #define ADCL _SFR_MEM8(0x78)
456
- // #define ADCL0 0
457
- // #define ADCL1 1
458
- // #define ADCL2 2
459
- // #define ADCL3 3
460
- // #define ADCL4 4
461
- // #define ADCL5 5
462
- // #define ADCL6 6
463
- // #define ADCL7 7
464
-
465
- // #define ADCH _SFR_MEM8(0x79)
466
- // #define ADCH0 0
467
- // #define ADCH1 1
468
- // #define ADCH2 2
469
- // #define ADCH3 3
470
- // #define ADCH4 4
471
- // #define ADCH5 5
472
- // #define ADCH6 6
473
- // #define ADCH7 7
474
-
475
- // #define ADCSRA _SFR_MEM8(0x7A)
476
- // #define ADPS0 0
477
- // #define ADPS1 1
478
- // #define ADPS2 2
479
- // #define ADIE 3
480
- // #define ADIF 4
481
- // #define ADATE 5
482
- // #define ADSC 6
483
- // #define ADEN 7
484
-
485
- // #define ADCSRB _SFR_MEM8(0x7B)
486
- // #define ADTS0 0
487
- // #define ADTS1 1
488
- // #define ADTS2 2
489
- // #define ACME 6
490
-
491
- // #define ADMUX _SFR_MEM8(0x7C)
492
- // #define MUX0 0
493
- // #define MUX1 1
494
- // #define MUX2 2
495
- // #define MUX3 3
496
- // #define ADLAR 5
497
- // #define REFS0 6
498
- // #define REFS1 7
499
-
500
- // #define DIDR0 _SFR_MEM8(0x7E)
501
- // #define ADC0D 0
502
- // #define ADC1D 1
503
- // #define ADC2D 2
504
- // #define ADC3D 3
505
- // #define ADC4D 4
506
- // #define ADC5D 5
507
-
508
- // #define DIDR1 _SFR_MEM8(0x7F)
509
- // #define AIN0D 0
510
- // #define AIN1D 1
511
-
512
- // #define TCCR1A _SFR_MEM8(0x80)
513
- // #define WGM10 0
514
- // #define WGM11 1
515
- // #define COM1B0 4
516
- // #define COM1B1 5
517
- // #define COM1A0 6
518
- // #define COM1A1 7
519
-
520
- // #define TCCR1B _SFR_MEM8(0x81)
521
- // #define CS10 0
522
- // #define CS11 1
523
- // #define CS12 2
524
- // #define WGM12 3
525
- // #define WGM13 4
526
- // #define ICES1 6
527
- // #define ICNC1 7
528
-
529
- // #define TCCR1C _SFR_MEM8(0x82)
530
- // #define FOC1B 6
531
- // #define FOC1A 7
532
-
533
- // #define TCNT1 _SFR_MEM16(0x84)
534
-
535
- // #define TCNT1L _SFR_MEM8(0x84)
536
- // #define TCNT1L0 0
537
- // #define TCNT1L1 1
538
- // #define TCNT1L2 2
539
- // #define TCNT1L3 3
540
- // #define TCNT1L4 4
541
- // #define TCNT1L5 5
542
- // #define TCNT1L6 6
543
- // #define TCNT1L7 7
544
-
545
- // #define TCNT1H _SFR_MEM8(0x85)
546
- // #define TCNT1H0 0
547
- // #define TCNT1H1 1
548
- // #define TCNT1H2 2
549
- // #define TCNT1H3 3
550
- // #define TCNT1H4 4
551
- // #define TCNT1H5 5
552
- // #define TCNT1H6 6
553
- // #define TCNT1H7 7
554
-
555
- // #define ICR1 _SFR_MEM16(0x86)
556
-
557
- // #define ICR1L _SFR_MEM8(0x86)
558
- // #define ICR1L0 0
559
- // #define ICR1L1 1
560
- // #define ICR1L2 2
561
- // #define ICR1L3 3
562
- // #define ICR1L4 4
563
- // #define ICR1L5 5
564
- // #define ICR1L6 6
565
- // #define ICR1L7 7
566
-
567
- // #define ICR1H _SFR_MEM8(0x87)
568
- // #define ICR1H0 0
569
- // #define ICR1H1 1
570
- // #define ICR1H2 2
571
- // #define ICR1H3 3
572
- // #define ICR1H4 4
573
- // #define ICR1H5 5
574
- // #define ICR1H6 6
575
- // #define ICR1H7 7
576
-
577
- // #define OCR1A _SFR_MEM16(0x88)
578
-
579
- // #define OCR1AL _SFR_MEM8(0x88)
580
- // #define OCR1AL0 0
581
- // #define OCR1AL1 1
582
- // #define OCR1AL2 2
583
- // #define OCR1AL3 3
584
- // #define OCR1AL4 4
585
- // #define OCR1AL5 5
586
- // #define OCR1AL6 6
587
- // #define OCR1AL7 7
588
-
589
- // #define OCR1AH _SFR_MEM8(0x89)
590
- // #define OCR1AH0 0
591
- // #define OCR1AH1 1
592
- // #define OCR1AH2 2
593
- // #define OCR1AH3 3
594
- // #define OCR1AH4 4
595
- // #define OCR1AH5 5
596
- // #define OCR1AH6 6
597
- // #define OCR1AH7 7
598
-
599
- // #define OCR1B _SFR_MEM16(0x8A)
600
-
601
- // #define OCR1BL _SFR_MEM8(0x8A)
602
- // #define OCR1BL0 0
603
- // #define OCR1BL1 1
604
- // #define OCR1BL2 2
605
- // #define OCR1BL3 3
606
- // #define OCR1BL4 4
607
- // #define OCR1BL5 5
608
- // #define OCR1BL6 6
609
- // #define OCR1BL7 7
610
-
611
- // #define OCR1BH _SFR_MEM8(0x8B)
612
- // #define OCR1BH0 0
613
- // #define OCR1BH1 1
614
- // #define OCR1BH2 2
615
- // #define OCR1BH3 3
616
- // #define OCR1BH4 4
617
- // #define OCR1BH5 5
618
- // #define OCR1BH6 6
619
- // #define OCR1BH7 7
620
-
621
- // #define TCCR2A _SFR_MEM8(0xB0)
622
- // #define WGM20 0
623
- // #define WGM21 1
624
- // #define COM2B0 4
625
- // #define COM2B1 5
626
- // #define COM2A0 6
627
- // #define COM2A1 7
628
-
629
- // #define TCCR2B _SFR_MEM8(0xB1)
630
- // #define CS20 0
631
- // #define CS21 1
632
- // #define CS22 2
633
- // #define WGM22 3
634
- // #define FOC2B 6
635
- // #define FOC2A 7
636
-
637
- // #define TCNT2 _SFR_MEM8(0xB2)
638
- // #define TCNT2_0 0
639
- // #define TCNT2_1 1
640
- // #define TCNT2_2 2
641
- // #define TCNT2_3 3
642
- // #define TCNT2_4 4
643
- // #define TCNT2_5 5
644
- // #define TCNT2_6 6
645
- // #define TCNT2_7 7
646
-
647
- // #define OCR2A _SFR_MEM8(0xB3)
648
- // #define OCR2_0 0
649
- // #define OCR2_1 1
650
- // #define OCR2_2 2
651
- // #define OCR2_3 3
652
- // #define OCR2_4 4
653
- // #define OCR2_5 5
654
- // #define OCR2_6 6
655
- // #define OCR2_7 7
656
-
657
- // #define OCR2B _SFR_MEM8(0xB4)
658
- // #define OCR2_0 0
659
- // #define OCR2_1 1
660
- // #define OCR2_2 2
661
- // #define OCR2_3 3
662
- // #define OCR2_4 4
663
- // #define OCR2_5 5
664
- // #define OCR2_6 6
665
- // #define OCR2_7 7
666
-
667
- // #define ASSR _SFR_MEM8(0xB6)
668
- // #define TCR2BUB 0
669
- // #define TCR2AUB 1
670
- // #define OCR2BUB 2
671
- // #define OCR2AUB 3
672
- // #define TCN2UB 4
673
- // #define AS2 5
674
- // #define EXCLK 6
675
-
676
- // #define TWBR _SFR_MEM8(0xB8)
677
- // #define TWBR0 0
678
- // #define TWBR1 1
679
- // #define TWBR2 2
680
- // #define TWBR3 3
681
- // #define TWBR4 4
682
- // #define TWBR5 5
683
- // #define TWBR6 6
684
- // #define TWBR7 7
685
-
686
- // #define TWSR _SFR_MEM8(0xB9)
687
- // #define TWPS0 0
688
- // #define TWPS1 1
689
- // #define TWS3 3
690
- // #define TWS4 4
691
- // #define TWS5 5
692
- // #define TWS6 6
693
- // #define TWS7 7
694
-
695
- // #define TWAR _SFR_MEM8(0xBA)
696
- // #define TWGCE 0
697
- // #define TWA0 1
698
- // #define TWA1 2
699
- // #define TWA2 3
700
- // #define TWA3 4
701
- // #define TWA4 5
702
- // #define TWA5 6
703
- // #define TWA6 7
704
-
705
- // #define TWDR _SFR_MEM8(0xBB)
706
- // #define TWD0 0
707
- // #define TWD1 1
708
- // #define TWD2 2
709
- // #define TWD3 3
710
- // #define TWD4 4
711
- // #define TWD5 5
712
- // #define TWD6 6
713
- // #define TWD7 7
714
-
715
- // #define TWCR _SFR_MEM8(0xBC)
716
- // #define TWIE 0
717
- // #define TWEN 2
718
- // #define TWWC 3
719
- // #define TWSTO 4
720
- // #define TWSTA 5
721
- // #define TWEA 6
722
- // #define TWINT 7
723
-
724
- // #define TWAMR _SFR_MEM8(0xBD)
725
- // #define TWAM0 0
726
- // #define TWAM1 1
727
- // #define TWAM2 2
728
- // #define TWAM3 3
729
- // #define TWAM4 4
730
- // #define TWAM5 5
731
- // #define TWAM6 6
732
-
733
- // #define UCSR0A _SFR_MEM8(0xC0)
734
- // #define MPCM0 0
735
- // #define U2X0 1
736
- // #define UPE0 2
737
- // #define DOR0 3
738
- // #define FE0 4
739
- // #define UDRE0 5
740
- // #define TXC0 6
741
- // #define RXC0 7
742
-
743
- // #define UCSR0B _SFR_MEM8(0xC1)
744
- // #define TXB80 0
745
- // #define RXB80 1
746
- // #define UCSZ02 2
747
- // #define TXEN0 3
748
- // #define RXEN0 4
749
- // #define UDRIE0 5
750
- // #define TXCIE0 6
751
- // #define RXCIE0 7
752
-
753
- // #define UCSR0C _SFR_MEM8(0xC2)
754
- // #define UCPOL0 0
755
- // #define UCSZ00 1
756
- // #define UCPHA0 1
757
- // #define UCSZ01 2
758
- // #define UDORD0 2
759
- // #define USBS0 3
760
- // #define UPM00 4
761
- // #define UPM01 5
762
- // #define UMSEL00 6
763
- // #define UMSEL01 7
764
-
765
- // #define UBRR0 _SFR_MEM16(0xC4)
766
-
767
- // #define UBRR0L _SFR_MEM8(0xC4)
768
- // #define UBRR0_0 0
769
- // #define UBRR0_1 1
770
- // #define UBRR0_2 2
771
- // #define UBRR0_3 3
772
- // #define UBRR0_4 4
773
- // #define UBRR0_5 5
774
- // #define UBRR0_6 6
775
- // #define UBRR0_7 7
776
-
777
- // #define UBRR0H _SFR_MEM8(0xC5)
778
- // #define UBRR0_8 0
779
- // #define UBRR0_9 1
780
- // #define UBRR0_10 2
781
- // #define UBRR0_11 3
782
-
783
- // #define UDR0 _SFR_MEM8(0xC6)
784
- // #define UDR0_0 0
785
- // #define UDR0_1 1
786
- // #define UDR0_2 2
787
- // #define UDR0_3 3
788
- // #define UDR0_4 4
789
- // #define UDR0_5 5
790
- // #define UDR0_6 6
791
- // #define UDR0_7 7
792
-
793
-
794
-
795
- // /* Interrupt Vectors */
796
- // /* Interrupt Vector 0 is the reset vector. */
797
- // #define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */
798
- // #define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */
799
- // #define PCINT0_vect _VECTOR(3) /* Pin Change Interrupt Request 0 */
800
- // #define PCINT1_vect _VECTOR(4) /* Pin Change Interrupt Request 0 */
801
- // #define PCINT2_vect _VECTOR(5) /* Pin Change Interrupt Request 1 */
802
- // #define WDT_vect _VECTOR(6) /* Watchdog Time-out Interrupt */
803
- // #define TIMER2_COMPA_vect _VECTOR(7) /* Timer/Counter2 Compare Match A */
804
- // #define TIMER2_COMPB_vect _VECTOR(8) /* Timer/Counter2 Compare Match A */
805
- // #define TIMER2_OVF_vect _VECTOR(9) /* Timer/Counter2 Overflow */
806
- // #define TIMER1_CAPT_vect _VECTOR(10) /* Timer/Counter1 Capture Event */
807
- // #define TIMER1_COMPA_vect _VECTOR(11) /* Timer/Counter1 Compare Match A */
808
- // #define TIMER1_COMPB_vect _VECTOR(12) /* Timer/Counter1 Compare Match B */
809
- // #define TIMER1_OVF_vect _VECTOR(13) /* Timer/Counter1 Overflow */
810
- // #define TIMER0_COMPA_vect _VECTOR(14) /* TimerCounter0 Compare Match A */
811
- // #define TIMER0_COMPB_vect _VECTOR(15) /* TimerCounter0 Compare Match B */
812
- // #define TIMER0_OVF_vect _VECTOR(16) /* Timer/Couner0 Overflow */
813
- // #define SPI_STC_vect _VECTOR(17) /* SPI Serial Transfer Complete */
814
- // #define USART_RX_vect _VECTOR(18) /* USART Rx Complete */
815
- // #define USART_UDRE_vect _VECTOR(19) /* USART, Data Register Empty */
816
- // #define USART_TX_vect _VECTOR(20) /* USART Tx Complete */
817
- // #define ADC_vect _VECTOR(21) /* ADC Conversion Complete */
818
- // #define EE_READY_vect _VECTOR(22) /* EEPROM Ready */
819
- // #define ANALOG_COMP_vect _VECTOR(23) /* Analog Comparator */
820
- // #define TWI_vect _VECTOR(24) /* Two-wire Serial Interface */
821
- // #define SPM_READY_vect _VECTOR(25) /* Store Program Memory Read */
822
-
823
- // #define _VECTORS_SIZE (26 * 4)
824
-
825
-
826
-
827
- // /* Constants */
828
- // #define SPM_PAGESIZE 128
829
- // #define RAMEND 0x8FF /* Last On-Chip SRAM Location */
830
- // #define XRAMSIZE 0
831
- // #define XRAMEND RAMEND
832
- // #define E2END 0x3FF
833
- // #define E2PAGESIZE 4
834
- // #define FLASHEND 0x7FFF
835
-
836
-
837
-
838
- // /* Fuses */
839
- // #define FUSE_MEMORY_SIZE 3
840
-
841
- // /* Low Fuse Byte */
842
- // #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */
843
- // #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */
844
- // #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */
845
- // #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */
846
- // #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */
847
- // #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */
848
- // #define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */
849
- // #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */
850
- // #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
851
-
852
- // /* High Fuse Byte */
853
- // #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */
854
- // #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */
855
- // #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */
856
- // #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */
857
- // #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */
858
- // #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */
859
- // #define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */
860
- // #define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */
861
- // #define HFUSE_DEFAULT (FUSE_SPIEN)
862
-
863
- // /* Extended Fuse Byte */
864
- // #define FUSE_BOOTRST (unsigned char)~_BV(0)
865
- // #define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
866
- // #define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
867
- // #define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1)
868
-
869
-
870
-
871
- // /* Lock Bits */
872
- // #define __LOCK_BITS_EXIST
873
- // #define __BOOT_LOCK_BITS_0_EXIST
874
- // #define __BOOT_LOCK_BITS_1_EXIST
875
-
876
-
877
- // /* Signature */
878
- // #define SIGNATURE_0 0x1E
879
- // #define SIGNATURE_1 0x95
880
- // #define SIGNATURE_2 0x0F
881
-
882
-
883
- #endif /* _AVR_IOM328P_H_ */
1
+ /* Copyright (c) 2007 Atmel Corporation
2
+ All rights reserved.
3
+
4
+ Redistribution and use in source and binary forms, with or without
5
+ modification, are permitted provided that the following conditions are met:
6
+
7
+ * Redistributions of source code must retain the above copyright
8
+ notice, this list of conditions and the following disclaimer.
9
+
10
+ * Redistributions in binary form must reproduce the above copyright
11
+ notice, this list of conditions and the following disclaimer in
12
+ the documentation and/or other materials provided with the
13
+ distribution.
14
+
15
+ * Neither the name of the copyright holders nor the names of
16
+ contributors may be used to endorse or promote products derived
17
+ from this software without specific prior written permission.
18
+
19
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29
+ POSSIBILITY OF SUCH DAMAGE.
30
+ */
31
+
32
+ /* $Id: iom328p.h,v 1.3.2.14 2009/02/11 18:05:28 arcanum Exp $ */
33
+
34
+ /* avr/iom328p.h - definitions for ATmega328P. */
35
+
36
+ /* This file should only be included from <avr/io.h>, never directly. */
37
+
38
+ // #ifndef _AVR_IO_H_
39
+ // # error "Include <avr/io.h> instead of this file."
40
+ // #endif
41
+
42
+ // #ifndef _AVR_IOXXX_H_
43
+ // # define _AVR_IOXXX_H_ "iom328p.h"
44
+ // #else
45
+ // # error "Attempt to include more than one <avr/ioXXX.h> file."
46
+ // #endif
47
+
48
+
49
+ #ifndef _AVR_IOM328P_H_
50
+ #define _AVR_IOM328P_H_ 1
51
+
52
+ /* Registers and associated bit numbers */
53
+
54
+ // #define PINB _SFR_IO8(0x03)
55
+ // #define PINB0 0
56
+ // #define PINB1 1
57
+ // #define PINB2 2
58
+ // #define PINB3 3
59
+ // #define PINB4 4
60
+ // #define PINB5 5
61
+ // #define PINB6 6
62
+ // #define PINB7 7
63
+
64
+ // #define DDRB _SFR_IO8(0x04)
65
+ char DDRB;
66
+ #define DDB0 0
67
+ #define DDB1 1
68
+ #define DDB2 2
69
+ #define DDB3 3
70
+ #define DDB4 4
71
+ #define DDB5 5
72
+ #define DDB6 6
73
+ #define DDB7 7
74
+
75
+ // #define PORTB _SFR_IO8(0x05)
76
+ char PORTB;
77
+ #define PORTB0 0
78
+ #define PORTB1 1
79
+ #define PORTB2 2
80
+ #define PORTB3 3
81
+ #define PORTB4 4
82
+ #define PORTB5 5
83
+ #define PORTB6 6
84
+ #define PORTB7 7
85
+
86
+ // #define PINC _SFR_IO8(0x06)
87
+ // #define PINC0 0
88
+ // #define PINC1 1
89
+ // #define PINC2 2
90
+ // #define PINC3 3
91
+ // #define PINC4 4
92
+ // #define PINC5 5
93
+ // #define PINC6 6
94
+
95
+ // #define DDRC _SFR_IO8(0x07)
96
+ // #define DDC0 0
97
+ // #define DDC1 1
98
+ // #define DDC2 2
99
+ // #define DDC3 3
100
+ // #define DDC4 4
101
+ // #define DDC5 5
102
+ // #define DDC6 6
103
+
104
+ // #define PORTC _SFR_IO8(0x08)
105
+ // #define PORTC0 0
106
+ // #define PORTC1 1
107
+ // #define PORTC2 2
108
+ // #define PORTC3 3
109
+ // #define PORTC4 4
110
+ // #define PORTC5 5
111
+ // #define PORTC6 6
112
+
113
+ // #define PIND _SFR_IO8(0x09)
114
+ char PIND;
115
+ #define PIND0 0
116
+ #define PIND1 1
117
+ #define PIND2 2
118
+ #define PIND3 3
119
+ #define PIND4 4
120
+ #define PIND5 5
121
+ #define PIND6 6
122
+ #define PIND7 7
123
+
124
+ // #define DDRD _SFR_IO8(0x0A)
125
+ char DDRD;
126
+ #define DDD0 0
127
+ #define DDD1 1
128
+ #define DDD2 2
129
+ #define DDD3 3
130
+ #define DDD4 4
131
+ #define DDD5 5
132
+ #define DDD6 6
133
+ #define DDD7 7
134
+
135
+ // #define PORTD _SFR_IO8(0x0B)
136
+ char PORTD;
137
+ #define PORTD0 0
138
+ #define PORTD1 1
139
+ #define PORTD2 2
140
+ #define PORTD3 3
141
+ #define PORTD4 4
142
+ #define PORTD5 5
143
+ #define PORTD6 6
144
+ #define PORTD7 7
145
+
146
+ // #define TIFR0 _SFR_IO8(0x15)
147
+ // #define TOV0 0
148
+ // #define OCF0A 1
149
+ // #define OCF0B 2
150
+
151
+ // #define TIFR1 _SFR_IO8(0x16)
152
+ // #define TOV1 0
153
+ // #define OCF1A 1
154
+ // #define OCF1B 2
155
+ // #define ICF1 5
156
+
157
+ // #define TIFR2 _SFR_IO8(0x17)
158
+ // #define TOV2 0
159
+ // #define OCF2A 1
160
+ // #define OCF2B 2
161
+
162
+ // #define PCIFR _SFR_IO8(0x1B)
163
+ // #define PCIF0 0
164
+ // #define PCIF1 1
165
+ // #define PCIF2 2
166
+
167
+ // #define EIFR _SFR_IO8(0x1C)
168
+ // #define INTF0 0
169
+ // #define INTF1 1
170
+
171
+ // #define EIMSK _SFR_IO8(0x1D)
172
+ // #define INT0 0
173
+ // #define INT1 1
174
+
175
+ // #define GPIOR0 _SFR_IO8(0x1E)
176
+ // #define GPIOR00 0
177
+ // #define GPIOR01 1
178
+ // #define GPIOR02 2
179
+ // #define GPIOR03 3
180
+ // #define GPIOR04 4
181
+ // #define GPIOR05 5
182
+ // #define GPIOR06 6
183
+ // #define GPIOR07 7
184
+
185
+ // #define EECR _SFR_IO8(0x1F)
186
+ // #define EERE 0
187
+ // #define EEPE 1
188
+ // #define EEMPE 2
189
+ // #define EERIE 3
190
+ // #define EEPM0 4
191
+ // #define EEPM1 5
192
+
193
+ // #define EEDR _SFR_IO8(0x20)
194
+ // #define EEDR0 0
195
+ // #define EEDR1 1
196
+ // #define EEDR2 2
197
+ // #define EEDR3 3
198
+ // #define EEDR4 4
199
+ // #define EEDR5 5
200
+ // #define EEDR6 6
201
+ // #define EEDR7 7
202
+
203
+ // #define EEAR _SFR_IO16(0x21)
204
+
205
+ // #define EEARL _SFR_IO8(0x21)
206
+ // #define EEAR0 0
207
+ // #define EEAR1 1
208
+ // #define EEAR2 2
209
+ // #define EEAR3 3
210
+ // #define EEAR4 4
211
+ // #define EEAR5 5
212
+ // #define EEAR6 6
213
+ // #define EEAR7 7
214
+
215
+ // #define EEARH _SFR_IO8(0x22)
216
+ // #define EEAR8 0
217
+ // #define EEAR9 1
218
+
219
+ // #define _EEPROM_REG_LOCATIONS_ 1F2021
220
+
221
+ // #define GTCCR _SFR_IO8(0x23)
222
+ // #define PSRSYNC 0
223
+ // #define PSRASY 1
224
+ // #define TSM 7
225
+
226
+ // #define TCCR0A _SFR_IO8(0x24)
227
+ // #define WGM00 0
228
+ // #define WGM01 1
229
+ // #define COM0B0 4
230
+ // #define COM0B1 5
231
+ // #define COM0A0 6
232
+ // #define COM0A1 7
233
+
234
+ // #define TCCR0B _SFR_IO8(0x25)
235
+ char TCCR0B;
236
+ #define CS00 0
237
+ #define CS01 1
238
+ #define CS02 2
239
+ #define WGM02 3
240
+ #define FOC0B 6
241
+ #define FOC0A 7
242
+
243
+ // #define TCNT0 _SFR_IO8(0x26)
244
+ char TCNT0;
245
+ #define TCNT0_0 0
246
+ #define TCNT0_1 1
247
+ #define TCNT0_2 2
248
+ #define TCNT0_3 3
249
+ #define TCNT0_4 4
250
+ #define TCNT0_5 5
251
+ #define TCNT0_6 6
252
+ #define TCNT0_7 7
253
+
254
+ // #define OCR0A _SFR_IO8(0x27)
255
+ // #define OCR0A_0 0
256
+ // #define OCR0A_1 1
257
+ // #define OCR0A_2 2
258
+ // #define OCR0A_3 3
259
+ // #define OCR0A_4 4
260
+ // #define OCR0A_5 5
261
+ // #define OCR0A_6 6
262
+ // #define OCR0A_7 7
263
+
264
+ // #define OCR0B _SFR_IO8(0x28)
265
+ // #define OCR0B_0 0
266
+ // #define OCR0B_1 1
267
+ // #define OCR0B_2 2
268
+ // #define OCR0B_3 3
269
+ // #define OCR0B_4 4
270
+ // #define OCR0B_5 5
271
+ // #define OCR0B_6 6
272
+ // #define OCR0B_7 7
273
+
274
+ // #define GPIOR1 _SFR_IO8(0x2A)
275
+ // #define GPIOR10 0
276
+ // #define GPIOR11 1
277
+ // #define GPIOR12 2
278
+ // #define GPIOR13 3
279
+ // #define GPIOR14 4
280
+ // #define GPIOR15 5
281
+ // #define GPIOR16 6
282
+ // #define GPIOR17 7
283
+
284
+ // #define GPIOR2 _SFR_IO8(0x2B)
285
+ // #define GPIOR20 0
286
+ // #define GPIOR21 1
287
+ // #define GPIOR22 2
288
+ // #define GPIOR23 3
289
+ // #define GPIOR24 4
290
+ // #define GPIOR25 5
291
+ // #define GPIOR26 6
292
+ // #define GPIOR27 7
293
+
294
+ // #define SPCR _SFR_IO8(0x2C)
295
+ // #define SPR0 0
296
+ // #define SPR1 1
297
+ // #define CPHA 2
298
+ // #define CPOL 3
299
+ // #define MSTR 4
300
+ // #define DORD 5
301
+ // #define SPE 6
302
+ // #define SPIE 7
303
+
304
+ // #define SPSR _SFR_IO8(0x2D)
305
+ // #define SPI2X 0
306
+ // #define WCOL 6
307
+ // #define SPIF 7
308
+
309
+ // #define SPDR _SFR_IO8(0x2E)
310
+ // #define SPDR0 0
311
+ // #define SPDR1 1
312
+ // #define SPDR2 2
313
+ // #define SPDR3 3
314
+ // #define SPDR4 4
315
+ // #define SPDR5 5
316
+ // #define SPDR6 6
317
+ // #define SPDR7 7
318
+
319
+ // #define ACSR _SFR_IO8(0x30)
320
+ // #define ACIS0 0
321
+ // #define ACIS1 1
322
+ // #define ACIC 2
323
+ // #define ACIE 3
324
+ // #define ACI 4
325
+ // #define ACO 5
326
+ // #define ACBG 6
327
+ // #define ACD 7
328
+
329
+ // #define SMCR _SFR_IO8(0x33)
330
+ // #define SE 0
331
+ // #define SM0 1
332
+ // #define SM1 2
333
+ // #define SM2 3
334
+
335
+ // #define MCUSR _SFR_IO8(0x34)
336
+ // #define PORF 0
337
+ // #define EXTRF 1
338
+ // #define BORF 2
339
+ // #define WDRF 3
340
+
341
+ // #define MCUCR _SFR_IO8(0x35)
342
+ // #define IVCE 0
343
+ // #define IVSEL 1
344
+ // #define PUD 4
345
+ // #define BODSE 5
346
+ // #define BODS 6
347
+
348
+ // #define SPMCSR _SFR_IO8(0x37)
349
+ // #define SELFPRGEN 0
350
+ // #define PGERS 1
351
+ // #define PGWRT 2
352
+ // #define BLBSET 3
353
+ // #define RWWSRE 4
354
+ // #define RWWSB 6
355
+ // #define SPMIE 7
356
+
357
+ // #define WDTCSR _SFR_MEM8(0x60)
358
+ // #define WDP0 0
359
+ // #define WDP1 1
360
+ // #define WDP2 2
361
+ // #define WDE 3
362
+ // #define WDCE 4
363
+ // #define WDP3 5
364
+ // #define WDIE 6
365
+ // #define WDIF 7
366
+
367
+ // #define CLKPR _SFR_MEM8(0x61)
368
+ // #define CLKPS0 0
369
+ // #define CLKPS1 1
370
+ // #define CLKPS2 2
371
+ // #define CLKPS3 3
372
+ // #define CLKPCE 7
373
+
374
+ // #define PRR _SFR_MEM8(0x64)
375
+ // #define PRADC 0
376
+ // #define PRUSART0 1
377
+ // #define PRSPI 2
378
+ // #define PRTIM1 3
379
+ // #define PRTIM0 5
380
+ // #define PRTIM2 6
381
+ // #define PRTWI 7
382
+
383
+ // #define OSCCAL _SFR_MEM8(0x66)
384
+ // #define CAL0 0
385
+ // #define CAL1 1
386
+ // #define CAL2 2
387
+ // #define CAL3 3
388
+ // #define CAL4 4
389
+ // #define CAL5 5
390
+ // #define CAL6 6
391
+ // #define CAL7 7
392
+
393
+ // #define PCICR _SFR_MEM8(0x68)
394
+ // #define PCIE0 0
395
+ // #define PCIE1 1
396
+ // #define PCIE2 2
397
+
398
+ // #define EICRA _SFR_MEM8(0x69)
399
+ // #define ISC00 0
400
+ // #define ISC01 1
401
+ // #define ISC10 2
402
+ // #define ISC11 3
403
+
404
+ // #define PCMSK0 _SFR_MEM8(0x6B)
405
+ // #define PCINT0 0
406
+ // #define PCINT1 1
407
+ // #define PCINT2 2
408
+ // #define PCINT3 3
409
+ // #define PCINT4 4
410
+ // #define PCINT5 5
411
+ // #define PCINT6 6
412
+ // #define PCINT7 7
413
+
414
+ // #define PCMSK1 _SFR_MEM8(0x6C)
415
+ // #define PCINT8 0
416
+ // #define PCINT9 1
417
+ // #define PCINT10 2
418
+ // #define PCINT11 3
419
+ // #define PCINT12 4
420
+ // #define PCINT13 5
421
+ // #define PCINT14 6
422
+
423
+ // #define PCMSK2 _SFR_MEM8(0x6D)
424
+ // #define PCINT16 0
425
+ // #define PCINT17 1
426
+ // #define PCINT18 2
427
+ // #define PCINT19 3
428
+ // #define PCINT20 4
429
+ // #define PCINT21 5
430
+ // #define PCINT22 6
431
+ // #define PCINT23 7
432
+
433
+ // #define TIMSK0 _SFR_MEM8(0x6E)
434
+ char TIMSK0;
435
+ #define TOIE0 0
436
+ #define OCIE0A 1
437
+ #define OCIE0B 2
438
+
439
+ // #define TIMSK1 _SFR_MEM8(0x6F)
440
+ // #define TOIE1 0
441
+ // #define OCIE1A 1
442
+ // #define OCIE1B 2
443
+ // #define ICIE1 5
444
+
445
+ // #define TIMSK2 _SFR_MEM8(0x70)
446
+ // #define TOIE2 0
447
+ // #define OCIE2A 1
448
+ // #define OCIE2B 2
449
+
450
+ // #ifndef __ASSEMBLER__
451
+ // #define ADC _SFR_MEM16(0x78)
452
+ // #endif
453
+ // #define ADCW _SFR_MEM16(0x78)
454
+
455
+ // #define ADCL _SFR_MEM8(0x78)
456
+ // #define ADCL0 0
457
+ // #define ADCL1 1
458
+ // #define ADCL2 2
459
+ // #define ADCL3 3
460
+ // #define ADCL4 4
461
+ // #define ADCL5 5
462
+ // #define ADCL6 6
463
+ // #define ADCL7 7
464
+
465
+ // #define ADCH _SFR_MEM8(0x79)
466
+ // #define ADCH0 0
467
+ // #define ADCH1 1
468
+ // #define ADCH2 2
469
+ // #define ADCH3 3
470
+ // #define ADCH4 4
471
+ // #define ADCH5 5
472
+ // #define ADCH6 6
473
+ // #define ADCH7 7
474
+
475
+ // #define ADCSRA _SFR_MEM8(0x7A)
476
+ // #define ADPS0 0
477
+ // #define ADPS1 1
478
+ // #define ADPS2 2
479
+ // #define ADIE 3
480
+ // #define ADIF 4
481
+ // #define ADATE 5
482
+ // #define ADSC 6
483
+ // #define ADEN 7
484
+
485
+ // #define ADCSRB _SFR_MEM8(0x7B)
486
+ // #define ADTS0 0
487
+ // #define ADTS1 1
488
+ // #define ADTS2 2
489
+ // #define ACME 6
490
+
491
+ // #define ADMUX _SFR_MEM8(0x7C)
492
+ // #define MUX0 0
493
+ // #define MUX1 1
494
+ // #define MUX2 2
495
+ // #define MUX3 3
496
+ // #define ADLAR 5
497
+ // #define REFS0 6
498
+ // #define REFS1 7
499
+
500
+ // #define DIDR0 _SFR_MEM8(0x7E)
501
+ // #define ADC0D 0
502
+ // #define ADC1D 1
503
+ // #define ADC2D 2
504
+ // #define ADC3D 3
505
+ // #define ADC4D 4
506
+ // #define ADC5D 5
507
+
508
+ // #define DIDR1 _SFR_MEM8(0x7F)
509
+ // #define AIN0D 0
510
+ // #define AIN1D 1
511
+
512
+ // #define TCCR1A _SFR_MEM8(0x80)
513
+ // #define WGM10 0
514
+ // #define WGM11 1
515
+ // #define COM1B0 4
516
+ // #define COM1B1 5
517
+ // #define COM1A0 6
518
+ // #define COM1A1 7
519
+
520
+ // #define TCCR1B _SFR_MEM8(0x81)
521
+ // #define CS10 0
522
+ // #define CS11 1
523
+ // #define CS12 2
524
+ // #define WGM12 3
525
+ // #define WGM13 4
526
+ // #define ICES1 6
527
+ // #define ICNC1 7
528
+
529
+ // #define TCCR1C _SFR_MEM8(0x82)
530
+ // #define FOC1B 6
531
+ // #define FOC1A 7
532
+
533
+ // #define TCNT1 _SFR_MEM16(0x84)
534
+
535
+ // #define TCNT1L _SFR_MEM8(0x84)
536
+ // #define TCNT1L0 0
537
+ // #define TCNT1L1 1
538
+ // #define TCNT1L2 2
539
+ // #define TCNT1L3 3
540
+ // #define TCNT1L4 4
541
+ // #define TCNT1L5 5
542
+ // #define TCNT1L6 6
543
+ // #define TCNT1L7 7
544
+
545
+ // #define TCNT1H _SFR_MEM8(0x85)
546
+ // #define TCNT1H0 0
547
+ // #define TCNT1H1 1
548
+ // #define TCNT1H2 2
549
+ // #define TCNT1H3 3
550
+ // #define TCNT1H4 4
551
+ // #define TCNT1H5 5
552
+ // #define TCNT1H6 6
553
+ // #define TCNT1H7 7
554
+
555
+ // #define ICR1 _SFR_MEM16(0x86)
556
+
557
+ // #define ICR1L _SFR_MEM8(0x86)
558
+ // #define ICR1L0 0
559
+ // #define ICR1L1 1
560
+ // #define ICR1L2 2
561
+ // #define ICR1L3 3
562
+ // #define ICR1L4 4
563
+ // #define ICR1L5 5
564
+ // #define ICR1L6 6
565
+ // #define ICR1L7 7
566
+
567
+ // #define ICR1H _SFR_MEM8(0x87)
568
+ // #define ICR1H0 0
569
+ // #define ICR1H1 1
570
+ // #define ICR1H2 2
571
+ // #define ICR1H3 3
572
+ // #define ICR1H4 4
573
+ // #define ICR1H5 5
574
+ // #define ICR1H6 6
575
+ // #define ICR1H7 7
576
+
577
+ // #define OCR1A _SFR_MEM16(0x88)
578
+
579
+ // #define OCR1AL _SFR_MEM8(0x88)
580
+ // #define OCR1AL0 0
581
+ // #define OCR1AL1 1
582
+ // #define OCR1AL2 2
583
+ // #define OCR1AL3 3
584
+ // #define OCR1AL4 4
585
+ // #define OCR1AL5 5
586
+ // #define OCR1AL6 6
587
+ // #define OCR1AL7 7
588
+
589
+ // #define OCR1AH _SFR_MEM8(0x89)
590
+ // #define OCR1AH0 0
591
+ // #define OCR1AH1 1
592
+ // #define OCR1AH2 2
593
+ // #define OCR1AH3 3
594
+ // #define OCR1AH4 4
595
+ // #define OCR1AH5 5
596
+ // #define OCR1AH6 6
597
+ // #define OCR1AH7 7
598
+
599
+ // #define OCR1B _SFR_MEM16(0x8A)
600
+
601
+ // #define OCR1BL _SFR_MEM8(0x8A)
602
+ // #define OCR1BL0 0
603
+ // #define OCR1BL1 1
604
+ // #define OCR1BL2 2
605
+ // #define OCR1BL3 3
606
+ // #define OCR1BL4 4
607
+ // #define OCR1BL5 5
608
+ // #define OCR1BL6 6
609
+ // #define OCR1BL7 7
610
+
611
+ // #define OCR1BH _SFR_MEM8(0x8B)
612
+ // #define OCR1BH0 0
613
+ // #define OCR1BH1 1
614
+ // #define OCR1BH2 2
615
+ // #define OCR1BH3 3
616
+ // #define OCR1BH4 4
617
+ // #define OCR1BH5 5
618
+ // #define OCR1BH6 6
619
+ // #define OCR1BH7 7
620
+
621
+ // #define TCCR2A _SFR_MEM8(0xB0)
622
+ // #define WGM20 0
623
+ // #define WGM21 1
624
+ // #define COM2B0 4
625
+ // #define COM2B1 5
626
+ // #define COM2A0 6
627
+ // #define COM2A1 7
628
+
629
+ // #define TCCR2B _SFR_MEM8(0xB1)
630
+ // #define CS20 0
631
+ // #define CS21 1
632
+ // #define CS22 2
633
+ // #define WGM22 3
634
+ // #define FOC2B 6
635
+ // #define FOC2A 7
636
+
637
+ // #define TCNT2 _SFR_MEM8(0xB2)
638
+ // #define TCNT2_0 0
639
+ // #define TCNT2_1 1
640
+ // #define TCNT2_2 2
641
+ // #define TCNT2_3 3
642
+ // #define TCNT2_4 4
643
+ // #define TCNT2_5 5
644
+ // #define TCNT2_6 6
645
+ // #define TCNT2_7 7
646
+
647
+ // #define OCR2A _SFR_MEM8(0xB3)
648
+ // #define OCR2_0 0
649
+ // #define OCR2_1 1
650
+ // #define OCR2_2 2
651
+ // #define OCR2_3 3
652
+ // #define OCR2_4 4
653
+ // #define OCR2_5 5
654
+ // #define OCR2_6 6
655
+ // #define OCR2_7 7
656
+
657
+ // #define OCR2B _SFR_MEM8(0xB4)
658
+ // #define OCR2_0 0
659
+ // #define OCR2_1 1
660
+ // #define OCR2_2 2
661
+ // #define OCR2_3 3
662
+ // #define OCR2_4 4
663
+ // #define OCR2_5 5
664
+ // #define OCR2_6 6
665
+ // #define OCR2_7 7
666
+
667
+ // #define ASSR _SFR_MEM8(0xB6)
668
+ // #define TCR2BUB 0
669
+ // #define TCR2AUB 1
670
+ // #define OCR2BUB 2
671
+ // #define OCR2AUB 3
672
+ // #define TCN2UB 4
673
+ // #define AS2 5
674
+ // #define EXCLK 6
675
+
676
+ // #define TWBR _SFR_MEM8(0xB8)
677
+ // #define TWBR0 0
678
+ // #define TWBR1 1
679
+ // #define TWBR2 2
680
+ // #define TWBR3 3
681
+ // #define TWBR4 4
682
+ // #define TWBR5 5
683
+ // #define TWBR6 6
684
+ // #define TWBR7 7
685
+
686
+ // #define TWSR _SFR_MEM8(0xB9)
687
+ // #define TWPS0 0
688
+ // #define TWPS1 1
689
+ // #define TWS3 3
690
+ // #define TWS4 4
691
+ // #define TWS5 5
692
+ // #define TWS6 6
693
+ // #define TWS7 7
694
+
695
+ // #define TWAR _SFR_MEM8(0xBA)
696
+ // #define TWGCE 0
697
+ // #define TWA0 1
698
+ // #define TWA1 2
699
+ // #define TWA2 3
700
+ // #define TWA3 4
701
+ // #define TWA4 5
702
+ // #define TWA5 6
703
+ // #define TWA6 7
704
+
705
+ // #define TWDR _SFR_MEM8(0xBB)
706
+ // #define TWD0 0
707
+ // #define TWD1 1
708
+ // #define TWD2 2
709
+ // #define TWD3 3
710
+ // #define TWD4 4
711
+ // #define TWD5 5
712
+ // #define TWD6 6
713
+ // #define TWD7 7
714
+
715
+ // #define TWCR _SFR_MEM8(0xBC)
716
+ // #define TWIE 0
717
+ // #define TWEN 2
718
+ // #define TWWC 3
719
+ // #define TWSTO 4
720
+ // #define TWSTA 5
721
+ // #define TWEA 6
722
+ // #define TWINT 7
723
+
724
+ // #define TWAMR _SFR_MEM8(0xBD)
725
+ // #define TWAM0 0
726
+ // #define TWAM1 1
727
+ // #define TWAM2 2
728
+ // #define TWAM3 3
729
+ // #define TWAM4 4
730
+ // #define TWAM5 5
731
+ // #define TWAM6 6
732
+
733
+ // #define UCSR0A _SFR_MEM8(0xC0)
734
+ // #define MPCM0 0
735
+ // #define U2X0 1
736
+ // #define UPE0 2
737
+ // #define DOR0 3
738
+ // #define FE0 4
739
+ // #define UDRE0 5
740
+ // #define TXC0 6
741
+ // #define RXC0 7
742
+
743
+ // #define UCSR0B _SFR_MEM8(0xC1)
744
+ // #define TXB80 0
745
+ // #define RXB80 1
746
+ // #define UCSZ02 2
747
+ // #define TXEN0 3
748
+ // #define RXEN0 4
749
+ // #define UDRIE0 5
750
+ // #define TXCIE0 6
751
+ // #define RXCIE0 7
752
+
753
+ // #define UCSR0C _SFR_MEM8(0xC2)
754
+ // #define UCPOL0 0
755
+ // #define UCSZ00 1
756
+ // #define UCPHA0 1
757
+ // #define UCSZ01 2
758
+ // #define UDORD0 2
759
+ // #define USBS0 3
760
+ // #define UPM00 4
761
+ // #define UPM01 5
762
+ // #define UMSEL00 6
763
+ // #define UMSEL01 7
764
+
765
+ // #define UBRR0 _SFR_MEM16(0xC4)
766
+
767
+ // #define UBRR0L _SFR_MEM8(0xC4)
768
+ // #define UBRR0_0 0
769
+ // #define UBRR0_1 1
770
+ // #define UBRR0_2 2
771
+ // #define UBRR0_3 3
772
+ // #define UBRR0_4 4
773
+ // #define UBRR0_5 5
774
+ // #define UBRR0_6 6
775
+ // #define UBRR0_7 7
776
+
777
+ // #define UBRR0H _SFR_MEM8(0xC5)
778
+ // #define UBRR0_8 0
779
+ // #define UBRR0_9 1
780
+ // #define UBRR0_10 2
781
+ // #define UBRR0_11 3
782
+
783
+ // #define UDR0 _SFR_MEM8(0xC6)
784
+ // #define UDR0_0 0
785
+ // #define UDR0_1 1
786
+ // #define UDR0_2 2
787
+ // #define UDR0_3 3
788
+ // #define UDR0_4 4
789
+ // #define UDR0_5 5
790
+ // #define UDR0_6 6
791
+ // #define UDR0_7 7
792
+
793
+
794
+
795
+ // /* Interrupt Vectors */
796
+ // /* Interrupt Vector 0 is the reset vector. */
797
+ // #define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */
798
+ // #define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */
799
+ // #define PCINT0_vect _VECTOR(3) /* Pin Change Interrupt Request 0 */
800
+ // #define PCINT1_vect _VECTOR(4) /* Pin Change Interrupt Request 0 */
801
+ // #define PCINT2_vect _VECTOR(5) /* Pin Change Interrupt Request 1 */
802
+ // #define WDT_vect _VECTOR(6) /* Watchdog Time-out Interrupt */
803
+ // #define TIMER2_COMPA_vect _VECTOR(7) /* Timer/Counter2 Compare Match A */
804
+ // #define TIMER2_COMPB_vect _VECTOR(8) /* Timer/Counter2 Compare Match A */
805
+ // #define TIMER2_OVF_vect _VECTOR(9) /* Timer/Counter2 Overflow */
806
+ // #define TIMER1_CAPT_vect _VECTOR(10) /* Timer/Counter1 Capture Event */
807
+ // #define TIMER1_COMPA_vect _VECTOR(11) /* Timer/Counter1 Compare Match A */
808
+ // #define TIMER1_COMPB_vect _VECTOR(12) /* Timer/Counter1 Compare Match B */
809
+ // #define TIMER1_OVF_vect _VECTOR(13) /* Timer/Counter1 Overflow */
810
+ // #define TIMER0_COMPA_vect _VECTOR(14) /* TimerCounter0 Compare Match A */
811
+ // #define TIMER0_COMPB_vect _VECTOR(15) /* TimerCounter0 Compare Match B */
812
+ // #define TIMER0_OVF_vect _VECTOR(16) /* Timer/Couner0 Overflow */
813
+ // #define SPI_STC_vect _VECTOR(17) /* SPI Serial Transfer Complete */
814
+ // #define USART_RX_vect _VECTOR(18) /* USART Rx Complete */
815
+ // #define USART_UDRE_vect _VECTOR(19) /* USART, Data Register Empty */
816
+ // #define USART_TX_vect _VECTOR(20) /* USART Tx Complete */
817
+ // #define ADC_vect _VECTOR(21) /* ADC Conversion Complete */
818
+ // #define EE_READY_vect _VECTOR(22) /* EEPROM Ready */
819
+ // #define ANALOG_COMP_vect _VECTOR(23) /* Analog Comparator */
820
+ // #define TWI_vect _VECTOR(24) /* Two-wire Serial Interface */
821
+ // #define SPM_READY_vect _VECTOR(25) /* Store Program Memory Read */
822
+
823
+ // #define _VECTORS_SIZE (26 * 4)
824
+
825
+
826
+
827
+ // /* Constants */
828
+ // #define SPM_PAGESIZE 128
829
+ // #define RAMEND 0x8FF /* Last On-Chip SRAM Location */
830
+ // #define XRAMSIZE 0
831
+ // #define XRAMEND RAMEND
832
+ // #define E2END 0x3FF
833
+ // #define E2PAGESIZE 4
834
+ // #define FLASHEND 0x7FFF
835
+
836
+
837
+
838
+ // /* Fuses */
839
+ // #define FUSE_MEMORY_SIZE 3
840
+
841
+ // /* Low Fuse Byte */
842
+ // #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */
843
+ // #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */
844
+ // #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */
845
+ // #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */
846
+ // #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */
847
+ // #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */
848
+ // #define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */
849
+ // #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */
850
+ // #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
851
+
852
+ // /* High Fuse Byte */
853
+ // #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */
854
+ // #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */
855
+ // #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */
856
+ // #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */
857
+ // #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */
858
+ // #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */
859
+ // #define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */
860
+ // #define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */
861
+ // #define HFUSE_DEFAULT (FUSE_SPIEN)
862
+
863
+ // /* Extended Fuse Byte */
864
+ // #define FUSE_BOOTRST (unsigned char)~_BV(0)
865
+ // #define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
866
+ // #define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
867
+ // #define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1)
868
+
869
+
870
+
871
+ // /* Lock Bits */
872
+ // #define __LOCK_BITS_EXIST
873
+ // #define __BOOT_LOCK_BITS_0_EXIST
874
+ // #define __BOOT_LOCK_BITS_1_EXIST
875
+
876
+
877
+ // /* Signature */
878
+ // #define SIGNATURE_0 0x1E
879
+ // #define SIGNATURE_1 0x95
880
+ // #define SIGNATURE_2 0x0F
881
+
882
+
883
+ #endif /* _AVR_IOM328P_H_ */