v86 0.4.0 → 0.5.11
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- package/Readme.md +56 -111
- package/build/libv86-debug.js +12680 -0
- package/build/libv86-debug.mjs +732 -0
- package/build/libv86.js +710 -0
- package/build/libv86.mjs +637 -0
- package/build/v86-debug.wasm +0 -0
- package/build/v86-fallback.wasm +0 -0
- package/build/v86.wasm +0 -0
- package/package.json +12 -35
- package/bios/.gitignore +0 -1
- package/bios/COPYING.LESSER +0 -165
- package/bios/bochs-bios.bin +0 -0
- package/bios/bochs-vgabios.bin +0 -0
- package/bios/fetch-and-build-seabios.sh +0 -13
- package/bios/seabios/.config +0 -113
- package/bios/seabios/.config.old +0 -114
- package/bios/seabios/.gitignore +0 -4
- package/bios/seabios/COPYING +0 -674
- package/bios/seabios/COPYING.LESSER +0 -165
- package/bios/seabios/Makefile +0 -286
- package/bios/seabios/README +0 -17
- package/bios/seabios/docs/Build_overview.md +0 -104
- package/bios/seabios/docs/Contributing.md +0 -20
- package/bios/seabios/docs/Debugging.md +0 -111
- package/bios/seabios/docs/Developer_Documentation.md +0 -25
- package/bios/seabios/docs/Developer_links.md +0 -86
- package/bios/seabios/docs/Download.md +0 -27
- package/bios/seabios/docs/Execution_and_code_flow.md +0 -178
- package/bios/seabios/docs/Linking_overview.md +0 -160
- package/bios/seabios/docs/Mailinglist.md +0 -8
- package/bios/seabios/docs/Memory_Model.md +0 -253
- package/bios/seabios/docs/README +0 -5
- package/bios/seabios/docs/Releases.md +0 -482
- package/bios/seabios/docs/Runtime_config.md +0 -193
- package/bios/seabios/docs/SeaBIOS.md +0 -17
- package/bios/seabios/docs/SeaVGABIOS.md +0 -39
- package/bios/seabios/out/autoconf.h +0 -117
- package/bios/seabios/out/include/config/acpi/dsdt.h +0 -0
- package/bios/seabios/out/include/config/acpi.h +0 -0
- package/bios/seabios/out/include/config/ahci.h +0 -0
- package/bios/seabios/out/include/config/apmbios.h +0 -0
- package/bios/seabios/out/include/config/ata/dma.h +0 -0
- package/bios/seabios/out/include/config/ata/pio32.h +0 -0
- package/bios/seabios/out/include/config/ata.h +0 -0
- package/bios/seabios/out/include/config/auto.conf +0 -69
- package/bios/seabios/out/include/config/auto.conf.cmd +0 -9
- package/bios/seabios/out/include/config/boot.h +0 -0
- package/bios/seabios/out/include/config/bootorder.h +0 -0
- package/bios/seabios/out/include/config/build/vgabios.h +0 -0
- package/bios/seabios/out/include/config/call32/smm.h +0 -0
- package/bios/seabios/out/include/config/cdrom/boot.h +0 -0
- package/bios/seabios/out/include/config/cdrom/emu.h +0 -0
- package/bios/seabios/out/include/config/debug/level.h +0 -0
- package/bios/seabios/out/include/config/drives.h +0 -0
- package/bios/seabios/out/include/config/entry/extrastack.h +0 -0
- package/bios/seabios/out/include/config/esp/scsi.h +0 -0
- package/bios/seabios/out/include/config/flash/floppy.h +0 -0
- package/bios/seabios/out/include/config/floppy.h +0 -0
- package/bios/seabios/out/include/config/fw/romfile/load.h +0 -0
- package/bios/seabios/out/include/config/hardware/irq.h +0 -0
- package/bios/seabios/out/include/config/kbd/call/int15/4f.h +0 -0
- package/bios/seabios/out/include/config/keyboard.h +0 -0
- package/bios/seabios/out/include/config/lpt.h +0 -0
- package/bios/seabios/out/include/config/lsi/scsi.h +0 -0
- package/bios/seabios/out/include/config/malloc/uppermemory.h +0 -0
- package/bios/seabios/out/include/config/megasas.h +0 -0
- package/bios/seabios/out/include/config/mouse.h +0 -0
- package/bios/seabios/out/include/config/mpt/scsi.h +0 -0
- package/bios/seabios/out/include/config/mptable.h +0 -0
- package/bios/seabios/out/include/config/mtrr/init.h +0 -0
- package/bios/seabios/out/include/config/optionroms.h +0 -0
- package/bios/seabios/out/include/config/override/pci/id.h +0 -0
- package/bios/seabios/out/include/config/pcibios.h +0 -0
- package/bios/seabios/out/include/config/pirtable.h +0 -0
- package/bios/seabios/out/include/config/pmm.h +0 -0
- package/bios/seabios/out/include/config/pmtimer.h +0 -0
- package/bios/seabios/out/include/config/pnpbios.h +0 -0
- package/bios/seabios/out/include/config/ps2port.h +0 -0
- package/bios/seabios/out/include/config/pvscsi.h +0 -0
- package/bios/seabios/out/include/config/qemu/hardware.h +0 -0
- package/bios/seabios/out/include/config/qemu.h +0 -0
- package/bios/seabios/out/include/config/rom/size.h +0 -0
- package/bios/seabios/out/include/config/rtc/timer.h +0 -0
- package/bios/seabios/out/include/config/s3/resume.h +0 -0
- package/bios/seabios/out/include/config/sdcard.h +0 -0
- package/bios/seabios/out/include/config/serial.h +0 -0
- package/bios/seabios/out/include/config/tcgbios.h +0 -0
- package/bios/seabios/out/include/config/threads.h +0 -0
- package/bios/seabios/out/include/config/tristate.conf +0 -4
- package/bios/seabios/out/include/config/tsc/timer.h +0 -0
- package/bios/seabios/out/include/config/use/smm.h +0 -0
- package/bios/seabios/out/include/config/vga/allocate/extra/stack.h +0 -0
- package/bios/seabios/out/include/config/vga/bochs/stdvga.h +0 -0
- package/bios/seabios/out/include/config/vga/bochs.h +0 -0
- package/bios/seabios/out/include/config/vga/did.h +0 -0
- package/bios/seabios/out/include/config/vga/extra/stack/size.h +0 -0
- package/bios/seabios/out/include/config/vga/fixup/asm.h +0 -0
- package/bios/seabios/out/include/config/vga/pci.h +0 -0
- package/bios/seabios/out/include/config/vga/stdvga/ports.h +0 -0
- package/bios/seabios/out/include/config/vga/vbe.h +0 -0
- package/bios/seabios/out/include/config/vga/vid.h +0 -0
- package/bios/seabios/out/include/config/vgahooks.h +0 -0
- package/bios/seabios/out/include/config/virtio/blk.h +0 -0
- package/bios/seabios/out/include/config/virtio/scsi.h +0 -0
- package/bios/seabios/out/include/config/xen.h +0 -0
- package/bios/seabios/out/scripts/kconfig/conf +0 -0
- package/bios/seabios/out/scripts/kconfig/conf.o +0 -0
- package/bios/seabios/out/scripts/kconfig/zconf.hash.c +0 -289
- package/bios/seabios/out/scripts/kconfig/zconf.lex.c +0 -2420
- package/bios/seabios/out/scripts/kconfig/zconf.tab.c +0 -2538
- package/bios/seabios/out/scripts/kconfig/zconf.tab.o +0 -0
- package/bios/seabios/scripts/acpi_extract.py +0 -366
- package/bios/seabios/scripts/acpi_extract_preprocess.py +0 -41
- package/bios/seabios/scripts/buildrom.py +0 -56
- package/bios/seabios/scripts/buildversion.py +0 -134
- package/bios/seabios/scripts/checkrom.py +0 -95
- package/bios/seabios/scripts/checkstack.py +0 -226
- package/bios/seabios/scripts/checksum.py +0 -16
- package/bios/seabios/scripts/encodeint.py +0 -21
- package/bios/seabios/scripts/gen-offsets.sh +0 -17
- package/bios/seabios/scripts/kconfig/.gitignore +0 -22
- package/bios/seabios/scripts/kconfig/Makefile +0 -331
- package/bios/seabios/scripts/kconfig/POTFILES.in +0 -12
- package/bios/seabios/scripts/kconfig/check.sh +0 -13
- package/bios/seabios/scripts/kconfig/conf.c +0 -718
- package/bios/seabios/scripts/kconfig/confdata.c +0 -1250
- package/bios/seabios/scripts/kconfig/expr.c +0 -1168
- package/bios/seabios/scripts/kconfig/expr.h +0 -241
- package/bios/seabios/scripts/kconfig/gconf.c +0 -1542
- package/bios/seabios/scripts/kconfig/gconf.glade +0 -661
- package/bios/seabios/scripts/kconfig/images.c +0 -326
- package/bios/seabios/scripts/kconfig/kxgettext.c +0 -235
- package/bios/seabios/scripts/kconfig/lex.zconf.c +0 -2430
- package/bios/seabios/scripts/kconfig/list.h +0 -131
- package/bios/seabios/scripts/kconfig/lkc.h +0 -200
- package/bios/seabios/scripts/kconfig/lkc_proto.h +0 -57
- package/bios/seabios/scripts/kconfig/lxdialog/.gitignore +0 -4
- package/bios/seabios/scripts/kconfig/lxdialog/BIG.FAT.WARNING +0 -4
- package/bios/seabios/scripts/kconfig/lxdialog/check-lxdialog.sh +0 -87
- package/bios/seabios/scripts/kconfig/lxdialog/checklist.c +0 -332
- package/bios/seabios/scripts/kconfig/lxdialog/dialog.h +0 -257
- package/bios/seabios/scripts/kconfig/lxdialog/inputbox.c +0 -301
- package/bios/seabios/scripts/kconfig/lxdialog/menubox.c +0 -437
- package/bios/seabios/scripts/kconfig/lxdialog/textbox.c +0 -408
- package/bios/seabios/scripts/kconfig/lxdialog/util.c +0 -713
- package/bios/seabios/scripts/kconfig/lxdialog/yesno.c +0 -114
- package/bios/seabios/scripts/kconfig/mconf.c +0 -1036
- package/bios/seabios/scripts/kconfig/menu.c +0 -697
- package/bios/seabios/scripts/kconfig/merge_config.sh +0 -150
- package/bios/seabios/scripts/kconfig/nconf.c +0 -1556
- package/bios/seabios/scripts/kconfig/nconf.gui.c +0 -656
- package/bios/seabios/scripts/kconfig/nconf.h +0 -96
- package/bios/seabios/scripts/kconfig/qconf.cc +0 -1795
- package/bios/seabios/scripts/kconfig/qconf.h +0 -338
- package/bios/seabios/scripts/kconfig/streamline_config.pl +0 -647
- package/bios/seabios/scripts/kconfig/symbol.c +0 -1373
- package/bios/seabios/scripts/kconfig/util.c +0 -157
- package/bios/seabios/scripts/kconfig/zconf.gperf +0 -48
- package/bios/seabios/scripts/kconfig/zconf.hash.c_shipped +0 -289
- package/bios/seabios/scripts/kconfig/zconf.l +0 -363
- package/bios/seabios/scripts/kconfig/zconf.lex.c_shipped +0 -2420
- package/bios/seabios/scripts/kconfig/zconf.tab.c_shipped +0 -2538
- package/bios/seabios/scripts/kconfig/zconf.y +0 -733
- package/bios/seabios/scripts/layoutrom.py +0 -705
- package/bios/seabios/scripts/python23compat.py +0 -14
- package/bios/seabios/scripts/readserial.py +0 -190
- package/bios/seabios/scripts/tarball.sh +0 -36
- package/bios/seabios/scripts/test-build.sh +0 -90
- package/bios/seabios/scripts/transdump.py +0 -53
- package/bios/seabios/scripts/vgafixup.py +0 -96
- package/bios/seabios/src/Kconfig +0 -579
- package/bios/seabios/src/apm.c +0 -215
- package/bios/seabios/src/asm-offsets.c +0 -23
- package/bios/seabios/src/biosvar.h +0 -130
- package/bios/seabios/src/block.c +0 -623
- package/bios/seabios/src/block.h +0 -121
- package/bios/seabios/src/bmp.c +0 -117
- package/bios/seabios/src/boot.c +0 -793
- package/bios/seabios/src/bootsplash.c +0 -255
- package/bios/seabios/src/bregs.h +0 -80
- package/bios/seabios/src/byteorder.h +0 -71
- package/bios/seabios/src/cdrom.c +0 -322
- package/bios/seabios/src/clock.c +0 -506
- package/bios/seabios/src/code16gcc.s +0 -1
- package/bios/seabios/src/config.h +0 -108
- package/bios/seabios/src/cp437.c +0 -275
- package/bios/seabios/src/cp437.h +0 -1
- package/bios/seabios/src/disk.c +0 -779
- package/bios/seabios/src/e820map.c +0 -152
- package/bios/seabios/src/e820map.h +0 -26
- package/bios/seabios/src/entryfuncs.S +0 -165
- package/bios/seabios/src/farptr.h +0 -208
- package/bios/seabios/src/font.c +0 -139
- package/bios/seabios/src/fw/acpi-dsdt-cpu-hotplug.dsl +0 -78
- package/bios/seabios/src/fw/acpi-dsdt-dbug.dsl +0 -26
- package/bios/seabios/src/fw/acpi-dsdt-hpet.dsl +0 -36
- package/bios/seabios/src/fw/acpi-dsdt-isa.dsl +0 -102
- package/bios/seabios/src/fw/acpi-dsdt-pci-crs.dsl +0 -90
- package/bios/seabios/src/fw/acpi-dsdt.dsl +0 -342
- package/bios/seabios/src/fw/acpi-dsdt.hex +0 -554
- package/bios/seabios/src/fw/acpi.c +0 -685
- package/bios/seabios/src/fw/biostables.c +0 -491
- package/bios/seabios/src/fw/coreboot.c +0 -569
- package/bios/seabios/src/fw/csm.c +0 -347
- package/bios/seabios/src/fw/dev-pci.h +0 -52
- package/bios/seabios/src/fw/dev-piix.h +0 -29
- package/bios/seabios/src/fw/dev-q35.h +0 -52
- package/bios/seabios/src/fw/lzmadecode.c +0 -398
- package/bios/seabios/src/fw/lzmadecode.h +0 -67
- package/bios/seabios/src/fw/mptable.c +0 -197
- package/bios/seabios/src/fw/mtrr.c +0 -105
- package/bios/seabios/src/fw/multiboot.c +0 -111
- package/bios/seabios/src/fw/paravirt.c +0 -624
- package/bios/seabios/src/fw/paravirt.h +0 -63
- package/bios/seabios/src/fw/pciinit.c +0 -1187
- package/bios/seabios/src/fw/pirtable.c +0 -103
- package/bios/seabios/src/fw/q35-acpi-dsdt.dsl +0 -450
- package/bios/seabios/src/fw/romfile_loader.c +0 -259
- package/bios/seabios/src/fw/romfile_loader.h +0 -91
- package/bios/seabios/src/fw/shadow.c +0 -208
- package/bios/seabios/src/fw/smbios.c +0 -585
- package/bios/seabios/src/fw/smm.c +0 -269
- package/bios/seabios/src/fw/smp.c +0 -194
- package/bios/seabios/src/fw/ssdt-misc.dsl +0 -104
- package/bios/seabios/src/fw/ssdt-misc.hex +0 -88
- package/bios/seabios/src/fw/ssdt-pcihp.dsl +0 -36
- package/bios/seabios/src/fw/ssdt-pcihp.hex +0 -38
- package/bios/seabios/src/fw/ssdt-proc.dsl +0 -48
- package/bios/seabios/src/fw/ssdt-proc.hex +0 -35
- package/bios/seabios/src/fw/xen.c +0 -149
- package/bios/seabios/src/fw/xen.h +0 -125
- package/bios/seabios/src/gen-defs.h +0 -19
- package/bios/seabios/src/hw/ahci.c +0 -697
- package/bios/seabios/src/hw/ahci.h +0 -201
- package/bios/seabios/src/hw/ata.c +0 -1046
- package/bios/seabios/src/hw/ata.h +0 -163
- package/bios/seabios/src/hw/blockcmd.c +0 -372
- package/bios/seabios/src/hw/blockcmd.h +0 -114
- package/bios/seabios/src/hw/dma.c +0 -67
- package/bios/seabios/src/hw/esp-scsi.c +0 -241
- package/bios/seabios/src/hw/esp-scsi.h +0 -8
- package/bios/seabios/src/hw/floppy.c +0 -741
- package/bios/seabios/src/hw/lsi-scsi.c +0 -221
- package/bios/seabios/src/hw/lsi-scsi.h +0 -8
- package/bios/seabios/src/hw/megasas.c +0 -405
- package/bios/seabios/src/hw/megasas.h +0 -8
- package/bios/seabios/src/hw/mpt-scsi.c +0 -319
- package/bios/seabios/src/hw/mpt-scsi.h +0 -8
- package/bios/seabios/src/hw/nvme-int.h +0 -199
- package/bios/seabios/src/hw/nvme.c +0 -708
- package/bios/seabios/src/hw/nvme.h +0 -17
- package/bios/seabios/src/hw/pci.c +0 -133
- package/bios/seabios/src/hw/pci.h +0 -47
- package/bios/seabios/src/hw/pci_ids.h +0 -2632
- package/bios/seabios/src/hw/pci_regs.h +0 -556
- package/bios/seabios/src/hw/pcidevice.c +0 -192
- package/bios/seabios/src/hw/pcidevice.h +0 -76
- package/bios/seabios/src/hw/pic.c +0 -115
- package/bios/seabios/src/hw/pic.h +0 -60
- package/bios/seabios/src/hw/ps2port.c +0 -543
- package/bios/seabios/src/hw/ps2port.h +0 -67
- package/bios/seabios/src/hw/pvscsi.c +0 -333
- package/bios/seabios/src/hw/pvscsi.h +0 -8
- package/bios/seabios/src/hw/ramdisk.c +0 -108
- package/bios/seabios/src/hw/rtc.c +0 -100
- package/bios/seabios/src/hw/rtc.h +0 -75
- package/bios/seabios/src/hw/sdcard.c +0 -572
- package/bios/seabios/src/hw/serialio.c +0 -113
- package/bios/seabios/src/hw/serialio.h +0 -29
- package/bios/seabios/src/hw/timer.c +0 -259
- package/bios/seabios/src/hw/tpm_drivers.c +0 -636
- package/bios/seabios/src/hw/tpm_drivers.h +0 -127
- package/bios/seabios/src/hw/usb-ehci.c +0 -650
- package/bios/seabios/src/hw/usb-ehci.h +0 -177
- package/bios/seabios/src/hw/usb-hid.c +0 -442
- package/bios/seabios/src/hw/usb-hid.h +0 -29
- package/bios/seabios/src/hw/usb-hub.c +0 -205
- package/bios/seabios/src/hw/usb-hub.h +0 -64
- package/bios/seabios/src/hw/usb-msc.c +0 -222
- package/bios/seabios/src/hw/usb-msc.h +0 -10
- package/bios/seabios/src/hw/usb-ohci.c +0 -568
- package/bios/seabios/src/hw/usb-ohci.h +0 -144
- package/bios/seabios/src/hw/usb-uas.c +0 -289
- package/bios/seabios/src/hw/usb-uas.h +0 -9
- package/bios/seabios/src/hw/usb-uhci.c +0 -571
- package/bios/seabios/src/hw/usb-uhci.h +0 -128
- package/bios/seabios/src/hw/usb-xhci.c +0 -1161
- package/bios/seabios/src/hw/usb-xhci.h +0 -133
- package/bios/seabios/src/hw/usb.c +0 -499
- package/bios/seabios/src/hw/usb.h +0 -254
- package/bios/seabios/src/hw/virtio-blk.c +0 -211
- package/bios/seabios/src/hw/virtio-blk.h +0 -43
- package/bios/seabios/src/hw/virtio-pci.c +0 -501
- package/bios/seabios/src/hw/virtio-pci.h +0 -151
- package/bios/seabios/src/hw/virtio-ring.c +0 -147
- package/bios/seabios/src/hw/virtio-ring.h +0 -121
- package/bios/seabios/src/hw/virtio-scsi.c +0 -220
- package/bios/seabios/src/hw/virtio-scsi.h +0 -47
- package/bios/seabios/src/jpeg.c +0 -1055
- package/bios/seabios/src/kbd.c +0 -599
- package/bios/seabios/src/list.h +0 -91
- package/bios/seabios/src/malloc.c +0 -561
- package/bios/seabios/src/malloc.h +0 -70
- package/bios/seabios/src/memmap.h +0 -21
- package/bios/seabios/src/misc.c +0 -195
- package/bios/seabios/src/mouse.c +0 -342
- package/bios/seabios/src/optionroms.c +0 -475
- package/bios/seabios/src/output.c +0 -584
- package/bios/seabios/src/output.h +0 -68
- package/bios/seabios/src/pcibios.c +0 -241
- package/bios/seabios/src/pmm.c +0 -176
- package/bios/seabios/src/pnpbios.c +0 -88
- package/bios/seabios/src/post.c +0 -337
- package/bios/seabios/src/resume.c +0 -157
- package/bios/seabios/src/romfile.c +0 -146
- package/bios/seabios/src/romfile.h +0 -21
- package/bios/seabios/src/romlayout.S +0 -698
- package/bios/seabios/src/sercon.c +0 -677
- package/bios/seabios/src/serial.c +0 -317
- package/bios/seabios/src/sha1.c +0 -147
- package/bios/seabios/src/sha1.h +0 -8
- package/bios/seabios/src/stacks.c +0 -771
- package/bios/seabios/src/stacks.h +0 -68
- package/bios/seabios/src/std/LegacyBios.h +0 -985
- package/bios/seabios/src/std/acpi.h +0 -323
- package/bios/seabios/src/std/bda.h +0 -174
- package/bios/seabios/src/std/disk.h +0 -175
- package/bios/seabios/src/std/mptable.h +0 -77
- package/bios/seabios/src/std/multiboot.h +0 -260
- package/bios/seabios/src/std/optionrom.h +0 -59
- package/bios/seabios/src/std/pirtable.h +0 -35
- package/bios/seabios/src/std/pmm.h +0 -19
- package/bios/seabios/src/std/pnpbios.h +0 -24
- package/bios/seabios/src/std/smbios.h +0 -167
- package/bios/seabios/src/std/tcg.h +0 -554
- package/bios/seabios/src/std/vbe.h +0 -156
- package/bios/seabios/src/std/vga.h +0 -63
- package/bios/seabios/src/string.c +0 -251
- package/bios/seabios/src/string.h +0 -31
- package/bios/seabios/src/system.c +0 -357
- package/bios/seabios/src/tcgbios.c +0 -2014
- package/bios/seabios/src/tcgbios.h +0 -19
- package/bios/seabios/src/types.h +0 -156
- package/bios/seabios/src/util.h +0 -251
- package/bios/seabios/src/version.c +0 -5
- package/bios/seabios/src/vgahooks.c +0 -355
- package/bios/seabios/src/x86.c +0 -23
- package/bios/seabios/src/x86.h +0 -277
- package/bios/seabios/vgasrc/Kconfig +0 -211
- package/bios/seabios/vgasrc/bochsdisplay.c +0 -59
- package/bios/seabios/vgasrc/bochsvga.c +0 -447
- package/bios/seabios/vgasrc/bochsvga.h +0 -57
- package/bios/seabios/vgasrc/cbvga.c +0 -337
- package/bios/seabios/vgasrc/clext.c +0 -627
- package/bios/seabios/vgasrc/geodevga.c +0 -434
- package/bios/seabios/vgasrc/geodevga.h +0 -89
- package/bios/seabios/vgasrc/ramfb.c +0 -163
- package/bios/seabios/vgasrc/stdvga.c +0 -485
- package/bios/seabios/vgasrc/stdvga.h +0 -81
- package/bios/seabios/vgasrc/stdvgaio.c +0 -186
- package/bios/seabios/vgasrc/stdvgamodes.c +0 -534
- package/bios/seabios/vgasrc/swcursor.c +0 -96
- package/bios/seabios/vgasrc/vbe.c +0 -432
- package/bios/seabios/vgasrc/vgabios.c +0 -1131
- package/bios/seabios/vgasrc/vgabios.h +0 -88
- package/bios/seabios/vgasrc/vgaentry.S +0 -161
- package/bios/seabios/vgasrc/vgafb.c +0 -661
- package/bios/seabios/vgasrc/vgafb.h +0 -42
- package/bios/seabios/vgasrc/vgafonts.c +0 -785
- package/bios/seabios/vgasrc/vgahw.h +0 -152
- package/bios/seabios/vgasrc/vgainit.c +0 -202
- package/bios/seabios/vgasrc/vgalayout.lds.S +0 -23
- package/bios/seabios/vgasrc/vgautil.h +0 -103
- package/bios/seabios/vgasrc/vgaversion.c +0 -6
- package/bios/seabios-debug.bin +0 -0
- package/bios/seabios-debug.config +0 -117
- package/bios/seabios.bin +0 -0
- package/bios/seabios.config +0 -114
- package/bios/vgabios-debug.bin +0 -0
- package/bios/vgabios.bin +0 -0
- package/build/binaries.js +0 -1
- package/build/index-debug.cjs +0 -1
- package/build/index-debug.js +0 -1
- package/build/index.cjs +0 -1
- package/build/index.js +0 -1
- package/v86.css +0 -259
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// Support for handling the PS/2 mouse/keyboard ports.
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//
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// Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
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// Several ideas taken from code Copyright (c) 1999-2004 Vojtech Pavlik
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//
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// This file may be distributed under the terms of the GNU LGPLv3 license.
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#include "biosvar.h" // GET_LOW
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#include "output.h" // dprintf
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10
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#include "pic.h" // pic_eoi1
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11
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#include "ps2port.h" // ps2_kbd_command
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#include "romfile.h" // romfile_loadint
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#include "stacks.h" // yield
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#include "util.h" // udelay
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#include "x86.h" // inb
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/****************************************************************
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* Low level i8042 commands.
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****************************************************************/
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// Timeout value.
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#define I8042_CTL_TIMEOUT 10000
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#define I8042_BUFFER_SIZE 16
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static int
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i8042_wait_read(void)
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{
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dprintf(7, "i8042_wait_read\n");
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int i;
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32
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for (i=0; i<I8042_CTL_TIMEOUT; i++) {
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u8 status = inb(PORT_PS2_STATUS);
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if (status & I8042_STR_OBF)
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return 0;
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udelay(50);
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}
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warn_timeout();
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return -1;
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}
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static int
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i8042_wait_write(void)
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{
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dprintf(7, "i8042_wait_write\n");
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int i;
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47
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for (i=0; i<I8042_CTL_TIMEOUT; i++) {
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u8 status = inb(PORT_PS2_STATUS);
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if (! (status & I8042_STR_IBF))
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return 0;
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51
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udelay(50);
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}
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warn_timeout();
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return -1;
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}
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static int
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i8042_flush(void)
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{
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dprintf(7, "i8042_flush\n");
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int i;
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62
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for (i=0; i<I8042_BUFFER_SIZE; i++) {
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u8 status = inb(PORT_PS2_STATUS);
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if (! (status & I8042_STR_OBF))
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return 0;
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udelay(50);
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67
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u8 data = inb(PORT_PS2_DATA);
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dprintf(7, "i8042 flushed %x (status=%x)\n", data, status);
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}
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warn_timeout();
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return -1;
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}
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static int
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__i8042_command(int command, u8 *param)
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{
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int receive = (command >> 8) & 0xf;
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int send = (command >> 12) & 0xf;
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// Send the command.
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int ret = i8042_wait_write();
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if (ret)
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return ret;
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outb(command, PORT_PS2_STATUS);
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// Send parameters (if any).
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int i;
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for (i = 0; i < send; i++) {
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ret = i8042_wait_write();
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if (ret)
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return ret;
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outb(param[i], PORT_PS2_DATA);
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}
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// Receive parameters (if any).
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for (i = 0; i < receive; i++) {
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ret = i8042_wait_read();
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if (ret)
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return ret;
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param[i] = inb(PORT_PS2_DATA);
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dprintf(7, "i8042 param=%x\n", param[i]);
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}
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return 0;
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}
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static int
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i8042_command(int command, u8 *param)
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{
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dprintf(7, "i8042_command cmd=%x\n", command);
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int ret = __i8042_command(command, param);
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if (ret)
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dprintf(2, "i8042 command %x failed\n", command);
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return ret;
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}
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static int
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i8042_kbd_write(u8 c)
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{
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dprintf(7, "i8042_kbd_write c=%d\n", c);
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int ret = i8042_wait_write();
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if (! ret)
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outb(c, PORT_PS2_DATA);
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return ret;
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}
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static int
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i8042_aux_write(u8 c)
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{
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return i8042_command(I8042_CMD_AUX_SEND, &c);
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}
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void
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i8042_reboot(void)
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{
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if (! CONFIG_PS2PORT)
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return;
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int i;
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for (i=0; i<10; i++) {
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i8042_wait_write();
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udelay(50);
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outb(0xfe, PORT_PS2_STATUS); /* pulse reset low */
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udelay(50);
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}
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}
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148
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149
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/****************************************************************
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* Device commands.
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151
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****************************************************************/
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152
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-
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#define PS2_RET_ACK 0xfa
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#define PS2_RET_NAK 0xfe
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155
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156
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static int
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157
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ps2_recvbyte(int aux, int needack, int timeout)
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{
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u32 end = timer_calc(timeout);
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for (;;) {
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u8 status = inb(PORT_PS2_STATUS);
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if (status & I8042_STR_OBF) {
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u8 data = inb(PORT_PS2_DATA);
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dprintf(7, "ps2 read %x\n", data);
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166
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if (!!(status & I8042_STR_AUXDATA) == aux) {
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if (!needack)
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return data;
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if (data == PS2_RET_ACK)
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return data;
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if (data == PS2_RET_NAK) {
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dprintf(1, "Got ps2 nak (status=%x)\n", status);
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return data;
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}
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}
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// This data not part of command - just discard it.
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dprintf(1, "Discarding ps2 data %02x (status=%02x)\n", data, status);
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}
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180
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-
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181
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if (timer_check(end)) {
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182
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warn_timeout();
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183
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return -1;
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184
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}
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185
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yield();
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186
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}
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187
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}
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188
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-
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189
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static int
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190
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ps2_sendbyte(int aux, u8 command, int timeout)
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191
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{
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192
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dprintf(7, "ps2_sendbyte aux=%d cmd=%x\n", aux, command);
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int ret;
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194
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if (aux)
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195
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ret = i8042_aux_write(command);
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196
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else
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197
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ret = i8042_kbd_write(command);
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198
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if (ret)
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199
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return ret;
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200
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-
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201
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// Read ack.
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202
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ret = ps2_recvbyte(aux, 1, timeout);
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203
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if (ret < 0)
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204
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return ret;
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205
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if (ret != PS2_RET_ACK)
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206
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return -1;
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207
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-
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208
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return 0;
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209
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-
}
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210
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-
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211
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u8 Ps2ctr VARLOW = I8042_CTR_KBDDIS | I8042_CTR_AUXDIS;
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212
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-
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213
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static int
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214
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__ps2_command(int aux, int command, u8 *param)
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215
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{
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216
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int ret2;
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217
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int receive = (command >> 8) & 0xf;
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218
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int send = (command >> 12) & 0xf;
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219
|
-
|
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220
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// Disable interrupts and keyboard/mouse.
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221
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u8 ps2ctr = GET_LOW(Ps2ctr);
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222
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u8 newctr = ((ps2ctr | I8042_CTR_AUXDIS | I8042_CTR_KBDDIS)
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223
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& ~(I8042_CTR_KBDINT|I8042_CTR_AUXINT));
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224
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dprintf(6, "i8042 ctr old=%x new=%x\n", ps2ctr, newctr);
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225
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int ret = i8042_command(I8042_CMD_CTL_WCTR, &newctr);
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226
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if (ret)
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227
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return ret;
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228
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-
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229
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// Flush any interrupts already pending.
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230
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yield();
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231
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-
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232
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// Enable port command is being sent to.
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233
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SET_LOW(Ps2ctr, newctr);
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234
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if (aux)
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235
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newctr &= ~I8042_CTR_AUXDIS;
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236
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else
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237
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newctr &= ~I8042_CTR_KBDDIS;
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238
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ret = i8042_command(I8042_CMD_CTL_WCTR, &newctr);
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239
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if (ret)
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240
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goto fail;
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|
241
|
-
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242
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if ((u8)command == (u8)ATKBD_CMD_RESET_BAT) {
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243
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// Reset is special wrt timeouts.
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244
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-
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245
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// Send command.
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246
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ret = ps2_sendbyte(aux, command, 1000);
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247
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if (ret)
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248
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goto fail;
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249
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-
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250
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// Receive parameters.
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251
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ret = ps2_recvbyte(aux, 0, 4000);
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252
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if (ret < 0)
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253
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goto fail;
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254
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param[0] = ret;
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255
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if (receive > 1) {
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256
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ret = ps2_recvbyte(aux, 0, 500);
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257
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if (ret < 0)
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258
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goto fail;
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259
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param[1] = ret;
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260
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-
}
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261
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-
} else if (command == ATKBD_CMD_GETID) {
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262
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// Getid is special wrt bytes received.
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263
|
-
|
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264
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-
// Send command.
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265
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ret = ps2_sendbyte(aux, command, 200);
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266
|
-
if (ret)
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267
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goto fail;
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268
|
-
|
|
269
|
-
// Receive parameters.
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270
|
-
ret = ps2_recvbyte(aux, 0, 500);
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271
|
-
if (ret < 0)
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272
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goto fail;
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273
|
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param[0] = ret;
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274
|
-
if (ret == 0xab || ret == 0xac || ret == 0x2b || ret == 0x5d
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275
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-
|| ret == 0x60 || ret == 0x47) {
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276
|
-
// These ids (keyboards) return two bytes.
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|
277
|
-
ret = ps2_recvbyte(aux, 0, 500);
|
|
278
|
-
if (ret < 0)
|
|
279
|
-
goto fail;
|
|
280
|
-
param[1] = ret;
|
|
281
|
-
} else {
|
|
282
|
-
param[1] = 0;
|
|
283
|
-
}
|
|
284
|
-
} else {
|
|
285
|
-
// Send command.
|
|
286
|
-
ret = ps2_sendbyte(aux, command, 200);
|
|
287
|
-
if (ret)
|
|
288
|
-
goto fail;
|
|
289
|
-
|
|
290
|
-
// Send parameters (if any).
|
|
291
|
-
int i;
|
|
292
|
-
for (i = 0; i < send; i++) {
|
|
293
|
-
ret = ps2_sendbyte(aux, param[i], 200);
|
|
294
|
-
if (ret)
|
|
295
|
-
goto fail;
|
|
296
|
-
}
|
|
297
|
-
|
|
298
|
-
// Receive parameters (if any).
|
|
299
|
-
for (i = 0; i < receive; i++) {
|
|
300
|
-
ret = ps2_recvbyte(aux, 0, 500);
|
|
301
|
-
if (ret < 0)
|
|
302
|
-
goto fail;
|
|
303
|
-
param[i] = ret;
|
|
304
|
-
}
|
|
305
|
-
}
|
|
306
|
-
|
|
307
|
-
ret = 0;
|
|
308
|
-
|
|
309
|
-
fail:
|
|
310
|
-
// Restore interrupts and keyboard/mouse.
|
|
311
|
-
SET_LOW(Ps2ctr, ps2ctr);
|
|
312
|
-
ret2 = i8042_command(I8042_CMD_CTL_WCTR, &ps2ctr);
|
|
313
|
-
if (ret2)
|
|
314
|
-
return ret2;
|
|
315
|
-
|
|
316
|
-
return ret;
|
|
317
|
-
}
|
|
318
|
-
|
|
319
|
-
static int
|
|
320
|
-
ps2_command(int aux, int command, u8 *param)
|
|
321
|
-
{
|
|
322
|
-
dprintf(7, "ps2_command aux=%d cmd=%x\n", aux, command);
|
|
323
|
-
int ret = __ps2_command(aux, command, param);
|
|
324
|
-
if (ret)
|
|
325
|
-
dprintf(2, "ps2 command %x failed (aux=%d)\n", command, aux);
|
|
326
|
-
return ret;
|
|
327
|
-
}
|
|
328
|
-
|
|
329
|
-
int
|
|
330
|
-
ps2_kbd_command(int command, u8 *param)
|
|
331
|
-
{
|
|
332
|
-
if (! CONFIG_PS2PORT)
|
|
333
|
-
return -1;
|
|
334
|
-
return ps2_command(0, command, param);
|
|
335
|
-
}
|
|
336
|
-
|
|
337
|
-
int
|
|
338
|
-
ps2_mouse_command(int command, u8 *param)
|
|
339
|
-
{
|
|
340
|
-
if (! CONFIG_PS2PORT)
|
|
341
|
-
return -1;
|
|
342
|
-
|
|
343
|
-
// Update ps2ctr for mouse enable/disable.
|
|
344
|
-
if (command == PSMOUSE_CMD_ENABLE || command == PSMOUSE_CMD_DISABLE) {
|
|
345
|
-
u8 ps2ctr = GET_LOW(Ps2ctr);
|
|
346
|
-
if (command == PSMOUSE_CMD_ENABLE)
|
|
347
|
-
ps2ctr = ((ps2ctr | (CONFIG_HARDWARE_IRQ ? I8042_CTR_AUXINT : 0))
|
|
348
|
-
& ~I8042_CTR_AUXDIS);
|
|
349
|
-
else
|
|
350
|
-
ps2ctr = (ps2ctr | I8042_CTR_AUXDIS) & ~I8042_CTR_AUXINT;
|
|
351
|
-
SET_LOW(Ps2ctr, ps2ctr);
|
|
352
|
-
}
|
|
353
|
-
|
|
354
|
-
return ps2_command(1, command, param);
|
|
355
|
-
}
|
|
356
|
-
|
|
357
|
-
|
|
358
|
-
/****************************************************************
|
|
359
|
-
* IRQ handlers
|
|
360
|
-
****************************************************************/
|
|
361
|
-
|
|
362
|
-
// INT74h : PS/2 mouse hardware interrupt
|
|
363
|
-
void VISIBLE16
|
|
364
|
-
handle_74(void)
|
|
365
|
-
{
|
|
366
|
-
if (! CONFIG_PS2PORT)
|
|
367
|
-
return;
|
|
368
|
-
|
|
369
|
-
debug_isr(DEBUG_ISR_74);
|
|
370
|
-
|
|
371
|
-
u8 v = inb(PORT_PS2_STATUS);
|
|
372
|
-
if ((v & (I8042_STR_OBF|I8042_STR_AUXDATA))
|
|
373
|
-
!= (I8042_STR_OBF|I8042_STR_AUXDATA)) {
|
|
374
|
-
dprintf(1, "ps2 mouse irq but no mouse data.\n");
|
|
375
|
-
goto done;
|
|
376
|
-
}
|
|
377
|
-
v = inb(PORT_PS2_DATA);
|
|
378
|
-
|
|
379
|
-
if (!(GET_LOW(Ps2ctr) & I8042_CTR_AUXINT))
|
|
380
|
-
// Interrupts not enabled.
|
|
381
|
-
goto done;
|
|
382
|
-
|
|
383
|
-
process_mouse(v);
|
|
384
|
-
|
|
385
|
-
done:
|
|
386
|
-
pic_eoi2();
|
|
387
|
-
}
|
|
388
|
-
|
|
389
|
-
// INT09h : Keyboard Hardware Service Entry Point
|
|
390
|
-
void VISIBLE16
|
|
391
|
-
handle_09(void)
|
|
392
|
-
{
|
|
393
|
-
if (! CONFIG_PS2PORT)
|
|
394
|
-
return;
|
|
395
|
-
|
|
396
|
-
debug_isr(DEBUG_ISR_09);
|
|
397
|
-
|
|
398
|
-
// read key from keyboard controller
|
|
399
|
-
u8 v = inb(PORT_PS2_STATUS);
|
|
400
|
-
if (v & I8042_STR_AUXDATA) {
|
|
401
|
-
dprintf(1, "ps2 keyboard irq but found mouse data?!\n");
|
|
402
|
-
goto done;
|
|
403
|
-
}
|
|
404
|
-
v = inb(PORT_PS2_DATA);
|
|
405
|
-
|
|
406
|
-
if (!(GET_LOW(Ps2ctr) & I8042_CTR_KBDINT))
|
|
407
|
-
// Interrupts not enabled.
|
|
408
|
-
goto done;
|
|
409
|
-
|
|
410
|
-
process_key(v);
|
|
411
|
-
|
|
412
|
-
// Some old programs expect ISR to turn keyboard back on.
|
|
413
|
-
i8042_command(I8042_CMD_KBD_ENABLE, NULL);
|
|
414
|
-
|
|
415
|
-
done:
|
|
416
|
-
pic_eoi1();
|
|
417
|
-
}
|
|
418
|
-
|
|
419
|
-
// Check for ps2 activity on machines without hardware irqs
|
|
420
|
-
void
|
|
421
|
-
ps2_check_event(void)
|
|
422
|
-
{
|
|
423
|
-
if (! CONFIG_PS2PORT || CONFIG_HARDWARE_IRQ)
|
|
424
|
-
return;
|
|
425
|
-
u8 ps2ctr = GET_LOW(Ps2ctr);
|
|
426
|
-
if ((ps2ctr & (I8042_CTR_KBDDIS|I8042_CTR_AUXDIS))
|
|
427
|
-
== (I8042_CTR_KBDDIS|I8042_CTR_AUXDIS))
|
|
428
|
-
return;
|
|
429
|
-
for (;;) {
|
|
430
|
-
u8 status = inb(PORT_PS2_STATUS);
|
|
431
|
-
if (!(status & I8042_STR_OBF))
|
|
432
|
-
break;
|
|
433
|
-
u8 data = inb(PORT_PS2_DATA);
|
|
434
|
-
if (status & I8042_STR_AUXDATA) {
|
|
435
|
-
if (!(ps2ctr & I8042_CTR_AUXDIS))
|
|
436
|
-
process_mouse(data);
|
|
437
|
-
} else {
|
|
438
|
-
if (!(ps2ctr & I8042_CTR_KBDDIS))
|
|
439
|
-
process_key(data);
|
|
440
|
-
}
|
|
441
|
-
}
|
|
442
|
-
}
|
|
443
|
-
|
|
444
|
-
|
|
445
|
-
/****************************************************************
|
|
446
|
-
* Setup
|
|
447
|
-
****************************************************************/
|
|
448
|
-
|
|
449
|
-
static void
|
|
450
|
-
ps2_keyboard_setup(void *data)
|
|
451
|
-
{
|
|
452
|
-
// flush incoming keys (also verifies port is likely present)
|
|
453
|
-
int ret = i8042_flush();
|
|
454
|
-
if (ret)
|
|
455
|
-
return;
|
|
456
|
-
|
|
457
|
-
// Disable keyboard / mouse and drain any input they may have sent
|
|
458
|
-
ret = i8042_command(I8042_CMD_KBD_DISABLE, NULL);
|
|
459
|
-
if (ret)
|
|
460
|
-
return;
|
|
461
|
-
ret = i8042_command(I8042_CMD_AUX_DISABLE, NULL);
|
|
462
|
-
if (ret)
|
|
463
|
-
return;
|
|
464
|
-
ret = i8042_flush();
|
|
465
|
-
if (ret)
|
|
466
|
-
return;
|
|
467
|
-
|
|
468
|
-
// Controller self-test.
|
|
469
|
-
u8 param[2];
|
|
470
|
-
ret = i8042_command(I8042_CMD_CTL_TEST, param);
|
|
471
|
-
if (ret)
|
|
472
|
-
return;
|
|
473
|
-
if (param[0] != 0x55) {
|
|
474
|
-
dprintf(1, "i8042 self test failed (got %x not 0x55)\n", param[0]);
|
|
475
|
-
return;
|
|
476
|
-
}
|
|
477
|
-
|
|
478
|
-
// Controller keyboard test.
|
|
479
|
-
ret = i8042_command(I8042_CMD_KBD_TEST, param);
|
|
480
|
-
if (ret)
|
|
481
|
-
return;
|
|
482
|
-
if (param[0] != 0x00) {
|
|
483
|
-
dprintf(1, "i8042 keyboard test failed (got %x not 0x00)\n", param[0]);
|
|
484
|
-
return;
|
|
485
|
-
}
|
|
486
|
-
|
|
487
|
-
|
|
488
|
-
/* ------------------- keyboard side ------------------------*/
|
|
489
|
-
/* reset keyboard and self test (keyboard side) */
|
|
490
|
-
int spinupdelay = romfile_loadint("etc/ps2-keyboard-spinup", 0);
|
|
491
|
-
u32 end = timer_calc(spinupdelay);
|
|
492
|
-
for (;;) {
|
|
493
|
-
ret = ps2_kbd_command(ATKBD_CMD_RESET_BAT, param);
|
|
494
|
-
if (!ret)
|
|
495
|
-
break;
|
|
496
|
-
if (timer_check(end)) {
|
|
497
|
-
if (spinupdelay)
|
|
498
|
-
warn_timeout();
|
|
499
|
-
return;
|
|
500
|
-
}
|
|
501
|
-
yield();
|
|
502
|
-
}
|
|
503
|
-
if (param[0] != 0xaa) {
|
|
504
|
-
dprintf(1, "keyboard self test failed (got %x not 0xaa)\n", param[0]);
|
|
505
|
-
return;
|
|
506
|
-
}
|
|
507
|
-
|
|
508
|
-
/* Disable keyboard */
|
|
509
|
-
ret = ps2_kbd_command(ATKBD_CMD_RESET_DIS, NULL);
|
|
510
|
-
if (ret)
|
|
511
|
-
return;
|
|
512
|
-
|
|
513
|
-
// Set scancode command (mode 2)
|
|
514
|
-
param[0] = 0x02;
|
|
515
|
-
ret = ps2_kbd_command(ATKBD_CMD_SSCANSET, param);
|
|
516
|
-
if (ret)
|
|
517
|
-
return;
|
|
518
|
-
|
|
519
|
-
// Keyboard Mode: disable mouse, scan code convert, enable kbd IRQ
|
|
520
|
-
Ps2ctr = (I8042_CTR_AUXDIS | I8042_CTR_XLATE
|
|
521
|
-
| (CONFIG_HARDWARE_IRQ ? I8042_CTR_KBDINT : 0));
|
|
522
|
-
|
|
523
|
-
/* Enable keyboard */
|
|
524
|
-
ret = ps2_kbd_command(ATKBD_CMD_ENABLE, NULL);
|
|
525
|
-
if (ret)
|
|
526
|
-
return;
|
|
527
|
-
|
|
528
|
-
dprintf(1, "PS2 keyboard initialized\n");
|
|
529
|
-
}
|
|
530
|
-
|
|
531
|
-
void
|
|
532
|
-
ps2port_setup(void)
|
|
533
|
-
{
|
|
534
|
-
ASSERT32FLAT();
|
|
535
|
-
if (! CONFIG_PS2PORT)
|
|
536
|
-
return;
|
|
537
|
-
dprintf(3, "init ps2port\n");
|
|
538
|
-
|
|
539
|
-
enable_hwirq(1, FUNC16(entry_09));
|
|
540
|
-
enable_hwirq(12, FUNC16(entry_74));
|
|
541
|
-
|
|
542
|
-
run_thread(ps2_keyboard_setup, NULL);
|
|
543
|
-
}
|
|
@@ -1,67 +0,0 @@
|
|
|
1
|
-
// Basic ps2 port (keyboard/mouse) command handling.
|
|
2
|
-
#ifndef __PS2PORT_H
|
|
3
|
-
#define __PS2PORT_H
|
|
4
|
-
|
|
5
|
-
#include "types.h" // u8
|
|
6
|
-
|
|
7
|
-
#define PORT_PS2_DATA 0x0060
|
|
8
|
-
#define PORT_PS2_STATUS 0x0064
|
|
9
|
-
|
|
10
|
-
// Standard commands.
|
|
11
|
-
#define I8042_CMD_CTL_RCTR 0x0120
|
|
12
|
-
#define I8042_CMD_CTL_WCTR 0x1060
|
|
13
|
-
#define I8042_CMD_CTL_TEST 0x01aa
|
|
14
|
-
|
|
15
|
-
#define I8042_CMD_KBD_TEST 0x01ab
|
|
16
|
-
#define I8042_CMD_KBD_DISABLE 0x00ad
|
|
17
|
-
#define I8042_CMD_KBD_ENABLE 0x00ae
|
|
18
|
-
|
|
19
|
-
#define I8042_CMD_AUX_DISABLE 0x00a7
|
|
20
|
-
#define I8042_CMD_AUX_ENABLE 0x00a8
|
|
21
|
-
#define I8042_CMD_AUX_SEND 0x10d4
|
|
22
|
-
|
|
23
|
-
// Keyboard commands
|
|
24
|
-
#define ATKBD_CMD_SETLEDS 0x10ed
|
|
25
|
-
#define ATKBD_CMD_SSCANSET 0x10f0
|
|
26
|
-
#define ATKBD_CMD_GETID 0x02f2
|
|
27
|
-
#define ATKBD_CMD_ENABLE 0x00f4
|
|
28
|
-
#define ATKBD_CMD_RESET_DIS 0x00f5
|
|
29
|
-
#define ATKBD_CMD_RESET_BAT 0x01ff
|
|
30
|
-
|
|
31
|
-
// Mouse commands
|
|
32
|
-
#define PSMOUSE_CMD_SETSCALE11 0x00e6
|
|
33
|
-
#define PSMOUSE_CMD_SETSCALE21 0x00e7
|
|
34
|
-
#define PSMOUSE_CMD_SETRES 0x10e8
|
|
35
|
-
#define PSMOUSE_CMD_GETINFO 0x03e9
|
|
36
|
-
#define PSMOUSE_CMD_GETID 0x02f2
|
|
37
|
-
#define PSMOUSE_CMD_SETRATE 0x10f3
|
|
38
|
-
#define PSMOUSE_CMD_ENABLE 0x00f4
|
|
39
|
-
#define PSMOUSE_CMD_DISABLE 0x00f5
|
|
40
|
-
#define PSMOUSE_CMD_RESET_BAT 0x02ff
|
|
41
|
-
|
|
42
|
-
// Status register bits.
|
|
43
|
-
#define I8042_STR_PARITY 0x80
|
|
44
|
-
#define I8042_STR_TIMEOUT 0x40
|
|
45
|
-
#define I8042_STR_AUXDATA 0x20
|
|
46
|
-
#define I8042_STR_KEYLOCK 0x10
|
|
47
|
-
#define I8042_STR_CMDDAT 0x08
|
|
48
|
-
#define I8042_STR_MUXERR 0x04
|
|
49
|
-
#define I8042_STR_IBF 0x02
|
|
50
|
-
#define I8042_STR_OBF 0x01
|
|
51
|
-
|
|
52
|
-
// Control register bits.
|
|
53
|
-
#define I8042_CTR_KBDINT 0x01
|
|
54
|
-
#define I8042_CTR_AUXINT 0x02
|
|
55
|
-
#define I8042_CTR_IGNKEYLOCK 0x08
|
|
56
|
-
#define I8042_CTR_KBDDIS 0x10
|
|
57
|
-
#define I8042_CTR_AUXDIS 0x20
|
|
58
|
-
#define I8042_CTR_XLATE 0x40
|
|
59
|
-
|
|
60
|
-
// ps2port.c
|
|
61
|
-
void i8042_reboot(void);
|
|
62
|
-
int ps2_kbd_command(int command, u8 *param);
|
|
63
|
-
int ps2_mouse_command(int command, u8 *param);
|
|
64
|
-
void ps2_check_event(void);
|
|
65
|
-
void ps2port_setup(void);
|
|
66
|
-
|
|
67
|
-
#endif // ps2port.h
|