@joezilla/8sim 0.10.0

package/dist/clock/SystemClock.js

@@ -0,0 +1,71 @@
+/**
+ * A real-time clock that tracks how far the simulation has run relative to a
+ * target CPU frequency. Uses performance.now() for timing — works in Node 16+,
+ * all browsers, Deno, Bun. Uses setTimeout(fn, 0) for yielding — no
+ * setImmediate or process.* dependencies.
+ *
+ * Drift accounting is absolute (cycles vs. wall time since the last baseline),
+ * so oversleeping or scheduler jitter self-corrects instead of accumulating.
+ */
+export class SystemClock {
+    elapsed = 0n;
+    hz;
+    startTime;
+    cyclesAtStart = 0n;
+    now;
+    constructor(hz = 2_000_000, now = () => performance.now()) {
+        this.hz = hz;
+        this.now = now;
+        this.startTime = now();
+    }
+    addCycles(cycles) {
+        this.elapsed += BigInt(cycles);
+    }
+    getElapsedCycles() {
+        return this.elapsed;
+    }
+    reset() {
+        this.elapsed = 0n;
+        this.rebaseline();
+    }
+    get targetHz() {
+        return this.hz;
+    }
+    /**
+     * Change the target frequency. Re-baselines so the new rate applies from
+     * this moment — cycles already executed are not retroactively repriced.
+     */
+    setHz(hz) {
+        this.rebaseline();
+        this.hz = hz;
+    }
+    /**
+     * Forfeit any accumulated drift and restart pacing from "now". Used after
+     * host stalls (GC pause, suspended tab) so the simulation doesn't sprint to
+     * catch up on lost wall time.
+     */
+    resync() {
+        this.rebaseline();
+    }
+    /**
+     * Returns a promise that resolves after yielding to the event loop.
+     * Callers should await this periodically to avoid blocking.
+     */
+    yield() {
+        return new Promise(resolve => setTimeout(resolve, 0));
+    }
+    /**
+     * How far ahead (in ms) the simulation is relative to wall time.
+     * Positive = running too fast (should sleep); negative = behind.
+     */
+    getAheadMs() {
+        const wallMs = this.now() - this.startTime;
+        const simMs = Number(this.elapsed - this.cyclesAtStart) / this.hz * 1000;
+        return simMs - wallMs;
+    }
+    rebaseline() {
+        this.cyclesAtStart = this.elapsed;
+        this.startTime = this.now();
+    }
+}
+//# sourceMappingURL=SystemClock.js.map

package/dist/clock/SystemClock.js.map

@@ -0,0 +1 @@
+{"version":3,"file":"SystemClock.js","sourceRoot":"","sources":["../../src/clock/SystemClock.ts"],"names":[],"mappings":"AAEA;;;;;;;;GAQG;AACH,MAAM,OAAO,WAAW;IACd,OAAO,GAAG,EAAE,CAAC;IACb,EAAE,CAAS;IACX,SAAS,CAAS;IAClB,aAAa,GAAG,EAAE,CAAC;IACV,GAAG,CAAe;IAEnC,YAAY,EAAE,GAAG,SAAS,EAAE,MAAoB,GAAG,EAAE,CAAC,WAAW,CAAC,GAAG,EAAE;QACrE,IAAI,CAAC,EAAE,GAAG,EAAE,CAAC;QACb,IAAI,CAAC,GAAG,GAAG,GAAG,CAAC;QACf,IAAI,CAAC,SAAS,GAAG,GAAG,EAAE,CAAC;IACzB,CAAC;IAED,SAAS,CAAC,MAAc;QACtB,IAAI,CAAC,OAAO,IAAI,MAAM,CAAC,MAAM,CAAC,CAAC;IACjC,CAAC;IAED,gBAAgB;QACd,OAAO,IAAI,CAAC,OAAO,CAAC;IACtB,CAAC;IAED,KAAK;QACH,IAAI,CAAC,OAAO,GAAG,EAAE,CAAC;QAClB,IAAI,CAAC,UAAU,EAAE,CAAC;IACpB,CAAC;IAED,IAAI,QAAQ;QACV,OAAO,IAAI,CAAC,EAAE,CAAC;IACjB,CAAC;IAED;;;OAGG;IACH,KAAK,CAAC,EAAU;QACd,IAAI,CAAC,UAAU,EAAE,CAAC;QAClB,IAAI,CAAC,EAAE,GAAG,EAAE,CAAC;IACf,CAAC;IAED;;;;OAIG;IACH,MAAM;QACJ,IAAI,CAAC,UAAU,EAAE,CAAC;IACpB,CAAC;IAED;;;OAGG;IACH,KAAK;QACH,OAAO,IAAI,OAAO,CAAC,OAAO,CAAC,EAAE,CAAC,UAAU,CAAC,OAAO,EAAE,CAAC,CAAC,CAAC,CAAC;IACxD,CAAC;IAED;;;OAGG;IACH,UAAU;QACR,MAAM,MAAM,GAAG,IAAI,CAAC,GAAG,EAAE,GAAG,IAAI,CAAC,SAAS,CAAC;QAC3C,MAAM,KAAK,GAAG,MAAM,CAAC,IAAI,CAAC,OAAO,GAAG,IAAI,CAAC,aAAa,CAAC,GAAG,IAAI,CAAC,EAAE,GAAG,IAAI,CAAC;QACzE,OAAO,KAAK,GAAG,MAAM,CAAC;IACxB,CAAC;IAEO,UAAU;QAChB,IAAI,CAAC,aAAa,GAAG,IAAI,CAAC,OAAO,CAAC;QAClC,IAAI,CAAC,SAAS,GAAG,IAAI,CAAC,GAAG,EAAE,CAAC;IAC9B,CAAC;CACF"}

package/dist/cpu/Cpu8080.d.ts

@@ -0,0 +1,34 @@
+import type { IBus } from '../interfaces/IBus.js';
+import type { ICpu, CpuState } from '../interfaces/ICpu.js';
+import type { IInterruptController } from '../interfaces/IInterruptController.js';
+import { Registers } from './Registers.js';
+import { Flags } from './Flags.js';
+export declare class Cpu8080 implements ICpu {
+    readonly registers: Registers;
+    readonly flags: Flags;
+    private bus;
+    private pic;
+    private decoder;
+    inte: boolean;
+    pendingEI: boolean;
+    halted: boolean;
+    /** Front-panel status byte of the last instruction (Bitsby8 cockpit). */
+    private lastStatus;
+    private readonly statusTable;
+    /** Program counter accessor (ICpu); proxies the register file. */
+    get pc(): number;
+    set pc(v: number);
+    /** Uniform register/flags snapshot for introspection (ICpu). */
+    state(): CpuState;
+    constructor(bus: IBus, pic: IInterruptController);
+    private buildDecoder;
+    reset(): void;
+    step(): number;
+    private handleInterrupt;
+    /**
+     * Run until halted or maxCycles exceeded.
+     * Returns total T-states executed.
+     */
+    run(maxCycles?: number): bigint;
+}
+//# sourceMappingURL=Cpu8080.d.ts.map

package/dist/cpu/Cpu8080.d.ts.map

@@ -0,0 +1 @@
+{"version":3,"file":"Cpu8080.d.ts","sourceRoot":"","sources":["../../src/cpu/Cpu8080.ts"],"names":[],"mappings":"AAAA,OAAO,KAAK,EAAE,IAAI,EAAE,MAAM,uBAAuB,CAAC;AAClD,OAAO,KAAK,EAAE,IAAI,EAAE,QAAQ,EAAE,MAAM,uBAAuB,CAAC;AAC5D,OAAO,KAAK,EAAE,oBAAoB,EAAE,MAAM,uCAAuC,CAAC;AAClF,OAAO,EAAE,SAAS,EAAE,MAAM,gBAAgB,CAAC;AAC3C,OAAO,EAAE,KAAK,EAAE,MAAM,YAAY,CAAC;AAanC,qBAAa,OAAQ,YAAW,IAAI;IAClC,QAAQ,CAAC,SAAS,EAAE,SAAS,CAAC;IAC9B,QAAQ,CAAC,KAAK,EAAE,KAAK,CAAC;IACtB,OAAO,CAAC,GAAG,CAAO;IAClB,OAAO,CAAC,GAAG,CAAuB;IAClC,OAAO,CAAC,OAAO,CAAU;IAEzB,IAAI,UAAS;IACb,SAAS,UAAS;IAClB,MAAM,UAAS;IACf,yEAAyE;IACzE,OAAO,CAAC,UAAU,CAAgB;IAClC,OAAO,CAAC,QAAQ,CAAC,WAAW,CAAsB;IAElD,kEAAkE;IAClE,IAAI,EAAE,IAAI,MAAM,CAA8B;IAC9C,IAAI,EAAE,CAAC,CAAC,EAAE,MAAM,EAAiC;IAEjD,gEAAgE;IAChE,KAAK,IAAI,QAAQ;gBAKL,GAAG,EAAE,IAAI,EAAE,GAAG,EAAE,oBAAoB;IAShD,OAAO,CAAC,YAAY;IAWpB,KAAK,IAAI,IAAI;IASb,IAAI,IAAI,MAAM;IA+Cd,OAAO,CAAC,eAAe;IAevB;;;OAGG;IACH,GAAG,CAAC,SAAS,SAAW,GAAG,MAAM;CAOlC"}

package/dist/cpu/Cpu8080.js

@@ -0,0 +1,126 @@
+import { Registers } from './Registers.js';
+import { Flags } from './Flags.js';
+import { Decoder } from './Decoder.js';
+import { buildStatusTable, FETCH_STATUS, INTA_STATUS } from './status8080.js';
+import { registerControl } from './instructions/control.js';
+import { registerData } from './instructions/data.js';
+import { registerAlu } from './instructions/alu.js';
+import { registerLogical } from './instructions/logical.js';
+import { registerRotate } from './instructions/rotate.js';
+import { registerBranch } from './instructions/branch.js';
+import { registerStack } from './instructions/stack.js';
+import { registerIO } from './instructions/io.js';
+import { u16 } from '../util/bits.js';
+export class Cpu8080 {
+    registers;
+    flags;
+    bus;
+    pic;
+    decoder;
+    inte = false;
+    pendingEI = false;
+    halted = false;
+    /** Front-panel status byte of the last instruction (Bitsby8 cockpit). */
+    lastStatus = FETCH_STATUS;
+    statusTable = buildStatusTable();
+    /** Program counter accessor (ICpu); proxies the register file. */
+    get pc() { return this.registers.pc; }
+    set pc(v) { this.registers.pc = u16(v); }
+    /** Uniform register/flags snapshot for introspection (ICpu). */
+    state() {
+        const r = this.registers;
+        return { pc: r.pc, sp: r.sp, a: r.a, f: this.flags.toByte(), b: r.b, c: r.c, d: r.d, e: r.e, h: r.h, l: r.l, halted: this.halted, inte: this.inte, intPending: this.pic.hasPendingInterrupt(), status: this.lastStatus };
+    }
+    constructor(bus, pic) {
+        this.bus = bus;
+        this.pic = pic;
+        this.registers = new Registers();
+        this.flags = new Flags();
+        this.decoder = new Decoder();
+        this.buildDecoder();
+    }
+    buildDecoder() {
+        registerControl(this.decoder);
+        registerData(this.decoder);
+        registerAlu(this.decoder);
+        registerLogical(this.decoder);
+        registerRotate(this.decoder);
+        registerBranch(this.decoder);
+        registerStack(this.decoder);
+        registerIO(this.decoder);
+    }
+    reset() {
+        this.registers.reset();
+        this.flags.reset();
+        this.inte = false;
+        this.pendingEI = false;
+        this.halted = false;
+        this.lastStatus = FETCH_STATUS;
+    }
+    step() {
+        const regs = this.registers;
+        // Handle halted state
+        if (this.halted) {
+            if (this.inte && this.pic.hasPendingInterrupt()) {
+                this.handleInterrupt();
+                return 11;
+            }
+            return 4;
+        }
+        // Commit pendingEI: the instruction after EI is the first that can be interrupted
+        if (this.pendingEI) {
+            this.inte = true;
+            this.pendingEI = false;
+        }
+        // Check for interrupt
+        if (this.inte && this.pic.hasPendingInterrupt()) {
+            this.handleInterrupt();
+            return 11;
+        }
+        const opcode = this.bus.read(regs.pc);
+        regs.pc = u16(regs.pc + 1);
+        this.lastStatus = this.statusTable[opcode]; // latch the panel status byte
+        // Handle special opcodes inline
+        if (opcode === 0x76) { // HLT
+            this.halted = true;
+            return 7;
+        }
+        if (opcode === 0xfb) { // EI
+            this.pendingEI = true;
+            return 4;
+        }
+        if (opcode === 0xf3) { // DI
+            this.inte = false;
+            this.pendingEI = false;
+            return 4;
+        }
+        const handler = this.decoder.decode(opcode);
+        return handler(regs, this.flags, this.bus);
+    }
+    handleInterrupt() {
+        this.inte = false;
+        this.halted = false;
+        this.lastStatus = INTA_STATUS;
+        const rstByte = this.bus.acknowledgeInterrupt();
+        const regs = this.registers;
+        // Push current PC
+        regs.sp = u16(regs.sp - 1);
+        this.bus.write(regs.sp, (regs.pc >> 8) & 0xff);
+        regs.sp = u16(regs.sp - 1);
+        this.bus.write(regs.sp, regs.pc & 0xff);
+        // Jump to RST vector
+        regs.pc = (rstByte & 0x38);
+    }
+    /**
+     * Run until halted or maxCycles exceeded.
+     * Returns total T-states executed.
+     */
+    run(maxCycles = Infinity) {
+        let total = 0n;
+        while (!this.halted && total < BigInt(maxCycles)) {
+            total += BigInt(this.step());
+        }
+        return total;
+    }
+}
+//# sourceMappingURL=Cpu8080.js.map

package/dist/cpu/Cpu8080.js.map

@@ -0,0 +1 @@
+{"version":3,"file":"Cpu8080.js","sourceRoot":"","sources":["../../src/cpu/Cpu8080.ts"],"names":[],"mappings":"AAGA,OAAO,EAAE,SAAS,EAAE,MAAM,gBAAgB,CAAC;AAC3C,OAAO,EAAE,KAAK,EAAE,MAAM,YAAY,CAAC;AACnC,OAAO,EAAE,OAAO,EAAE,MAAM,cAAc,CAAC;AACvC,OAAO,EAAE,gBAAgB,EAAE,YAAY,EAAE,WAAW,EAAE,MAAM,iBAAiB,CAAC;AAC9E,OAAO,EAAE,eAAe,EAAE,MAAM,2BAA2B,CAAC;AAC5D,OAAO,EAAE,YAAY,EAAE,MAAM,wBAAwB,CAAC;AACtD,OAAO,EAAE,WAAW,EAAE,MAAM,uBAAuB,CAAC;AACpD,OAAO,EAAE,eAAe,EAAE,MAAM,2BAA2B,CAAC;AAC5D,OAAO,EAAE,cAAc,EAAE,MAAM,0BAA0B,CAAC;AAC1D,OAAO,EAAE,cAAc,EAAE,MAAM,0BAA0B,CAAC;AAC1D,OAAO,EAAE,aAAa,EAAE,MAAM,yBAAyB,CAAC;AACxD,OAAO,EAAE,UAAU,EAAE,MAAM,sBAAsB,CAAC;AAClD,OAAO,EAAE,GAAG,EAAE,MAAM,iBAAiB,CAAC;AAEtC,MAAM,OAAO,OAAO;IACT,SAAS,CAAY;IACrB,KAAK,CAAQ;IACd,GAAG,CAAO;IACV,GAAG,CAAuB;IAC1B,OAAO,CAAU;IAEzB,IAAI,GAAG,KAAK,CAAC;IACb,SAAS,GAAG,KAAK,CAAC;IAClB,MAAM,GAAG,KAAK,CAAC;IACf,yEAAyE;IACjE,UAAU,GAAG,YAAY,CAAC;IACjB,WAAW,GAAG,gBAAgB,EAAE,CAAC;IAElD,kEAAkE;IAClE,IAAI,EAAE,KAAa,OAAO,IAAI,CAAC,SAAS,CAAC,EAAE,CAAC,CAAC,CAAC;IAC9C,IAAI,EAAE,CAAC,CAAS,IAAI,IAAI,CAAC,SAAS,CAAC,EAAE,GAAG,GAAG,CAAC,CAAC,CAAC,CAAC,CAAC,CAAC;IAEjD,gEAAgE;IAChE,KAAK;QACH,MAAM,CAAC,GAAG,IAAI,CAAC,SAAS,CAAC;QACzB,OAAO,EAAE,EAAE,EAAE,CAAC,CAAC,EAAE,EAAE,EAAE,EAAE,CAAC,CAAC,EAAE,EAAE,CAAC,EAAE,CAAC,CAAC,CAAC,EAAE,CAAC,EAAE,IAAI,CAAC,KAAK,CAAC,MAAM,EAAE,EAAE,CAAC,EAAE,CAAC,CAAC,CAAC,EAAE,CAAC,EAAE,CAAC,CAAC,CAAC,EAAE,CAAC,EAAE,CAAC,CAAC,CAAC,EAAE,CAAC,EAAE,CAAC,CAAC,CAAC,EAAE,CAAC,EAAE,CAAC,CAAC,CAAC,EAAE,CAAC,EAAE,CAAC,CAAC,CAAC,EAAE,MAAM,EAAE,IAAI,CAAC,MAAM,EAAE,IAAI,EAAE,IAAI,CAAC,IAAI,EAAE,UAAU,EAAE,IAAI,CAAC,GAAG,CAAC,mBAAmB,EAAE,EAAE,MAAM,EAAE,IAAI,CAAC,UAAU,EAAE,CAAC;IAC3N,CAAC;IAED,YAAY,GAAS,EAAE,GAAyB;QAC9C,IAAI,CAAC,GAAG,GAAG,GAAG,CAAC;QACf,IAAI,CAAC,GAAG,GAAG,GAAG,CAAC;QACf,IAAI,CAAC,SAAS,GAAG,IAAI,SAAS,EAAE,CAAC;QACjC,IAAI,CAAC,KAAK,GAAG,IAAI,KAAK,EAAE,CAAC;QACzB,IAAI,CAAC,OAAO,GAAG,IAAI,OAAO,EAAE,CAAC;QAC7B,IAAI,CAAC,YAAY,EAAE,CAAC;IACtB,CAAC;IAEO,YAAY;QAClB,eAAe,CAAC,IAAI,CAAC,OAAO,CAAC,CAAC;QAC9B,YAAY,CAAC,IAAI,CAAC,OAAO,CAAC,CAAC;QAC3B,WAAW,CAAC,IAAI,CAAC,OAAO,CAAC,CAAC;QAC1B,eAAe,CAAC,IAAI,CAAC,OAAO,CAAC,CAAC;QAC9B,cAAc,CAAC,IAAI,CAAC,OAAO,CAAC,CAAC;QAC7B,cAAc,CAAC,IAAI,CAAC,OAAO,CAAC,CAAC;QAC7B,aAAa,CAAC,IAAI,CAAC,OAAO,CAAC,CAAC;QAC5B,UAAU,CAAC,IAAI,CAAC,OAAO,CAAC,CAAC;IAC3B,CAAC;IAED,KAAK;QACH,IAAI,CAAC,SAAS,CAAC,KAAK,EAAE,CAAC;QACvB,IAAI,CAAC,KAAK,CAAC,KAAK,EAAE,CAAC;QACnB,IAAI,CAAC,IAAI,GAAG,KAAK,CAAC;QAClB,IAAI,CAAC,SAAS,GAAG,KAAK,CAAC;QACvB,IAAI,CAAC,MAAM,GAAG,KAAK,CAAC;QACpB,IAAI,CAAC,UAAU,GAAG,YAAY,CAAC;IACjC,CAAC;IAED,IAAI;QACF,MAAM,IAAI,GAAG,IAAI,CAAC,SAAS,CAAC;QAE5B,sBAAsB;QACtB,IAAI,IAAI,CAAC,MAAM,EAAE,CAAC;YAChB,IAAI,IAAI,CAAC,IAAI,IAAI,IAAI,CAAC,GAAG,CAAC,mBAAmB,EAAE,EAAE,CAAC;gBAChD,IAAI,CAAC,eAAe,EAAE,CAAC;gBACvB,OAAO,EAAE,CAAC;YACZ,CAAC;YACD,OAAO,CAAC,CAAC;QACX,CAAC;QAED,kFAAkF;QAClF,IAAI,IAAI,CAAC,SAAS,EAAE,CAAC;YACnB,IAAI,CAAC,IAAI,GAAG,IAAI,CAAC;YACjB,IAAI,CAAC,SAAS,GAAG,KAAK,CAAC;QACzB,CAAC;QAED,sBAAsB;QACtB,IAAI,IAAI,CAAC,IAAI,IAAI,IAAI,CAAC,GAAG,CAAC,mBAAmB,EAAE,EAAE,CAAC;YAChD,IAAI,CAAC,eAAe,EAAE,CAAC;YACvB,OAAO,EAAE,CAAC;QACZ,CAAC;QAED,MAAM,MAAM,GAAG,IAAI,CAAC,GAAG,CAAC,IAAI,CAAC,IAAI,CAAC,EAAE,CAAC,CAAC;QACtC,IAAI,CAAC,EAAE,GAAG,GAAG,CAAC,IAAI,CAAC,EAAE,GAAG,CAAC,CAAC,CAAC;QAC3B,IAAI,CAAC,UAAU,GAAG,IAAI,CAAC,WAAW,CAAC,MAAM,CAAE,CAAC,CAAC,8BAA8B;QAE3E,gCAAgC;QAChC,IAAI,MAAM,KAAK,IAAI,EAAE,CAAC,CAAC,MAAM;YAC3B,IAAI,CAAC,MAAM,GAAG,IAAI,CAAC;YACnB,OAAO,CAAC,CAAC;QACX,CAAC;QACD,IAAI,MAAM,KAAK,IAAI,EAAE,CAAC,CAAC,KAAK;YAC1B,IAAI,CAAC,SAAS,GAAG,IAAI,CAAC;YACtB,OAAO,CAAC,CAAC;QACX,CAAC;QACD,IAAI,MAAM,KAAK,IAAI,EAAE,CAAC,CAAC,KAAK;YAC1B,IAAI,CAAC,IAAI,GAAG,KAAK,CAAC;YAClB,IAAI,CAAC,SAAS,GAAG,KAAK,CAAC;YACvB,OAAO,CAAC,CAAC;QACX,CAAC;QAED,MAAM,OAAO,GAAG,IAAI,CAAC,OAAO,CAAC,MAAM,CAAC,MAAM,CAAC,CAAC;QAC5C,OAAO,OAAO,CAAC,IAAI,EAAE,IAAI,CAAC,KAAK,EAAE,IAAI,CAAC,GAAG,CAAC,CAAC;IAC7C,CAAC;IAEO,eAAe;QACrB,IAAI,CAAC,IAAI,GAAG,KAAK,CAAC;QAClB,IAAI,CAAC,MAAM,GAAG,KAAK,CAAC;QACpB,IAAI,CAAC,UAAU,GAAG,WAAW,CAAC;QAC9B,MAAM,OAAO,GAAG,IAAI,CAAC,GAAG,CAAC,oBAAoB,EAAE,CAAC;QAChD,MAAM,IAAI,GAAG,IAAI,CAAC,SAAS,CAAC;QAC5B,kBAAkB;QAClB,IAAI,CAAC,EAAE,GAAG,GAAG,CAAC,IAAI,CAAC,EAAE,GAAG,CAAC,CAAC,CAAC;QAC3B,IAAI,CAAC,GAAG,CAAC,KAAK,CAAC,IAAI,CAAC,EAAE,EAAE,CAAC,IAAI,CAAC,EAAE,IAAI,CAAC,CAAC,GAAG,IAAI,CAAC,CAAC;QAC/C,IAAI,CAAC,EAAE,GAAG,GAAG,CAAC,IAAI,CAAC,EAAE,GAAG,CAAC,CAAC,CAAC;QAC3B,IAAI,CAAC,GAAG,CAAC,KAAK,CAAC,IAAI,CAAC,EAAE,EAAE,IAAI,CAAC,EAAE,GAAG,IAAI,CAAC,CAAC;QACxC,qBAAqB;QACrB,IAAI,CAAC,EAAE,GAAG,CAAC,OAAO,GAAG,IAAI,CAAC,CAAC;IAC7B,CAAC;IAED;;;OAGG;IACH,GAAG,CAAC,SAAS,GAAG,QAAQ;QACtB,IAAI,KAAK,GAAG,EAAE,CAAC;QACf,OAAO,CAAC,IAAI,CAAC,MAAM,IAAI,KAAK,GAAG,MAAM,CAAC,SAAS,CAAC,EAAE,CAAC;YACjD,KAAK,IAAI,MAAM,CAAC,IAAI,CAAC,IAAI,EAAE,CAAC,CAAC;QAC/B,CAAC;QACD,OAAO,KAAK,CAAC;IACf,CAAC;CACF"}

package/dist/cpu/Decoder.d.ts

@@ -0,0 +1,12 @@
+import type { IBus } from '../interfaces/IBus.js';
+import type { Registers } from './Registers.js';
+import type { Flags } from './Flags.js';
+export type InstructionHandler = (regs: Registers, flags: Flags, bus: IBus) => number;
+export declare class Decoder {
+    private table;
+    constructor();
+    register(opcode: number, handler: InstructionHandler): void;
+    registerMany(opcodes: number[], handler: InstructionHandler): void;
+    decode(opcode: number): InstructionHandler;
+}
+//# sourceMappingURL=Decoder.d.ts.map

package/dist/cpu/Decoder.d.ts.map

@@ -0,0 +1 @@
+{"version":3,"file":"Decoder.d.ts","sourceRoot":"","sources":["../../src/cpu/Decoder.ts"],"names":[],"mappings":"AAAA,OAAO,KAAK,EAAE,IAAI,EAAE,MAAM,uBAAuB,CAAC;AAClD,OAAO,KAAK,EAAE,SAAS,EAAE,MAAM,gBAAgB,CAAC;AAChD,OAAO,KAAK,EAAE,KAAK,EAAE,MAAM,YAAY,CAAC;AAExC,MAAM,MAAM,kBAAkB,GAAG,CAAC,IAAI,EAAE,SAAS,EAAE,KAAK,EAAE,KAAK,EAAE,GAAG,EAAE,IAAI,KAAK,MAAM,CAAC;AAEtF,qBAAa,OAAO;IAClB,OAAO,CAAC,KAAK,CAAuB;;IAWpC,QAAQ,CAAC,MAAM,EAAE,MAAM,EAAE,OAAO,EAAE,kBAAkB,GAAG,IAAI;IAI3D,YAAY,CAAC,OAAO,EAAE,MAAM,EAAE,EAAE,OAAO,EAAE,kBAAkB,GAAG,IAAI;IAMlE,MAAM,CAAC,MAAM,EAAE,MAAM,GAAG,kBAAkB;CAG3C"}

package/dist/cpu/Decoder.js

@@ -0,0 +1,23 @@
+export class Decoder {
+    table;
+    constructor() {
+        this.table = new Array(256).fill(undefined).map((_, i) => {
+            return (_regs, _flags, _bus) => {
+                console.warn(`Unimplemented opcode: 0x${i.toString(16).padStart(2, '0')}`);
+                return 4;
+            };
+        });
+    }
+    register(opcode, handler) {
+        this.table[opcode] = handler;
+    }
+    registerMany(opcodes, handler) {
+        for (const op of opcodes) {
+            this.register(op, handler);
+        }
+    }
+    decode(opcode) {
+        return this.table[opcode & 0xff];
+    }
+}
+//# sourceMappingURL=Decoder.js.map

package/dist/cpu/Decoder.js.map

@@ -0,0 +1 @@
+{"version":3,"file":"Decoder.js","sourceRoot":"","sources":["../../src/cpu/Decoder.ts"],"names":[],"mappings":"AAMA,MAAM,OAAO,OAAO;IACV,KAAK,CAAuB;IAEpC;QACE,IAAI,CAAC,KAAK,GAAG,IAAI,KAAK,CAAC,GAAG,CAAC,CAAC,IAAI,CAAC,SAAS,CAAC,CAAC,GAAG,CAAC,CAAC,CAAC,EAAE,CAAC,EAAE,EAAE;YACvD,OAAO,CAAC,KAAgB,EAAE,MAAa,EAAE,IAAU,EAAU,EAAE;gBAC7D,OAAO,CAAC,IAAI,CAAC,2BAA2B,CAAC,CAAC,QAAQ,CAAC,EAAE,CAAC,CAAC,QAAQ,CAAC,CAAC,EAAE,GAAG,CAAC,EAAE,CAAC,CAAC;gBAC3E,OAAO,CAAC,CAAC;YACX,CAAC,CAAC;QACJ,CAAC,CAAC,CAAC;IACL,CAAC;IAED,QAAQ,CAAC,MAAc,EAAE,OAA2B;QAClD,IAAI,CAAC,KAAK,CAAC,MAAM,CAAC,GAAG,OAAO,CAAC;IAC/B,CAAC;IAED,YAAY,CAAC,OAAiB,EAAE,OAA2B;QACzD,KAAK,MAAM,EAAE,IAAI,OAAO,EAAE,CAAC;YACzB,IAAI,CAAC,QAAQ,CAAC,EAAE,EAAE,OAAO,CAAC,CAAC;QAC7B,CAAC;IACH,CAAC;IAED,MAAM,CAAC,MAAc;QACnB,OAAO,IAAI,CAAC,KAAK,CAAC,MAAM,GAAG,IAAI,CAAE,CAAC;IACpC,CAAC;CACF"}

package/dist/cpu/Flags.d.ts

@@ -0,0 +1,18 @@
+/**
+ * Intel 8080 flags register.
+ * Stored in PSW byte format: S Z 0 AC 0 P 1 CY
+ * Bits: 7=S, 6=Z, 5=0, 4=AC, 3=0, 2=P, 1=1, 0=CY
+ */
+export declare class Flags {
+    s: boolean;
+    z: boolean;
+    ac: boolean;
+    p: boolean;
+    cy: boolean;
+    /** Serialize to PSW byte */
+    toByte(): number;
+    /** Deserialize from PSW byte */
+    fromByte(b: number): void;
+    reset(): void;
+}
+//# sourceMappingURL=Flags.d.ts.map

package/dist/cpu/Flags.d.ts.map

@@ -0,0 +1 @@
+{"version":3,"file":"Flags.d.ts","sourceRoot":"","sources":["../../src/cpu/Flags.ts"],"names":[],"mappings":"AAAA;;;;GAIG;AACH,qBAAa,KAAK;IAChB,CAAC,UAAS;IACV,CAAC,UAAS;IACV,EAAE,UAAS;IACX,CAAC,UAAS;IACV,EAAE,UAAS;IAEX,4BAA4B;IAC5B,MAAM,IAAI,MAAM;IAWhB,gCAAgC;IAChC,QAAQ,CAAC,CAAC,EAAE,MAAM,GAAG,IAAI;IAQzB,KAAK,IAAI,IAAI;CAGd"}

package/dist/cpu/Flags.js

@@ -0,0 +1,33 @@
+/**
+ * Intel 8080 flags register.
+ * Stored in PSW byte format: S Z 0 AC 0 P 1 CY
+ * Bits: 7=S, 6=Z, 5=0, 4=AC, 3=0, 2=P, 1=1, 0=CY
+ */
+export class Flags {
+    s = false; // Sign
+    z = false; // Zero
+    ac = false; // Auxiliary Carry (half-carry)
+    p = false; // Parity (even)
+    cy = false; // Carry
+    /** Serialize to PSW byte */
+    toByte() {
+        return ((this.s ? 0x80 : 0) |
+            (this.z ? 0x40 : 0) |
+            (this.ac ? 0x10 : 0) |
+            (this.p ? 0x04 : 0) |
+            0x02 | // bit 1 always 1
+            (this.cy ? 0x01 : 0));
+    }
+    /** Deserialize from PSW byte */
+    fromByte(b) {
+        this.s = (b & 0x80) !== 0;
+        this.z = (b & 0x40) !== 0;
+        this.ac = (b & 0x10) !== 0;
+        this.p = (b & 0x04) !== 0;
+        this.cy = (b & 0x01) !== 0;
+    }
+    reset() {
+        this.s = this.z = this.ac = this.p = this.cy = false;
+    }
+}
+//# sourceMappingURL=Flags.js.map

package/dist/cpu/Flags.js.map

@@ -0,0 +1 @@
+{"version":3,"file":"Flags.js","sourceRoot":"","sources":["../../src/cpu/Flags.ts"],"names":[],"mappings":"AAAA;;;;GAIG;AACH,MAAM,OAAO,KAAK;IAChB,CAAC,GAAG,KAAK,CAAC,CAAG,OAAO;IACpB,CAAC,GAAG,KAAK,CAAC,CAAG,OAAO;IACpB,EAAE,GAAG,KAAK,CAAC,CAAE,+BAA+B;IAC5C,CAAC,GAAG,KAAK,CAAC,CAAG,gBAAgB;IAC7B,EAAE,GAAG,KAAK,CAAC,CAAE,QAAQ;IAErB,4BAA4B;IAC5B,MAAM;QACJ,OAAO,CACL,CAAC,IAAI,CAAC,CAAC,CAAE,CAAC,CAAC,IAAI,CAAC,CAAC,CAAC,CAAC,CAAC;YACpB,CAAC,IAAI,CAAC,CAAC,CAAE,CAAC,CAAC,IAAI,CAAC,CAAC,CAAC,CAAC,CAAC;YACpB,CAAC,IAAI,CAAC,EAAE,CAAC,CAAC,CAAC,IAAI,CAAC,CAAC,CAAC,CAAC,CAAC;YACpB,CAAC,IAAI,CAAC,CAAC,CAAE,CAAC,CAAC,IAAI,CAAC,CAAC,CAAC,CAAC,CAAC;YACpB,IAAI,GAAoB,iBAAiB;YACzC,CAAC,IAAI,CAAC,EAAE,CAAC,CAAC,CAAC,IAAI,CAAC,CAAC,CAAC,CAAC,CAAC,CACrB,CAAC;IACJ,CAAC;IAED,gCAAgC;IAChC,QAAQ,CAAC,CAAS;QAChB,IAAI,CAAC,CAAC,GAAI,CAAC,CAAC,GAAG,IAAI,CAAC,KAAK,CAAC,CAAC;QAC3B,IAAI,CAAC,CAAC,GAAI,CAAC,CAAC,GAAG,IAAI,CAAC,KAAK,CAAC,CAAC;QAC3B,IAAI,CAAC,EAAE,GAAG,CAAC,CAAC,GAAG,IAAI,CAAC,KAAK,CAAC,CAAC;QAC3B,IAAI,CAAC,CAAC,GAAI,CAAC,CAAC,GAAG,IAAI,CAAC,KAAK,CAAC,CAAC;QAC3B,IAAI,CAAC,EAAE,GAAG,CAAC,CAAC,GAAG,IAAI,CAAC,KAAK,CAAC,CAAC;IAC7B,CAAC;IAED,KAAK;QACH,IAAI,CAAC,CAAC,GAAG,IAAI,CAAC,CAAC,GAAG,IAAI,CAAC,EAAE,GAAG,IAAI,CAAC,CAAC,GAAG,IAAI,CAAC,EAAE,GAAG,KAAK,CAAC;IACvD,CAAC;CACF"}

package/dist/cpu/Registers.d.ts

@@ -0,0 +1,22 @@
+export declare class Registers {
+    a: number;
+    b: number;
+    c: number;
+    d: number;
+    e: number;
+    h: number;
+    l: number;
+    sp: number;
+    pc: number;
+    /** BC register pair */
+    get bc(): number;
+    set bc(v: number);
+    /** DE register pair */
+    get de(): number;
+    set de(v: number);
+    /** HL register pair */
+    get hl(): number;
+    set hl(v: number);
+    reset(): void;
+}
+//# sourceMappingURL=Registers.d.ts.map

package/dist/cpu/Registers.d.ts.map

@@ -0,0 +1 @@
+{"version":3,"file":"Registers.d.ts","sourceRoot":"","sources":["../../src/cpu/Registers.ts"],"names":[],"mappings":"AAAA,qBAAa,SAAS;IACpB,CAAC,SAAK;IACN,CAAC,SAAK;IACN,CAAC,SAAK;IACN,CAAC,SAAK;IACN,CAAC,SAAK;IACN,CAAC,SAAK;IACN,CAAC,SAAK;IACN,EAAE,SAAK;IACP,EAAE,SAAK;IAEP,uBAAuB;IACvB,IAAI,EAAE,IAAI,MAAM,CAAmC;IACnD,IAAI,EAAE,CAAC,CAAC,EAAE,MAAM,EAAkD;IAElE,uBAAuB;IACvB,IAAI,EAAE,IAAI,MAAM,CAAmC;IACnD,IAAI,EAAE,CAAC,CAAC,EAAE,MAAM,EAAkD;IAElE,uBAAuB;IACvB,IAAI,EAAE,IAAI,MAAM,CAAmC;IACnD,IAAI,EAAE,CAAC,CAAC,EAAE,MAAM,EAAkD;IAElE,KAAK,IAAI,IAAI;CAKd"}

package/dist/cpu/Registers.js

@@ -0,0 +1,26 @@
+export class Registers {
+    a = 0;
+    b = 0;
+    c = 0;
+    d = 0;
+    e = 0;
+    h = 0;
+    l = 0;
+    sp = 0;
+    pc = 0;
+    /** BC register pair */
+    get bc() { return (this.b << 8) | this.c; }
+    set bc(v) { this.b = (v >> 8) & 0xff; this.c = v & 0xff; }
+    /** DE register pair */
+    get de() { return (this.d << 8) | this.e; }
+    set de(v) { this.d = (v >> 8) & 0xff; this.e = v & 0xff; }
+    /** HL register pair */
+    get hl() { return (this.h << 8) | this.l; }
+    set hl(v) { this.h = (v >> 8) & 0xff; this.l = v & 0xff; }
+    reset() {
+        this.a = this.b = this.c = this.d = this.e = this.h = this.l = 0;
+        this.sp = 0;
+        this.pc = 0;
+    }
+}
+//# sourceMappingURL=Registers.js.map

package/dist/cpu/Registers.js.map

@@ -0,0 +1 @@
+{"version":3,"file":"Registers.js","sourceRoot":"","sources":["../../src/cpu/Registers.ts"],"names":[],"mappings":"AAAA,MAAM,OAAO,SAAS;IACpB,CAAC,GAAG,CAAC,CAAC;IACN,CAAC,GAAG,CAAC,CAAC;IACN,CAAC,GAAG,CAAC,CAAC;IACN,CAAC,GAAG,CAAC,CAAC;IACN,CAAC,GAAG,CAAC,CAAC;IACN,CAAC,GAAG,CAAC,CAAC;IACN,CAAC,GAAG,CAAC,CAAC;IACN,EAAE,GAAG,CAAC,CAAC;IACP,EAAE,GAAG,CAAC,CAAC;IAEP,uBAAuB;IACvB,IAAI,EAAE,KAAa,OAAO,CAAC,IAAI,CAAC,CAAC,IAAI,CAAC,CAAC,GAAG,IAAI,CAAC,CAAC,CAAC,CAAC,CAAC;IACnD,IAAI,EAAE,CAAC,CAAS,IAAI,IAAI,CAAC,CAAC,GAAG,CAAC,CAAC,IAAI,CAAC,CAAC,GAAG,IAAI,CAAC,CAAC,IAAI,CAAC,CAAC,GAAG,CAAC,GAAG,IAAI,CAAC,CAAC,CAAC;IAElE,uBAAuB;IACvB,IAAI,EAAE,KAAa,OAAO,CAAC,IAAI,CAAC,CAAC,IAAI,CAAC,CAAC,GAAG,IAAI,CAAC,CAAC,CAAC,CAAC,CAAC;IACnD,IAAI,EAAE,CAAC,CAAS,IAAI,IAAI,CAAC,CAAC,GAAG,CAAC,CAAC,IAAI,CAAC,CAAC,GAAG,IAAI,CAAC,CAAC,IAAI,CAAC,CAAC,GAAG,CAAC,GAAG,IAAI,CAAC,CAAC,CAAC;IAElE,uBAAuB;IACvB,IAAI,EAAE,KAAa,OAAO,CAAC,IAAI,CAAC,CAAC,IAAI,CAAC,CAAC,GAAG,IAAI,CAAC,CAAC,CAAC,CAAC,CAAC;IACnD,IAAI,EAAE,CAAC,CAAS,IAAI,IAAI,CAAC,CAAC,GAAG,CAAC,CAAC,IAAI,CAAC,CAAC,GAAG,IAAI,CAAC,CAAC,IAAI,CAAC,CAAC,GAAG,CAAC,GAAG,IAAI,CAAC,CAAC,CAAC;IAElE,KAAK;QACH,IAAI,CAAC,CAAC,GAAG,IAAI,CAAC,CAAC,GAAG,IAAI,CAAC,CAAC,GAAG,IAAI,CAAC,CAAC,GAAG,IAAI,CAAC,CAAC,GAAG,IAAI,CAAC,CAAC,GAAG,IAAI,CAAC,CAAC,GAAG,CAAC,CAAC;QACjE,IAAI,CAAC,EAAE,GAAG,CAAC,CAAC;QACZ,IAAI,CAAC,EAAE,GAAG,CAAC,CAAC;IACd,CAAC;CACF"}

package/dist/cpu/instructions/alu.d.ts

@@ -0,0 +1,3 @@
+import type { Decoder } from '../Decoder.js';
+export declare function registerAlu(decoder: Decoder): void;
+//# sourceMappingURL=alu.d.ts.map

package/dist/cpu/instructions/alu.d.ts.map

@@ -0,0 +1 @@
+{"version":3,"file":"alu.d.ts","sourceRoot":"","sources":["../../../src/cpu/instructions/alu.ts"],"names":[],"mappings":"AAAA,OAAO,KAAK,EAAE,OAAO,EAAE,MAAM,eAAe,CAAC;AAsB7C,wBAAgB,WAAW,CAAC,OAAO,EAAE,OAAO,GAAG,IAAI,CAmNlD"}

package/dist/cpu/instructions/alu.js

@@ -0,0 +1,221 @@
+import { u8, u16, signBit, zeroFlag, parityFlag, auxCarryAdd, auxCarrySub } from '../../util/bits.js';
+const REG_ORDER = ['b', 'c', 'd', 'e', 'h', 'l', 'M', 'a'];
+function getReg(regs, r, bus) {
+    if (r === 'M')
+        return bus.read(regs.hl);
+    return regs[r];
+}
+function setArithFlags(flags, result, ac) {
+    const r8 = u8(result);
+    flags.s = signBit(r8);
+    flags.z = zeroFlag(r8);
+    flags.ac = ac;
+    flags.p = parityFlag(r8);
+}
+export function registerAlu(decoder) {
+    // ADD r / ADD M (0x80..0x87)
+    for (let r = 0; r < 8; r++) {
+        const opcode = 0x80 | r;
+        const reg = REG_ORDER[r];
+        const cycles = reg === 'M' ? 7 : 4;
+        decoder.register(opcode, (regs, flags, bus) => {
+            const a = regs.a;
+            const b = getReg(regs, reg, bus);
+            const result = a + b;
+            flags.cy = result > 0xff;
+            flags.ac = auxCarryAdd(a, b);
+            setArithFlags(flags, result, flags.ac);
+            regs.a = u8(result);
+            return cycles;
+        });
+    }
+    // ADC r / ADC M (0x88..0x8F)
+    for (let r = 0; r < 8; r++) {
+        const opcode = 0x88 | r;
+        const reg = REG_ORDER[r];
+        const cycles = reg === 'M' ? 7 : 4;
+        decoder.register(opcode, (regs, flags, bus) => {
+            const a = regs.a;
+            const b = getReg(regs, reg, bus);
+            const cy = flags.cy ? 1 : 0;
+            const result = a + b + cy;
+            flags.cy = result > 0xff;
+            flags.ac = auxCarryAdd(a, b, cy);
+            setArithFlags(flags, result, flags.ac);
+            regs.a = u8(result);
+            return cycles;
+        });
+    }
+    // SUB r / SUB M (0x90..0x97)
+    for (let r = 0; r < 8; r++) {
+        const opcode = 0x90 | r;
+        const reg = REG_ORDER[r];
+        const cycles = reg === 'M' ? 7 : 4;
+        decoder.register(opcode, (regs, flags, bus) => {
+            const a = regs.a;
+            const b = getReg(regs, reg, bus);
+            const result = a - b;
+            flags.cy = result < 0;
+            flags.ac = auxCarrySub(a, b);
+            setArithFlags(flags, result, flags.ac);
+            regs.a = u8(result);
+            return cycles;
+        });
+    }
+    // SBB r / SBB M (0x98..0x9F)
+    for (let r = 0; r < 8; r++) {
+        const opcode = 0x98 | r;
+        const reg = REG_ORDER[r];
+        const cycles = reg === 'M' ? 7 : 4;
+        decoder.register(opcode, (regs, flags, bus) => {
+            const a = regs.a;
+            const b = getReg(regs, reg, bus);
+            const borrow = flags.cy ? 1 : 0;
+            const result = a - b - borrow;
+            flags.cy = result < 0;
+            flags.ac = auxCarrySub(a, b, borrow);
+            setArithFlags(flags, result, flags.ac);
+            regs.a = u8(result);
+            return cycles;
+        });
+    }
+    // ADI d8 (0xC6)
+    decoder.register(0xc6, (regs, flags, bus) => {
+        const a = regs.a;
+        const b = bus.read(regs.pc);
+        regs.pc = u16(regs.pc + 1);
+        const result = a + b;
+        flags.cy = result > 0xff;
+        flags.ac = auxCarryAdd(a, b);
+        setArithFlags(flags, result, flags.ac);
+        regs.a = u8(result);
+        return 7;
+    });
+    // ACI d8 (0xCE)
+    decoder.register(0xce, (regs, flags, bus) => {
+        const a = regs.a;
+        const b = bus.read(regs.pc);
+        regs.pc = u16(regs.pc + 1);
+        const cy = flags.cy ? 1 : 0;
+        const result = a + b + cy;
+        flags.cy = result > 0xff;
+        flags.ac = auxCarryAdd(a, b, cy);
+        setArithFlags(flags, result, flags.ac);
+        regs.a = u8(result);
+        return 7;
+    });
+    // SUI d8 (0xD6)
+    decoder.register(0xd6, (regs, flags, bus) => {
+        const a = regs.a;
+        const b = bus.read(regs.pc);
+        regs.pc = u16(regs.pc + 1);
+        const result = a - b;
+        flags.cy = result < 0;
+        flags.ac = auxCarrySub(a, b);
+        setArithFlags(flags, result, flags.ac);
+        regs.a = u8(result);
+        return 7;
+    });
+    // SBI d8 (0xDE)
+    decoder.register(0xde, (regs, flags, bus) => {
+        const a = regs.a;
+        const b = bus.read(regs.pc);
+        regs.pc = u16(regs.pc + 1);
+        const borrow = flags.cy ? 1 : 0;
+        const result = a - b - borrow;
+        flags.cy = result < 0;
+        flags.ac = auxCarrySub(a, b, borrow);
+        setArithFlags(flags, result, flags.ac);
+        regs.a = u8(result);
+        return 7;
+    });
+    // INR r (0x04, 0x0C, 0x14, 0x1C, 0x24, 0x2C, 0x34, 0x3C)
+    for (let r = 0; r < 8; r++) {
+        const opcode = 0x04 | (r << 3);
+        const reg = REG_ORDER[r];
+        const cycles = reg === 'M' ? 10 : 5;
+        decoder.register(opcode, (regs, flags, bus) => {
+            const old = getReg(regs, reg, bus);
+            const result = old + 1;
+            flags.ac = auxCarryAdd(old, 1);
+            // CY not affected by INR
+            flags.s = signBit(u8(result));
+            flags.z = zeroFlag(u8(result));
+            flags.p = parityFlag(u8(result));
+            if (reg === 'M') {
+                bus.write(regs.hl, u8(result));
+            }
+            else {
+                regs[reg] = u8(result);
+            }
+            return cycles;
+        });
+    }
+    // DCR r (0x05, 0x0D, 0x15, 0x1D, 0x25, 0x2D, 0x35, 0x3D)
+    for (let r = 0; r < 8; r++) {
+        const opcode = 0x05 | (r << 3);
+        const reg = REG_ORDER[r];
+        const cycles = reg === 'M' ? 10 : 5;
+        decoder.register(opcode, (regs, flags, bus) => {
+            const old = getReg(regs, reg, bus);
+            const result = old - 1;
+            flags.ac = auxCarrySub(old, 1);
+            // CY not affected by DCR
+            flags.s = signBit(u8(result));
+            flags.z = zeroFlag(u8(result));
+            flags.p = parityFlag(u8(result));
+            if (reg === 'M') {
+                bus.write(regs.hl, u8(result));
+            }
+            else {
+                regs[reg] = u8(result);
+            }
+            return cycles;
+        });
+    }
+    // INX B (0x03), INX D (0x13), INX H (0x23), INX SP (0x33)
+    decoder.register(0x03, (regs, _flags, _bus) => { regs.bc = u16(regs.bc + 1); return 5; });
+    decoder.register(0x13, (regs, _flags, _bus) => { regs.de = u16(regs.de + 1); return 5; });
+    decoder.register(0x23, (regs, _flags, _bus) => { regs.hl = u16(regs.hl + 1); return 5; });
+    decoder.register(0x33, (regs, _flags, _bus) => { regs.sp = u16(regs.sp + 1); return 5; });
+    // DCX B (0x0B), DCX D (0x1B), DCX H (0x2B), DCX SP (0x3B)
+    decoder.register(0x0b, (regs, _flags, _bus) => { regs.bc = u16(regs.bc - 1); return 5; });
+    decoder.register(0x1b, (regs, _flags, _bus) => { regs.de = u16(regs.de - 1); return 5; });
+    decoder.register(0x2b, (regs, _flags, _bus) => { regs.hl = u16(regs.hl - 1); return 5; });
+    decoder.register(0x3b, (regs, _flags, _bus) => { regs.sp = u16(regs.sp - 1); return 5; });
+    // DAD B (0x09), DAD D (0x19), DAD H (0x29), DAD SP (0x39)
+    // Add register pair to HL; sets CY only
+    function dad(regs, flags, rp) {
+        const result = regs.hl + rp;
+        flags.cy = result > 0xffff;
+        regs.hl = u16(result);
+        return 10;
+    }
+    decoder.register(0x09, (regs, flags, _bus) => dad(regs, flags, regs.bc));
+    decoder.register(0x19, (regs, flags, _bus) => dad(regs, flags, regs.de));
+    decoder.register(0x29, (regs, flags, _bus) => dad(regs, flags, regs.hl));
+    decoder.register(0x39, (regs, flags, _bus) => dad(regs, flags, regs.sp));
+    // DAA (0x27) — Decimal Adjust Accumulator
+    decoder.register(0x27, (regs, flags, _bus) => {
+        let a = regs.a;
+        let correction = 0;
+        let setCY = false;
+        if (flags.ac || (a & 0x0f) > 9) {
+            correction |= 0x06;
+        }
+        if (flags.cy || a > 0x99) {
+            correction |= 0x60;
+            setCY = true;
+        }
+        const result = a + correction;
+        flags.ac = auxCarryAdd(a, correction);
+        flags.cy = setCY;
+        a = u8(result);
+        flags.s = signBit(a);
+        flags.z = zeroFlag(a);
+        flags.p = parityFlag(a);
+        regs.a = a;
+        return 4;
+    });
+}
+//# sourceMappingURL=alu.js.map