@joezilla/8sim 0.10.0

package/dist/bundles/CardBundle.d.ts

@@ -0,0 +1,83 @@
+import type { CardFactory, MemoryRegionSpec, CpuKind } from '../machine/MachineSpec.js';
+/**
+ * Declarative description of a card's configurable surface — the source both
+ * the settings UI (later, fdcplus-web) and define-time validation are generated
+ * from. Kept minimal and 8sim-native; the rich catalog metadata (docs, media,
+ * identity, versioning) lives in fdcplus-web.
+ */
+export type ConfigParamType = 'u8' | 'u16' | 'enum';
+export interface ConfigParamSpec {
+    type: ConfigParamType;
+    default: number | string;
+    min?: number;
+    max?: number;
+    enum?: ReadonlyArray<number | string>;
+    description?: string;
+}
+/**
+ * The kind of bus primitive this bundle models. An S-100 machine is assembled
+ * from `card`s (things that occupy a bus slot); a `chip` is a component that
+ * lives ON a card (e.g. a 6850 ACIA on the 88-2SIO). 8sim can also expose a
+ * bare chip as a minimal bus device (via `deviceCard`), so a `chip` primitive
+ * is placeable, but it is a component reference — not a real S-100 board.
+ */
+export type PrimitiveKind = 'card' | 'chip';
+export interface CardManifest {
+    /** Bundle name (Identity is `name@version`). */
+    name: string;
+    version: string;
+    type: 'cpu' | 'serial' | 'floppy' | 'memory' | 'panel' | 'other';
+    /** Bus-ontology kind: an S-100 board vs. a component chip. Defaults to `card`. */
+    kind?: PrimitiveKind;
+    maker?: string;
+    summary?: string;
+    configSchema: Record<string, ConfigParamSpec>;
+}
+/** Resolved config → declared bus resources, for define-time collision rejection. */
+export type ClaimsFn = (config: Record<string, unknown>) => {
+    ports?: number[];
+    irq?: number | null;
+};
+/** Resolved config → the memory region(s) this card maps onto the bus. A memory
+ * card (RAM/EPROM board) resolves to regions; the host hoists them into the
+ * machine's declared `MachineSpec.memory` so they're overlap-validated (see the
+ * buildMachine note). Absent on pure I/O cards. */
+export type MemoryFn = (config: Record<string, unknown>) => MemoryRegionSpec[];
+/** Resolved config → the CPU this card provides. On real S-100 hardware the
+ * processor is a card (the 8080/Z80 CPU board), and it carries settings the bus
+ * doesn't — notably the power-on jump (`resetVector`), classically a CPU-card
+ * feature. A machine has exactly one CPU card; the host resolves its output into
+ * `MachineSpec.cpuKind`/`resetVector`. Absent on every non-CPU card. */
+export type CpuFn = (config: Record<string, unknown>) => {
+    kind: CpuKind;
+    resetVector?: number;
+};
+/**
+ * A self-contained card bundle (AR-5): the manifest (data) + the uniform
+ * factory (code) + a claims deriver. Seed bundles wrap the built-in 8sim card
+ * classes; downstream bundles have the same shape. A `memory` card additionally
+ * declares the RAM/ROM region(s) it maps; a `cpu` card declares the processor —
+ * both resolved by the host into the MachineSpec (memory map / CPU).
+ */
+export interface CardBundle {
+    manifest: CardManifest;
+    cardFactory: CardFactory;
+    claims: ClaimsFn;
+    memory?: MemoryFn;
+    cpu?: CpuFn;
+}
+/** Thrown when a card config violates its manifest's Config Schema. */
+export declare class CardConfigError extends Error {
+    constructor(message: string);
+}
+/**
+ * Merge a resolved config over the manifest's schema defaults, validating each
+ * value against its ConfigParamSpec (range for `u8`/`u16`, membership for
+ * `enum`). Throws {@link CardConfigError} on a violation so an out-of-range
+ * port can't be silently masked into a different (and mis-claimed) one.
+ *
+ * Keys present in `config` but absent from the schema are ignored (the schema
+ * is the contract) — a typo'd key silently takes its default.
+ */
+export declare function withDefaults(manifest: CardManifest, config?: Record<string, unknown>): Record<string, unknown>;
+//# sourceMappingURL=CardBundle.d.ts.map

package/dist/bundles/CardBundle.d.ts.map

@@ -0,0 +1 @@
+{"version":3,"file":"CardBundle.d.ts","sourceRoot":"","sources":["../../src/bundles/CardBundle.ts"],"names":[],"mappings":"AAAA,OAAO,KAAK,EAAE,WAAW,EAAE,gBAAgB,EAAE,OAAO,EAAE,MAAM,2BAA2B,CAAC;AAExF;;;;;GAKG;AACH,MAAM,MAAM,eAAe,GAAG,IAAI,GAAG,KAAK,GAAG,MAAM,CAAC;AAEpD,MAAM,WAAW,eAAe;IAC9B,IAAI,EAAE,eAAe,CAAC;IACtB,OAAO,EAAE,MAAM,GAAG,MAAM,CAAC;IACzB,GAAG,CAAC,EAAE,MAAM,CAAC;IACb,GAAG,CAAC,EAAE,MAAM,CAAC;IACb,IAAI,CAAC,EAAE,aAAa,CAAC,MAAM,GAAG,MAAM,CAAC,CAAC;IACtC,WAAW,CAAC,EAAE,MAAM,CAAC;CACtB;AAED;;;;;;GAMG;AACH,MAAM,MAAM,aAAa,GAAG,MAAM,GAAG,MAAM,CAAC;AAE5C,MAAM,WAAW,YAAY;IAC3B,gDAAgD;IAChD,IAAI,EAAE,MAAM,CAAC;IACb,OAAO,EAAE,MAAM,CAAC;IAChB,IAAI,EAAE,KAAK,GAAG,QAAQ,GAAG,QAAQ,GAAG,QAAQ,GAAG,OAAO,GAAG,OAAO,CAAC;IACjE,kFAAkF;IAClF,IAAI,CAAC,EAAE,aAAa,CAAC;IACrB,KAAK,CAAC,EAAE,MAAM,CAAC;IACf,OAAO,CAAC,EAAE,MAAM,CAAC;IACjB,YAAY,EAAE,MAAM,CAAC,MAAM,EAAE,eAAe,CAAC,CAAC;CAC/C;AAED,qFAAqF;AACrF,MAAM,MAAM,QAAQ,GAAG,CAAC,MAAM,EAAE,MAAM,CAAC,MAAM,EAAE,OAAO,CAAC,KAAK;IAC1D,KAAK,CAAC,EAAE,MAAM,EAAE,CAAC;IACjB,GAAG,CAAC,EAAE,MAAM,GAAG,IAAI,CAAC;CACrB,CAAC;AAEF;;;mDAGmD;AACnD,MAAM,MAAM,QAAQ,GAAG,CAAC,MAAM,EAAE,MAAM,CAAC,MAAM,EAAE,OAAO,CAAC,KAAK,gBAAgB,EAAE,CAAC;AAE/E;;;;wEAIwE;AACxE,MAAM,MAAM,KAAK,GAAG,CAAC,MAAM,EAAE,MAAM,CAAC,MAAM,EAAE,OAAO,CAAC,KAAK;IACvD,IAAI,EAAE,OAAO,CAAC;IACd,WAAW,CAAC,EAAE,MAAM,CAAC;CACtB,CAAC;AAEF;;;;;;GAMG;AACH,MAAM,WAAW,UAAU;IACzB,QAAQ,EAAE,YAAY,CAAC;IACvB,WAAW,EAAE,WAAW,CAAC;IACzB,MAAM,EAAE,QAAQ,CAAC;IACjB,MAAM,CAAC,EAAE,QAAQ,CAAC;IAClB,GAAG,CAAC,EAAE,KAAK,CAAC;CACb;AAED,uEAAuE;AACvE,qBAAa,eAAgB,SAAQ,KAAK;gBAC5B,OAAO,EAAE,MAAM;CAI5B;AAED;;;;;;;;GAQG;AACH,wBAAgB,YAAY,CAC1B,QAAQ,EAAE,YAAY,EACtB,MAAM,GAAE,MAAM,CAAC,MAAM,EAAE,OAAO,CAAM,GACnC,MAAM,CAAC,MAAM,EAAE,OAAO,CAAC,CAQzB"}

package/dist/bundles/CardBundle.js

@@ -0,0 +1,41 @@
+/** Thrown when a card config violates its manifest's Config Schema. */
+export class CardConfigError extends Error {
+    constructor(message) {
+        super(message);
+        this.name = 'CardConfigError';
+    }
+}
+/**
+ * Merge a resolved config over the manifest's schema defaults, validating each
+ * value against its ConfigParamSpec (range for `u8`/`u16`, membership for
+ * `enum`). Throws {@link CardConfigError} on a violation so an out-of-range
+ * port can't be silently masked into a different (and mis-claimed) one.
+ *
+ * Keys present in `config` but absent from the schema are ignored (the schema
+ * is the contract) — a typo'd key silently takes its default.
+ */
+export function withDefaults(manifest, config = {}) {
+    const out = {};
+    for (const [key, spec] of Object.entries(manifest.configSchema)) {
+        const value = key in config ? config[key] : spec.default;
+        validateParam(manifest.name, key, spec, value);
+        out[key] = value;
+    }
+    return out;
+}
+function validateParam(card, key, spec, value) {
+    const where = `card "${card}" config "${key}"`;
+    if (spec.type === 'enum') {
+        if (!spec.enum || !spec.enum.includes(value)) {
+            throw new CardConfigError(`${where}: ${JSON.stringify(value)} is not one of ${JSON.stringify(spec.enum ?? [])}`);
+        }
+        return;
+    }
+    // u8 / u16 numeric range.
+    const hi = spec.max ?? (spec.type === 'u16' ? 0xffff : 0xff);
+    const lo = spec.min ?? 0;
+    if (typeof value !== 'number' || !Number.isInteger(value) || value < lo || value > hi) {
+        throw new CardConfigError(`${where}: ${JSON.stringify(value)} must be an integer in ${lo}..${hi}`);
+    }
+}
+//# sourceMappingURL=CardBundle.js.map

package/dist/bundles/CardBundle.js.map

@@ -0,0 +1 @@
+{"version":3,"file":"CardBundle.js","sourceRoot":"","sources":["../../src/bundles/CardBundle.ts"],"names":[],"mappings":"AA6EA,uEAAuE;AACvE,MAAM,OAAO,eAAgB,SAAQ,KAAK;IACxC,YAAY,OAAe;QACzB,KAAK,CAAC,OAAO,CAAC,CAAC;QACf,IAAI,CAAC,IAAI,GAAG,iBAAiB,CAAC;IAChC,CAAC;CACF;AAED;;;;;;;;GAQG;AACH,MAAM,UAAU,YAAY,CAC1B,QAAsB,EACtB,SAAkC,EAAE;IAEpC,MAAM,GAAG,GAA4B,EAAE,CAAC;IACxC,KAAK,MAAM,CAAC,GAAG,EAAE,IAAI,CAAC,IAAI,MAAM,CAAC,OAAO,CAAC,QAAQ,CAAC,YAAY,CAAC,EAAE,CAAC;QAChE,MAAM,KAAK,GAAG,GAAG,IAAI,MAAM,CAAC,CAAC,CAAC,MAAM,CAAC,GAAG,CAAC,CAAC,CAAC,CAAC,IAAI,CAAC,OAAO,CAAC;QACzD,aAAa,CAAC,QAAQ,CAAC,IAAI,EAAE,GAAG,EAAE,IAAI,EAAE,KAAK,CAAC,CAAC;QAC/C,GAAG,CAAC,GAAG,CAAC,GAAG,KAAK,CAAC;IACnB,CAAC;IACD,OAAO,GAAG,CAAC;AACb,CAAC;AAED,SAAS,aAAa,CAAC,IAAY,EAAE,GAAW,EAAE,IAAqB,EAAE,KAAc;IACrF,MAAM,KAAK,GAAG,SAAS,IAAI,aAAa,GAAG,GAAG,CAAC;IAC/C,IAAI,IAAI,CAAC,IAAI,KAAK,MAAM,EAAE,CAAC;QACzB,IAAI,CAAC,IAAI,CAAC,IAAI,IAAI,CAAC,IAAI,CAAC,IAAI,CAAC,QAAQ,CAAC,KAAwB,CAAC,EAAE,CAAC;YAChE,MAAM,IAAI,eAAe,CAAC,GAAG,KAAK,KAAK,IAAI,CAAC,SAAS,CAAC,KAAK,CAAC,kBAAkB,IAAI,CAAC,SAAS,CAAC,IAAI,CAAC,IAAI,IAAI,EAAE,CAAC,EAAE,CAAC,CAAC;QACnH,CAAC;QACD,OAAO;IACT,CAAC;IACD,0BAA0B;IAC1B,MAAM,EAAE,GAAG,IAAI,CAAC,GAAG,IAAI,CAAC,IAAI,CAAC,IAAI,KAAK,KAAK,CAAC,CAAC,CAAC,MAAM,CAAC,CAAC,CAAC,IAAI,CAAC,CAAC;IAC7D,MAAM,EAAE,GAAG,IAAI,CAAC,GAAG,IAAI,CAAC,CAAC;IACzB,IAAI,OAAO,KAAK,KAAK,QAAQ,IAAI,CAAC,MAAM,CAAC,SAAS,CAAC,KAAK,CAAC,IAAI,KAAK,GAAG,EAAE,IAAI,KAAK,GAAG,EAAE,EAAE,CAAC;QACtF,MAAM,IAAI,eAAe,CAAC,GAAG,KAAK,KAAK,IAAI,CAAC,SAAS,CAAC,KAAK,CAAC,0BAA0B,EAAE,KAAK,EAAE,EAAE,CAAC,CAAC;IACrG,CAAC;AACH,CAAC"}

package/dist/bundles/kernels.d.ts

@@ -0,0 +1,48 @@
+import type { CardFactory, MemoryRegionSpec } from '../machine/MachineSpec.js';
+import type { ConfigParamSpec, ClaimsFn } from './CardBundle.js';
+/**
+ * Card behavior kernels (Bitsby8 Story 5.7).
+ *
+ * A kernel is a trusted, parameterized device state machine the host can build
+ * an authored I/O card from — WITHOUT any user code. The host (fdcplus-web)
+ * references a kernel by `id` in an authored card's declarative behavior, and
+ * synthesizes a bundle from `create` + `claims`, exposing `configSchema` to its
+ * settings UI. `binding` names the peripheral endpoint the card's far side
+ * attaches to. This is the "behavior-kernel library" from the card taxonomy.
+ */
+export interface CardKernel {
+    /** Kernel id referenced by an authored card's `behavior.kernel`. */
+    id: string;
+    label: string;
+    /** 8sim-native card type (serial | other | …). */
+    type: string;
+    /** Peripheral endpoint this kernel's card binds to (e.g. 'terminal'). */
+    binding?: string;
+    /** Config surface the authored card inherits. */
+    configSchema: Record<string, ConfigParamSpec>;
+    /** Build the card's device (the same shape as a bundle's cardFactory). */
+    create: CardFactory;
+    /** Declared bus resources for define-time collision checks. */
+    claims: ClaimsFn;
+    /** Memory region(s) this kernel's card maps — e.g. a video card's RAM. Hoisted
+     * into MachineSpec.memory so it's overlap-validated and shows on the ribbon. */
+    memory?: (config: Record<string, unknown>) => MemoryRegionSpec[];
+}
+/** A serial (UART) console card: a data + status/control port, bound to a terminal. */
+export declare const serialKernel: CardKernel;
+/** A parallel I/O port: a single 8-bit latched port bound to GPIO (LEDs, switches, printer). */
+export declare const parallelKernel: CardKernel;
+/** An ASCII keyboard input port: a data + status port bound to the operator's keyboard. */
+export declare const keyboardKernel: CardKernel;
+/** Processor Technology VDM-1: a memory-mapped 64×16 character display, bound to a monitor. */
+export declare const vdmKernel: CardKernel;
+/** Cromemco Dazzler: a DMA colour-graphics card driven by two I/O ports, bound to a monitor. */
+export declare const dazzlerKernel: CardKernel;
+/** National MM58167 real-time clock: BCD time registers on an I/O window, bound to the host clock. */
+export declare const rtcKernel: CardKernel;
+/** Bank-switching RAM: N banks of RAM behind a fixed window, selected by an I/O port (>64K). */
+export declare const bankRamKernel: CardKernel;
+/** All built-in behavior kernels, keyed by id. */
+export declare const kernels: ReadonlyArray<CardKernel>;
+export declare const kernelById: (id: string) => CardKernel | undefined;
+//# sourceMappingURL=kernels.d.ts.map

package/dist/bundles/kernels.d.ts.map

@@ -0,0 +1 @@
+{"version":3,"file":"kernels.d.ts","sourceRoot":"","sources":["../../src/bundles/kernels.ts"],"names":[],"mappings":"AAAA,OAAO,KAAK,EAAE,WAAW,EAAE,gBAAgB,EAAE,MAAM,2BAA2B,CAAC;AAC/E,OAAO,KAAK,EAAE,eAAe,EAAE,QAAQ,EAAE,MAAM,iBAAiB,CAAC;AAYjE;;;;;;;;;GASG;AACH,MAAM,WAAW,UAAU;IACzB,oEAAoE;IACpE,EAAE,EAAE,MAAM,CAAC;IACX,KAAK,EAAE,MAAM,CAAC;IACd,kDAAkD;IAClD,IAAI,EAAE,MAAM,CAAC;IACb,yEAAyE;IACzE,OAAO,CAAC,EAAE,MAAM,CAAC;IACjB,iDAAiD;IACjD,YAAY,EAAE,MAAM,CAAC,MAAM,EAAE,eAAe,CAAC,CAAC;IAC9C,0EAA0E;IAC1E,MAAM,EAAE,WAAW,CAAC;IACpB,+DAA+D;IAC/D,MAAM,EAAE,QAAQ,CAAC;IACjB;oFACgF;IAChF,MAAM,CAAC,EAAE,CAAC,MAAM,EAAE,MAAM,CAAC,MAAM,EAAE,OAAO,CAAC,KAAK,gBAAgB,EAAE,CAAC;CAClE;AAED,uFAAuF;AACvF,eAAO,MAAM,YAAY,EAAE,UAiB1B,CAAC;AAEF,gGAAgG;AAChG,eAAO,MAAM,cAAc,EAAE,UAY5B,CAAC;AAEF,2FAA2F;AAC3F,eAAO,MAAM,cAAc,EAAE,UAiB5B,CAAC;AAEF,+FAA+F;AAC/F,eAAO,MAAM,SAAS,EAAE,UAWvB,CAAC;AAEF,gGAAgG;AAChG,eAAO,MAAM,aAAa,EAAE,UAa3B,CAAC;AAEF,sGAAsG;AACtG,eAAO,MAAM,SAAS,EAAE,UAevB,CAAC;AAEF,gGAAgG;AAChG,eAAO,MAAM,aAAa,EAAE,UAkB3B,CAAC;AAEF,kDAAkD;AAClD,eAAO,MAAM,OAAO,EAAE,aAAa,CAAC,UAAU,CAQ7C,CAAC;AAEF,eAAO,MAAM,UAAU,GAAI,IAAI,MAAM,KAAG,UAAU,GAAG,SAA6C,CAAC"}

package/dist/bundles/kernels.js

@@ -0,0 +1,132 @@
+import { SerialCard } from '../cards/SerialCard.js';
+import { ParallelCard } from '../cards/ParallelCard.js';
+import { KeyboardCard } from '../cards/KeyboardCard.js';
+import { VdmCard } from '../cards/VdmCard.js';
+import { DazzlerCard } from '../cards/DazzlerCard.js';
+import { RtcCard } from '../cards/RtcCard.js';
+import { BankRamCard } from '../cards/BankRamCard.js';
+const u8 = (v, fallback) => (typeof v === 'number' ? v & 0xff : fallback);
+const u16 = (v, fallback) => (typeof v === 'number' ? v & 0xffff : fallback);
+/** A serial (UART) console card: a data + status/control port, bound to a terminal. */
+export const serialKernel = {
+    id: 'serial',
+    label: 'Serial UART (console)',
+    type: 'serial',
+    binding: 'terminal',
+    configSchema: {
+        dataPort: { type: 'u8', default: 0x10, min: 0, max: 0xff, description: 'Data register port' },
+        ctrlPort: { type: 'u8', default: 0x11, min: 0, max: 0xff, description: 'Status/control port' },
+        chip: { type: 'enum', default: 'i8251', enum: ['i8251', 'm6850'], description: 'UART chip' },
+    },
+    create: (id, cfg) => new SerialCard(id, {
+        dataPort: u8(cfg.dataPort, 0x10),
+        ctrlPort: u8(cfg.ctrlPort, 0x11),
+        chip: cfg.chip ?? 'i8251',
+    }),
+    claims: (cfg) => ({ ports: [u8(cfg.dataPort, 0x10), u8(cfg.ctrlPort, 0x11)] }),
+};
+/** A parallel I/O port: a single 8-bit latched port bound to GPIO (LEDs, switches, printer). */
+export const parallelKernel = {
+    id: 'parallel',
+    label: 'Parallel I/O port',
+    type: 'parallel',
+    binding: 'gpio',
+    configSchema: {
+        port: { type: 'u8', default: 0x00, min: 0, max: 0xff, description: 'I/O port' },
+        direction: { type: 'enum', default: 'out', enum: ['out', 'in', 'inout'], description: 'Data direction' },
+    },
+    create: (id, cfg) => new ParallelCard(id, { port: u8(cfg.port, 0x00), direction: cfg.direction ?? 'out' }),
+    claims: (cfg) => ({ ports: [u8(cfg.port, 0x00)] }),
+};
+/** An ASCII keyboard input port: a data + status port bound to the operator's keyboard. */
+export const keyboardKernel = {
+    id: 'keyboard',
+    label: 'Keyboard input port (ASCII)',
+    type: 'keyboard',
+    binding: 'keyboard',
+    configSchema: {
+        dataPort: { type: 'u8', default: 0x01, min: 0, max: 0xff, description: 'Key data register port' },
+        statusPort: { type: 'u8', default: 0x00, min: 0, max: 0xff, description: 'Key-ready status port' },
+        readyMask: { type: 'u8', default: 0x01, min: 0, max: 0xff, description: 'Status bits set while a key waits' },
+    },
+    create: (id, cfg) => new KeyboardCard(id, {
+        dataPort: u8(cfg.dataPort, 0x01),
+        statusPort: u8(cfg.statusPort, 0x00),
+        readyMask: u8(cfg.readyMask, 0x01),
+    }),
+    claims: (cfg) => ({ ports: [u8(cfg.dataPort, 0x01), u8(cfg.statusPort, 0x00)] }),
+};
+/** Processor Technology VDM-1: a memory-mapped 64×16 character display, bound to a monitor. */
+export const vdmKernel = {
+    id: 'vdm-video',
+    label: 'VDM-1 video (64×16 characters)',
+    type: 'video',
+    binding: 'display',
+    configSchema: {
+        base: { type: 'u16', default: 0xcc00, min: 0, max: 0xffff, description: 'Video RAM base' },
+    },
+    create: (id, cfg) => new VdmCard(id, { base: u16(cfg.base, 0xcc00) }),
+    claims: () => ({ ports: [] }),
+    memory: (cfg) => [{ id: 'vram', base: u16(cfg.base, 0xcc00), size: 0x400, kind: 'ram' }],
+};
+/** Cromemco Dazzler: a DMA colour-graphics card driven by two I/O ports, bound to a monitor. */
+export const dazzlerKernel = {
+    id: 'dazzler-video',
+    label: 'Cromemco Dazzler (colour graphics)',
+    type: 'video',
+    binding: 'display',
+    configSchema: {
+        controlPort: { type: 'u8', default: 0x0e, min: 0, max: 0xff, description: 'Control port (picture on + buffer page)' },
+        formatPort: { type: 'u8', default: 0x0f, min: 0, max: 0xff, description: 'Format port (resolution / colour)' },
+    },
+    create: (id, cfg) => new DazzlerCard(id, { controlPort: u8(cfg.controlPort, 0x0e), formatPort: u8(cfg.formatPort, 0x0f) }),
+    claims: (cfg) => ({ ports: [u8(cfg.controlPort, 0x0e), u8(cfg.formatPort, 0x0f)] }),
+    // No `memory`: the Dazzler DMAs ordinary system RAM, so it declares no region.
+};
+/** National MM58167 real-time clock: BCD time registers on an I/O window, bound to the host clock. */
+export const rtcKernel = {
+    id: 'mm58167-rtc',
+    label: 'MM58167 real-time clock',
+    type: 'rtc',
+    binding: 'clock',
+    configSchema: {
+        base: { type: 'u8', default: 0x40, min: 0, max: 0xe0, description: 'Base I/O port (occupies base..base+0x1F)' },
+    },
+    create: (id, cfg, ctx) => new RtcCard(id, { base: u8(cfg.base, 0x40) }, ctx.services.clock),
+    // 32 consecutive registers.
+    claims: (cfg) => {
+        const b = u8(cfg.base, 0x40);
+        return { ports: Array.from({ length: 0x20 }, (_v, i) => (b + i) & 0xff) };
+    },
+};
+/** Bank-switching RAM: N banks of RAM behind a fixed window, selected by an I/O port (>64K). */
+export const bankRamKernel = {
+    id: 'bank-ram',
+    label: 'Bank-switching RAM (MMU)',
+    type: 'memory',
+    configSchema: {
+        window: { type: 'u16', default: 0xc000, min: 0, max: 0xffff, description: 'Switched window base address' },
+        size: { type: 'u16', default: 0x4000, min: 1, max: 0xffff, description: 'Bytes visible per bank' },
+        banks: { type: 'u8', default: 4, min: 1, max: 0xff, description: 'Number of RAM banks' },
+        selectPort: { type: 'u8', default: 0x40, min: 0, max: 0xff, description: 'Bank-select I/O port' },
+    },
+    create: (id, cfg) => new BankRamCard(id, {
+        window: u16(cfg.window, 0xc000),
+        size: u16(cfg.size, 0x4000),
+        banks: u8(cfg.banks, 4),
+        selectPort: u8(cfg.selectPort, 0x40),
+    }),
+    claims: (cfg) => ({ ports: [u8(cfg.selectPort, 0x40)] }),
+};
+/** All built-in behavior kernels, keyed by id. */
+export const kernels = [
+    serialKernel,
+    parallelKernel,
+    keyboardKernel,
+    vdmKernel,
+    dazzlerKernel,
+    rtcKernel,
+    bankRamKernel,
+];
+export const kernelById = (id) => kernels.find((k) => k.id === id);
+//# sourceMappingURL=kernels.js.map

package/dist/bundles/kernels.js.map

@@ -0,0 +1 @@
+{"version":3,"file":"kernels.js","sourceRoot":"","sources":["../../src/bundles/kernels.ts"],"names":[],"mappings":"AAEA,OAAO,EAAE,UAAU,EAAmB,MAAM,wBAAwB,CAAC;AACrE,OAAO,EAAE,YAAY,EAAsB,MAAM,0BAA0B,CAAC;AAC5E,OAAO,EAAE,YAAY,EAAE,MAAM,0BAA0B,CAAC;AACxD,OAAO,EAAE,OAAO,EAAE,MAAM,qBAAqB,CAAC;AAC9C,OAAO,EAAE,WAAW,EAAE,MAAM,yBAAyB,CAAC;AACtD,OAAO,EAAE,OAAO,EAAiB,MAAM,qBAAqB,CAAC;AAC7D,OAAO,EAAE,WAAW,EAAE,MAAM,yBAAyB,CAAC;AAEtD,MAAM,EAAE,GAAG,CAAC,CAAU,EAAE,QAAgB,EAAU,EAAE,CAAC,CAAC,OAAO,CAAC,KAAK,QAAQ,CAAC,CAAC,CAAC,CAAC,GAAG,IAAI,CAAC,CAAC,CAAC,QAAQ,CAAC,CAAC;AACnG,MAAM,GAAG,GAAG,CAAC,CAAU,EAAE,QAAgB,EAAU,EAAE,CAAC,CAAC,OAAO,CAAC,KAAK,QAAQ,CAAC,CAAC,CAAC,CAAC,GAAG,MAAM,CAAC,CAAC,CAAC,QAAQ,CAAC,CAAC;AA+BtG,uFAAuF;AACvF,MAAM,CAAC,MAAM,YAAY,GAAe;IACtC,EAAE,EAAE,QAAQ;IACZ,KAAK,EAAE,uBAAuB;IAC9B,IAAI,EAAE,QAAQ;IACd,OAAO,EAAE,UAAU;IACnB,YAAY,EAAE;QACZ,QAAQ,EAAE,EAAE,IAAI,EAAE,IAAI,EAAE,OAAO,EAAE,IAAI,EAAE,GAAG,EAAE,CAAC,EAAE,GAAG,EAAE,IAAI,EAAE,WAAW,EAAE,oBAAoB,EAAE;QAC7F,QAAQ,EAAE,EAAE,IAAI,EAAE,IAAI,EAAE,OAAO,EAAE,IAAI,EAAE,GAAG,EAAE,CAAC,EAAE,GAAG,EAAE,IAAI,EAAE,WAAW,EAAE,qBAAqB,EAAE;QAC9F,IAAI,EAAE,EAAE,IAAI,EAAE,MAAM,EAAE,OAAO,EAAE,OAAO,EAAE,IAAI,EAAE,CAAC,OAAO,EAAE,OAAO,CAAC,EAAE,WAAW,EAAE,WAAW,EAAE;KAC7F;IACD,MAAM,EAAE,CAAC,EAAE,EAAE,GAAG,EAAE,EAAE,CAClB,IAAI,UAAU,CAAC,EAAE,EAAE;QACjB,QAAQ,EAAE,EAAE,CAAC,GAAG,CAAC,QAAQ,EAAE,IAAI,CAAC;QAChC,QAAQ,EAAE,EAAE,CAAC,GAAG,CAAC,QAAQ,EAAE,IAAI,CAAC;QAChC,IAAI,EAAG,GAAG,CAAC,IAAmB,IAAI,OAAO;KAC1C,CAAC;IACJ,MAAM,EAAE,CAAC,GAAG,EAAE,EAAE,CAAC,CAAC,EAAE,KAAK,EAAE,CAAC,EAAE,CAAC,GAAG,CAAC,QAAQ,EAAE,IAAI,CAAC,EAAE,EAAE,CAAC,GAAG,CAAC,QAAQ,EAAE,IAAI,CAAC,CAAC,EAAE,CAAC;CAC/E,CAAC;AAEF,gGAAgG;AAChG,MAAM,CAAC,MAAM,cAAc,GAAe;IACxC,EAAE,EAAE,UAAU;IACd,KAAK,EAAE,mBAAmB;IAC1B,IAAI,EAAE,UAAU;IAChB,OAAO,EAAE,MAAM;IACf,YAAY,EAAE;QACZ,IAAI,EAAE,EAAE,IAAI,EAAE,IAAI,EAAE,OAAO,EAAE,IAAI,EAAE,GAAG,EAAE,CAAC,EAAE,GAAG,EAAE,IAAI,EAAE,WAAW,EAAE,UAAU,EAAE;QAC/E,SAAS,EAAE,EAAE,IAAI,EAAE,MAAM,EAAE,OAAO,EAAE,KAAK,EAAE,IAAI,EAAE,CAAC,KAAK,EAAE,IAAI,EAAE,OAAO,CAAC,EAAE,WAAW,EAAE,gBAAgB,EAAE;KACzG;IACD,MAAM,EAAE,CAAC,EAAE,EAAE,GAAG,EAAE,EAAE,CAClB,IAAI,YAAY,CAAC,EAAE,EAAE,EAAE,IAAI,EAAE,EAAE,CAAC,GAAG,CAAC,IAAI,EAAE,IAAI,CAAC,EAAE,SAAS,EAAG,GAAG,CAAC,SAA2B,IAAI,KAAK,EAAE,CAAC;IAC1G,MAAM,EAAE,CAAC,GAAG,EAAE,EAAE,CAAC,CAAC,EAAE,KAAK,EAAE,CAAC,EAAE,CAAC,GAAG,CAAC,IAAI,EAAE,IAAI,CAAC,CAAC,EAAE,CAAC;CACnD,CAAC;AAEF,2FAA2F;AAC3F,MAAM,CAAC,MAAM,cAAc,GAAe;IACxC,EAAE,EAAE,UAAU;IACd,KAAK,EAAE,6BAA6B;IACpC,IAAI,EAAE,UAAU;IAChB,OAAO,EAAE,UAAU;IACnB,YAAY,EAAE;QACZ,QAAQ,EAAE,EAAE,IAAI,EAAE,IAAI,EAAE,OAAO,EAAE,IAAI,EAAE,GAAG,EAAE,CAAC,EAAE,GAAG,EAAE,IAAI,EAAE,WAAW,EAAE,wBAAwB,EAAE;QACjG,UAAU,EAAE,EAAE,IAAI,EAAE,IAAI,EAAE,OAAO,EAAE,IAAI,EAAE,GAAG,EAAE,CAAC,EAAE,GAAG,EAAE,IAAI,EAAE,WAAW,EAAE,uBAAuB,EAAE;QAClG,SAAS,EAAE,EAAE,IAAI,EAAE,IAAI,EAAE,OAAO,EAAE,IAAI,EAAE,GAAG,EAAE,CAAC,EAAE,GAAG,EAAE,IAAI,EAAE,WAAW,EAAE,mCAAmC,EAAE;KAC9G;IACD,MAAM,EAAE,CAAC,EAAE,EAAE,GAAG,EAAE,EAAE,CAClB,IAAI,YAAY,CAAC,EAAE,EAAE;QACnB,QAAQ,EAAE,EAAE,CAAC,GAAG,CAAC,QAAQ,EAAE,IAAI,CAAC;QAChC,UAAU,EAAE,EAAE,CAAC,GAAG,CAAC,UAAU,EAAE,IAAI,CAAC;QACpC,SAAS,EAAE,EAAE,CAAC,GAAG,CAAC,SAAS,EAAE,IAAI,CAAC;KACnC,CAAC;IACJ,MAAM,EAAE,CAAC,GAAG,EAAE,EAAE,CAAC,CAAC,EAAE,KAAK,EAAE,CAAC,EAAE,CAAC,GAAG,CAAC,QAAQ,EAAE,IAAI,CAAC,EAAE,EAAE,CAAC,GAAG,CAAC,UAAU,EAAE,IAAI,CAAC,CAAC,EAAE,CAAC;CACjF,CAAC;AAEF,+FAA+F;AAC/F,MAAM,CAAC,MAAM,SAAS,GAAe;IACnC,EAAE,EAAE,WAAW;IACf,KAAK,EAAE,gCAAgC;IACvC,IAAI,EAAE,OAAO;IACb,OAAO,EAAE,SAAS;IAClB,YAAY,EAAE;QACZ,IAAI,EAAE,EAAE,IAAI,EAAE,KAAK,EAAE,OAAO,EAAE,MAAM,EAAE,GAAG,EAAE,CAAC,EAAE,GAAG,EAAE,MAAM,EAAE,WAAW,EAAE,gBAAgB,EAAE;KAC3F;IACD,MAAM,EAAE,CAAC,EAAE,EAAE,GAAG,EAAE,EAAE,CAAC,IAAI,OAAO,CAAC,EAAE,EAAE,EAAE,IAAI,EAAE,GAAG,CAAC,GAAG,CAAC,IAAI,EAAE,MAAM,CAAC,EAAE,CAAC;IACrE,MAAM,EAAE,GAAG,EAAE,CAAC,CAAC,EAAE,KAAK,EAAE,EAAE,EAAE,CAAC;IAC7B,MAAM,EAAE,CAAC,GAAG,EAAE,EAAE,CAAC,CAAC,EAAE,EAAE,EAAE,MAAM,EAAE,IAAI,EAAE,GAAG,CAAC,GAAG,CAAC,IAAI,EAAE,MAAM,CAAC,EAAE,IAAI,EAAE,KAAK,EAAE,IAAI,EAAE,KAAK,EAAE,CAAC;CACzF,CAAC;AAEF,gGAAgG;AAChG,MAAM,CAAC,MAAM,aAAa,GAAe;IACvC,EAAE,EAAE,eAAe;IACnB,KAAK,EAAE,oCAAoC;IAC3C,IAAI,EAAE,OAAO;IACb,OAAO,EAAE,SAAS;IAClB,YAAY,EAAE;QACZ,WAAW,EAAE,EAAE,IAAI,EAAE,IAAI,EAAE,OAAO,EAAE,IAAI,EAAE,GAAG,EAAE,CAAC,EAAE,GAAG,EAAE,IAAI,EAAE,WAAW,EAAE,yCAAyC,EAAE;QACrH,UAAU,EAAE,EAAE,IAAI,EAAE,IAAI,EAAE,OAAO,EAAE,IAAI,EAAE,GAAG,EAAE,CAAC,EAAE,GAAG,EAAE,IAAI,EAAE,WAAW,EAAE,mCAAmC,EAAE;KAC/G;IACD,MAAM,EAAE,CAAC,EAAE,EAAE,GAAG,EAAE,EAAE,CAClB,IAAI,WAAW,CAAC,EAAE,EAAE,EAAE,WAAW,EAAE,EAAE,CAAC,GAAG,CAAC,WAAW,EAAE,IAAI,CAAC,EAAE,UAAU,EAAE,EAAE,CAAC,GAAG,CAAC,UAAU,EAAE,IAAI,CAAC,EAAE,CAAC;IACvG,MAAM,EAAE,CAAC,GAAG,EAAE,EAAE,CAAC,CAAC,EAAE,KAAK,EAAE,CAAC,EAAE,CAAC,GAAG,CAAC,WAAW,EAAE,IAAI,CAAC,EAAE,EAAE,CAAC,GAAG,CAAC,UAAU,EAAE,IAAI,CAAC,CAAC,EAAE,CAAC;IACnF,+EAA+E;CAChF,CAAC;AAEF,sGAAsG;AACtG,MAAM,CAAC,MAAM,SAAS,GAAe;IACnC,EAAE,EAAE,aAAa;IACjB,KAAK,EAAE,yBAAyB;IAChC,IAAI,EAAE,KAAK;IACX,OAAO,EAAE,OAAO;IAChB,YAAY,EAAE;QACZ,IAAI,EAAE,EAAE,IAAI,EAAE,IAAI,EAAE,OAAO,EAAE,IAAI,EAAE,GAAG,EAAE,CAAC,EAAE,GAAG,EAAE,IAAI,EAAE,WAAW,EAAE,0CAA0C,EAAE;KAChH;IACD,MAAM,EAAE,CAAC,EAAE,EAAE,GAAG,EAAE,GAAG,EAAE,EAAE,CACvB,IAAI,OAAO,CAAC,EAAE,EAAE,EAAE,IAAI,EAAE,EAAE,CAAC,GAAG,CAAC,IAAI,EAAE,IAAI,CAAC,EAAE,EAAE,GAAG,CAAC,QAAQ,CAAC,KAA6B,CAAC;IAC3F,4BAA4B;IAC5B,MAAM,EAAE,CAAC,GAAG,EAAE,EAAE;QACd,MAAM,CAAC,GAAG,EAAE,CAAC,GAAG,CAAC,IAAI,EAAE,IAAI,CAAC,CAAC;QAC7B,OAAO,EAAE,KAAK,EAAE,KAAK,CAAC,IAAI,CAAC,EAAE,MAAM,EAAE,IAAI,EAAE,EAAE,CAAC,EAAE,EAAE,CAAC,EAAE,EAAE,CAAC,CAAC,CAAC,GAAG,CAAC,CAAC,GAAG,IAAI,CAAC,EAAE,CAAC;IAC5E,CAAC;CACF,CAAC;AAEF,gGAAgG;AAChG,MAAM,CAAC,MAAM,aAAa,GAAe;IACvC,EAAE,EAAE,UAAU;IACd,KAAK,EAAE,0BAA0B;IACjC,IAAI,EAAE,QAAQ;IACd,YAAY,EAAE;QACZ,MAAM,EAAE,EAAE,IAAI,EAAE,KAAK,EAAE,OAAO,EAAE,MAAM,EAAE,GAAG,EAAE,CAAC,EAAE,GAAG,EAAE,MAAM,EAAE,WAAW,EAAE,8BAA8B,EAAE;QAC1G,IAAI,EAAE,EAAE,IAAI,EAAE,KAAK,EAAE,OAAO,EAAE,MAAM,EAAE,GAAG,EAAE,CAAC,EAAE,GAAG,EAAE,MAAM,EAAE,WAAW,EAAE,wBAAwB,EAAE;QAClG,KAAK,EAAE,EAAE,IAAI,EAAE,IAAI,EAAE,OAAO,EAAE,CAAC,EAAE,GAAG,EAAE,CAAC,EAAE,GAAG,EAAE,IAAI,EAAE,WAAW,EAAE,qBAAqB,EAAE;QACxF,UAAU,EAAE,EAAE,IAAI,EAAE,IAAI,EAAE,OAAO,EAAE,IAAI,EAAE,GAAG,EAAE,CAAC,EAAE,GAAG,EAAE,IAAI,EAAE,WAAW,EAAE,sBAAsB,EAAE;KAClG;IACD,MAAM,EAAE,CAAC,EAAE,EAAE,GAAG,EAAE,EAAE,CAClB,IAAI,WAAW,CAAC,EAAE,EAAE;QAClB,MAAM,EAAE,GAAG,CAAC,GAAG,CAAC,MAAM,EAAE,MAAM,CAAC;QAC/B,IAAI,EAAE,GAAG,CAAC,GAAG,CAAC,IAAI,EAAE,MAAM,CAAC;QAC3B,KAAK,EAAE,EAAE,CAAC,GAAG,CAAC,KAAK,EAAE,CAAC,CAAC;QACvB,UAAU,EAAE,EAAE,CAAC,GAAG,CAAC,UAAU,EAAE,IAAI,CAAC;KACrC,CAAC;IACJ,MAAM,EAAE,CAAC,GAAG,EAAE,EAAE,CAAC,CAAC,EAAE,KAAK,EAAE,CAAC,EAAE,CAAC,GAAG,CAAC,UAAU,EAAE,IAAI,CAAC,CAAC,EAAE,CAAC;CACzD,CAAC;AAEF,kDAAkD;AAClD,MAAM,CAAC,MAAM,OAAO,GAA8B;IAChD,YAAY;IACZ,cAAc;IACd,cAAc;IACd,SAAS;IACT,aAAa;IACb,SAAS;IACT,aAAa;CACd,CAAC;AAEF,MAAM,CAAC,MAAM,UAAU,GAAG,CAAC,EAAU,EAA0B,EAAE,CAAC,OAAO,CAAC,IAAI,CAAC,CAAC,CAAC,EAAE,EAAE,CAAC,CAAC,CAAC,EAAE,KAAK,EAAE,CAAC,CAAC"}

package/dist/bundles/seed/index.d.ts

@@ -0,0 +1,24 @@
+import type { CardBundle } from '../CardBundle.js';
+export declare const mits2SioBundle: CardBundle;
+export declare const imsaiSioBundle: CardBundle;
+export declare const imsaiMioBundle: CardBundle;
+export declare const mitsDcddBundle: CardBundle;
+export declare const usart8251Bundle: CardBundle;
+export declare const mc6850Bundle: CardBundle;
+export declare const port8212Bundle: CardBundle;
+export declare const tr1602Bundle: CardBundle;
+/** Static RAM card — maps RAM at a base address for a size. A memory card:
+ * contributes no I/O device, only a RAM region hoisted into the memory map. */
+export declare const ramCardBundle: CardBundle;
+/** EPROM card — maps a ROM at a base address. The chip ships empty (zero-filled);
+ * an image is burned in later. A memory card: no I/O, just a ROM region. */
+export declare const epromCardBundle: CardBundle;
+/** Intel 8080 CPU card — the processor board. Declares the CPU family and the
+ * power-on jump (resetVector), authentically a CPU-card feature. No bus I/O. */
+export declare const i8080CpuBundle: CardBundle;
+/** Zilog Z80 CPU card — 8080-compatible bus master with the Z80 instruction set. */
+export declare const z80CpuBundle: CardBundle;
+/** All built-in seed bundles, keyed by manifest name. */
+export declare const seedBundles: ReadonlyArray<CardBundle>;
+export declare const seedBundleByName: (name: string) => CardBundle | undefined;
+//# sourceMappingURL=index.d.ts.map

package/dist/bundles/seed/index.d.ts.map

@@ -0,0 +1 @@
+{"version":3,"file":"index.d.ts","sourceRoot":"","sources":["../../../src/bundles/seed/index.ts"],"names":[],"mappings":"AAWA,OAAO,KAAK,EAAE,UAAU,EAAE,MAAM,kBAAkB,CAAC;AAyCnD,eAAO,MAAM,cAAc,EAAE,UAY5B,CAAC;AAEF,eAAO,MAAM,cAAc,EAAE,UA0B5B,CAAC;AAEF,eAAO,MAAM,cAAc,EAAE,UAa5B,CAAC;AAEF,eAAO,MAAM,cAAc,EAAE,UAoB5B,CAAC;AAEF,eAAO,MAAM,eAAe,EAAE,UAgB7B,CAAC;AAEF,eAAO,MAAM,YAAY,EAAE,UAgB1B,CAAC;AAEF,eAAO,MAAM,cAAc,EAAE,UAY5B,CAAC;AAEF,eAAO,MAAM,YAAY,EAAE,UAgB1B,CAAC;AAEF;+EAC+E;AAC/E,eAAO,MAAM,aAAa,EAAE,UAgB3B,CAAC;AAEF;4EAC4E;AAC5E,eAAO,MAAM,eAAe,EAAE,UAoB7B,CAAC;AAEF;gFACgF;AAChF,eAAO,MAAM,cAAc,EAAE,UAe5B,CAAC;AAEF,oFAAoF;AACpF,eAAO,MAAM,YAAY,EAAE,UAe1B,CAAC;AAEF,yDAAyD;AACzD,eAAO,MAAM,WAAW,EAAE,aAAa,CAAC,UAAU,CAajD,CAAC;AAEF,eAAO,MAAM,gBAAgB,GAAI,MAAM,MAAM,KAAG,UAAU,GAAG,SACV,CAAC"}

package/dist/bundles/seed/index.js

@@ -0,0 +1,266 @@
+import { ImsaiSioCard } from '../../cards/ImsaiSioCard.js';
+import { Mits2SioCard } from '../../cards/Mits2SioCard.js';
+import { ImsaiMioCard } from '../../cards/ImsaiMioCard.js';
+import { MitsDcddCard } from '../../cards/MitsDcddCard.js';
+import { Usart8251 } from '../../cards/Usart8251.js';
+import { Mc6850Acia } from '../../cards/Mc6850Acia.js';
+import { Port8212 } from '../../cards/Port8212.js';
+import { Tr1602Uart } from '../../cards/Tr1602Uart.js';
+import { MachineSpecError } from '../../machine/MachineSpec.js';
+/**
+ * Seed Card Bundles (Story 1.2 / FR-4): the built-in 8sim cards packaged as
+ * self-contained bundles with a uniform `cardFactory(id, config, ctx)` and an
+ * in-bundle adapter to the underlying class (AR-5). fdcplus-web's Catalog
+ * registers these on startup.
+ */
+const u8 = (v, fallback) => typeof v === 'number' ? v & 0xff : fallback;
+const u16 = (v, fallback) => typeof v === 'number' ? v & 0xffff : fallback;
+/** Wrap a bare IIODevice as an IS100Card (attach → attachIODevice). */
+const deviceCard = (id, dev) => ({
+    id,
+    reset: () => dev.reset(),
+    attach: (bus) => bus.attachIODevice(dev),
+});
+/** A memory card contributes no I/O device — its region is hoisted into the
+ * machine's memory map and attached there, so the card itself is a no-op on the bus. */
+const memoryCard = (id) => ({
+    id,
+    reset: () => { },
+    attach: () => { },
+});
+/** A CPU card is the bus master, not a bus device — buildMachine instantiates the
+ * processor from the resolved MachineSpec.cpuKind. On the bus the card is a no-op;
+ * its real output is the `cpu()` resolution. (Its front-panel control lines, which
+ * bypass the S-100 bus, are a future concern — not modeled here.) */
+const cpuCard = (id) => ({
+    id,
+    reset: () => { },
+    attach: () => { },
+});
+export const mits2SioBundle = {
+    manifest: {
+        name: 'mits-88-2sio',
+        version: '1.0.0',
+        type: 'serial',
+        kind: 'card',
+        maker: 'MITS',
+        summary: 'MITS 88-2SIO dual serial interface (2× 6850 ACIA).',
+        configSchema: { basePort: { type: 'u8', default: 0x10, min: 0, max: 0xfc, description: 'Base I/O port (claims base..base+3)' } },
+    },
+    cardFactory: (id, cfg) => new Mits2SioCard(id, { basePort: u8(cfg.basePort, 0x10) }),
+    claims: (cfg) => { const b = u8(cfg.basePort, 0x10); return { ports: [b, b + 1, b + 2, b + 3] }; },
+};
+export const imsaiSioBundle = {
+    manifest: {
+        name: 'imsai-sio2',
+        version: '1.0.0',
+        type: 'serial',
+        kind: 'card',
+        maker: 'IMSAI',
+        summary: 'IMSAI SIO-2 dual 8251 serial card with a board-control port.',
+        configSchema: {
+            basePortA: { type: 'u8', default: 0x02, min: 0, max: 0xfe },
+            basePortB: { type: 'u8', default: 0x04, min: 0, max: 0xfe },
+            boardCtrlPort: { type: 'u8', default: 0x08, min: 0, max: 0xff },
+        },
+    },
+    cardFactory: (id, cfg) => new ImsaiSioCard(id, {
+        basePortA: u8(cfg.basePortA, 0x02),
+        basePortB: u8(cfg.basePortB, 0x04),
+        boardCtrlPort: u8(cfg.boardCtrlPort, 0x08),
+    }),
+    claims: (cfg) => {
+        const a = u8(cfg.basePortA, 0x02);
+        const b = u8(cfg.basePortB, 0x04);
+        const c = u8(cfg.boardCtrlPort, 0x08);
+        return { ports: [a, a + 1, b, b + 1, c] };
+    },
+};
+export const imsaiMioBundle = {
+    manifest: {
+        name: 'imsai-mio',
+        version: '1.0.0',
+        type: 'serial',
+        kind: 'card',
+        maker: 'IMSAI',
+        summary: 'IMSAI MIO multi-I/O card: two 8212 parallel ports (base+0/+1) and a TR1602 UART (base+2/+3).',
+        configSchema: { basePort: { type: 'u8', default: 0x10, min: 0, max: 0xfc } },
+    },
+    cardFactory: (id, cfg) => new ImsaiMioCard(id, { basePort: u8(cfg.basePort, 0x10) }),
+    // Registers 4 consecutive ports: portA(base), portB(base+1), UART(base+2/+3).
+    claims: (cfg) => { const b = u8(cfg.basePort, 0x10); return { ports: [b, b + 1, b + 2, b + 3] }; },
+};
+export const mitsDcddBundle = {
+    manifest: {
+        name: 'mits-88-dcdd',
+        version: '1.0.0',
+        type: 'floppy',
+        kind: 'card',
+        maker: 'MITS',
+        summary: 'MITS 88-DCDD 8-inch floppy controller; disk I/O over the FDC channel.',
+        configSchema: { basePort: { type: 'u8', default: 0x08, min: 0, max: 0xfd } },
+    },
+    cardFactory: (id, cfg, ctx) => {
+        const ws = ctx.services.fdc;
+        if (!ws) {
+            throw new MachineSpecError(`card "${id}" (mits-88-dcdd) requires an FDC channel in ctx.services.fdc`);
+        }
+        return new MitsDcddCard(id, ws, { basePort: u8(cfg.basePort, 0x08) });
+    },
+    claims: (cfg) => { const b = u8(cfg.basePort, 0x08); return { ports: [b, b + 1, b + 2] }; },
+};
+export const usart8251Bundle = {
+    manifest: {
+        name: 'intel-8251',
+        version: '1.0.0',
+        type: 'serial',
+        kind: 'chip',
+        maker: 'Intel',
+        summary: 'Intel 8251 USART (data + control port).',
+        configSchema: {
+            dataPort: { type: 'u8', default: 0x10, min: 0, max: 0xff },
+            ctrlPort: { type: 'u8', default: 0x11, min: 0, max: 0xff },
+        },
+    },
+    cardFactory: (id, cfg) => deviceCard(id, new Usart8251(id, u8(cfg.dataPort, 0x10), u8(cfg.ctrlPort, 0x11))),
+    claims: (cfg) => ({ ports: [u8(cfg.dataPort, 0x10), u8(cfg.ctrlPort, 0x11)] }),
+};
+export const mc6850Bundle = {
+    manifest: {
+        name: 'motorola-6850',
+        version: '1.0.0',
+        type: 'serial',
+        kind: 'chip',
+        maker: 'Motorola',
+        summary: 'Motorola 6850 ACIA (status + data port).',
+        configSchema: {
+            statusPort: { type: 'u8', default: 0x10, min: 0, max: 0xff },
+            dataPort: { type: 'u8', default: 0x11, min: 0, max: 0xff },
+        },
+    },
+    cardFactory: (id, cfg) => deviceCard(id, new Mc6850Acia(id, u8(cfg.statusPort, 0x10), u8(cfg.dataPort, 0x11))),
+    claims: (cfg) => ({ ports: [u8(cfg.statusPort, 0x10), u8(cfg.dataPort, 0x11)] }),
+};
+export const port8212Bundle = {
+    manifest: {
+        name: 'intel-8212',
+        version: '1.0.0',
+        type: 'other',
+        kind: 'chip',
+        maker: 'Intel',
+        summary: 'Intel 8212 8-bit I/O port.',
+        configSchema: { port: { type: 'u8', default: 0xff, min: 0, max: 0xff } },
+    },
+    cardFactory: (id, cfg) => deviceCard(id, new Port8212(id, u8(cfg.port, 0xff))),
+    claims: (cfg) => ({ ports: [u8(cfg.port, 0xff)] }),
+};
+export const tr1602Bundle = {
+    manifest: {
+        name: 'tr1602-uart',
+        version: '1.0.0',
+        type: 'serial',
+        kind: 'chip',
+        maker: 'Western Digital',
+        summary: 'TR1602 UART (data + status port).',
+        configSchema: {
+            dataPort: { type: 'u8', default: 0x00, min: 0, max: 0xff },
+            statusPort: { type: 'u8', default: 0x01, min: 0, max: 0xff },
+        },
+    },
+    cardFactory: (id, cfg) => deviceCard(id, new Tr1602Uart(id, u8(cfg.dataPort, 0x00), u8(cfg.statusPort, 0x01))),
+    claims: (cfg) => ({ ports: [u8(cfg.dataPort, 0x00), u8(cfg.statusPort, 0x01)] }),
+};
+/** Static RAM card — maps RAM at a base address for a size. A memory card:
+ * contributes no I/O device, only a RAM region hoisted into the memory map. */
+export const ramCardBundle = {
+    manifest: {
+        name: 'ram-card',
+        version: '1.0.0',
+        type: 'memory',
+        kind: 'card',
+        maker: 'generic',
+        summary: 'Static RAM board — maps read/write RAM at a configurable base address.',
+        configSchema: {
+            base: { type: 'u16', default: 0x0000, min: 0, max: 0xffff, description: 'Start address' },
+            size: { type: 'u16', default: 0x4000, min: 1, max: 0xffff, description: 'Bytes of RAM' },
+        },
+    },
+    cardFactory: (id) => memoryCard(id),
+    claims: () => ({ ports: [] }),
+    memory: (cfg) => [{ id: 'ram', base: u16(cfg.base, 0x0000), size: u16(cfg.size, 0x4000), kind: 'ram' }],
+};
+/** EPROM card — maps a ROM at a base address. The chip ships empty (zero-filled);
+ * an image is burned in later. A memory card: no I/O, just a ROM region. */
+export const epromCardBundle = {
+    manifest: {
+        name: 'eprom-card',
+        version: '1.0.0',
+        type: 'memory',
+        kind: 'card',
+        maker: 'generic',
+        summary: 'EPROM board — maps a read-only region at a base address; burn a .bin/Intel-HEX image into it.',
+        configSchema: {
+            base: { type: 'u16', default: 0xf000, min: 0, max: 0xffff, description: 'Start address' },
+            size: { type: 'u16', default: 0x0800, min: 1, max: 0xffff, description: 'EPROM size in bytes' },
+        },
+    },
+    cardFactory: (id) => memoryCard(id),
+    claims: () => ({ ports: [] }),
+    memory: (cfg) => {
+        const base = u16(cfg.base, 0xf000);
+        const size = u16(cfg.size, 0x0800);
+        return [{ id: 'rom', base, size, kind: 'rom', image: new Uint8Array(size) }];
+    },
+};
+/** Intel 8080 CPU card — the processor board. Declares the CPU family and the
+ * power-on jump (resetVector), authentically a CPU-card feature. No bus I/O. */
+export const i8080CpuBundle = {
+    manifest: {
+        name: 'i8080-cpu',
+        version: '1.0.0',
+        type: 'cpu',
+        kind: 'card',
+        maker: 'Intel',
+        summary: 'Intel 8080 CPU board — the bus master; sets the power-on jump address.',
+        configSchema: {
+            resetVector: { type: 'u16', default: 0x0000, min: 0, max: 0xffff, description: 'Power-on jump (program counter at reset)' },
+        },
+    },
+    cardFactory: (id) => cpuCard(id),
+    claims: () => ({ ports: [] }),
+    cpu: (cfg) => ({ kind: 'i8080', resetVector: u16(cfg.resetVector, 0x0000) }),
+};
+/** Zilog Z80 CPU card — 8080-compatible bus master with the Z80 instruction set. */
+export const z80CpuBundle = {
+    manifest: {
+        name: 'z80-cpu',
+        version: '1.0.0',
+        type: 'cpu',
+        kind: 'card',
+        maker: 'Zilog',
+        summary: 'Zilog Z80 CPU board — the bus master; sets the power-on jump address.',
+        configSchema: {
+            resetVector: { type: 'u16', default: 0x0000, min: 0, max: 0xffff, description: 'Power-on jump (program counter at reset)' },
+        },
+    },
+    cardFactory: (id) => cpuCard(id),
+    claims: () => ({ ports: [] }),
+    cpu: (cfg) => ({ kind: 'z80', resetVector: u16(cfg.resetVector, 0x0000) }),
+};
+/** All built-in seed bundles, keyed by manifest name. */
+export const seedBundles = [
+    i8080CpuBundle,
+    z80CpuBundle,
+    mits2SioBundle,
+    imsaiSioBundle,
+    imsaiMioBundle,
+    mitsDcddBundle,
+    usart8251Bundle,
+    mc6850Bundle,
+    port8212Bundle,
+    tr1602Bundle,
+    ramCardBundle,
+    epromCardBundle,
+];
+export const seedBundleByName = (name) => seedBundles.find((b) => b.manifest.name === name);
+//# sourceMappingURL=index.js.map