@joezilla/8sim 0.10.0

package/dist/cpu/z80/instructions/exchange.js.map

@@ -0,0 +1 @@
+{"version":3,"file":"exchange.js","sourceRoot":"","sources":["../../../../src/cpu/z80/instructions/exchange.ts"],"names":[],"mappings":"AACA,OAAO,EAAE,GAAG,EAAE,MAAM,uBAAuB,CAAC;AAE5C,oCAAoC;AACpC,MAAM,UAAU,gBAAgB,CAAC,KAAmB,EAAE,IAAe;IACnE,iFAAiF;IACjF,KAAK,CAAC,IAAI,CAAC,GAAG,CAAC,GAAG,EAAE,EAAE;QACpB,MAAM,EAAE,GAAG,GAAG,CAAC,IAAI,CAAC,EAAE,CAAC;QACvB,GAAG,CAAC,IAAI,CAAC,EAAE,GAAG,GAAG,CAAC,IAAI,CAAC,EAAE,CAAC;QAC1B,GAAG,CAAC,IAAI,CAAC,EAAE,GAAG,EAAE,CAAC;QACjB,OAAO,CAAC,CAAC;IACX,CAAC,CAAC;IAEF,YAAY;IACZ,KAAK,CAAC,IAAI,CAAC,GAAG,CAAC,GAAG,EAAE,EAAE;QACpB,MAAM,CAAC,GAAG,GAAG,CAAC,IAAI,CAAC,CAAC,CAAC;QACrB,MAAM,CAAC,GAAG,GAAG,CAAC,KAAK,CAAC,MAAM,EAAE,CAAC;QAC7B,GAAG,CAAC,IAAI,CAAC,CAAC,GAAG,GAAG,CAAC,IAAI,CAAC,EAAE,CAAC;QACzB,GAAG,CAAC,KAAK,CAAC,QAAQ,CAAC,GAAG,CAAC,IAAI,CAAC,EAAE,CAAC,CAAC;QAChC,GAAG,CAAC,IAAI,CAAC,EAAE,GAAG,CAAC,CAAC;QAChB,GAAG,CAAC,IAAI,CAAC,EAAE,GAAG,CAAC,CAAC;QAChB,OAAO,CAAC,CAAC;IACX,CAAC,CAAC;IAEF,MAAM;IACN,KAAK,CAAC,IAAI,CAAC,GAAG,CAAC,GAAG,EAAE,EAAE,GAAG,GAAG,CAAC,IAAI,CAAC,GAAG,EAAE,CAAC,CAAC,OAAO,CAAC,CAAC,CAAC,CAAC,CAAC;IAErD,uCAAuC;IACvC,KAAK,CAAC,IAAI,CAAC,GAAG,CAAC,GAAG,EAAE,EAAE;QACpB,MAAM,EAAE,GAAG,GAAG,CAAC,IAAI,CAAC,EAAE,CAAC;QACvB,MAAM,EAAE,GAAG,GAAG,CAAC,GAAG,CAAC,IAAI,CAAC,EAAE,CAAC,CAAC;QAC5B,MAAM,EAAE,GAAG,GAAG,CAAC,GAAG,CAAC,IAAI,CAAC,GAAG,CAAC,EAAE,GAAG,CAAC,CAAC,CAAC,CAAC;QACrC,MAAM,GAAG,GAAG,IAAI,CAAC,OAAO,CAAC,GAAG,CAAC,IAAI,CAAC,CAAC;QACnC,GAAG,CAAC,GAAG,CAAC,KAAK,CAAC,EAAE,EAAE,GAAG,GAAG,IAAI,CAAC,CAAC;QAC9B,GAAG,CAAC,GAAG,CAAC,KAAK,CAAC,GAAG,CAAC,EAAE,GAAG,CAAC,CAAC,EAAE,CAAC,GAAG,IAAI,CAAC,CAAC,GAAG,IAAI,CAAC,CAAC;QAC9C,MAAM,OAAO,GAAG,CAAC,EAAE,IAAI,CAAC,CAAC,GAAG,EAAE,CAAC;QAC/B,IAAI,CAAC,OAAO,CAAC,GAAG,CAAC,IAAI,EAAE,OAAO,CAAC,CAAC;QAChC,GAAG,CAAC,IAAI,CAAC,EAAE,GAAG,OAAO,CAAC;QACtB,OAAO,EAAE,CAAC;IACZ,CAAC,CAAC;AACJ,CAAC"}

package/dist/cpu/z80/instructions/io.d.ts

@@ -0,0 +1,8 @@
+import type { Z80Handler, IndexView } from '../types.js';
+/**
+ * Main-table I/O: IN A,(n) and OUT (n),A. The ED-prefixed IN r,(C)/OUT (C),r
+ * and the block I/O ops live in ed.ts / block.ts. Ports are addressed by the
+ * low 8 bits to match the emulator's 8-bit IoSpace.
+ */
+export declare function registerIO(table: Z80Handler[], _view: IndexView): void;
+//# sourceMappingURL=io.d.ts.map

package/dist/cpu/z80/instructions/io.d.ts.map

@@ -0,0 +1 @@
+{"version":3,"file":"io.d.ts","sourceRoot":"","sources":["../../../../src/cpu/z80/instructions/io.ts"],"names":[],"mappings":"AAAA,OAAO,KAAK,EAAE,UAAU,EAAE,SAAS,EAAE,MAAM,aAAa,CAAC;AAEzD;;;;GAIG;AACH,wBAAgB,UAAU,CAAC,KAAK,EAAE,UAAU,EAAE,EAAE,KAAK,EAAE,SAAS,GAAG,IAAI,CAgBtE"}

package/dist/cpu/z80/instructions/io.js

@@ -0,0 +1,22 @@
+/**
+ * Main-table I/O: IN A,(n) and OUT (n),A. The ED-prefixed IN r,(C)/OUT (C),r
+ * and the block I/O ops live in ed.ts / block.ts. Ports are addressed by the
+ * low 8 bits to match the emulator's 8-bit IoSpace.
+ */
+export function registerIO(table, _view) {
+    // IN A,(n) — WZ = (A<<8 | n) + 1
+    table[0xdb] = (cpu) => {
+        const n = cpu.fetchByte();
+        cpu.regs.wz = (((cpu.regs.a << 8) | n) + 1) & 0xffff;
+        cpu.regs.a = cpu.bus.ioRead(n) & 0xff;
+        return 11;
+    };
+    // OUT (n),A — WZ low = (n+1)&0xff, WZ high = A
+    table[0xd3] = (cpu) => {
+        const n = cpu.fetchByte();
+        cpu.bus.ioWrite(n, cpu.regs.a);
+        cpu.regs.wz = ((cpu.regs.a << 8) | ((n + 1) & 0xff)) & 0xffff;
+        return 11;
+    };
+}
+//# sourceMappingURL=io.js.map

package/dist/cpu/z80/instructions/io.js.map

@@ -0,0 +1 @@
+{"version":3,"file":"io.js","sourceRoot":"","sources":["../../../../src/cpu/z80/instructions/io.ts"],"names":[],"mappings":"AAEA;;;;GAIG;AACH,MAAM,UAAU,UAAU,CAAC,KAAmB,EAAE,KAAgB;IAC9D,iCAAiC;IACjC,KAAK,CAAC,IAAI,CAAC,GAAG,CAAC,GAAG,EAAE,EAAE;QACpB,MAAM,CAAC,GAAG,GAAG,CAAC,SAAS,EAAE,CAAC;QAC1B,GAAG,CAAC,IAAI,CAAC,EAAE,GAAG,CAAC,CAAC,CAAC,GAAG,CAAC,IAAI,CAAC,CAAC,IAAI,CAAC,CAAC,GAAG,CAAC,CAAC,GAAG,CAAC,CAAC,GAAG,MAAM,CAAC;QACrD,GAAG,CAAC,IAAI,CAAC,CAAC,GAAG,GAAG,CAAC,GAAG,CAAC,MAAM,CAAC,CAAC,CAAC,GAAG,IAAI,CAAC;QACtC,OAAO,EAAE,CAAC;IACZ,CAAC,CAAC;IAEF,+CAA+C;IAC/C,KAAK,CAAC,IAAI,CAAC,GAAG,CAAC,GAAG,EAAE,EAAE;QACpB,MAAM,CAAC,GAAG,GAAG,CAAC,SAAS,EAAE,CAAC;QAC1B,GAAG,CAAC,GAAG,CAAC,OAAO,CAAC,CAAC,EAAE,GAAG,CAAC,IAAI,CAAC,CAAC,CAAC,CAAC;QAC/B,GAAG,CAAC,IAAI,CAAC,EAAE,GAAG,CAAC,CAAC,GAAG,CAAC,IAAI,CAAC,CAAC,IAAI,CAAC,CAAC,GAAG,CAAC,CAAC,CAAC,GAAG,CAAC,CAAC,GAAG,IAAI,CAAC,CAAC,GAAG,MAAM,CAAC;QAC9D,OAAO,EAAE,CAAC;IACZ,CAAC,CAAC;AACJ,CAAC"}

package/dist/cpu/z80/instructions/jump.d.ts

@@ -0,0 +1,4 @@
+import type { Z80Handler, IndexView } from '../types.js';
+/** Jump, call, return, and restart instructions (mostly view-independent). */
+export declare function registerJump(table: Z80Handler[], view: IndexView): void;
+//# sourceMappingURL=jump.d.ts.map

package/dist/cpu/z80/instructions/jump.d.ts.map

@@ -0,0 +1 @@
+{"version":3,"file":"jump.d.ts","sourceRoot":"","sources":["../../../../src/cpu/z80/instructions/jump.ts"],"names":[],"mappings":"AAAA,OAAO,KAAK,EAAE,UAAU,EAAE,SAAS,EAAE,MAAM,aAAa,CAAC;AAmBzD,8EAA8E;AAC9E,wBAAgB,YAAY,CAAC,KAAK,EAAE,UAAU,EAAE,EAAE,IAAI,EAAE,SAAS,GAAG,IAAI,CAwGvE"}

package/dist/cpu/z80/instructions/jump.js

@@ -0,0 +1,113 @@
+import { sext8 } from '../views.js';
+import { u16 } from '../../../util/bits.js';
+/** Evaluate condition code cc (0=NZ,1=Z,2=NC,3=C,4=PO,5=PE,6=P,7=M). */
+function cond(f, cc) {
+    switch (cc) {
+        case 0: return !f.z;
+        case 1: return f.z;
+        case 2: return !f.c;
+        case 3: return f.c;
+        case 4: return !f.pv;
+        case 5: return f.pv;
+        case 6: return !f.s;
+        default: return f.s;
+    }
+}
+/** Jump, call, return, and restart instructions (mostly view-independent). */
+export function registerJump(table, view) {
+    // JP nn
+    table[0xc3] = (cpu) => { const nn = cpu.fetchWord(); cpu.regs.pc = nn; cpu.regs.wz = nn; return 10; };
+    // JP cc,nn
+    for (let cc = 0; cc < 8; cc++) {
+        const op = 0xc2 | (cc << 3);
+        table[op] = (cpu) => {
+            const nn = cpu.fetchWord();
+            cpu.regs.wz = nn;
+            if (cond(cpu.flags, cc))
+                cpu.regs.pc = nn;
+            return 10;
+        };
+    }
+    // JR e
+    table[0x18] = (cpu) => {
+        const e = sext8(cpu.fetchByte());
+        cpu.regs.pc = u16(cpu.regs.pc + e);
+        cpu.regs.wz = cpu.regs.pc;
+        return 12;
+    };
+    // JR cc,e  (cc: 0=NZ,1=Z,2=NC,3=C at 0x20/0x28/0x30/0x38)
+    for (let cc = 0; cc < 4; cc++) {
+        const op = 0x20 | (cc << 3);
+        table[op] = (cpu) => {
+            const e = sext8(cpu.fetchByte());
+            if (cond(cpu.flags, cc)) {
+                cpu.regs.pc = u16(cpu.regs.pc + e);
+                cpu.regs.wz = cpu.regs.pc;
+                return 12;
+            }
+            return 7;
+        };
+    }
+    // DJNZ e
+    table[0x10] = (cpu) => {
+        const e = sext8(cpu.fetchByte());
+        cpu.regs.b = (cpu.regs.b - 1) & 0xff;
+        if (cpu.regs.b !== 0) {
+            cpu.regs.pc = u16(cpu.regs.pc + e);
+            cpu.regs.wz = cpu.regs.pc;
+            return 13;
+        }
+        return 8;
+    };
+    // CALL nn
+    table[0xcd] = (cpu) => {
+        const nn = cpu.fetchWord();
+        cpu.regs.wz = nn;
+        cpu.push16(cpu.regs.pc);
+        cpu.regs.pc = nn;
+        return 17;
+    };
+    // CALL cc,nn
+    for (let cc = 0; cc < 8; cc++) {
+        const op = 0xc4 | (cc << 3);
+        table[op] = (cpu) => {
+            const nn = cpu.fetchWord();
+            cpu.regs.wz = nn;
+            if (cond(cpu.flags, cc)) {
+                cpu.push16(cpu.regs.pc);
+                cpu.regs.pc = nn;
+                return 17;
+            }
+            return 10;
+        };
+    }
+    // RET
+    table[0xc9] = (cpu) => { const pc = cpu.pop16(); cpu.regs.pc = pc; cpu.regs.wz = pc; return 10; };
+    // RET cc
+    for (let cc = 0; cc < 8; cc++) {
+        const op = 0xc0 | (cc << 3);
+        table[op] = (cpu) => {
+            if (cond(cpu.flags, cc)) {
+                const pc = cpu.pop16();
+                cpu.regs.pc = pc;
+                cpu.regs.wz = pc;
+                return 11;
+            }
+            return 5;
+        };
+    }
+    // RST n
+    for (let n = 0; n < 8; n++) {
+        const op = 0xc7 | (n << 3);
+        const target = n << 3;
+        table[op] = (cpu) => {
+            cpu.push16(cpu.regs.pc);
+            cpu.regs.pc = target;
+            cpu.regs.wz = target;
+            return 11;
+        };
+    }
+    // JP (HL) / JP (IX) / JP (IY)
+    table[0xe9] = (cpu) => { cpu.regs.pc = view.getPair(cpu.regs); return 4; };
+}
+//# sourceMappingURL=jump.js.map

package/dist/cpu/z80/instructions/jump.js.map

@@ -0,0 +1 @@
+{"version":3,"file":"jump.js","sourceRoot":"","sources":["../../../../src/cpu/z80/instructions/jump.ts"],"names":[],"mappings":"AAEA,OAAO,EAAE,KAAK,EAAE,MAAM,aAAa,CAAC;AACpC,OAAO,EAAE,GAAG,EAAE,MAAM,uBAAuB,CAAC;AAE5C,wEAAwE;AACxE,SAAS,IAAI,CAAC,CAAW,EAAE,EAAU;IACnC,QAAQ,EAAE,EAAE,CAAC;QACX,KAAK,CAAC,CAAC,CAAC,OAAO,CAAC,CAAC,CAAC,CAAC,CAAC;QACpB,KAAK,CAAC,CAAC,CAAC,OAAO,CAAC,CAAC,CAAC,CAAC;QACnB,KAAK,CAAC,CAAC,CAAC,OAAO,CAAC,CAAC,CAAC,CAAC,CAAC;QACpB,KAAK,CAAC,CAAC,CAAC,OAAO,CAAC,CAAC,CAAC,CAAC;QACnB,KAAK,CAAC,CAAC,CAAC,OAAO,CAAC,CAAC,CAAC,EAAE,CAAC;QACrB,KAAK,CAAC,CAAC,CAAC,OAAO,CAAC,CAAC,EAAE,CAAC;QACpB,KAAK,CAAC,CAAC,CAAC,OAAO,CAAC,CAAC,CAAC,CAAC,CAAC;QACpB,OAAO,CAAC,CAAC,OAAO,CAAC,CAAC,CAAC,CAAC;IACtB,CAAC;AACH,CAAC;AAED,8EAA8E;AAC9E,MAAM,UAAU,YAAY,CAAC,KAAmB,EAAE,IAAe;IAC/D,QAAQ;IACR,KAAK,CAAC,IAAI,CAAC,GAAG,CAAC,GAAG,EAAE,EAAE,GAAG,MAAM,EAAE,GAAG,GAAG,CAAC,SAAS,EAAE,CAAC,CAAC,GAAG,CAAC,IAAI,CAAC,EAAE,GAAG,EAAE,CAAC,CAAC,GAAG,CAAC,IAAI,CAAC,EAAE,GAAG,EAAE,CAAC,CAAC,OAAO,EAAE,CAAC,CAAC,CAAC,CAAC;IAEtG,WAAW;IACX,KAAK,IAAI,EAAE,GAAG,CAAC,EAAE,EAAE,GAAG,CAAC,EAAE,EAAE,EAAE,EAAE,CAAC;QAC9B,MAAM,EAAE,GAAG,IAAI,GAAG,CAAC,EAAE,IAAI,CAAC,CAAC,CAAC;QAC5B,KAAK,CAAC,EAAE,CAAC,GAAG,CAAC,GAAG,EAAE,EAAE;YAClB,MAAM,EAAE,GAAG,GAAG,CAAC,SAAS,EAAE,CAAC;YAC3B,GAAG,CAAC,IAAI,CAAC,EAAE,GAAG,EAAE,CAAC;YACjB,IAAI,IAAI,CAAC,GAAG,CAAC,KAAK,EAAE,EAAE,CAAC;gBAAE,GAAG,CAAC,IAAI,CAAC,EAAE,GAAG,EAAE,CAAC;YAC1C,OAAO,EAAE,CAAC;QACZ,CAAC,CAAC;IACJ,CAAC;IAED,OAAO;IACP,KAAK,CAAC,IAAI,CAAC,GAAG,CAAC,GAAG,EAAE,EAAE;QACpB,MAAM,CAAC,GAAG,KAAK,CAAC,GAAG,CAAC,SAAS,EAAE,CAAC,CAAC;QACjC,GAAG,CAAC,IAAI,CAAC,EAAE,GAAG,GAAG,CAAC,GAAG,CAAC,IAAI,CAAC,EAAE,GAAG,CAAC,CAAC,CAAC;QACnC,GAAG,CAAC,IAAI,CAAC,EAAE,GAAG,GAAG,CAAC,IAAI,CAAC,EAAE,CAAC;QAC1B,OAAO,EAAE,CAAC;IACZ,CAAC,CAAC;IAEF,0DAA0D;IAC1D,KAAK,IAAI,EAAE,GAAG,CAAC,EAAE,EAAE,GAAG,CAAC,EAAE,EAAE,EAAE,EAAE,CAAC;QAC9B,MAAM,EAAE,GAAG,IAAI,GAAG,CAAC,EAAE,IAAI,CAAC,CAAC,CAAC;QAC5B,KAAK,CAAC,EAAE,CAAC,GAAG,CAAC,GAAG,EAAE,EAAE;YAClB,MAAM,CAAC,GAAG,KAAK,CAAC,GAAG,CAAC,SAAS,EAAE,CAAC,CAAC;YACjC,IAAI,IAAI,CAAC,GAAG,CAAC,KAAK,EAAE,EAAE,CAAC,EAAE,CAAC;gBACxB,GAAG,CAAC,IAAI,CAAC,EAAE,GAAG,GAAG,CAAC,GAAG,CAAC,IAAI,CAAC,EAAE,GAAG,CAAC,CAAC,CAAC;gBACnC,GAAG,CAAC,IAAI,CAAC,EAAE,GAAG,GAAG,CAAC,IAAI,CAAC,EAAE,CAAC;gBAC1B,OAAO,EAAE,CAAC;YACZ,CAAC;YACD,OAAO,CAAC,CAAC;QACX,CAAC,CAAC;IACJ,CAAC;IAED,SAAS;IACT,KAAK,CAAC,IAAI,CAAC,GAAG,CAAC,GAAG,EAAE,EAAE;QACpB,MAAM,CAAC,GAAG,KAAK,CAAC,GAAG,CAAC,SAAS,EAAE,CAAC,CAAC;QACjC,GAAG,CAAC,IAAI,CAAC,CAAC,GAAG,CAAC,GAAG,CAAC,IAAI,CAAC,CAAC,GAAG,CAAC,CAAC,GAAG,IAAI,CAAC;QACrC,IAAI,GAAG,CAAC,IAAI,CAAC,CAAC,KAAK,CAAC,EAAE,CAAC;YACrB,GAAG,CAAC,IAAI,CAAC,EAAE,GAAG,GAAG,CAAC,GAAG,CAAC,IAAI,CAAC,EAAE,GAAG,CAAC,CAAC,CAAC;YACnC,GAAG,CAAC,IAAI,CAAC,EAAE,GAAG,GAAG,CAAC,IAAI,CAAC,EAAE,CAAC;YAC1B,OAAO,EAAE,CAAC;QACZ,CAAC;QACD,OAAO,CAAC,CAAC;IACX,CAAC,CAAC;IAEF,UAAU;IACV,KAAK,CAAC,IAAI,CAAC,GAAG,CAAC,GAAG,EAAE,EAAE;QACpB,MAAM,EAAE,GAAG,GAAG,CAAC,SAAS,EAAE,CAAC;QAC3B,GAAG,CAAC,IAAI,CAAC,EAAE,GAAG,EAAE,CAAC;QACjB,GAAG,CAAC,MAAM,CAAC,GAAG,CAAC,IAAI,CAAC,EAAE,CAAC,CAAC;QACxB,GAAG,CAAC,IAAI,CAAC,EAAE,GAAG,EAAE,CAAC;QACjB,OAAO,EAAE,CAAC;IACZ,CAAC,CAAC;IAEF,aAAa;IACb,KAAK,IAAI,EAAE,GAAG,CAAC,EAAE,EAAE,GAAG,CAAC,EAAE,EAAE,EAAE,EAAE,CAAC;QAC9B,MAAM,EAAE,GAAG,IAAI,GAAG,CAAC,EAAE,IAAI,CAAC,CAAC,CAAC;QAC5B,KAAK,CAAC,EAAE,CAAC,GAAG,CAAC,GAAG,EAAE,EAAE;YAClB,MAAM,EAAE,GAAG,GAAG,CAAC,SAAS,EAAE,CAAC;YAC3B,GAAG,CAAC,IAAI,CAAC,EAAE,GAAG,EAAE,CAAC;YACjB,IAAI,IAAI,CAAC,GAAG,CAAC,KAAK,EAAE,EAAE,CAAC,EAAE,CAAC;gBACxB,GAAG,CAAC,MAAM,CAAC,GAAG,CAAC,IAAI,CAAC,EAAE,CAAC,CAAC;gBACxB,GAAG,CAAC,IAAI,CAAC,EAAE,GAAG,EAAE,CAAC;gBACjB,OAAO,EAAE,CAAC;YACZ,CAAC;YACD,OAAO,EAAE,CAAC;QACZ,CAAC,CAAC;IACJ,CAAC;IAED,MAAM;IACN,KAAK,CAAC,IAAI,CAAC,GAAG,CAAC,GAAG,EAAE,EAAE,GAAG,MAAM,EAAE,GAAG,GAAG,CAAC,KAAK,EAAE,CAAC,CAAC,GAAG,CAAC,IAAI,CAAC,EAAE,GAAG,EAAE,CAAC,CAAC,GAAG,CAAC,IAAI,CAAC,EAAE,GAAG,EAAE,CAAC,CAAC,OAAO,EAAE,CAAC,CAAC,CAAC,CAAC;IAElG,SAAS;IACT,KAAK,IAAI,EAAE,GAAG,CAAC,EAAE,EAAE,GAAG,CAAC,EAAE,EAAE,EAAE,EAAE,CAAC;QAC9B,MAAM,EAAE,GAAG,IAAI,GAAG,CAAC,EAAE,IAAI,CAAC,CAAC,CAAC;QAC5B,KAAK,CAAC,EAAE,CAAC,GAAG,CAAC,GAAG,EAAE,EAAE;YAClB,IAAI,IAAI,CAAC,GAAG,CAAC,KAAK,EAAE,EAAE,CAAC,EAAE,CAAC;gBACxB,MAAM,EAAE,GAAG,GAAG,CAAC,KAAK,EAAE,CAAC;gBACvB,GAAG,CAAC,IAAI,CAAC,EAAE,GAAG,EAAE,CAAC;gBACjB,GAAG,CAAC,IAAI,CAAC,EAAE,GAAG,EAAE,CAAC;gBACjB,OAAO,EAAE,CAAC;YACZ,CAAC;YACD,OAAO,CAAC,CAAC;QACX,CAAC,CAAC;IACJ,CAAC;IAED,QAAQ;IACR,KAAK,IAAI,CAAC,GAAG,CAAC,EAAE,CAAC,GAAG,CAAC,EAAE,CAAC,EAAE,EAAE,CAAC;QAC3B,MAAM,EAAE,GAAG,IAAI,GAAG,CAAC,CAAC,IAAI,CAAC,CAAC,CAAC;QAC3B,MAAM,MAAM,GAAG,CAAC,IAAI,CAAC,CAAC;QACtB,KAAK,CAAC,EAAE,CAAC,GAAG,CAAC,GAAG,EAAE,EAAE;YAClB,GAAG,CAAC,MAAM,CAAC,GAAG,CAAC,IAAI,CAAC,EAAE,CAAC,CAAC;YACxB,GAAG,CAAC,IAAI,CAAC,EAAE,GAAG,MAAM,CAAC;YACrB,GAAG,CAAC,IAAI,CAAC,EAAE,GAAG,MAAM,CAAC;YACrB,OAAO,EAAE,CAAC;QACZ,CAAC,CAAC;IACJ,CAAC;IAED,8BAA8B;IAC9B,KAAK,CAAC,IAAI,CAAC,GAAG,CAAC,GAAG,EAAE,EAAE,GAAG,GAAG,CAAC,IAAI,CAAC,EAAE,GAAG,IAAI,CAAC,OAAO,CAAC,GAAG,CAAC,IAAI,CAAC,CAAC,CAAC,OAAO,CAAC,CAAC,CAAC,CAAC,CAAC;AAC7E,CAAC"}

package/dist/cpu/z80/instructions/load.d.ts

@@ -0,0 +1,7 @@
+import type { Z80Handler, IndexView } from '../types.js';
+/**
+ * 8-bit and 16-bit LD instructions in the main table (view-parameterized).
+ * The 0x76 slot of the LD block is HALT and is registered by control.ts.
+ */
+export declare function registerLoad(table: Z80Handler[], view: IndexView): void;
+//# sourceMappingURL=load.d.ts.map

package/dist/cpu/z80/instructions/load.d.ts.map

@@ -0,0 +1 @@
+{"version":3,"file":"load.d.ts","sourceRoot":"","sources":["../../../../src/cpu/z80/instructions/load.ts"],"names":[],"mappings":"AAAA,OAAO,KAAK,EAAE,UAAU,EAAE,SAAS,EAAW,MAAM,aAAa,CAAC;AAelE;;;GAGG;AACH,wBAAgB,YAAY,CAAC,KAAK,EAAE,UAAU,EAAE,EAAE,IAAI,EAAE,SAAS,GAAG,IAAI,CAwFvE"}

package/dist/cpu/z80/instructions/load.js

@@ -0,0 +1,103 @@
+import { getR, setR, getRealR, setRealR } from '../regcodes.js';
+import { u16 } from '../../../util/bits.js';
+function read16(cpu, addr) {
+    const lo = cpu.bus.read(addr);
+    const hi = cpu.bus.read(u16(addr + 1));
+    return (hi << 8) | lo;
+}
+function write16(cpu, addr, v) {
+    cpu.bus.write(addr, v & 0xff);
+    cpu.bus.write(u16(addr + 1), (v >> 8) & 0xff);
+}
+/**
+ * 8-bit and 16-bit LD instructions in the main table (view-parameterized).
+ * The 0x76 slot of the LD block is HALT and is registered by control.ts.
+ */
+export function registerLoad(table, view) {
+    // LD r,r' / LD r,(HL) / LD (HL),r  (0x40..0x7F, minus 0x76 = HALT)
+    for (let op = 0x40; op <= 0x7f; op++) {
+        if (op === 0x76)
+            continue;
+        const dst = (op >> 3) & 7;
+        const src = op & 7;
+        if (src === 6) {
+            // LD dst,(HL/IX+d) — destination register is never index-substituted.
+            table[op] = (cpu) => {
+                const addr = view.memAddr(cpu);
+                setRealR(cpu.regs, dst, cpu.bus.read(addr));
+                return 7 + view.memExtra;
+            };
+        }
+        else if (dst === 6) {
+            // LD (HL/IX+d),src — source register is never index-substituted.
+            table[op] = (cpu) => {
+                const addr = view.memAddr(cpu);
+                cpu.bus.write(addr, getRealR(cpu.regs, src));
+                return 7 + view.memExtra;
+            };
+        }
+        else {
+            table[op] = (cpu) => {
+                setR(cpu.regs, view, dst, getR(cpu.regs, view, src));
+                return 4;
+            };
+        }
+    }
+    // LD r,n  (0x06,0x0E,0x16,0x1E,0x26,0x2E,0x36,0x3E)
+    for (let r = 0; r < 8; r++) {
+        const op = 0x06 | (r << 3);
+        if (r === 6) {
+            // LD (HL),n / LD (IX+d),n — indexed form has a special 19T timing (not +8).
+            table[op] = (cpu) => {
+                const addr = view.memAddr(cpu); // fetches d first for indexed
+                cpu.bus.write(addr, cpu.fetchByte());
+                return view.indexed ? 15 : 10;
+            };
+        }
+        else {
+            table[op] = (cpu) => {
+                setR(cpu.regs, view, r, cpu.fetchByte());
+                return 7;
+            };
+        }
+    }
+    // LD A,(BC) / LD A,(DE) / LD A,(nn)  — WZ = source address + 1
+    table[0x0a] = (cpu) => { const a = cpu.regs.bc; cpu.regs.a = cpu.bus.read(a); cpu.regs.wz = u16(a + 1); return 7; };
+    table[0x1a] = (cpu) => { const a = cpu.regs.de; cpu.regs.a = cpu.bus.read(a); cpu.regs.wz = u16(a + 1); return 7; };
+    table[0x3a] = (cpu) => {
+        const nn = cpu.fetchWord();
+        cpu.regs.a = cpu.bus.read(nn);
+        cpu.regs.wz = u16(nn + 1);
+        return 13;
+    };
+    // LD (BC),A / LD (DE),A / LD (nn),A  — WZ = A in high byte, (addr+1) low byte
+    table[0x02] = (cpu) => { const a = cpu.regs.bc; cpu.bus.write(a, cpu.regs.a); cpu.regs.wz = ((cpu.regs.a << 8) | ((a + 1) & 0xff)) & 0xffff; return 7; };
+    table[0x12] = (cpu) => { const a = cpu.regs.de; cpu.bus.write(a, cpu.regs.a); cpu.regs.wz = ((cpu.regs.a << 8) | ((a + 1) & 0xff)) & 0xffff; return 7; };
+    table[0x32] = (cpu) => {
+        const nn = cpu.fetchWord();
+        cpu.bus.write(nn, cpu.regs.a);
+        cpu.regs.wz = ((cpu.regs.a << 8) | ((nn + 1) & 0xff)) & 0xffff;
+        return 13;
+    };
+    // LD rr,nn
+    table[0x01] = (cpu) => { cpu.regs.bc = cpu.fetchWord(); return 10; };
+    table[0x11] = (cpu) => { cpu.regs.de = cpu.fetchWord(); return 10; };
+    table[0x21] = (cpu) => { view.setPair(cpu.regs, cpu.fetchWord()); return 10; };
+    table[0x31] = (cpu) => { cpu.regs.sp = cpu.fetchWord(); return 10; };
+    // LD (nn),HL / LD HL,(nn)  (HL / IX / IY)
+    table[0x22] = (cpu) => {
+        const nn = cpu.fetchWord();
+        write16(cpu, nn, view.getPair(cpu.regs));
+        cpu.regs.wz = u16(nn + 1);
+        return 16;
+    };
+    table[0x2a] = (cpu) => {
+        const nn = cpu.fetchWord();
+        view.setPair(cpu.regs, read16(cpu, nn));
+        cpu.regs.wz = u16(nn + 1);
+        return 16;
+    };
+    // LD SP,HL / LD SP,IX / LD SP,IY
+    table[0xf9] = (cpu) => { cpu.regs.sp = view.getPair(cpu.regs); return 6; };
+}
+//# sourceMappingURL=load.js.map

package/dist/cpu/z80/instructions/load.js.map

@@ -0,0 +1 @@
+{"version":3,"file":"load.js","sourceRoot":"","sources":["../../../../src/cpu/z80/instructions/load.ts"],"names":[],"mappings":"AACA,OAAO,EAAE,IAAI,EAAE,IAAI,EAAE,QAAQ,EAAE,QAAQ,EAAE,MAAM,gBAAgB,CAAC;AAChE,OAAO,EAAE,GAAG,EAAE,MAAM,uBAAuB,CAAC;AAE5C,SAAS,MAAM,CAAC,GAAY,EAAE,IAAY;IACxC,MAAM,EAAE,GAAG,GAAG,CAAC,GAAG,CAAC,IAAI,CAAC,IAAI,CAAC,CAAC;IAC9B,MAAM,EAAE,GAAG,GAAG,CAAC,GAAG,CAAC,IAAI,CAAC,GAAG,CAAC,IAAI,GAAG,CAAC,CAAC,CAAC,CAAC;IACvC,OAAO,CAAC,EAAE,IAAI,CAAC,CAAC,GAAG,EAAE,CAAC;AACxB,CAAC;AAED,SAAS,OAAO,CAAC,GAAY,EAAE,IAAY,EAAE,CAAS;IACpD,GAAG,CAAC,GAAG,CAAC,KAAK,CAAC,IAAI,EAAE,CAAC,GAAG,IAAI,CAAC,CAAC;IAC9B,GAAG,CAAC,GAAG,CAAC,KAAK,CAAC,GAAG,CAAC,IAAI,GAAG,CAAC,CAAC,EAAE,CAAC,CAAC,IAAI,CAAC,CAAC,GAAG,IAAI,CAAC,CAAC;AAChD,CAAC;AAED;;;GAGG;AACH,MAAM,UAAU,YAAY,CAAC,KAAmB,EAAE,IAAe;IAC/D,mEAAmE;IACnE,KAAK,IAAI,EAAE,GAAG,IAAI,EAAE,EAAE,IAAI,IAAI,EAAE,EAAE,EAAE,EAAE,CAAC;QACrC,IAAI,EAAE,KAAK,IAAI;YAAE,SAAS;QAC1B,MAAM,GAAG,GAAG,CAAC,EAAE,IAAI,CAAC,CAAC,GAAG,CAAC,CAAC;QAC1B,MAAM,GAAG,GAAG,EAAE,GAAG,CAAC,CAAC;QACnB,IAAI,GAAG,KAAK,CAAC,EAAE,CAAC;YACd,sEAAsE;YACtE,KAAK,CAAC,EAAE,CAAC,GAAG,CAAC,GAAG,EAAE,EAAE;gBAClB,MAAM,IAAI,GAAG,IAAI,CAAC,OAAO,CAAC,GAAG,CAAC,CAAC;gBAC/B,QAAQ,CAAC,GAAG,CAAC,IAAI,EAAE,GAAG,EAAE,GAAG,CAAC,GAAG,CAAC,IAAI,CAAC,IAAI,CAAC,CAAC,CAAC;gBAC5C,OAAO,CAAC,GAAG,IAAI,CAAC,QAAQ,CAAC;YAC3B,CAAC,CAAC;QACJ,CAAC;aAAM,IAAI,GAAG,KAAK,CAAC,EAAE,CAAC;YACrB,iEAAiE;YACjE,KAAK,CAAC,EAAE,CAAC,GAAG,CAAC,GAAG,EAAE,EAAE;gBAClB,MAAM,IAAI,GAAG,IAAI,CAAC,OAAO,CAAC,GAAG,CAAC,CAAC;gBAC/B,GAAG,CAAC,GAAG,CAAC,KAAK,CAAC,IAAI,EAAE,QAAQ,CAAC,GAAG,CAAC,IAAI,EAAE,GAAG,CAAC,CAAC,CAAC;gBAC7C,OAAO,CAAC,GAAG,IAAI,CAAC,QAAQ,CAAC;YAC3B,CAAC,CAAC;QACJ,CAAC;aAAM,CAAC;YACN,KAAK,CAAC,EAAE,CAAC,GAAG,CAAC,GAAG,EAAE,EAAE;gBAClB,IAAI,CAAC,GAAG,CAAC,IAAI,EAAE,IAAI,EAAE,GAAG,EAAE,IAAI,CAAC,GAAG,CAAC,IAAI,EAAE,IAAI,EAAE,GAAG,CAAC,CAAC,CAAC;gBACrD,OAAO,CAAC,CAAC;YACX,CAAC,CAAC;QACJ,CAAC;IACH,CAAC;IAED,oDAAoD;IACpD,KAAK,IAAI,CAAC,GAAG,CAAC,EAAE,CAAC,GAAG,CAAC,EAAE,CAAC,EAAE,EAAE,CAAC;QAC3B,MAAM,EAAE,GAAG,IAAI,GAAG,CAAC,CAAC,IAAI,CAAC,CAAC,CAAC;QAC3B,IAAI,CAAC,KAAK,CAAC,EAAE,CAAC;YACZ,4EAA4E;YAC5E,KAAK,CAAC,EAAE,CAAC,GAAG,CAAC,GAAG,EAAE,EAAE;gBAClB,MAAM,IAAI,GAAG,IAAI,CAAC,OAAO,CAAC,GAAG,CAAC,CAAC,CAAC,8BAA8B;gBAC9D,GAAG,CAAC,GAAG,CAAC,KAAK,CAAC,IAAI,EAAE,GAAG,CAAC,SAAS,EAAE,CAAC,CAAC;gBACrC,OAAO,IAAI,CAAC,OAAO,CAAC,CAAC,CAAC,EAAE,CAAC,CAAC,CAAC,EAAE,CAAC;YAChC,CAAC,CAAC;QACJ,CAAC;aAAM,CAAC;YACN,KAAK,CAAC,EAAE,CAAC,GAAG,CAAC,GAAG,EAAE,EAAE;gBAClB,IAAI,CAAC,GAAG,CAAC,IAAI,EAAE,IAAI,EAAE,CAAC,EAAE,GAAG,CAAC,SAAS,EAAE,CAAC,CAAC;gBACzC,OAAO,CAAC,CAAC;YACX,CAAC,CAAC;QACJ,CAAC;IACH,CAAC;IAED,+DAA+D;IAC/D,KAAK,CAAC,IAAI,CAAC,GAAG,CAAC,GAAG,EAAE,EAAE,GAAG,MAAM,CAAC,GAAG,GAAG,CAAC,IAAI,CAAC,EAAE,CAAC,CAAC,GAAG,CAAC,IAAI,CAAC,CAAC,GAAG,GAAG,CAAC,GAAG,CAAC,IAAI,CAAC,CAAC,CAAC,CAAC,CAAC,GAAG,CAAC,IAAI,CAAC,EAAE,GAAG,GAAG,CAAC,CAAC,GAAG,CAAC,CAAC,CAAC,CAAC,OAAO,CAAC,CAAC,CAAC,CAAC,CAAC;IACpH,KAAK,CAAC,IAAI,CAAC,GAAG,CAAC,GAAG,EAAE,EAAE,GAAG,MAAM,CAAC,GAAG,GAAG,CAAC,IAAI,CAAC,EAAE,CAAC,CAAC,GAAG,CAAC,IAAI,CAAC,CAAC,GAAG,GAAG,CAAC,GAAG,CAAC,IAAI,CAAC,CAAC,CAAC,CAAC,CAAC,GAAG,CAAC,IAAI,CAAC,EAAE,GAAG,GAAG,CAAC,CAAC,GAAG,CAAC,CAAC,CAAC,CAAC,OAAO,CAAC,CAAC,CAAC,CAAC,CAAC;IACpH,KAAK,CAAC,IAAI,CAAC,GAAG,CAAC,GAAG,EAAE,EAAE;QACpB,MAAM,EAAE,GAAG,GAAG,CAAC,SAAS,EAAE,CAAC;QAC3B,GAAG,CAAC,IAAI,CAAC,CAAC,GAAG,GAAG,CAAC,GAAG,CAAC,IAAI,CAAC,EAAE,CAAC,CAAC;QAC9B,GAAG,CAAC,IAAI,CAAC,EAAE,GAAG,GAAG,CAAC,EAAE,GAAG,CAAC,CAAC,CAAC;QAC1B,OAAO,EAAE,CAAC;IACZ,CAAC,CAAC;IAEF,8EAA8E;IAC9E,KAAK,CAAC,IAAI,CAAC,GAAG,CAAC,GAAG,EAAE,EAAE,GAAG,MAAM,CAAC,GAAG,GAAG,CAAC,IAAI,CAAC,EAAE,CAAC,CAAC,GAAG,CAAC,GAAG,CAAC,KAAK,CAAC,CAAC,EAAE,GAAG,CAAC,IAAI,CAAC,CAAC,CAAC,CAAC,CAAC,GAAG,CAAC,IAAI,CAAC,EAAE,GAAG,CAAC,CAAC,GAAG,CAAC,IAAI,CAAC,CAAC,IAAI,CAAC,CAAC,GAAG,CAAC,CAAC,CAAC,GAAG,CAAC,CAAC,GAAG,IAAI,CAAC,CAAC,GAAG,MAAM,CAAC,CAAC,OAAO,CAAC,CAAC,CAAC,CAAC,CAAC;IACzJ,KAAK,CAAC,IAAI,CAAC,GAAG,CAAC,GAAG,EAAE,EAAE,GAAG,MAAM,CAAC,GAAG,GAAG,CAAC,IAAI,CAAC,EAAE,CAAC,CAAC,GAAG,CAAC,GAAG,CAAC,KAAK,CAAC,CAAC,EAAE,GAAG,CAAC,IAAI,CAAC,CAAC,CAAC,CAAC,CAAC,GAAG,CAAC,IAAI,CAAC,EAAE,GAAG,CAAC,CAAC,GAAG,CAAC,IAAI,CAAC,CAAC,IAAI,CAAC,CAAC,GAAG,CAAC,CAAC,CAAC,GAAG,CAAC,CAAC,GAAG,IAAI,CAAC,CAAC,GAAG,MAAM,CAAC,CAAC,OAAO,CAAC,CAAC,CAAC,CAAC,CAAC;IACzJ,KAAK,CAAC,IAAI,CAAC,GAAG,CAAC,GAAG,EAAE,EAAE;QACpB,MAAM,EAAE,GAAG,GAAG,CAAC,SAAS,EAAE,CAAC;QAC3B,GAAG,CAAC,GAAG,CAAC,KAAK,CAAC,EAAE,EAAE,GAAG,CAAC,IAAI,CAAC,CAAC,CAAC,CAAC;QAC9B,GAAG,CAAC,IAAI,CAAC,EAAE,GAAG,CAAC,CAAC,GAAG,CAAC,IAAI,CAAC,CAAC,IAAI,CAAC,CAAC,GAAG,CAAC,CAAC,EAAE,GAAG,CAAC,CAAC,GAAG,IAAI,CAAC,CAAC,GAAG,MAAM,CAAC;QAC/D,OAAO,EAAE,CAAC;IACZ,CAAC,CAAC;IAEF,WAAW;IACX,KAAK,CAAC,IAAI,CAAC,GAAG,CAAC,GAAG,EAAE,EAAE,GAAG,GAAG,CAAC,IAAI,CAAC,EAAE,GAAG,GAAG,CAAC,SAAS,EAAE,CAAC,CAAC,OAAO,EAAE,CAAC,CAAC,CAAC,CAAC;IACrE,KAAK,CAAC,IAAI,CAAC,GAAG,CAAC,GAAG,EAAE,EAAE,GAAG,GAAG,CAAC,IAAI,CAAC,EAAE,GAAG,GAAG,CAAC,SAAS,EAAE,CAAC,CAAC,OAAO,EAAE,CAAC,CAAC,CAAC,CAAC;IACrE,KAAK,CAAC,IAAI,CAAC,GAAG,CAAC,GAAG,EAAE,EAAE,GAAG,IAAI,CAAC,OAAO,CAAC,GAAG,CAAC,IAAI,EAAE,GAAG,CAAC,SAAS,EAAE,CAAC,CAAC,CAAC,OAAO,EAAE,CAAC,CAAC,CAAC,CAAC;IAC/E,KAAK,CAAC,IAAI,CAAC,GAAG,CAAC,GAAG,EAAE,EAAE,GAAG,GAAG,CAAC,IAAI,CAAC,EAAE,GAAG,GAAG,CAAC,SAAS,EAAE,CAAC,CAAC,OAAO,EAAE,CAAC,CAAC,CAAC,CAAC;IAErE,0CAA0C;IAC1C,KAAK,CAAC,IAAI,CAAC,GAAG,CAAC,GAAG,EAAE,EAAE;QACpB,MAAM,EAAE,GAAG,GAAG,CAAC,SAAS,EAAE,CAAC;QAC3B,OAAO,CAAC,GAAG,EAAE,EAAE,EAAE,IAAI,CAAC,OAAO,CAAC,GAAG,CAAC,IAAI,CAAC,CAAC,CAAC;QACzC,GAAG,CAAC,IAAI,CAAC,EAAE,GAAG,GAAG,CAAC,EAAE,GAAG,CAAC,CAAC,CAAC;QAC1B,OAAO,EAAE,CAAC;IACZ,CAAC,CAAC;IACF,KAAK,CAAC,IAAI,CAAC,GAAG,CAAC,GAAG,EAAE,EAAE;QACpB,MAAM,EAAE,GAAG,GAAG,CAAC,SAAS,EAAE,CAAC;QAC3B,IAAI,CAAC,OAAO,CAAC,GAAG,CAAC,IAAI,EAAE,MAAM,CAAC,GAAG,EAAE,EAAE,CAAC,CAAC,CAAC;QACxC,GAAG,CAAC,IAAI,CAAC,EAAE,GAAG,GAAG,CAAC,EAAE,GAAG,CAAC,CAAC,CAAC;QAC1B,OAAO,EAAE,CAAC;IACZ,CAAC,CAAC;IAEF,iCAAiC;IACjC,KAAK,CAAC,IAAI,CAAC,GAAG,CAAC,GAAG,EAAE,EAAE,GAAG,GAAG,CAAC,IAAI,CAAC,EAAE,GAAG,IAAI,CAAC,OAAO,CAAC,GAAG,CAAC,IAAI,CAAC,CAAC,CAAC,OAAO,CAAC,CAAC,CAAC,CAAC,CAAC;AAC7E,CAAC"}

package/dist/cpu/z80/instructions/rotate.d.ts

@@ -0,0 +1,9 @@
+import type { Z80Handler, IndexView } from '../types.js';
+/**
+ * Accumulator rotates RLCA/RRCA/RLA/RRA (0x07/0x0F/0x17/0x1F).
+ * Unlike the CB-prefixed rotates, these affect only H, N, C, and the
+ * undocumented X/Y (copied from the new A); S, Z, PV are left untouched.
+ * Not view-dependent, but they live in the main table so are registered per view.
+ */
+export declare function registerRotate(table: Z80Handler[], _view: IndexView): void;
+//# sourceMappingURL=rotate.d.ts.map

package/dist/cpu/z80/instructions/rotate.d.ts.map

@@ -0,0 +1 @@
+{"version":3,"file":"rotate.d.ts","sourceRoot":"","sources":["../../../../src/cpu/z80/instructions/rotate.ts"],"names":[],"mappings":"AAAA,OAAO,KAAK,EAAE,UAAU,EAAE,SAAS,EAAE,MAAM,aAAa,CAAC;AAGzD;;;;;GAKG;AACH,wBAAgB,cAAc,CAAC,KAAK,EAAE,UAAU,EAAE,EAAE,KAAK,EAAE,SAAS,GAAG,IAAI,CA4C1E"}

package/dist/cpu/z80/instructions/rotate.js

@@ -0,0 +1,48 @@
+/**
+ * Accumulator rotates RLCA/RRCA/RLA/RRA (0x07/0x0F/0x17/0x1F).
+ * Unlike the CB-prefixed rotates, these affect only H, N, C, and the
+ * undocumented X/Y (copied from the new A); S, Z, PV are left untouched.
+ * Not view-dependent, but they live in the main table so are registered per view.
+ */
+export function registerRotate(table, _view) {
+    const finish = (f, a, carry) => {
+        f.c = carry !== 0;
+        f.h = false;
+        f.n = false;
+        f.y = (a & 0x20) !== 0;
+        f.x = (a & 0x08) !== 0;
+    };
+    // RLCA
+    table[0x07] = (cpu) => {
+        const a = cpu.regs.a;
+        const c = (a >> 7) & 1;
+        cpu.regs.a = ((a << 1) | c) & 0xff;
+        finish(cpu.flags, cpu.regs.a, c);
+        return 4;
+    };
+    // RRCA
+    table[0x0f] = (cpu) => {
+        const a = cpu.regs.a;
+        const c = a & 1;
+        cpu.regs.a = ((a >> 1) | (c << 7)) & 0xff;
+        finish(cpu.flags, cpu.regs.a, c);
+        return 4;
+    };
+    // RLA (rotate left through carry)
+    table[0x17] = (cpu) => {
+        const a = cpu.regs.a;
+        const c = (a >> 7) & 1;
+        cpu.regs.a = ((a << 1) | (cpu.flags.c ? 1 : 0)) & 0xff;
+        finish(cpu.flags, cpu.regs.a, c);
+        return 4;
+    };
+    // RRA (rotate right through carry)
+    table[0x1f] = (cpu) => {
+        const a = cpu.regs.a;
+        const c = a & 1;
+        cpu.regs.a = ((a >> 1) | (cpu.flags.c ? 0x80 : 0)) & 0xff;
+        finish(cpu.flags, cpu.regs.a, c);
+        return 4;
+    };
+}
+//# sourceMappingURL=rotate.js.map

package/dist/cpu/z80/instructions/rotate.js.map

@@ -0,0 +1 @@
+{"version":3,"file":"rotate.js","sourceRoot":"","sources":["../../../../src/cpu/z80/instructions/rotate.ts"],"names":[],"mappings":"AAGA;;;;;GAKG;AACH,MAAM,UAAU,cAAc,CAAC,KAAmB,EAAE,KAAgB;IAClE,MAAM,MAAM,GAAG,CAAC,CAAW,EAAE,CAAS,EAAE,KAAa,EAAQ,EAAE;QAC7D,CAAC,CAAC,CAAC,GAAG,KAAK,KAAK,CAAC,CAAC;QAClB,CAAC,CAAC,CAAC,GAAG,KAAK,CAAC;QACZ,CAAC,CAAC,CAAC,GAAG,KAAK,CAAC;QACZ,CAAC,CAAC,CAAC,GAAG,CAAC,CAAC,GAAG,IAAI,CAAC,KAAK,CAAC,CAAC;QACvB,CAAC,CAAC,CAAC,GAAG,CAAC,CAAC,GAAG,IAAI,CAAC,KAAK,CAAC,CAAC;IACzB,CAAC,CAAC;IAEF,OAAO;IACP,KAAK,CAAC,IAAI,CAAC,GAAG,CAAC,GAAG,EAAE,EAAE;QACpB,MAAM,CAAC,GAAG,GAAG,CAAC,IAAI,CAAC,CAAC,CAAC;QACrB,MAAM,CAAC,GAAG,CAAC,CAAC,IAAI,CAAC,CAAC,GAAG,CAAC,CAAC;QACvB,GAAG,CAAC,IAAI,CAAC,CAAC,GAAG,CAAC,CAAC,CAAC,IAAI,CAAC,CAAC,GAAG,CAAC,CAAC,GAAG,IAAI,CAAC;QACnC,MAAM,CAAC,GAAG,CAAC,KAAK,EAAE,GAAG,CAAC,IAAI,CAAC,CAAC,EAAE,CAAC,CAAC,CAAC;QACjC,OAAO,CAAC,CAAC;IACX,CAAC,CAAC;IAEF,OAAO;IACP,KAAK,CAAC,IAAI,CAAC,GAAG,CAAC,GAAG,EAAE,EAAE;QACpB,MAAM,CAAC,GAAG,GAAG,CAAC,IAAI,CAAC,CAAC,CAAC;QACrB,MAAM,CAAC,GAAG,CAAC,GAAG,CAAC,CAAC;QAChB,GAAG,CAAC,IAAI,CAAC,CAAC,GAAG,CAAC,CAAC,CAAC,IAAI,CAAC,CAAC,GAAG,CAAC,CAAC,IAAI,CAAC,CAAC,CAAC,GAAG,IAAI,CAAC;QAC1C,MAAM,CAAC,GAAG,CAAC,KAAK,EAAE,GAAG,CAAC,IAAI,CAAC,CAAC,EAAE,CAAC,CAAC,CAAC;QACjC,OAAO,CAAC,CAAC;IACX,CAAC,CAAC;IAEF,kCAAkC;IAClC,KAAK,CAAC,IAAI,CAAC,GAAG,CAAC,GAAG,EAAE,EAAE;QACpB,MAAM,CAAC,GAAG,GAAG,CAAC,IAAI,CAAC,CAAC,CAAC;QACrB,MAAM,CAAC,GAAG,CAAC,CAAC,IAAI,CAAC,CAAC,GAAG,CAAC,CAAC;QACvB,GAAG,CAAC,IAAI,CAAC,CAAC,GAAG,CAAC,CAAC,CAAC,IAAI,CAAC,CAAC,GAAG,CAAC,GAAG,CAAC,KAAK,CAAC,CAAC,CAAC,CAAC,CAAC,CAAC,CAAC,CAAC,CAAC,CAAC,CAAC,CAAC,GAAG,IAAI,CAAC;QACvD,MAAM,CAAC,GAAG,CAAC,KAAK,EAAE,GAAG,CAAC,IAAI,CAAC,CAAC,EAAE,CAAC,CAAC,CAAC;QACjC,OAAO,CAAC,CAAC;IACX,CAAC,CAAC;IAEF,mCAAmC;IACnC,KAAK,CAAC,IAAI,CAAC,GAAG,CAAC,GAAG,EAAE,EAAE;QACpB,MAAM,CAAC,GAAG,GAAG,CAAC,IAAI,CAAC,CAAC,CAAC;QACrB,MAAM,CAAC,GAAG,CAAC,GAAG,CAAC,CAAC;QAChB,GAAG,CAAC,IAAI,CAAC,CAAC,GAAG,CAAC,CAAC,CAAC,IAAI,CAAC,CAAC,GAAG,CAAC,GAAG,CAAC,KAAK,CAAC,CAAC,CAAC,CAAC,CAAC,IAAI,CAAC,CAAC,CAAC,CAAC,CAAC,CAAC,GAAG,IAAI,CAAC;QAC1D,MAAM,CAAC,GAAG,CAAC,KAAK,EAAE,GAAG,CAAC,IAAI,CAAC,CAAC,EAAE,CAAC,CAAC,CAAC;QACjC,OAAO,CAAC,CAAC;IACX,CAAC,CAAC;AACJ,CAAC"}

package/dist/cpu/z80/instructions/stack.d.ts

@@ -0,0 +1,4 @@
+import type { Z80Handler, IndexView } from '../types.js';
+/** PUSH / POP for BC, DE, HL/IX/IY, and AF (view-parameterized). */
+export declare function registerStack(table: Z80Handler[], view: IndexView): void;
+//# sourceMappingURL=stack.d.ts.map

package/dist/cpu/z80/instructions/stack.d.ts.map

@@ -0,0 +1 @@
+{"version":3,"file":"stack.d.ts","sourceRoot":"","sources":["../../../../src/cpu/z80/instructions/stack.ts"],"names":[],"mappings":"AAAA,OAAO,KAAK,EAAE,UAAU,EAAE,SAAS,EAAE,MAAM,aAAa,CAAC;AAEzD,oEAAoE;AACpE,wBAAgB,aAAa,CAAC,KAAK,EAAE,UAAU,EAAE,EAAE,IAAI,EAAE,SAAS,GAAG,IAAI,CAiBxE"}

package/dist/cpu/z80/instructions/stack.js

@@ -0,0 +1,19 @@
+/** PUSH / POP for BC, DE, HL/IX/IY, and AF (view-parameterized). */
+export function registerStack(table, view) {
+    // PUSH rr
+    table[0xc5] = (cpu) => { cpu.push16(cpu.regs.bc); return 11; };
+    table[0xd5] = (cpu) => { cpu.push16(cpu.regs.de); return 11; };
+    table[0xe5] = (cpu) => { cpu.push16(view.getPair(cpu.regs)); return 11; };
+    table[0xf5] = (cpu) => { cpu.push16((cpu.regs.a << 8) | cpu.flags.toByte()); return 11; };
+    // POP rr
+    table[0xc1] = (cpu) => { cpu.regs.bc = cpu.pop16(); return 10; };
+    table[0xd1] = (cpu) => { cpu.regs.de = cpu.pop16(); return 10; };
+    table[0xe1] = (cpu) => { view.setPair(cpu.regs, cpu.pop16()); return 10; };
+    table[0xf1] = (cpu) => {
+        const v = cpu.pop16();
+        cpu.regs.a = (v >> 8) & 0xff;
+        cpu.flags.fromByte(v & 0xff);
+        return 10;
+    };
+}
+//# sourceMappingURL=stack.js.map

package/dist/cpu/z80/instructions/stack.js.map

@@ -0,0 +1 @@
+{"version":3,"file":"stack.js","sourceRoot":"","sources":["../../../../src/cpu/z80/instructions/stack.ts"],"names":[],"mappings":"AAEA,oEAAoE;AACpE,MAAM,UAAU,aAAa,CAAC,KAAmB,EAAE,IAAe;IAChE,UAAU;IACV,KAAK,CAAC,IAAI,CAAC,GAAG,CAAC,GAAG,EAAE,EAAE,GAAG,GAAG,CAAC,MAAM,CAAC,GAAG,CAAC,IAAI,CAAC,EAAE,CAAC,CAAC,CAAC,OAAO,EAAE,CAAC,CAAC,CAAC,CAAC;IAC/D,KAAK,CAAC,IAAI,CAAC,GAAG,CAAC,GAAG,EAAE,EAAE,GAAG,GAAG,CAAC,MAAM,CAAC,GAAG,CAAC,IAAI,CAAC,EAAE,CAAC,CAAC,CAAC,OAAO,EAAE,CAAC,CAAC,CAAC,CAAC;IAC/D,KAAK,CAAC,IAAI,CAAC,GAAG,CAAC,GAAG,EAAE,EAAE,GAAG,GAAG,CAAC,MAAM,CAAC,IAAI,CAAC,OAAO,CAAC,GAAG,CAAC,IAAI,CAAC,CAAC,CAAC,CAAC,OAAO,EAAE,CAAC,CAAC,CAAC,CAAC;IAC1E,KAAK,CAAC,IAAI,CAAC,GAAG,CAAC,GAAG,EAAE,EAAE,GAAG,GAAG,CAAC,MAAM,CAAC,CAAC,GAAG,CAAC,IAAI,CAAC,CAAC,IAAI,CAAC,CAAC,GAAG,GAAG,CAAC,KAAK,CAAC,MAAM,EAAE,CAAC,CAAC,CAAC,OAAO,EAAE,CAAC,CAAC,CAAC,CAAC;IAE1F,SAAS;IACT,KAAK,CAAC,IAAI,CAAC,GAAG,CAAC,GAAG,EAAE,EAAE,GAAG,GAAG,CAAC,IAAI,CAAC,EAAE,GAAG,GAAG,CAAC,KAAK,EAAE,CAAC,CAAC,OAAO,EAAE,CAAC,CAAC,CAAC,CAAC;IACjE,KAAK,CAAC,IAAI,CAAC,GAAG,CAAC,GAAG,EAAE,EAAE,GAAG,GAAG,CAAC,IAAI,CAAC,EAAE,GAAG,GAAG,CAAC,KAAK,EAAE,CAAC,CAAC,OAAO,EAAE,CAAC,CAAC,CAAC,CAAC;IACjE,KAAK,CAAC,IAAI,CAAC,GAAG,CAAC,GAAG,EAAE,EAAE,GAAG,IAAI,CAAC,OAAO,CAAC,GAAG,CAAC,IAAI,EAAE,GAAG,CAAC,KAAK,EAAE,CAAC,CAAC,CAAC,OAAO,EAAE,CAAC,CAAC,CAAC,CAAC;IAC3E,KAAK,CAAC,IAAI,CAAC,GAAG,CAAC,GAAG,EAAE,EAAE;QACpB,MAAM,CAAC,GAAG,GAAG,CAAC,KAAK,EAAE,CAAC;QACtB,GAAG,CAAC,IAAI,CAAC,CAAC,GAAG,CAAC,CAAC,IAAI,CAAC,CAAC,GAAG,IAAI,CAAC;QAC7B,GAAG,CAAC,KAAK,CAAC,QAAQ,CAAC,CAAC,GAAG,IAAI,CAAC,CAAC;QAC7B,OAAO,EAAE,CAAC;IACZ,CAAC,CAAC;AACJ,CAAC"}

package/dist/cpu/z80/regcodes.d.ts

@@ -0,0 +1,22 @@
+import type { RegistersZ80 } from './RegistersZ80.js';
+import type { IndexView } from './types.js';
+/**
+ * 8-bit register access by the 3-bit opcode field (B,C,D,E,H,L,(HL),A).
+ * Code 6 is the memory operand and is handled by callers (via {@link IndexView.memAddr}),
+ * never by these helpers.
+ *
+ * In an IX/IY view, codes 4 and 5 map to IXH/IXL (or IYH/IYL) — EXCEPT when the
+ * instruction also has a memory operand (an `LD r,(IX+d)` form), in which case H
+ * and L stay real. Those cases use the `*Real*` variants.
+ */
+/** Read register `code` honoring the index view for H/L (→ IXH/IXL). */
+export declare function getR(regs: RegistersZ80, view: IndexView, code: number): number;
+/** Write register `code` honoring the index view for H/L. */
+export declare function setR(regs: RegistersZ80, view: IndexView, code: number, v: number): void;
+/** Read register `code` using the real H/L (never index-substituted). */
+export declare function getRealR(regs: RegistersZ80, code: number): number;
+/** Write register `code` using the real H/L. */
+export declare function setRealR(regs: RegistersZ80, code: number, v: number): void;
+/** Human-readable operand name for debugging/tests. */
+export declare const REG_NAMES: readonly ["B", "C", "D", "E", "H", "L", "(HL)", "A"];
+//# sourceMappingURL=regcodes.d.ts.map

package/dist/cpu/z80/regcodes.d.ts.map

@@ -0,0 +1 @@
+{"version":3,"file":"regcodes.d.ts","sourceRoot":"","sources":["../../../src/cpu/z80/regcodes.ts"],"names":[],"mappings":"AAAA,OAAO,KAAK,EAAE,YAAY,EAAE,MAAM,mBAAmB,CAAC;AACtD,OAAO,KAAK,EAAE,SAAS,EAAE,MAAM,YAAY,CAAC;AAE5C;;;;;;;;GAQG;AAEH,wEAAwE;AACxE,wBAAgB,IAAI,CAAC,IAAI,EAAE,YAAY,EAAE,IAAI,EAAE,SAAS,EAAE,IAAI,EAAE,MAAM,GAAG,MAAM,CAW9E;AAED,6DAA6D;AAC7D,wBAAgB,IAAI,CAAC,IAAI,EAAE,YAAY,EAAE,IAAI,EAAE,SAAS,EAAE,IAAI,EAAE,MAAM,EAAE,CAAC,EAAE,MAAM,GAAG,IAAI,CAYvF;AAED,yEAAyE;AACzE,wBAAgB,QAAQ,CAAC,IAAI,EAAE,YAAY,EAAE,IAAI,EAAE,MAAM,GAAG,MAAM,CAWjE;AAED,gDAAgD;AAChD,wBAAgB,QAAQ,CAAC,IAAI,EAAE,YAAY,EAAE,IAAI,EAAE,MAAM,EAAE,CAAC,EAAE,MAAM,GAAG,IAAI,CAW1E;AAED,uDAAuD;AACvD,eAAO,MAAM,SAAS,sDAAuD,CAAC"}

package/dist/cpu/z80/regcodes.js

@@ -0,0 +1,93 @@
+/**
+ * 8-bit register access by the 3-bit opcode field (B,C,D,E,H,L,(HL),A).
+ * Code 6 is the memory operand and is handled by callers (via {@link IndexView.memAddr}),
+ * never by these helpers.
+ *
+ * In an IX/IY view, codes 4 and 5 map to IXH/IXL (or IYH/IYL) — EXCEPT when the
+ * instruction also has a memory operand (an `LD r,(IX+d)` form), in which case H
+ * and L stay real. Those cases use the `*Real*` variants.
+ */
+/** Read register `code` honoring the index view for H/L (→ IXH/IXL). */
+export function getR(regs, view, code) {
+    switch (code) {
+        case 0: return regs.b;
+        case 1: return regs.c;
+        case 2: return regs.d;
+        case 3: return regs.e;
+        case 4: return view.getHi(regs);
+        case 5: return view.getLo(regs);
+        case 7: return regs.a;
+        default: return 0; // code 6 (memory) handled by caller
+    }
+}
+/** Write register `code` honoring the index view for H/L. */
+export function setR(regs, view, code, v) {
+    const b = v & 0xff;
+    switch (code) {
+        case 0:
+            regs.b = b;
+            break;
+        case 1:
+            regs.c = b;
+            break;
+        case 2:
+            regs.d = b;
+            break;
+        case 3:
+            regs.e = b;
+            break;
+        case 4:
+            view.setHi(regs, b);
+            break;
+        case 5:
+            view.setLo(regs, b);
+            break;
+        case 7:
+            regs.a = b;
+            break;
+        // code 6 handled by caller
+    }
+}
+/** Read register `code` using the real H/L (never index-substituted). */
+export function getRealR(regs, code) {
+    switch (code) {
+        case 0: return regs.b;
+        case 1: return regs.c;
+        case 2: return regs.d;
+        case 3: return regs.e;
+        case 4: return regs.h;
+        case 5: return regs.l;
+        case 7: return regs.a;
+        default: return 0;
+    }
+}
+/** Write register `code` using the real H/L. */
+export function setRealR(regs, code, v) {
+    const b = v & 0xff;
+    switch (code) {
+        case 0:
+            regs.b = b;
+            break;
+        case 1:
+            regs.c = b;
+            break;
+        case 2:
+            regs.d = b;
+            break;
+        case 3:
+            regs.e = b;
+            break;
+        case 4:
+            regs.h = b;
+            break;
+        case 5:
+            regs.l = b;
+            break;
+        case 7:
+            regs.a = b;
+            break;
+    }
+}
+/** Human-readable operand name for debugging/tests. */
+export const REG_NAMES = ['B', 'C', 'D', 'E', 'H', 'L', '(HL)', 'A'];
+//# sourceMappingURL=regcodes.js.map

package/dist/cpu/z80/regcodes.js.map

@@ -0,0 +1 @@
+{"version":3,"file":"regcodes.js","sourceRoot":"","sources":["../../../src/cpu/z80/regcodes.ts"],"names":[],"mappings":"AAGA;;;;;;;;GAQG;AAEH,wEAAwE;AACxE,MAAM,UAAU,IAAI,CAAC,IAAkB,EAAE,IAAe,EAAE,IAAY;IACpE,QAAQ,IAAI,EAAE,CAAC;QACb,KAAK,CAAC,CAAC,CAAC,OAAO,IAAI,CAAC,CAAC,CAAC;QACtB,KAAK,CAAC,CAAC,CAAC,OAAO,IAAI,CAAC,CAAC,CAAC;QACtB,KAAK,CAAC,CAAC,CAAC,OAAO,IAAI,CAAC,CAAC,CAAC;QACtB,KAAK,CAAC,CAAC,CAAC,OAAO,IAAI,CAAC,CAAC,CAAC;QACtB,KAAK,CAAC,CAAC,CAAC,OAAO,IAAI,CAAC,KAAK,CAAC,IAAI,CAAC,CAAC;QAChC,KAAK,CAAC,CAAC,CAAC,OAAO,IAAI,CAAC,KAAK,CAAC,IAAI,CAAC,CAAC;QAChC,KAAK,CAAC,CAAC,CAAC,OAAO,IAAI,CAAC,CAAC,CAAC;QACtB,OAAO,CAAC,CAAC,OAAO,CAAC,CAAC,CAAC,oCAAoC;IACzD,CAAC;AACH,CAAC;AAED,6DAA6D;AAC7D,MAAM,UAAU,IAAI,CAAC,IAAkB,EAAE,IAAe,EAAE,IAAY,EAAE,CAAS;IAC/E,MAAM,CAAC,GAAG,CAAC,GAAG,IAAI,CAAC;IACnB,QAAQ,IAAI,EAAE,CAAC;QACb,KAAK,CAAC;YAAE,IAAI,CAAC,CAAC,GAAG,CAAC,CAAC;YAAC,MAAM;QAC1B,KAAK,CAAC;YAAE,IAAI,CAAC,CAAC,GAAG,CAAC,CAAC;YAAC,MAAM;QAC1B,KAAK,CAAC;YAAE,IAAI,CAAC,CAAC,GAAG,CAAC,CAAC;YAAC,MAAM;QAC1B,KAAK,CAAC;YAAE,IAAI,CAAC,CAAC,GAAG,CAAC,CAAC;YAAC,MAAM;QAC1B,KAAK,CAAC;YAAE,IAAI,CAAC,KAAK,CAAC,IAAI,EAAE,CAAC,CAAC,CAAC;YAAC,MAAM;QACnC,KAAK,CAAC;YAAE,IAAI,CAAC,KAAK,CAAC,IAAI,EAAE,CAAC,CAAC,CAAC;YAAC,MAAM;QACnC,KAAK,CAAC;YAAE,IAAI,CAAC,CAAC,GAAG,CAAC,CAAC;YAAC,MAAM;QAC1B,2BAA2B;IAC7B,CAAC;AACH,CAAC;AAED,yEAAyE;AACzE,MAAM,UAAU,QAAQ,CAAC,IAAkB,EAAE,IAAY;IACvD,QAAQ,IAAI,EAAE,CAAC;QACb,KAAK,CAAC,CAAC,CAAC,OAAO,IAAI,CAAC,CAAC,CAAC;QACtB,KAAK,CAAC,CAAC,CAAC,OAAO,IAAI,CAAC,CAAC,CAAC;QACtB,KAAK,CAAC,CAAC,CAAC,OAAO,IAAI,CAAC,CAAC,CAAC;QACtB,KAAK,CAAC,CAAC,CAAC,OAAO,IAAI,CAAC,CAAC,CAAC;QACtB,KAAK,CAAC,CAAC,CAAC,OAAO,IAAI,CAAC,CAAC,CAAC;QACtB,KAAK,CAAC,CAAC,CAAC,OAAO,IAAI,CAAC,CAAC,CAAC;QACtB,KAAK,CAAC,CAAC,CAAC,OAAO,IAAI,CAAC,CAAC,CAAC;QACtB,OAAO,CAAC,CAAC,OAAO,CAAC,CAAC;IACpB,CAAC;AACH,CAAC;AAED,gDAAgD;AAChD,MAAM,UAAU,QAAQ,CAAC,IAAkB,EAAE,IAAY,EAAE,CAAS;IAClE,MAAM,CAAC,GAAG,CAAC,GAAG,IAAI,CAAC;IACnB,QAAQ,IAAI,EAAE,CAAC;QACb,KAAK,CAAC;YAAE,IAAI,CAAC,CAAC,GAAG,CAAC,CAAC;YAAC,MAAM;QAC1B,KAAK,CAAC;YAAE,IAAI,CAAC,CAAC,GAAG,CAAC,CAAC;YAAC,MAAM;QAC1B,KAAK,CAAC;YAAE,IAAI,CAAC,CAAC,GAAG,CAAC,CAAC;YAAC,MAAM;QAC1B,KAAK,CAAC;YAAE,IAAI,CAAC,CAAC,GAAG,CAAC,CAAC;YAAC,MAAM;QAC1B,KAAK,CAAC;YAAE,IAAI,CAAC,CAAC,GAAG,CAAC,CAAC;YAAC,MAAM;QAC1B,KAAK,CAAC;YAAE,IAAI,CAAC,CAAC,GAAG,CAAC,CAAC;YAAC,MAAM;QAC1B,KAAK,CAAC;YAAE,IAAI,CAAC,CAAC,GAAG,CAAC,CAAC;YAAC,MAAM;IAC5B,CAAC;AACH,CAAC;AAED,uDAAuD;AACvD,MAAM,CAAC,MAAM,SAAS,GAAG,CAAC,GAAG,EAAE,GAAG,EAAE,GAAG,EAAE,GAAG,EAAE,GAAG,EAAE,GAAG,EAAE,MAAM,EAAE,GAAG,CAAU,CAAC"}

package/dist/cpu/z80/types.d.ts

@@ -0,0 +1,59 @@
+import type { IBus } from '../../interfaces/IBus.js';
+import type { RegistersZ80 } from './RegistersZ80.js';
+import type { FlagsZ80 } from './FlagsZ80.js';
+/**
+ * The core surface that instruction handlers operate on. {@link CpuZ80}
+ * implements it. Instruction tables import only this interface (never CpuZ80),
+ * keeping the dependency graph acyclic.
+ */
+export interface Z80Core {
+    readonly regs: RegistersZ80;
+    readonly flags: FlagsZ80;
+    readonly bus: IBus;
+    iff1: boolean;
+    iff2: boolean;
+    im: 0 | 1 | 2;
+    pendingEI: boolean;
+    halted: boolean;
+    /** Read the byte at PC and advance PC (a normal operand fetch — no R increment). */
+    fetchByte(): number;
+    /** Read a little-endian word at PC and advance PC by 2. */
+    fetchWord(): number;
+    /** Push a 16-bit value (SP -= 2, little-endian). */
+    push16(v: number): void;
+    /** Pop a 16-bit value (SP += 2). */
+    pop16(): number;
+}
+/** An instruction handler: mutates core state, returns T-states from the opcode byte onward. */
+export type Z80Handler = (cpu: Z80Core) => number;
+/** A DDCB/FDCB handler: the effective address is precomputed by the dispatcher. */
+export type Z80IndexedCbHandler = (cpu: Z80Core, addr: number) => number;
+/**
+ * Parameterizes the main instruction table over the active 16-bit pointer:
+ * HL (unprefixed), IX (DD prefix), or IY (FD prefix). The same registration
+ * factories build all three tables, so undocumented IXH/IXL/IYH/IYL forms and
+ * the (IX+d)/(IY+d) memory forms fall out automatically.
+ */
+export interface IndexView {
+    readonly kind: 'hl' | 'ix' | 'iy';
+    /** True for the IX/IY views. */
+    readonly indexed: boolean;
+    /** Extra T-states an indexed memory access adds over the HL form (0 for hl, 8 for ix/iy). */
+    readonly memExtra: number;
+    /** The active 16-bit pointer pair (HL / IX / IY). */
+    getPair(r: RegistersZ80): number;
+    setPair(r: RegistersZ80, v: number): void;
+    /** High byte of the pointer (H / IXH / IYH) — the "displaced" register operand. */
+    getHi(r: RegistersZ80): number;
+    setHi(r: RegistersZ80, v: number): void;
+    /** Low byte of the pointer (L / IXL / IYL). */
+    getLo(r: RegistersZ80): number;
+    setLo(r: RegistersZ80, v: number): void;
+    /**
+     * Effective memory address for (HL) / (IX+d) / (IY+d). For indexed views this
+     * fetches the displacement byte (advancing PC) and sets WZ to the computed
+     * address. Call at most once per instruction.
+     */
+    memAddr(cpu: Z80Core): number;
+}
+//# sourceMappingURL=types.d.ts.map

package/dist/cpu/z80/types.d.ts.map

@@ -0,0 +1 @@
+{"version":3,"file":"types.d.ts","sourceRoot":"","sources":["../../../src/cpu/z80/types.ts"],"names":[],"mappings":"AAAA,OAAO,KAAK,EAAE,IAAI,EAAE,MAAM,0BAA0B,CAAC;AACrD,OAAO,KAAK,EAAE,YAAY,EAAE,MAAM,mBAAmB,CAAC;AACtD,OAAO,KAAK,EAAE,QAAQ,EAAE,MAAM,eAAe,CAAC;AAE9C;;;;GAIG;AACH,MAAM,WAAW,OAAO;IACtB,QAAQ,CAAC,IAAI,EAAE,YAAY,CAAC;IAC5B,QAAQ,CAAC,KAAK,EAAE,QAAQ,CAAC;IACzB,QAAQ,CAAC,GAAG,EAAE,IAAI,CAAC;IAEnB,IAAI,EAAE,OAAO,CAAC;IACd,IAAI,EAAE,OAAO,CAAC;IACd,EAAE,EAAE,CAAC,GAAG,CAAC,GAAG,CAAC,CAAC;IACd,SAAS,EAAE,OAAO,CAAC;IACnB,MAAM,EAAE,OAAO,CAAC;IAEhB,oFAAoF;IACpF,SAAS,IAAI,MAAM,CAAC;IACpB,2DAA2D;IAC3D,SAAS,IAAI,MAAM,CAAC;IACpB,oDAAoD;IACpD,MAAM,CAAC,CAAC,EAAE,MAAM,GAAG,IAAI,CAAC;IACxB,oCAAoC;IACpC,KAAK,IAAI,MAAM,CAAC;CACjB;AAED,gGAAgG;AAChG,MAAM,MAAM,UAAU,GAAG,CAAC,GAAG,EAAE,OAAO,KAAK,MAAM,CAAC;AAElD,mFAAmF;AACnF,MAAM,MAAM,mBAAmB,GAAG,CAAC,GAAG,EAAE,OAAO,EAAE,IAAI,EAAE,MAAM,KAAK,MAAM,CAAC;AAEzE;;;;;GAKG;AACH,MAAM,WAAW,SAAS;IACxB,QAAQ,CAAC,IAAI,EAAE,IAAI,GAAG,IAAI,GAAG,IAAI,CAAC;IAClC,gCAAgC;IAChC,QAAQ,CAAC,OAAO,EAAE,OAAO,CAAC;IAC1B,6FAA6F;IAC7F,QAAQ,CAAC,QAAQ,EAAE,MAAM,CAAC;IAE1B,qDAAqD;IACrD,OAAO,CAAC,CAAC,EAAE,YAAY,GAAG,MAAM,CAAC;IACjC,OAAO,CAAC,CAAC,EAAE,YAAY,EAAE,CAAC,EAAE,MAAM,GAAG,IAAI,CAAC;IAE1C,mFAAmF;IACnF,KAAK,CAAC,CAAC,EAAE,YAAY,GAAG,MAAM,CAAC;IAC/B,KAAK,CAAC,CAAC,EAAE,YAAY,EAAE,CAAC,EAAE,MAAM,GAAG,IAAI,CAAC;IACxC,+CAA+C;IAC/C,KAAK,CAAC,CAAC,EAAE,YAAY,GAAG,MAAM,CAAC;IAC/B,KAAK,CAAC,CAAC,EAAE,YAAY,EAAE,CAAC,EAAE,MAAM,GAAG,IAAI,CAAC;IAExC;;;;OAIG;IACH,OAAO,CAAC,GAAG,EAAE,OAAO,GAAG,MAAM,CAAC;CAC/B"}

package/dist/cpu/z80/types.js

@@ -0,0 +1,2 @@
+export {};
+//# sourceMappingURL=types.js.map

package/dist/cpu/z80/types.js.map

@@ -0,0 +1 @@
+{"version":3,"file":"types.js","sourceRoot":"","sources":["../../../src/cpu/z80/types.ts"],"names":[],"mappings":""}

package/dist/cpu/z80/views.d.ts

@@ -0,0 +1,8 @@
+import type { IndexView } from './types.js';
+/** Sign-extend an 8-bit displacement to a signed JS number. */
+export declare function sext8(b: number): number;
+/** HL view — the unprefixed instruction table. */
+export declare const HL_VIEW: IndexView;
+export declare const IX_VIEW: IndexView;
+export declare const IY_VIEW: IndexView;
+//# sourceMappingURL=views.d.ts.map

package/dist/cpu/z80/views.d.ts.map

@@ -0,0 +1 @@
+{"version":3,"file":"views.d.ts","sourceRoot":"","sources":["../../../src/cpu/z80/views.ts"],"names":[],"mappings":"AACA,OAAO,KAAK,EAAE,SAAS,EAAW,MAAM,YAAY,CAAC;AAErD,+DAA+D;AAC/D,wBAAgB,KAAK,CAAC,CAAC,EAAE,MAAM,GAAG,MAAM,CAEvC;AAED,kDAAkD;AAClD,eAAO,MAAM,OAAO,EAAE,SAYrB,CAAC;AA8BF,eAAO,MAAM,OAAO,EAAE,SAQrB,CAAC;AAEF,eAAO,MAAM,OAAO,EAAE,SAQrB,CAAC"}