@joezilla/8sim 0.10.0

package/dist/cpu/z80/instructions/bits.js

@@ -0,0 +1,164 @@
+import { setSzyxp } from '../flagHelpers.js';
+import { getRealR, setRealR } from '../regcodes.js';
+/** Apply rotate/shift `kind` (0=RLC..7=SRL) to v, set flags, return result. */
+function rotShift(f, kind, v) {
+    let c = 0;
+    let r = 0;
+    switch (kind) {
+        case 0:
+            c = (v >> 7) & 1;
+            r = ((v << 1) | c) & 0xff;
+            break; // RLC
+        case 1:
+            c = v & 1;
+            r = ((v >> 1) | (c << 7)) & 0xff;
+            break; // RRC
+        case 2:
+            c = (v >> 7) & 1;
+            r = ((v << 1) | (f.c ? 1 : 0)) & 0xff;
+            break; // RL
+        case 3:
+            c = v & 1;
+            r = ((v >> 1) | (f.c ? 0x80 : 0)) & 0xff;
+            break; // RR
+        case 4:
+            c = (v >> 7) & 1;
+            r = (v << 1) & 0xff;
+            break; // SLA
+        case 5:
+            c = v & 1;
+            r = ((v >> 1) | (v & 0x80)) & 0xff;
+            break; // SRA
+        case 6:
+            c = (v >> 7) & 1;
+            r = ((v << 1) | 1) & 0xff;
+            break; // SLL (undocumented)
+        case 7:
+            c = v & 1;
+            r = (v >> 1) & 0xff;
+            break; // SRL
+    }
+    setSzyxp(f, r);
+    f.h = false;
+    f.n = false;
+    f.c = c === 1;
+    return r;
+}
+/** BIT b test. `xySource` supplies the undocumented X/Y flag bits. */
+function bitTest(f, b, v, xySource) {
+    const bit = v & (1 << b);
+    f.z = bit === 0;
+    f.pv = f.z; // parity flag mirrors zero for BIT
+    f.s = b === 7 && bit !== 0;
+    f.h = true;
+    f.n = false;
+    f.y = (xySource & 0x20) !== 0;
+    f.x = (xySource & 0x08) !== 0;
+    // C is unaffected
+}
+/**
+ * Registers the plain CB table and the DDCB/FDCB (indexed) bodies.
+ *
+ * Plain CB handlers return the FULL T-state count (the CB dispatcher does not add
+ * the prefix). Indexed handlers return the count minus the DD/FD prefix (which
+ * step() adds): rot/shift/res/set = 19 (→23), BIT = 16 (→20).
+ */
+export function registerBits(cb, idxCb) {
+    // ---- Plain CB (HL/real-register) space ----
+    for (let op = 0; op < 0x40; op++) {
+        const kind = (op >> 3) & 7;
+        const reg = op & 7;
+        if (reg === 6) {
+            cb[op] = (cpu) => {
+                const addr = cpu.regs.hl;
+                cpu.bus.write(addr, rotShift(cpu.flags, kind, cpu.bus.read(addr)));
+                return 15;
+            };
+        }
+        else {
+            cb[op] = (cpu) => {
+                setRealR(cpu.regs, reg, rotShift(cpu.flags, kind, getRealR(cpu.regs, reg)));
+                return 8;
+            };
+        }
+    }
+    // BIT b,r  (0x40..0x7F)
+    for (let op = 0x40; op <= 0x7f; op++) {
+        const b = (op >> 3) & 7;
+        const reg = op & 7;
+        if (reg === 6) {
+            cb[op] = (cpu) => {
+                // BIT b,(HL): X/Y come from the high byte of WZ (MEMPTR).
+                bitTest(cpu.flags, b, cpu.bus.read(cpu.regs.hl), cpu.regs.wz >> 8);
+                return 12;
+            };
+        }
+        else {
+            cb[op] = (cpu) => {
+                const v = getRealR(cpu.regs, reg);
+                bitTest(cpu.flags, b, v, v);
+                return 8;
+            };
+        }
+    }
+    // RES b,r (0x80..0xBF) and SET b,r (0xC0..0xFF)
+    for (let op = 0x80; op <= 0xff; op++) {
+        const b = (op >> 3) & 7;
+        const reg = op & 7;
+        const set = op >= 0xc0;
+        const mask = 1 << b;
+        if (reg === 6) {
+            cb[op] = (cpu) => {
+                const addr = cpu.regs.hl;
+                const v = cpu.bus.read(addr);
+                cpu.bus.write(addr, set ? v | mask : v & ~mask);
+                return 15;
+            };
+        }
+        else {
+            cb[op] = (cpu) => {
+                const v = getRealR(cpu.regs, reg);
+                setRealR(cpu.regs, reg, set ? v | mask : v & ~mask);
+                return 8;
+            };
+        }
+    }
+    // ---- DDCB / FDCB indexed space (address precomputed) ----
+    // rot/shift (0x00..0x3F): operate on (addr), write back, and copy the result
+    // into register op&7 unless it is 6 (undocumented result-copy variants).
+    for (let op = 0; op < 0x40; op++) {
+        const kind = (op >> 3) & 7;
+        const reg = op & 7;
+        idxCb[op] = (cpu, addr) => {
+            const r = rotShift(cpu.flags, kind, cpu.bus.read(addr));
+            cpu.bus.write(addr, r);
+            if (reg !== 6)
+                setRealR(cpu.regs, reg, r);
+            return 19;
+        };
+    }
+    // BIT b,(IX+d) (0x40..0x7F): X/Y from the high byte of the effective address.
+    for (let op = 0x40; op <= 0x7f; op++) {
+        const b = (op >> 3) & 7;
+        idxCb[op] = (cpu, addr) => {
+            bitTest(cpu.flags, b, cpu.bus.read(addr), addr >> 8);
+            return 16;
+        };
+    }
+    // RES/SET b,(IX+d) (0x80..0xFF): apply, write back, copy to reg op&7 unless 6.
+    for (let op = 0x80; op <= 0xff; op++) {
+        const b = (op >> 3) & 7;
+        const reg = op & 7;
+        const set = op >= 0xc0;
+        const mask = 1 << b;
+        idxCb[op] = (cpu, addr) => {
+            const v = cpu.bus.read(addr);
+            const r = set ? v | mask : v & ~mask;
+            cpu.bus.write(addr, r);
+            if (reg !== 6)
+                setRealR(cpu.regs, reg, r);
+            return 19;
+        };
+    }
+}
+//# sourceMappingURL=bits.js.map

package/dist/cpu/z80/instructions/bits.js.map

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package/dist/cpu/z80/instructions/block.d.ts

@@ -0,0 +1,10 @@
+import type { Z80Handler } from '../types.js';
+/**
+ * Block transfer (LDI/LDD/LDIR/LDDR), search (CPI/CPD/CPIR/CPDR), and I/O
+ * (INI/IND/INIR/INDR, OUTI/OUTD/OTIR/OTDR).
+ *
+ * Repeating variants execute one iteration per step() and rewind PC by 2 to
+ * re-enter, so interrupts are accepted between iterations (hardware-accurate).
+ */
+export declare function registerBlock(ed: Z80Handler[]): void;
+//# sourceMappingURL=block.d.ts.map

package/dist/cpu/z80/instructions/block.d.ts.map

@@ -0,0 +1 @@
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package/dist/cpu/z80/instructions/block.js

@@ -0,0 +1,141 @@
+import { parityEven } from '../flagHelpers.js';
+import { u16 } from '../../../util/bits.js';
+/**
+ * Block transfer (LDI/LDD/LDIR/LDDR), search (CPI/CPD/CPIR/CPDR), and I/O
+ * (INI/IND/INIR/INDR, OUTI/OUTD/OTIR/OTDR).
+ *
+ * Repeating variants execute one iteration per step() and rewind PC by 2 to
+ * re-enter, so interrupts are accepted between iterations (hardware-accurate).
+ */
+export function registerBlock(ed) {
+    // ---- LDI / LDD / LDIR / LDDR ----
+    const ld = (dir) => {
+        const v = (cpu) => {
+            const byte = cpu.bus.read(cpu.regs.hl);
+            cpu.bus.write(cpu.regs.de, byte);
+            cpu.regs.hl = u16(cpu.regs.hl + dir);
+            cpu.regs.de = u16(cpu.regs.de + dir);
+            cpu.regs.bc = u16(cpu.regs.bc - 1);
+            const n = (byte + cpu.regs.a) & 0xff;
+            const f = cpu.flags;
+            f.h = false;
+            f.n = false;
+            f.pv = cpu.regs.bc !== 0;
+            f.y = (n & 0x02) !== 0; // bit 1 → Y
+            f.x = (n & 0x08) !== 0; // bit 3 → X
+            // S, Z, C unaffected
+        };
+        // non-repeating (LDI 0xA0 / LDD 0xA8)
+        ed[dir === 1 ? 0xa0 : 0xa8] = (cpu) => { v(cpu); return 16; };
+        // repeating (LDIR 0xB0 / LDDR 0xB8)
+        ed[dir === 1 ? 0xb0 : 0xb8] = (cpu) => {
+            v(cpu);
+            if (cpu.regs.bc !== 0) {
+                cpu.regs.pc = u16(cpu.regs.pc - 2);
+                cpu.regs.wz = u16(cpu.regs.pc + 1);
+                return 21;
+            }
+            return 16;
+        };
+    };
+    ld(1);
+    ld(-1);
+    // ---- CPI / CPD / CPIR / CPDR ----
+    const cp = (dir) => {
+        const one = (cpu) => {
+            const a = cpu.regs.a;
+            const val = cpu.bus.read(cpu.regs.hl);
+            const result = (a - val) & 0xff;
+            cpu.regs.hl = u16(cpu.regs.hl + dir);
+            cpu.regs.bc = u16(cpu.regs.bc - 1);
+            cpu.regs.wz = u16(cpu.regs.wz + dir);
+            const f = cpu.flags;
+            f.n = true;
+            f.h = ((a & 0xf) - (val & 0xf)) < 0;
+            const n = (result - (f.h ? 1 : 0)) & 0xff;
+            f.s = (result & 0x80) !== 0;
+            f.z = result === 0;
+            f.pv = cpu.regs.bc !== 0;
+            f.y = (n & 0x02) !== 0;
+            f.x = (n & 0x08) !== 0;
+            // C unaffected
+        };
+        ed[dir === 1 ? 0xa1 : 0xa9] = (cpu) => { one(cpu); return 16; };
+        ed[dir === 1 ? 0xb1 : 0xb9] = (cpu) => {
+            one(cpu);
+            if (cpu.regs.bc !== 0 && !cpu.flags.z) {
+                cpu.regs.pc = u16(cpu.regs.pc - 2);
+                cpu.regs.wz = u16(cpu.regs.pc + 1);
+                return 21;
+            }
+            return 16;
+        };
+    };
+    cp(1);
+    cp(-1);
+    // ---- INI / IND / INIR / INDR ----
+    const ini = (dir) => {
+        const one = (cpu) => {
+            const f = cpu.flags;
+            cpu.regs.wz = u16(cpu.regs.bc + dir);
+            const val = cpu.bus.ioRead(cpu.regs.c) & 0xff;
+            cpu.bus.write(cpu.regs.hl, val);
+            cpu.regs.hl = u16(cpu.regs.hl + dir);
+            cpu.regs.b = (cpu.regs.b - 1) & 0xff;
+            const b = cpu.regs.b;
+            f.n = (val & 0x80) !== 0;
+            f.s = (b & 0x80) !== 0;
+            f.z = b === 0;
+            f.y = (b & 0x20) !== 0;
+            f.x = (b & 0x08) !== 0;
+            const k = val + ((cpu.regs.c + dir) & 0xff);
+            f.h = k > 0xff;
+            f.c = k > 0xff;
+            f.pv = parityEven((k & 7) ^ b);
+        };
+        ed[dir === 1 ? 0xa2 : 0xaa] = (cpu) => { one(cpu); return 16; };
+        ed[dir === 1 ? 0xb2 : 0xba] = (cpu) => {
+            one(cpu);
+            if (cpu.regs.b !== 0) {
+                cpu.regs.pc = u16(cpu.regs.pc - 2);
+                return 21;
+            }
+            return 16;
+        };
+    };
+    ini(1);
+    ini(-1);
+    // ---- OUTI / OUTD / OTIR / OTDR ----
+    const outi = (dir) => {
+        const one = (cpu) => {
+            const f = cpu.flags;
+            const val = cpu.bus.read(cpu.regs.hl);
+            cpu.regs.b = (cpu.regs.b - 1) & 0xff;
+            const b = cpu.regs.b;
+            cpu.bus.ioWrite(cpu.regs.c, val);
+            cpu.regs.hl = u16(cpu.regs.hl + dir);
+            cpu.regs.wz = u16(cpu.regs.bc + dir);
+            f.n = (val & 0x80) !== 0;
+            f.s = (b & 0x80) !== 0;
+            f.z = b === 0;
+            f.y = (b & 0x20) !== 0;
+            f.x = (b & 0x08) !== 0;
+            const k = val + (cpu.regs.l);
+            f.h = k > 0xff;
+            f.c = k > 0xff;
+            f.pv = parityEven((k & 7) ^ b);
+        };
+        ed[dir === 1 ? 0xa3 : 0xab] = (cpu) => { one(cpu); return 16; };
+        ed[dir === 1 ? 0xb3 : 0xbb] = (cpu) => {
+            one(cpu);
+            if (cpu.regs.b !== 0) {
+                cpu.regs.pc = u16(cpu.regs.pc - 2);
+                return 21;
+            }
+            return 16;
+        };
+    };
+    outi(1);
+    outi(-1);
+}
+//# sourceMappingURL=block.js.map

package/dist/cpu/z80/instructions/block.js.map

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package/dist/cpu/z80/instructions/control.d.ts

@@ -0,0 +1,4 @@
+import type { Z80Handler, IndexView } from '../types.js';
+/** NOP, HALT, DI, EI, DAA, CPL, SCF, CCF (view-independent, live in main table). */
+export declare function registerControl(table: Z80Handler[], _view: IndexView): void;
+//# sourceMappingURL=control.d.ts.map

package/dist/cpu/z80/instructions/control.d.ts.map

@@ -0,0 +1 @@
+{"version":3,"file":"control.d.ts","sourceRoot":"","sources":["../../../../src/cpu/z80/instructions/control.ts"],"names":[],"mappings":"AAAA,OAAO,KAAK,EAAE,UAAU,EAAE,SAAS,EAAE,MAAM,aAAa,CAAC;AAGzD,oFAAoF;AACpF,wBAAgB,eAAe,CAAC,KAAK,EAAE,UAAU,EAAE,EAAE,KAAK,EAAE,SAAS,GAAG,IAAI,CA6D3E"}

package/dist/cpu/z80/instructions/control.js

@@ -0,0 +1,62 @@
+import { setSzyxp } from '../flagHelpers.js';
+/** NOP, HALT, DI, EI, DAA, CPL, SCF, CCF (view-independent, live in main table). */
+export function registerControl(table, _view) {
+    // NOP
+    table[0x00] = (_cpu) => 4;
+    // HALT
+    table[0x76] = (cpu) => { cpu.halted = true; return 4; };
+    // DI
+    table[0xf3] = (cpu) => { cpu.iff1 = false; cpu.iff2 = false; cpu.pendingEI = false; return 4; };
+    // EI (interrupts become enabled after the following instruction)
+    table[0xfb] = (cpu) => { cpu.pendingEI = true; return 4; };
+    // DAA
+    table[0x27] = (cpu) => {
+        const f = cpu.flags;
+        const a0 = cpu.regs.a;
+        let corr = 0;
+        let carry = false;
+        if (f.h || (a0 & 0x0f) > 9)
+            corr |= 0x06;
+        if (f.c || a0 > 0x99) {
+            corr |= 0x60;
+            carry = true;
+        }
+        const a = (f.n ? a0 - corr : a0 + corr) & 0xff;
+        cpu.regs.a = a;
+        f.c = carry;
+        f.h = ((a0 ^ a) & 0x10) !== 0;
+        setSzyxp(f, a);
+        return 4;
+    };
+    // CPL (complement A)
+    table[0x2f] = (cpu) => {
+        const f = cpu.flags;
+        cpu.regs.a = ~cpu.regs.a & 0xff;
+        f.h = true;
+        f.n = true;
+        f.y = (cpu.regs.a & 0x20) !== 0;
+        f.x = (cpu.regs.a & 0x08) !== 0;
+        return 4;
+    };
+    // SCF (set carry)
+    table[0x37] = (cpu) => {
+        const f = cpu.flags;
+        f.c = true;
+        f.h = false;
+        f.n = false;
+        f.y = (cpu.regs.a & 0x20) !== 0;
+        f.x = (cpu.regs.a & 0x08) !== 0;
+        return 4;
+    };
+    // CCF (complement carry)
+    table[0x3f] = (cpu) => {
+        const f = cpu.flags;
+        f.h = f.c;
+        f.c = !f.c;
+        f.n = false;
+        f.y = (cpu.regs.a & 0x20) !== 0;
+        f.x = (cpu.regs.a & 0x08) !== 0;
+        return 4;
+    };
+}
+//# sourceMappingURL=control.js.map

package/dist/cpu/z80/instructions/control.js.map

@@ -0,0 +1 @@
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package/dist/cpu/z80/instructions/ed.d.ts

@@ -0,0 +1,4 @@
+import type { Z80Handler } from '../types.js';
+/** ED-prefixed instructions (excluding the block ops, which block.ts registers). */
+export declare function registerEd(ed: Z80Handler[]): void;
+//# sourceMappingURL=ed.d.ts.map

package/dist/cpu/z80/instructions/ed.d.ts.map

@@ -0,0 +1 @@
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package/dist/cpu/z80/instructions/ed.js

@@ -0,0 +1,149 @@
+import { adc16, sbc16, sub8, setSzyxp } from '../flagHelpers.js';
+import { getRealR, setRealR } from '../regcodes.js';
+import { u16 } from '../../../util/bits.js';
+function read16(cpu, addr) {
+    return cpu.bus.read(addr) | (cpu.bus.read(u16(addr + 1)) << 8);
+}
+function write16(cpu, addr, v) {
+    cpu.bus.write(addr, v & 0xff);
+    cpu.bus.write(u16(addr + 1), (v >> 8) & 0xff);
+}
+/** LD A,I / LD A,R flag behavior: PV takes the value of IFF2. */
+function ldAToIR(cpu, v) {
+    const f = cpu.flags;
+    cpu.regs.a = v & 0xff;
+    f.s = (v & 0x80) !== 0;
+    f.z = (v & 0xff) === 0;
+    f.y = (v & 0x20) !== 0;
+    f.x = (v & 0x08) !== 0;
+    f.h = false;
+    f.n = false;
+    f.pv = cpu.iff2;
+    // C unaffected
+}
+/** ED-prefixed instructions (excluding the block ops, which block.ts registers). */
+export function registerEd(ed) {
+    const pairGet = {
+        0: (cpu) => cpu.regs.bc,
+        1: (cpu) => cpu.regs.de,
+        2: (cpu) => cpu.regs.hl,
+        3: (cpu) => cpu.regs.sp,
+    };
+    const pairSet = {
+        0: (cpu, v) => { cpu.regs.bc = v; },
+        1: (cpu, v) => { cpu.regs.de = v; },
+        2: (cpu, v) => { cpu.regs.hl = v; },
+        3: (cpu, v) => { cpu.regs.sp = v; },
+    };
+    for (let p = 0; p < 4; p++) {
+        // SBC HL,rr  (ED 42/52/62/72)
+        ed[0x42 | (p << 4)] = (cpu) => {
+            const hl = cpu.regs.hl;
+            cpu.regs.wz = u16(hl + 1);
+            cpu.regs.hl = sbc16(cpu.flags, hl, pairGet[p](cpu), cpu.flags.c ? 1 : 0);
+            return 15;
+        };
+        // ADC HL,rr  (ED 4A/5A/6A/7A)
+        ed[0x4a | (p << 4)] = (cpu) => {
+            const hl = cpu.regs.hl;
+            cpu.regs.wz = u16(hl + 1);
+            cpu.regs.hl = adc16(cpu.flags, hl, pairGet[p](cpu), cpu.flags.c ? 1 : 0);
+            return 15;
+        };
+        // LD (nn),rr  (ED 43/53/63/73)
+        ed[0x43 | (p << 4)] = (cpu) => {
+            const nn = cpu.fetchWord();
+            write16(cpu, nn, pairGet[p](cpu));
+            cpu.regs.wz = u16(nn + 1);
+            return 20;
+        };
+        // LD rr,(nn)  (ED 4B/5B/6B/7B)
+        ed[0x4b | (p << 4)] = (cpu) => {
+            const nn = cpu.fetchWord();
+            pairSet[p](cpu, read16(cpu, nn));
+            cpu.regs.wz = u16(nn + 1);
+            return 20;
+        };
+    }
+    // NEG (ED 44) and its undocumented duplicates.
+    const neg = (cpu) => {
+        cpu.regs.a = sub8(cpu.flags, 0, cpu.regs.a, 0);
+        return 8;
+    };
+    for (const op of [0x44, 0x4c, 0x54, 0x5c, 0x64, 0x6c, 0x74, 0x7c])
+        ed[op] = neg;
+    // RETN (ED 45 + dups) and RETI (ED 4D): both restore IFF1 from IFF2.
+    const retn = (cpu) => {
+        cpu.iff1 = cpu.iff2;
+        const pc = cpu.pop16();
+        cpu.regs.pc = pc;
+        cpu.regs.wz = pc;
+        return 14;
+    };
+    for (const op of [0x45, 0x55, 0x5d, 0x65, 0x6d, 0x75, 0x7d])
+        ed[op] = retn;
+    ed[0x4d] = retn; // RETI
+    // IM 0/1/2 (ED 46/56/5E) + undocumented duplicates.
+    const setIm = (mode) => (cpu) => { cpu.im = mode; return 8; };
+    ed[0x46] = setIm(0);
+    ed[0x4e] = setIm(0);
+    ed[0x66] = setIm(0);
+    ed[0x6e] = setIm(0);
+    ed[0x56] = setIm(1);
+    ed[0x76] = setIm(1);
+    ed[0x5e] = setIm(2);
+    ed[0x7e] = setIm(2);
+    // LD I,A / LD R,A / LD A,I / LD A,R
+    ed[0x47] = (cpu) => { cpu.regs.i = cpu.regs.a; return 9; };
+    ed[0x4f] = (cpu) => { cpu.regs.r = cpu.regs.a; return 9; };
+    ed[0x57] = (cpu) => { ldAToIR(cpu, cpu.regs.i); return 9; };
+    ed[0x5f] = (cpu) => { ldAToIR(cpu, cpu.regs.r); return 9; };
+    // RRD (ED 67) / RLD (ED 6F)
+    ed[0x67] = (cpu) => {
+        const hl = cpu.regs.hl;
+        const m = cpu.bus.read(hl);
+        const a = cpu.regs.a;
+        cpu.bus.write(hl, ((a << 4) | (m >> 4)) & 0xff);
+        cpu.regs.a = (a & 0xf0) | (m & 0x0f);
+        setSzyxp(cpu.flags, cpu.regs.a);
+        cpu.flags.h = false;
+        cpu.flags.n = false;
+        cpu.regs.wz = u16(hl + 1);
+        return 18;
+    };
+    ed[0x6f] = (cpu) => {
+        const hl = cpu.regs.hl;
+        const m = cpu.bus.read(hl);
+        const a = cpu.regs.a;
+        cpu.bus.write(hl, ((m << 4) | (a & 0x0f)) & 0xff);
+        cpu.regs.a = (a & 0xf0) | ((m >> 4) & 0x0f);
+        setSzyxp(cpu.flags, cpu.regs.a);
+        cpu.flags.h = false;
+        cpu.flags.n = false;
+        cpu.regs.wz = u16(hl + 1);
+        return 18;
+    };
+    // IN r,(C)  (ED 40/48/50/58/60/68/70/78) — 0x70 is IN (C): flags only, no store.
+    for (let r = 0; r < 8; r++) {
+        ed[0x40 | (r << 3)] = (cpu) => {
+            const v = cpu.bus.ioRead(cpu.regs.c) & 0xff;
+            if (r !== 6)
+                setRealR(cpu.regs, r, v);
+            setSzyxp(cpu.flags, v);
+            cpu.flags.h = false;
+            cpu.flags.n = false;
+            cpu.regs.wz = u16(cpu.regs.bc + 1);
+            return 12;
+        };
+    }
+    // OUT (C),r  (ED 41/49/51/59/61/69/71/79) — 0x71 is OUT (C),0.
+    for (let r = 0; r < 8; r++) {
+        ed[0x41 | (r << 3)] = (cpu) => {
+            const v = r === 6 ? 0 : getRealR(cpu.regs, r);
+            cpu.bus.ioWrite(cpu.regs.c, v);
+            cpu.regs.wz = u16(cpu.regs.bc + 1);
+            return 12;
+        };
+    }
+}
+//# sourceMappingURL=ed.js.map

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package/dist/cpu/z80/instructions/exchange.d.ts

@@ -0,0 +1,4 @@
+import type { Z80Handler, IndexView } from '../types.js';
+/** EX/EXX exchange instructions. */
+export declare function registerExchange(table: Z80Handler[], view: IndexView): void;
+//# sourceMappingURL=exchange.d.ts.map

package/dist/cpu/z80/instructions/exchange.d.ts.map

@@ -0,0 +1 @@
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package/dist/cpu/z80/instructions/exchange.js

@@ -0,0 +1,37 @@
+import { u16 } from '../../../util/bits.js';
+/** EX/EXX exchange instructions. */
+export function registerExchange(table, view) {
+    // EX DE,HL — NOT index-affected (a DD/FD prefix still swaps DE and the real HL).
+    table[0xeb] = (cpu) => {
+        const de = cpu.regs.de;
+        cpu.regs.de = cpu.regs.hl;
+        cpu.regs.hl = de;
+        return 4;
+    };
+    // EX AF,AF'
+    table[0x08] = (cpu) => {
+        const a = cpu.regs.a;
+        const f = cpu.flags.toByte();
+        cpu.regs.a = cpu.regs.a2;
+        cpu.flags.fromByte(cpu.regs.f2);
+        cpu.regs.a2 = a;
+        cpu.regs.f2 = f;
+        return 4;
+    };
+    // EXX
+    table[0xd9] = (cpu) => { cpu.regs.exx(); return 4; };
+    // EX (SP),HL / EX (SP),IX / EX (SP),IY
+    table[0xe3] = (cpu) => {
+        const sp = cpu.regs.sp;
+        const lo = cpu.bus.read(sp);
+        const hi = cpu.bus.read(u16(sp + 1));
+        const val = view.getPair(cpu.regs);
+        cpu.bus.write(sp, val & 0xff);
+        cpu.bus.write(u16(sp + 1), (val >> 8) & 0xff);
+        const swapped = (hi << 8) | lo;
+        view.setPair(cpu.regs, swapped);
+        cpu.regs.wz = swapped;
+        return 19;
+    };
+}
+//# sourceMappingURL=exchange.js.map