@joezilla/8sim 0.10.0

package/dist/cpu/z80/views.js

@@ -0,0 +1,40 @@
+/** Sign-extend an 8-bit displacement to a signed JS number. */
+export function sext8(b) {
+    return (b & 0x80) !== 0 ? (b & 0xff) - 0x100 : b & 0xff;
+}
+/** HL view — the unprefixed instruction table. */
+export const HL_VIEW = {
+    kind: 'hl',
+    indexed: false,
+    memExtra: 0,
+    getPair: (r) => r.hl,
+    setPair: (r, v) => { r.hl = v & 0xffff; },
+    getHi: (r) => r.h,
+    setHi: (r, v) => { r.h = v & 0xff; },
+    getLo: (r) => r.l,
+    setLo: (r, v) => { r.l = v & 0xff; },
+    // Plain (HL) access does not touch WZ.
+    memAddr: (cpu) => cpu.regs.hl,
+};
+function makeIndexView(kind, getReg, setReg, getH, setH, getL, setL) {
+    return {
+        kind,
+        indexed: true,
+        memExtra: 8, // 3 T to read d + 5 T internal add
+        getPair: getReg,
+        setPair: setReg,
+        getHi: getH,
+        setHi: setH,
+        getLo: getL,
+        setLo: setL,
+        memAddr: (cpu) => {
+            const d = sext8(cpu.fetchByte());
+            const addr = (getReg(cpu.regs) + d) & 0xffff;
+            cpu.regs.wz = addr;
+            return addr;
+        },
+    };
+}
+export const IX_VIEW = makeIndexView('ix', (r) => r.ix, (r, v) => { r.ix = v & 0xffff; }, (r) => r.ixh, (r, v) => { r.ixh = v; }, (r) => r.ixl, (r, v) => { r.ixl = v; });
+export const IY_VIEW = makeIndexView('iy', (r) => r.iy, (r, v) => { r.iy = v & 0xffff; }, (r) => r.iyh, (r, v) => { r.iyh = v; }, (r) => r.iyl, (r, v) => { r.iyl = v; });
+//# sourceMappingURL=views.js.map

package/dist/cpu/z80/views.js.map

@@ -0,0 +1 @@
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package/dist/index.d.ts

@@ -0,0 +1,67 @@
+export type { IModule } from './interfaces/IModule.js';
+export type { ICpu, CpuState } from './interfaces/ICpu.js';
+export type { IBus } from './interfaces/IBus.js';
+export type { IMemory } from './interfaces/IMemory.js';
+export type { IIODevice } from './interfaces/IIODevice.js';
+export type { IInterruptController } from './interfaces/IInterruptController.js';
+export type { IClock } from './interfaces/IClock.js';
+export type { IBusObserver } from './interfaces/IBusObserver.js';
+export type { IS100Card } from './interfaces/IS100Card.js';
+export { Cpu8080 } from './cpu/Cpu8080.js';
+export { Registers } from './cpu/Registers.js';
+export { Flags } from './cpu/Flags.js';
+export { CpuZ80 } from './cpu/z80/CpuZ80.js';
+export { RegistersZ80 } from './cpu/z80/RegistersZ80.js';
+export { FlagsZ80 } from './cpu/z80/FlagsZ80.js';
+export { Bus } from './bus/Bus.js';
+export { SnoopBus } from './bus/SnoopBus.js';
+export type { BusRegion } from './bus/BusRegion.js';
+export { Ram } from './memory/Ram.js';
+export { Rom } from './memory/Rom.js';
+export { MemoryMappedIOAdapter } from './memory/MemoryMappedIOAdapter.js';
+export { IoSpace } from './io/IoSpace.js';
+export { InterruptController } from './interrupt/InterruptController.js';
+export { ImmediateClock } from './clock/ImmediateClock.js';
+export { SystemClock } from './clock/SystemClock.js';
+export { MachineRunner } from './machine/MachineRunner.js';
+export type { MachineRunnerOptions, CpuSpeed, ISteppable } from './machine/MachineRunner.js';
+export { buildMachine } from './machine/buildMachine.js';
+export type { BuildOptions } from './machine/buildMachine.js';
+export { MachineSpecError } from './machine/MachineSpec.js';
+export type { MachineSpec, Machine, CpuKind, Clock, MemoryRegionSpec, CardSpec, CardFactory, CardContext, } from './machine/MachineSpec.js';
+export { withDefaults, CardConfigError } from './bundles/CardBundle.js';
+export type { CardBundle, CardManifest, ConfigParamSpec, ClaimsFn } from './bundles/CardBundle.js';
+export { seedBundles, seedBundleByName } from './bundles/seed/index.js';
+export { kernels, kernelById, serialKernel, parallelKernel, keyboardKernel, vdmKernel, dazzlerKernel, rtcKernel, bankRamKernel } from './bundles/kernels.js';
+export type { CardKernel } from './bundles/kernels.js';
+export { SerialCard } from './cards/SerialCard.js';
+export type { SerialChip, SerialCardOptions } from './cards/SerialCard.js';
+export { ParallelCard } from './cards/ParallelCard.js';
+export type { PortDirection, ParallelCardOptions, GpioPort } from './cards/ParallelCard.js';
+export { KeyboardCard } from './cards/KeyboardCard.js';
+export type { KeyboardPort, KeyboardCardOptions } from './cards/KeyboardCard.js';
+export { VdmCard } from './cards/VdmCard.js';
+export type { VdmCardOptions } from './cards/VdmCard.js';
+export { DazzlerCard } from './cards/DazzlerCard.js';
+export type { DazzlerCardOptions } from './cards/DazzlerCard.js';
+export { RtcCard } from './cards/RtcCard.js';
+export type { RtcCardOptions, RtcClock } from './cards/RtcCard.js';
+export { BankRamCard } from './cards/BankRamCard.js';
+export type { BankRamCardOptions } from './cards/BankRamCard.js';
+export type { DisplaySurface, DisplayDescriptor, DisplayFrame } from './cards/DisplaySurface.js';
+export { Usart8251 } from './cards/Usart8251.js';
+export { ImsaiSioCard } from './cards/ImsaiSioCard.js';
+export type { SioCardOptions } from './cards/ImsaiSioCard.js';
+export { FdcPlusClient } from './cards/FdcPlusClient.js';
+export type { WebSocketLike } from './cards/FdcPlusClient.js';
+export { MitsDcddCard } from './cards/MitsDcddCard.js';
+export type { DcddOptions } from './cards/MitsDcddCard.js';
+export { Tr1602Uart } from './cards/Tr1602Uart.js';
+export { Port8212 } from './cards/Port8212.js';
+export { ImsaiMioCard } from './cards/ImsaiMioCard.js';
+export type { MioCardOptions } from './cards/ImsaiMioCard.js';
+export { Mc6850Acia } from './cards/Mc6850Acia.js';
+export { Mits2SioCard } from './cards/Mits2SioCard.js';
+export type { Sio2CardOptions } from './cards/Mits2SioCard.js';
+export * from './util/bits.js';
+//# sourceMappingURL=index.d.ts.map

package/dist/index.d.ts.map

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package/dist/index.js

@@ -0,0 +1,49 @@
+// CPU
+export { Cpu8080 } from './cpu/Cpu8080.js';
+export { Registers } from './cpu/Registers.js';
+export { Flags } from './cpu/Flags.js';
+export { CpuZ80 } from './cpu/z80/CpuZ80.js';
+export { RegistersZ80 } from './cpu/z80/RegistersZ80.js';
+export { FlagsZ80 } from './cpu/z80/FlagsZ80.js';
+// Bus
+export { Bus } from './bus/Bus.js';
+export { SnoopBus } from './bus/SnoopBus.js';
+// Memory
+export { Ram } from './memory/Ram.js';
+export { Rom } from './memory/Rom.js';
+export { MemoryMappedIOAdapter } from './memory/MemoryMappedIOAdapter.js';
+// IO
+export { IoSpace } from './io/IoSpace.js';
+// Interrupt
+export { InterruptController } from './interrupt/InterruptController.js';
+// Clock
+export { ImmediateClock } from './clock/ImmediateClock.js';
+export { SystemClock } from './clock/SystemClock.js';
+// Machine
+export { MachineRunner } from './machine/MachineRunner.js';
+export { buildMachine } from './machine/buildMachine.js';
+export { MachineSpecError } from './machine/MachineSpec.js';
+// Card bundles (seed)
+export { withDefaults, CardConfigError } from './bundles/CardBundle.js';
+export { seedBundles, seedBundleByName } from './bundles/seed/index.js';
+export { kernels, kernelById, serialKernel, parallelKernel, keyboardKernel, vdmKernel, dazzlerKernel, rtcKernel, bankRamKernel } from './bundles/kernels.js';
+export { SerialCard } from './cards/SerialCard.js';
+export { ParallelCard } from './cards/ParallelCard.js';
+export { KeyboardCard } from './cards/KeyboardCard.js';
+export { VdmCard } from './cards/VdmCard.js';
+export { DazzlerCard } from './cards/DazzlerCard.js';
+export { RtcCard } from './cards/RtcCard.js';
+export { BankRamCard } from './cards/BankRamCard.js';
+// Cards
+export { Usart8251 } from './cards/Usart8251.js';
+export { ImsaiSioCard } from './cards/ImsaiSioCard.js';
+export { FdcPlusClient } from './cards/FdcPlusClient.js';
+export { MitsDcddCard } from './cards/MitsDcddCard.js';
+export { Tr1602Uart } from './cards/Tr1602Uart.js';
+export { Port8212 } from './cards/Port8212.js';
+export { ImsaiMioCard } from './cards/ImsaiMioCard.js';
+export { Mc6850Acia } from './cards/Mc6850Acia.js';
+export { Mits2SioCard } from './cards/Mits2SioCard.js';
+// Utils
+export * from './util/bits.js';
+//# sourceMappingURL=index.js.map

package/dist/index.js.map

@@ -0,0 +1 @@
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package/dist/interfaces/IBus.d.ts

@@ -0,0 +1,8 @@
+export interface IBus {
+    read(address: number): number;
+    write(address: number, value: number): void;
+    ioRead(port: number): number;
+    ioWrite(port: number, value: number): void;
+    acknowledgeInterrupt(): number;
+}
+//# sourceMappingURL=IBus.d.ts.map

package/dist/interfaces/IBus.d.ts.map

@@ -0,0 +1 @@
+{"version":3,"file":"IBus.d.ts","sourceRoot":"","sources":["../../src/interfaces/IBus.ts"],"names":[],"mappings":"AAAA,MAAM,WAAW,IAAI;IACnB,IAAI,CAAC,OAAO,EAAE,MAAM,GAAG,MAAM,CAAC;IAC9B,KAAK,CAAC,OAAO,EAAE,MAAM,EAAE,KAAK,EAAE,MAAM,GAAG,IAAI,CAAC;IAC5C,MAAM,CAAC,IAAI,EAAE,MAAM,GAAG,MAAM,CAAC;IAC7B,OAAO,CAAC,IAAI,EAAE,MAAM,EAAE,KAAK,EAAE,MAAM,GAAG,IAAI,CAAC;IAC3C,oBAAoB,IAAI,MAAM,CAAC;CAChC"}

package/dist/interfaces/IBus.js

@@ -0,0 +1,2 @@
+export {};
+//# sourceMappingURL=IBus.js.map

package/dist/interfaces/IBus.js.map

@@ -0,0 +1 @@
+{"version":3,"file":"IBus.js","sourceRoot":"","sources":["../../src/interfaces/IBus.ts"],"names":[],"mappings":""}

package/dist/interfaces/IBusObserver.d.ts

@@ -0,0 +1,7 @@
+export interface IBusObserver {
+    onMemRead?(address: number, value: number): void;
+    onMemWrite?(address: number, value: number): void;
+    onIoRead?(port: number, value: number): void;
+    onIoWrite?(port: number, value: number): void;
+}
+//# sourceMappingURL=IBusObserver.d.ts.map

package/dist/interfaces/IBusObserver.d.ts.map

@@ -0,0 +1 @@
+{"version":3,"file":"IBusObserver.d.ts","sourceRoot":"","sources":["../../src/interfaces/IBusObserver.ts"],"names":[],"mappings":"AAAA,MAAM,WAAW,YAAY;IAC3B,SAAS,CAAC,CAAC,OAAO,EAAE,MAAM,EAAE,KAAK,EAAE,MAAM,GAAG,IAAI,CAAC;IACjD,UAAU,CAAC,CAAC,OAAO,EAAE,MAAM,EAAE,KAAK,EAAE,MAAM,GAAG,IAAI,CAAC;IAClD,QAAQ,CAAC,CAAC,IAAI,EAAE,MAAM,EAAE,KAAK,EAAE,MAAM,GAAG,IAAI,CAAC;IAC7C,SAAS,CAAC,CAAC,IAAI,EAAE,MAAM,EAAE,KAAK,EAAE,MAAM,GAAG,IAAI,CAAC;CAC/C"}

package/dist/interfaces/IBusObserver.js

@@ -0,0 +1,2 @@
+export {};
+//# sourceMappingURL=IBusObserver.js.map

package/dist/interfaces/IBusObserver.js.map

@@ -0,0 +1 @@
+{"version":3,"file":"IBusObserver.js","sourceRoot":"","sources":["../../src/interfaces/IBusObserver.ts"],"names":[],"mappings":""}

package/dist/interfaces/IClock.d.ts

@@ -0,0 +1,6 @@
+export interface IClock {
+    addCycles(cycles: number): void;
+    getElapsedCycles(): bigint;
+    reset(): void;
+}
+//# sourceMappingURL=IClock.d.ts.map

package/dist/interfaces/IClock.d.ts.map

@@ -0,0 +1 @@
+{"version":3,"file":"IClock.d.ts","sourceRoot":"","sources":["../../src/interfaces/IClock.ts"],"names":[],"mappings":"AAAA,MAAM,WAAW,MAAM;IACrB,SAAS,CAAC,MAAM,EAAE,MAAM,GAAG,IAAI,CAAC;IAChC,gBAAgB,IAAI,MAAM,CAAC;IAC3B,KAAK,IAAI,IAAI,CAAC;CACf"}

package/dist/interfaces/IClock.js

@@ -0,0 +1,2 @@
+export {};
+//# sourceMappingURL=IClock.js.map

package/dist/interfaces/IClock.js.map

@@ -0,0 +1 @@
+{"version":3,"file":"IClock.js","sourceRoot":"","sources":["../../src/interfaces/IClock.ts"],"names":[],"mappings":""}

package/dist/interfaces/ICpu.d.ts

@@ -0,0 +1,46 @@
+/**
+ * Minimal common surface shared by every CPU core (Cpu8080, CpuZ80).
+ *
+ * Deliberately lightweight: it does NOT expose the register file or flags,
+ * because those differ between CPUs. It re-declares `step(): number`, so any
+ * ICpu is structurally assignable to `ISteppable` (src/machine/MachineRunner.ts)
+ * and can be driven by MachineRunner without either module importing the other.
+ */
+export interface ICpu {
+    /** Execute one instruction (or service one pending interrupt); returns T-states consumed. */
+    step(): number;
+    /** Clear all registers, flags, and internal state to power-on defaults. */
+    reset(): void;
+    /** Run until halted or `maxCycles` T-states elapse; returns total T-states executed. */
+    run(maxCycles?: number): bigint;
+    /** True while the CPU is halted (HLT/HALT executed, awaiting an interrupt). */
+    halted: boolean;
+    /** Program counter, proxying the underlying register file. */
+    pc: number;
+    /** A uniform read-only register/flags snapshot for introspection (front panel,
+     * debuggers) — the common 8-bit registers both cores share. */
+    state(): CpuState;
+}
+/** A CPU register/flags snapshot — the registers common to the 8080 and Z80. */
+export interface CpuState {
+    pc: number;
+    sp: number;
+    a: number;
+    /** Flags packed to a byte (PSW low byte on the 8080; F on the Z80). */
+    f: number;
+    b: number;
+    c: number;
+    d: number;
+    e: number;
+    h: number;
+    l: number;
+    halted: boolean;
+    /** Interrupt-enable flip-flop (8080 INTE / Z80 IFF1) — drives the panel INTE lamp. */
+    inte: boolean;
+    /** A maskable interrupt is currently asserted at the controller — the INT lamp. */
+    intPending: boolean;
+    /** 8080 status byte of the last instruction — drives the panel machine-cycle
+     * lamps (MEMR/INP/M1/OUT/STACK/WO/HLTA/INTA). See `status8080.ts`. */
+    status: number;
+}
+//# sourceMappingURL=ICpu.d.ts.map

package/dist/interfaces/ICpu.d.ts.map

@@ -0,0 +1 @@
+{"version":3,"file":"ICpu.d.ts","sourceRoot":"","sources":["../../src/interfaces/ICpu.ts"],"names":[],"mappings":"AAAA;;;;;;;GAOG;AACH,MAAM,WAAW,IAAI;IACnB,6FAA6F;IAC7F,IAAI,IAAI,MAAM,CAAC;IACf,2EAA2E;IAC3E,KAAK,IAAI,IAAI,CAAC;IACd,wFAAwF;IACxF,GAAG,CAAC,SAAS,CAAC,EAAE,MAAM,GAAG,MAAM,CAAC;IAChC,+EAA+E;IAC/E,MAAM,EAAE,OAAO,CAAC;IAChB,8DAA8D;IAC9D,EAAE,EAAE,MAAM,CAAC;IACX;mEAC+D;IAC/D,KAAK,IAAI,QAAQ,CAAC;CACnB;AAED,gFAAgF;AAChF,MAAM,WAAW,QAAQ;IACvB,EAAE,EAAE,MAAM,CAAC;IACX,EAAE,EAAE,MAAM,CAAC;IACX,CAAC,EAAE,MAAM,CAAC;IACV,uEAAuE;IACvE,CAAC,EAAE,MAAM,CAAC;IACV,CAAC,EAAE,MAAM,CAAC;IACV,CAAC,EAAE,MAAM,CAAC;IACV,CAAC,EAAE,MAAM,CAAC;IACV,CAAC,EAAE,MAAM,CAAC;IACV,CAAC,EAAE,MAAM,CAAC;IACV,CAAC,EAAE,MAAM,CAAC;IACV,MAAM,EAAE,OAAO,CAAC;IAChB,sFAAsF;IACtF,IAAI,EAAE,OAAO,CAAC;IACd,mFAAmF;IACnF,UAAU,EAAE,OAAO,CAAC;IACpB;0EACsE;IACtE,MAAM,EAAE,MAAM,CAAC;CAChB"}

package/dist/interfaces/ICpu.js

@@ -0,0 +1,2 @@
+export {};
+//# sourceMappingURL=ICpu.js.map

package/dist/interfaces/ICpu.js.map

@@ -0,0 +1 @@
+{"version":3,"file":"ICpu.js","sourceRoot":"","sources":["../../src/interfaces/ICpu.ts"],"names":[],"mappings":""}

package/dist/interfaces/IIODevice.d.ts

@@ -0,0 +1,7 @@
+import type { IModule } from './IModule.js';
+export interface IIODevice extends IModule {
+    readonly basePorts: ReadonlyArray<number>;
+    ioRead(port: number): number;
+    ioWrite(port: number, value: number): void;
+}
+//# sourceMappingURL=IIODevice.d.ts.map

package/dist/interfaces/IIODevice.d.ts.map

@@ -0,0 +1 @@
+{"version":3,"file":"IIODevice.d.ts","sourceRoot":"","sources":["../../src/interfaces/IIODevice.ts"],"names":[],"mappings":"AAAA,OAAO,KAAK,EAAE,OAAO,EAAE,MAAM,cAAc,CAAC;AAE5C,MAAM,WAAW,SAAU,SAAQ,OAAO;IACxC,QAAQ,CAAC,SAAS,EAAE,aAAa,CAAC,MAAM,CAAC,CAAC;IAC1C,MAAM,CAAC,IAAI,EAAE,MAAM,GAAG,MAAM,CAAC;IAC7B,OAAO,CAAC,IAAI,EAAE,MAAM,EAAE,KAAK,EAAE,MAAM,GAAG,IAAI,CAAC;CAC5C"}

package/dist/interfaces/IIODevice.js

@@ -0,0 +1,2 @@
+export {};
+//# sourceMappingURL=IIODevice.js.map

package/dist/interfaces/IIODevice.js.map

@@ -0,0 +1 @@
+{"version":3,"file":"IIODevice.js","sourceRoot":"","sources":["../../src/interfaces/IIODevice.ts"],"names":[],"mappings":""}

package/dist/interfaces/IInterruptController.d.ts

@@ -0,0 +1,8 @@
+import type { IModule } from './IModule.js';
+export interface IInterruptController extends IModule {
+    hasPendingInterrupt(): boolean;
+    acknowledge(): number;
+    assertIRQ(line: number): void;
+    clearIRQ(line: number): void;
+}
+//# sourceMappingURL=IInterruptController.d.ts.map

package/dist/interfaces/IInterruptController.d.ts.map

@@ -0,0 +1 @@
+{"version":3,"file":"IInterruptController.d.ts","sourceRoot":"","sources":["../../src/interfaces/IInterruptController.ts"],"names":[],"mappings":"AAAA,OAAO,KAAK,EAAE,OAAO,EAAE,MAAM,cAAc,CAAC;AAE5C,MAAM,WAAW,oBAAqB,SAAQ,OAAO;IACnD,mBAAmB,IAAI,OAAO,CAAC;IAC/B,WAAW,IAAI,MAAM,CAAC;IACtB,SAAS,CAAC,IAAI,EAAE,MAAM,GAAG,IAAI,CAAC;IAC9B,QAAQ,CAAC,IAAI,EAAE,MAAM,GAAG,IAAI,CAAC;CAC9B"}

package/dist/interfaces/IInterruptController.js

@@ -0,0 +1,2 @@
+export {};
+//# sourceMappingURL=IInterruptController.js.map

package/dist/interfaces/IInterruptController.js.map

@@ -0,0 +1 @@
+{"version":3,"file":"IInterruptController.js","sourceRoot":"","sources":["../../src/interfaces/IInterruptController.ts"],"names":[],"mappings":""}

package/dist/interfaces/IMemory.d.ts

@@ -0,0 +1,9 @@
+import type { IModule } from './IModule.js';
+export interface IMemory extends IModule {
+    readonly baseAddress: number;
+    readonly size: number;
+    readonly readOnly: boolean;
+    read(offset: number): number;
+    write(offset: number, value: number): void;
+}
+//# sourceMappingURL=IMemory.d.ts.map

package/dist/interfaces/IMemory.d.ts.map

@@ -0,0 +1 @@
+{"version":3,"file":"IMemory.d.ts","sourceRoot":"","sources":["../../src/interfaces/IMemory.ts"],"names":[],"mappings":"AAAA,OAAO,KAAK,EAAE,OAAO,EAAE,MAAM,cAAc,CAAC;AAE5C,MAAM,WAAW,OAAQ,SAAQ,OAAO;IACtC,QAAQ,CAAC,WAAW,EAAE,MAAM,CAAC;IAC7B,QAAQ,CAAC,IAAI,EAAE,MAAM,CAAC;IACtB,QAAQ,CAAC,QAAQ,EAAE,OAAO,CAAC;IAC3B,IAAI,CAAC,MAAM,EAAE,MAAM,GAAG,MAAM,CAAC;IAC7B,KAAK,CAAC,MAAM,EAAE,MAAM,EAAE,KAAK,EAAE,MAAM,GAAG,IAAI,CAAC;CAC5C"}

package/dist/interfaces/IMemory.js

@@ -0,0 +1,2 @@
+export {};
+//# sourceMappingURL=IMemory.js.map

package/dist/interfaces/IMemory.js.map

@@ -0,0 +1 @@
+{"version":3,"file":"IMemory.js","sourceRoot":"","sources":["../../src/interfaces/IMemory.ts"],"names":[],"mappings":""}

package/dist/interfaces/IModule.d.ts

@@ -0,0 +1,5 @@
+export interface IModule {
+    readonly id: string;
+    reset(): void;
+}
+//# sourceMappingURL=IModule.d.ts.map

package/dist/interfaces/IModule.d.ts.map

@@ -0,0 +1 @@
+{"version":3,"file":"IModule.d.ts","sourceRoot":"","sources":["../../src/interfaces/IModule.ts"],"names":[],"mappings":"AAAA,MAAM,WAAW,OAAO;IACtB,QAAQ,CAAC,EAAE,EAAE,MAAM,CAAC;IACpB,KAAK,IAAI,IAAI,CAAC;CACf"}

package/dist/interfaces/IModule.js

@@ -0,0 +1,2 @@
+export {};
+//# sourceMappingURL=IModule.js.map

package/dist/interfaces/IModule.js.map

@@ -0,0 +1 @@
+{"version":3,"file":"IModule.js","sourceRoot":"","sources":["../../src/interfaces/IModule.ts"],"names":[],"mappings":""}

package/dist/interfaces/IS100Card.d.ts

@@ -0,0 +1,6 @@
+import type { IModule } from './IModule.js';
+import type { Bus } from '../bus/Bus.js';
+export interface IS100Card extends IModule {
+    attach(bus: Bus): void;
+}
+//# sourceMappingURL=IS100Card.d.ts.map

package/dist/interfaces/IS100Card.d.ts.map

@@ -0,0 +1 @@
+{"version":3,"file":"IS100Card.d.ts","sourceRoot":"","sources":["../../src/interfaces/IS100Card.ts"],"names":[],"mappings":"AAAA,OAAO,KAAK,EAAE,OAAO,EAAE,MAAM,cAAc,CAAC;AAC5C,OAAO,KAAK,EAAE,GAAG,EAAE,MAAM,eAAe,CAAC;AAEzC,MAAM,WAAW,SAAU,SAAQ,OAAO;IACxC,MAAM,CAAC,GAAG,EAAE,GAAG,GAAG,IAAI,CAAC;CACxB"}

package/dist/interfaces/IS100Card.js

@@ -0,0 +1,2 @@
+export {};
+//# sourceMappingURL=IS100Card.js.map

package/dist/interfaces/IS100Card.js.map

@@ -0,0 +1 @@
+{"version":3,"file":"IS100Card.js","sourceRoot":"","sources":["../../src/interfaces/IS100Card.ts"],"names":[],"mappings":""}

package/dist/interfaces/index.d.ts

@@ -0,0 +1,10 @@
+export type { IModule } from './IModule.js';
+export type { ICpu } from './ICpu.js';
+export type { IBus } from './IBus.js';
+export type { IMemory } from './IMemory.js';
+export type { IIODevice } from './IIODevice.js';
+export type { IInterruptController } from './IInterruptController.js';
+export type { IClock } from './IClock.js';
+export type { IBusObserver } from './IBusObserver.js';
+export type { IS100Card } from './IS100Card.js';
+//# sourceMappingURL=index.d.ts.map

package/dist/interfaces/index.d.ts.map

@@ -0,0 +1 @@
+{"version":3,"file":"index.d.ts","sourceRoot":"","sources":["../../src/interfaces/index.ts"],"names":[],"mappings":"AAAA,YAAY,EAAE,OAAO,EAAE,MAAM,cAAc,CAAC;AAC5C,YAAY,EAAE,IAAI,EAAE,MAAM,WAAW,CAAC;AACtC,YAAY,EAAE,IAAI,EAAE,MAAM,WAAW,CAAC;AACtC,YAAY,EAAE,OAAO,EAAE,MAAM,cAAc,CAAC;AAC5C,YAAY,EAAE,SAAS,EAAE,MAAM,gBAAgB,CAAC;AAChD,YAAY,EAAE,oBAAoB,EAAE,MAAM,2BAA2B,CAAC;AACtE,YAAY,EAAE,MAAM,EAAE,MAAM,aAAa,CAAC;AAC1C,YAAY,EAAE,YAAY,EAAE,MAAM,mBAAmB,CAAC;AACtD,YAAY,EAAE,SAAS,EAAE,MAAM,gBAAgB,CAAC"}

package/dist/interfaces/index.js

@@ -0,0 +1,2 @@
+export {};
+//# sourceMappingURL=index.js.map

package/dist/interfaces/index.js.map

@@ -0,0 +1 @@
+{"version":3,"file":"index.js","sourceRoot":"","sources":["../../src/interfaces/index.ts"],"names":[],"mappings":""}

package/dist/interrupt/InterruptController.d.ts

@@ -0,0 +1,13 @@
+import type { IInterruptController } from '../interfaces/IInterruptController.js';
+export declare class InterruptController implements IInterruptController {
+    readonly id = "pic";
+    private pending;
+    private readonly lines;
+    constructor(lines?: number);
+    hasPendingInterrupt(): boolean;
+    acknowledge(): number;
+    assertIRQ(line: number): void;
+    clearIRQ(line: number): void;
+    reset(): void;
+}
+//# sourceMappingURL=InterruptController.d.ts.map

package/dist/interrupt/InterruptController.d.ts.map

@@ -0,0 +1 @@
+{"version":3,"file":"InterruptController.d.ts","sourceRoot":"","sources":["../../src/interrupt/InterruptController.ts"],"names":[],"mappings":"AAAA,OAAO,KAAK,EAAE,oBAAoB,EAAE,MAAM,uCAAuC,CAAC;AAElF,qBAAa,mBAAoB,YAAW,oBAAoB;IAC9D,QAAQ,CAAC,EAAE,SAAS;IACpB,OAAO,CAAC,OAAO,CAAK;IACpB,OAAO,CAAC,QAAQ,CAAC,KAAK,CAAS;gBAEnB,KAAK,SAAI;IAIrB,mBAAmB,IAAI,OAAO;IAI9B,WAAW,IAAI,MAAM;IAYrB,SAAS,CAAC,IAAI,EAAE,MAAM,GAAG,IAAI;IAM7B,QAAQ,CAAC,IAAI,EAAE,MAAM,GAAG,IAAI;IAM5B,KAAK,IAAI,IAAI;CAGd"}

package/dist/interrupt/InterruptController.js

@@ -0,0 +1,36 @@
+export class InterruptController {
+    id = 'pic';
+    pending = 0; // bitmask of pending IRQ lines
+    lines;
+    constructor(lines = 8) {
+        this.lines = lines;
+    }
+    hasPendingInterrupt() {
+        return this.pending !== 0;
+    }
+    acknowledge() {
+        // Find lowest pending IRQ line
+        for (let i = 0; i < this.lines; i++) {
+            if ((this.pending & (1 << i)) !== 0) {
+                this.pending &= ~(1 << i);
+                // RST n instruction: 0b11_nnn_111
+                return 0xc7 | (i << 3);
+            }
+        }
+        return 0xff; // no interrupt (NOP)
+    }
+    assertIRQ(line) {
+        if (line >= 0 && line < this.lines) {
+            this.pending |= 1 << line;
+        }
+    }
+    clearIRQ(line) {
+        if (line >= 0 && line < this.lines) {
+            this.pending &= ~(1 << line);
+        }
+    }
+    reset() {
+        this.pending = 0;
+    }
+}
+//# sourceMappingURL=InterruptController.js.map

package/dist/interrupt/InterruptController.js.map

@@ -0,0 +1 @@
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package/dist/io/IoSpace.d.ts

@@ -0,0 +1,9 @@
+import type { IIODevice } from '../interfaces/IIODevice.js';
+export declare class IoSpace {
+    private devices;
+    register(dev: IIODevice): void;
+    read(port: number): number;
+    write(port: number, value: number): void;
+    reset(): void;
+}
+//# sourceMappingURL=IoSpace.d.ts.map

package/dist/io/IoSpace.d.ts.map

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package/dist/io/IoSpace.js

@@ -0,0 +1,30 @@
+export class IoSpace {
+    devices = new Map();
+    register(dev) {
+        for (const port of dev.basePorts) {
+            this.devices.set(port & 0xff, dev);
+        }
+    }
+    read(port) {
+        const dev = this.devices.get(port & 0xff);
+        if (dev === undefined)
+            return 0xff;
+        return dev.ioRead(port & 0xff);
+    }
+    write(port, value) {
+        const dev = this.devices.get(port & 0xff);
+        if (dev === undefined)
+            return;
+        dev.ioWrite(port & 0xff, value & 0xff);
+    }
+    reset() {
+        const seen = new Set();
+        for (const dev of this.devices.values()) {
+            if (!seen.has(dev)) {
+                seen.add(dev);
+                dev.reset();
+            }
+        }
+    }
+}
+//# sourceMappingURL=IoSpace.js.map

package/dist/io/IoSpace.js.map

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package/dist/machine/MachineRunner.d.ts

@@ -0,0 +1,54 @@
+/** Anything with a step() that executes one instruction and returns T-states. */
+export interface ISteppable {
+    step(): number;
+}
+/** Target CPU speed: a frequency in Hz, or 'max' for unthrottled execution. */
+export type CpuSpeed = number | 'max';
+export interface MachineRunnerOptions {
+    /** Target CPU clock. Default 2 MHz — a stock 8080. */
+    hz?: CpuSpeed;
+    /**
+     * Scheduler for the next tick. Defaults to setTimeout (browser-portable).
+     * Node callers wanting maximum throughput in 'max' mode can pass
+     * (fn, ms) => ms > 0 ? setTimeout(fn, ms) : setImmediate(fn).
+     */
+    schedule?: (fn: () => void, delayMs: number) => void;
+    /** Called after the runner stops itself because step() threw. */
+    onError?: (err: unknown) => void;
+    /** Time source in ms. Default performance.now — override for tests. */
+    now?: () => number;
+}
+/**
+ * Drives a CPU's step() loop at a configurable real-time speed.
+ *
+ * Throttled mode runs the CPU in ~1 ms slices of simulated time and compares
+ * simulated progress against wall time (absolute accounting via SystemClock,
+ * so timer jitter self-corrects): ahead → sleep the difference; behind → keep
+ * stepping up to MAX_SLICE_MS per tick, then yield so host I/O stays
+ * responsive. Host stalls beyond RESYNC_BEHIND_MS are forfeited rather than
+ * replayed at full speed.
+ */
+export declare class MachineRunner {
+    private readonly cpu;
+    private hz;
+    private readonly clock;
+    private readonly schedule;
+    private readonly onError;
+    private readonly now;
+    private running;
+    private startedAt;
+    private cyclesAtStart;
+    constructor(cpu: ISteppable, options?: MachineRunnerOptions);
+    get targetHz(): CpuSpeed;
+    /** Measured average speed in Hz since start() — for status displays. */
+    get effectiveHz(): number;
+    get isRunning(): boolean;
+    /** Total simulated T-states executed across the runner's lifetime. */
+    get elapsedCycles(): bigint;
+    start(): void;
+    stop(): void;
+    /** Change speed while running; pacing restarts from this moment. */
+    setHz(hz: CpuSpeed): void;
+    private readonly tick;
+}
+//# sourceMappingURL=MachineRunner.d.ts.map

package/dist/machine/MachineRunner.d.ts.map

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