@joezilla/8sim 0.10.0

package/dist/cpu/instructions/stack.js

@@ -0,0 +1,84 @@
+import { u16 } from '../../util/bits.js';
+export function registerStack(decoder) {
+    // PUSH B (0xC5)
+    decoder.register(0xc5, (regs, _flags, bus) => {
+        regs.sp = u16(regs.sp - 1);
+        bus.write(regs.sp, regs.b);
+        regs.sp = u16(regs.sp - 1);
+        bus.write(regs.sp, regs.c);
+        return 11;
+    });
+    // PUSH D (0xD5)
+    decoder.register(0xd5, (regs, _flags, bus) => {
+        regs.sp = u16(regs.sp - 1);
+        bus.write(regs.sp, regs.d);
+        regs.sp = u16(regs.sp - 1);
+        bus.write(regs.sp, regs.e);
+        return 11;
+    });
+    // PUSH H (0xE5)
+    decoder.register(0xe5, (regs, _flags, bus) => {
+        regs.sp = u16(regs.sp - 1);
+        bus.write(regs.sp, regs.h);
+        regs.sp = u16(regs.sp - 1);
+        bus.write(regs.sp, regs.l);
+        return 11;
+    });
+    // PUSH PSW (0xF5) — A and Flags
+    decoder.register(0xf5, (regs, flags, bus) => {
+        regs.sp = u16(regs.sp - 1);
+        bus.write(regs.sp, regs.a);
+        regs.sp = u16(regs.sp - 1);
+        bus.write(regs.sp, flags.toByte());
+        return 11;
+    });
+    // POP B (0xC1)
+    decoder.register(0xc1, (regs, _flags, bus) => {
+        regs.c = bus.read(regs.sp);
+        regs.sp = u16(regs.sp + 1);
+        regs.b = bus.read(regs.sp);
+        regs.sp = u16(regs.sp + 1);
+        return 10;
+    });
+    // POP D (0xD1)
+    decoder.register(0xd1, (regs, _flags, bus) => {
+        regs.e = bus.read(regs.sp);
+        regs.sp = u16(regs.sp + 1);
+        regs.d = bus.read(regs.sp);
+        regs.sp = u16(regs.sp + 1);
+        return 10;
+    });
+    // POP H (0xE1)
+    decoder.register(0xe1, (regs, _flags, bus) => {
+        regs.l = bus.read(regs.sp);
+        regs.sp = u16(regs.sp + 1);
+        regs.h = bus.read(regs.sp);
+        regs.sp = u16(regs.sp + 1);
+        return 10;
+    });
+    // POP PSW (0xF1) — A and Flags
+    decoder.register(0xf1, (regs, flags, bus) => {
+        const psw = bus.read(regs.sp);
+        regs.sp = u16(regs.sp + 1);
+        regs.a = bus.read(regs.sp);
+        regs.sp = u16(regs.sp + 1);
+        flags.fromByte(psw);
+        return 10;
+    });
+    // XTHL (0xE3) — Exchange top of stack with HL
+    decoder.register(0xe3, (regs, _flags, bus) => {
+        const lo = bus.read(regs.sp);
+        const hi = bus.read(u16(regs.sp + 1));
+        bus.write(regs.sp, regs.l);
+        bus.write(u16(regs.sp + 1), regs.h);
+        regs.l = lo;
+        regs.h = hi;
+        return 18;
+    });
+    // SPHL (0xF9) — SP = HL
+    decoder.register(0xf9, (regs, _flags, _bus) => {
+        regs.sp = regs.hl;
+        return 5;
+    });
+}
+//# sourceMappingURL=stack.js.map

package/dist/cpu/instructions/stack.js.map

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package/dist/cpu/status8080.d.ts

@@ -0,0 +1,33 @@
+/**
+ * 8080 status word (Bitsby8 cockpit front panel).
+ *
+ * At the start of every machine cycle the 8080 emits a status byte on the data
+ * bus (latched by the 8228 at SYNC); the Altair front panel wires eight of these
+ * to lamps. 8sim executes a whole instruction per `step()`, so there is no single
+ * live machine cycle to reflect — instead we characterize the instruction from
+ * its opcode into one representative status byte. That's exactly what a debugger
+ * single-stepping wants: after each step the lamps show what that instruction
+ * did (fetch, memory read/write, IN/OUT, stack, halt).
+ *
+ * `WO` is active-low on real hardware (1 = read cycle, 0 = write); we keep that
+ * convention so the panel's WO lamp lights on reads, as on the Altair.
+ */
+export declare const STATUS: {
+    readonly INTA: 1;
+    readonly WO: 2;
+    readonly STACK: 4;
+    readonly HLTA: 8;
+    readonly OUT: 16;
+    readonly M1: 32;
+    readonly INP: 64;
+    readonly MEMR: 128;
+};
+/** The status byte characterizing one opcode's machine cycles. */
+export declare function statusByteForOpcode(op: number): number;
+/** A 256-entry lookup so `step()` pays only one array read. */
+export declare function buildStatusTable(): Uint8Array;
+/** The status byte during an interrupt-acknowledge machine cycle. */
+export declare const INTA_STATUS: number;
+/** The idle/reset fetch pattern (about to fetch the first opcode). */
+export declare const FETCH_STATUS: number;
+//# sourceMappingURL=status8080.d.ts.map

package/dist/cpu/status8080.d.ts.map

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package/dist/cpu/status8080.js

@@ -0,0 +1,73 @@
+/**
+ * 8080 status word (Bitsby8 cockpit front panel).
+ *
+ * At the start of every machine cycle the 8080 emits a status byte on the data
+ * bus (latched by the 8228 at SYNC); the Altair front panel wires eight of these
+ * to lamps. 8sim executes a whole instruction per `step()`, so there is no single
+ * live machine cycle to reflect — instead we characterize the instruction from
+ * its opcode into one representative status byte. That's exactly what a debugger
+ * single-stepping wants: after each step the lamps show what that instruction
+ * did (fetch, memory read/write, IN/OUT, stack, halt).
+ *
+ * `WO` is active-low on real hardware (1 = read cycle, 0 = write); we keep that
+ * convention so the panel's WO lamp lights on reads, as on the Altair.
+ */
+export const STATUS = {
+    INTA: 0x01, // interrupt acknowledge
+    WO: 0x02, //   write/output — active LOW (set = a read cycle)
+    STACK: 0x04, // stack access
+    HLTA: 0x08, // halt acknowledge
+    OUT: 0x10, //  output write
+    M1: 0x20, //   first machine cycle (opcode fetch)
+    INP: 0x40, //  input read
+    MEMR: 0x80, // memory read
+};
+const isRst = (op) => (op & 0xc7) === 0xc7; // 11 xxx 111
+// PUSH / CALL (incl. conditional) / RST / XTHL push to the stack; plus the
+// direct memory stores. These make the cycle a write (WO low).
+const writesMemory = (op) => op === 0x32 || // STA
+    op === 0x22 || // SHLD
+    op === 0x02 || op === 0x12 || // STAX B/D
+    op === 0x36 || // MVI M,d8
+    (op >= 0x70 && op <= 0x77 && op !== 0x76) || // MOV M,r
+    op === 0xc5 || op === 0xd5 || op === 0xe5 || op === 0xf5 || // PUSH
+    op === 0xcd || op === 0xc4 || op === 0xcc || op === 0xd4 || op === 0xdc ||
+    op === 0xe4 || op === 0xec || op === 0xf4 || op === 0xfc || // CALL (all)
+    op === 0xe3 || // XTHL
+    isRst(op);
+const touchesStack = (op) => op === 0xc5 || op === 0xd5 || op === 0xe5 || op === 0xf5 || // PUSH
+    op === 0xc1 || op === 0xd1 || op === 0xe1 || op === 0xf1 || // POP
+    op === 0xcd || op === 0xc4 || op === 0xcc || op === 0xd4 || op === 0xdc ||
+    op === 0xe4 || op === 0xec || op === 0xf4 || op === 0xfc || // CALL (all)
+    op === 0xc9 || op === 0xc0 || op === 0xc8 || op === 0xd0 || op === 0xd8 ||
+    op === 0xe0 || op === 0xe8 || op === 0xf0 || op === 0xf8 || // RET (all)
+    op === 0xe3 || // XTHL
+    isRst(op);
+/** The status byte characterizing one opcode's machine cycles. */
+export function statusByteForOpcode(op) {
+    // Every instruction begins with an M1 opcode fetch — a memory read.
+    let s = STATUS.M1 | STATUS.MEMR | STATUS.WO;
+    if (op === 0x76)
+        return s | STATUS.HLTA; // HLT
+    if (op === 0xdb)
+        s |= STATUS.INP; // IN port
+    if (op === 0xd3)
+        s = (s | STATUS.OUT) & ~STATUS.WO; // OUT port (a write cycle)
+    if (touchesStack(op))
+        s |= STATUS.STACK;
+    if (writesMemory(op))
+        s &= ~STATUS.WO; // a write cycle drives WO low
+    return s;
+}
+/** A 256-entry lookup so `step()` pays only one array read. */
+export function buildStatusTable() {
+    const t = new Uint8Array(256);
+    for (let op = 0; op < 256; op++)
+        t[op] = statusByteForOpcode(op);
+    return t;
+}
+/** The status byte during an interrupt-acknowledge machine cycle. */
+export const INTA_STATUS = STATUS.INTA | STATUS.M1 | STATUS.WO;
+/** The idle/reset fetch pattern (about to fetch the first opcode). */
+export const FETCH_STATUS = STATUS.M1 | STATUS.MEMR | STATUS.WO;
+//# sourceMappingURL=status8080.js.map

package/dist/cpu/status8080.js.map

@@ -0,0 +1 @@
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package/dist/cpu/z80/CpuZ80.d.ts

@@ -0,0 +1,53 @@
+import type { IBus } from '../../interfaces/IBus.js';
+import type { ICpu, CpuState } from '../../interfaces/ICpu.js';
+import type { IInterruptController } from '../../interfaces/IInterruptController.js';
+import type { Z80Core } from './types.js';
+import { RegistersZ80 } from './RegistersZ80.js';
+import { FlagsZ80 } from './FlagsZ80.js';
+/**
+ * Zilog Z80 CPU core. Fully implements the documented and undocumented
+ * instruction set, IM 0/1/2 + NMI interrupts, and the shadow/index register file.
+ *
+ * Interrupt conventions (no change to {@link IInterruptController} required):
+ *   - IM 0: the byte from `acknowledge()` is executed as an opcode. The stock
+ *     controller returns a single-byte RST, which is the common real-world case.
+ *   - IM 2: the `acknowledge()` byte is used as the low half of the vector-table
+ *     pointer (`(I << 8) | ackByte`); the vector is read from memory.
+ * A maskable interrupt is serviced only when IFF1 is set; NMI (via
+ * {@link triggerNMI}) is always serviced and ignores IFF1.
+ */
+export declare class CpuZ80 implements ICpu, Z80Core {
+    readonly regs: RegistersZ80;
+    readonly flags: FlagsZ80;
+    readonly bus: IBus;
+    private readonly pic;
+    private readonly dec;
+    iff1: boolean;
+    iff2: boolean;
+    im: 0 | 1 | 2;
+    pendingEI: boolean;
+    halted: boolean;
+    private pendingNMI;
+    /** Front-panel status byte of the last instruction (8080-style approximation). */
+    private lastStatus;
+    private readonly statusTable;
+    constructor(bus: IBus, pic: IInterruptController);
+    /** Program counter accessor (ICpu). */
+    get pc(): number;
+    set pc(v: number);
+    /** Uniform register/flags snapshot for introspection (ICpu). */
+    state(): CpuState;
+    /** Assert a non-maskable interrupt (edge-triggered latch; serviced next step). */
+    triggerNMI(): void;
+    fetchByte(): number;
+    fetchWord(): number;
+    push16(v: number): void;
+    pop16(): number;
+    reset(): void;
+    step(): number;
+    private serviceINT;
+    private serviceNMI;
+    /** Run until halted or `maxCycles` T-states elapse; returns total T-states. */
+    run(maxCycles?: number): bigint;
+}
+//# sourceMappingURL=CpuZ80.d.ts.map

package/dist/cpu/z80/CpuZ80.d.ts.map

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package/dist/cpu/z80/CpuZ80.js

@@ -0,0 +1,168 @@
+import { RegistersZ80 } from './RegistersZ80.js';
+import { FlagsZ80 } from './FlagsZ80.js';
+import { DecoderZ80 } from './DecoderZ80.js';
+import { buildStatusTable, FETCH_STATUS, INTA_STATUS } from '../status8080.js';
+import { u16 } from '../../util/bits.js';
+/**
+ * Zilog Z80 CPU core. Fully implements the documented and undocumented
+ * instruction set, IM 0/1/2 + NMI interrupts, and the shadow/index register file.
+ *
+ * Interrupt conventions (no change to {@link IInterruptController} required):
+ *   - IM 0: the byte from `acknowledge()` is executed as an opcode. The stock
+ *     controller returns a single-byte RST, which is the common real-world case.
+ *   - IM 2: the `acknowledge()` byte is used as the low half of the vector-table
+ *     pointer (`(I << 8) | ackByte`); the vector is read from memory.
+ * A maskable interrupt is serviced only when IFF1 is set; NMI (via
+ * {@link triggerNMI}) is always serviced and ignores IFF1.
+ */
+export class CpuZ80 {
+    regs = new RegistersZ80();
+    flags = new FlagsZ80();
+    bus;
+    pic;
+    dec;
+    iff1 = false;
+    iff2 = false;
+    im = 0;
+    pendingEI = false;
+    halted = false;
+    pendingNMI = false;
+    /** Front-panel status byte of the last instruction (8080-style approximation). */
+    lastStatus = FETCH_STATUS;
+    statusTable = buildStatusTable();
+    constructor(bus, pic) {
+        this.bus = bus;
+        this.pic = pic;
+        this.dec = new DecoderZ80();
+    }
+    /** Program counter accessor (ICpu). */
+    get pc() { return this.regs.pc; }
+    set pc(v) { this.regs.pc = u16(v); }
+    /** Uniform register/flags snapshot for introspection (ICpu). */
+    state() {
+        const r = this.regs;
+        return { pc: r.pc, sp: r.sp, a: r.a, f: this.flags.toByte(), b: r.b, c: r.c, d: r.d, e: r.e, h: r.h, l: r.l, halted: this.halted, inte: this.iff1, intPending: this.pic.hasPendingInterrupt(), status: this.lastStatus };
+    }
+    /** Assert a non-maskable interrupt (edge-triggered latch; serviced next step). */
+    triggerNMI() {
+        this.pendingNMI = true;
+    }
+    // --- Z80Core memory/stack helpers ---
+    fetchByte() {
+        const b = this.bus.read(this.regs.pc);
+        this.regs.pc = u16(this.regs.pc + 1);
+        return b;
+    }
+    fetchWord() {
+        const lo = this.fetchByte();
+        const hi = this.fetchByte();
+        return (hi << 8) | lo;
+    }
+    push16(v) {
+        this.regs.sp = u16(this.regs.sp - 1);
+        this.bus.write(this.regs.sp, (v >> 8) & 0xff);
+        this.regs.sp = u16(this.regs.sp - 1);
+        this.bus.write(this.regs.sp, v & 0xff);
+    }
+    pop16() {
+        const lo = this.bus.read(this.regs.sp);
+        this.regs.sp = u16(this.regs.sp + 1);
+        const hi = this.bus.read(this.regs.sp);
+        this.regs.sp = u16(this.regs.sp + 1);
+        return (hi << 8) | lo;
+    }
+    reset() {
+        this.regs.reset();
+        this.flags.reset();
+        this.iff1 = false;
+        this.iff2 = false;
+        this.im = 0;
+        this.pendingEI = false;
+        this.halted = false;
+        this.pendingNMI = false;
+        this.lastStatus = FETCH_STATUS;
+    }
+    step() {
+        // 1. NMI has top priority; it wakes HALT and ignores IFF1.
+        if (this.pendingNMI)
+            return this.serviceNMI();
+        // 2. Commit a pending EI: the instruction after EI is the first that can be
+        //    interrupted, so remember whether the commit happened *this* step.
+        const eiJustCommitted = this.pendingEI;
+        if (this.pendingEI) {
+            this.iff1 = true;
+            this.iff2 = true;
+            this.pendingEI = false;
+        }
+        // 3. Maskable interrupt (not on the very step EI committed).
+        if (this.iff1 && !eiJustCommitted && this.pic.hasPendingInterrupt()) {
+            return this.serviceINT();
+        }
+        // 4. HALT executes internal NOPs; refresh keeps ticking.
+        if (this.halted) {
+            this.regs.incR();
+            return 4;
+        }
+        // 5. Fetch opcode, absorbing any DD/FD prefix chain.
+        let op = this.fetchByte();
+        this.regs.incR();
+        let table = this.dec.main;
+        let prefixT = 0;
+        while (op === 0xdd || op === 0xfd) {
+            table = op === 0xdd ? this.dec.mainIX : this.dec.mainIY;
+            prefixT += 4;
+            op = this.fetchByte();
+            this.regs.incR();
+        }
+        this.lastStatus = this.statusTable[op]; // latch the panel status byte
+        return prefixT + table[op](this);
+    }
+    serviceINT() {
+        this.iff1 = false;
+        this.iff2 = false;
+        this.halted = false;
+        this.lastStatus = INTA_STATUS;
+        this.regs.incR();
+        const ackByte = this.bus.acknowledgeInterrupt();
+        switch (this.im) {
+            case 0: {
+                // Execute the ack byte as an opcode (PC not advanced for this fetch).
+                // The stock controller returns a single-byte RST n.
+                return 2 + this.dec.main[ackByte & 0xff](this);
+            }
+            case 1:
+                this.push16(this.regs.pc);
+                this.regs.pc = 0x0038;
+                this.regs.wz = 0x0038;
+                return 13;
+            case 2: {
+                const vector = ((this.regs.i << 8) | (ackByte & 0xff)) & 0xffff;
+                this.push16(this.regs.pc);
+                const lo = this.bus.read(vector);
+                const hi = this.bus.read(u16(vector + 1));
+                this.regs.pc = (hi << 8) | lo;
+                this.regs.wz = this.regs.pc;
+                return 19;
+            }
+        }
+    }
+    serviceNMI() {
+        this.pendingNMI = false;
+        this.halted = false;
+        this.iff1 = false; // IFF2 preserved so RETN can restore IFF1
+        this.regs.incR();
+        this.push16(this.regs.pc);
+        this.regs.pc = 0x0066;
+        this.regs.wz = 0x0066;
+        return 11;
+    }
+    /** Run until halted or `maxCycles` T-states elapse; returns total T-states. */
+    run(maxCycles = Infinity) {
+        let total = 0n;
+        while (!this.halted && total < BigInt(maxCycles)) {
+            total += BigInt(this.step());
+        }
+        return total;
+    }
+}
+//# sourceMappingURL=CpuZ80.js.map

package/dist/cpu/z80/CpuZ80.js.map

@@ -0,0 +1 @@
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package/dist/cpu/z80/DecoderZ80.d.ts

@@ -0,0 +1,26 @@
+import type { Z80Handler, Z80IndexedCbHandler } from './types.js';
+/**
+ * The Z80 opcode tables. `main`/`mainIX`/`mainIY` are the three views of the
+ * unprefixed space; `cb` and `ed` are the CB- and ED-prefixed spaces; `idxCb`
+ * holds the DDCB/FDCB bodies (address precomputed by the dispatcher, shared
+ * between IX and IY).
+ */
+export declare class DecoderZ80 {
+    readonly main: Z80Handler[];
+    readonly mainIX: Z80Handler[];
+    readonly mainIY: Z80Handler[];
+    readonly cb: Z80Handler[];
+    readonly ed: Z80Handler[];
+    readonly idxCb: Z80IndexedCbHandler[];
+    constructor();
+    private buildMain;
+    /**
+     * main[0xCB]: plain CB dispatch (fetch op, R++, run cb table).
+     * mainIX/IY[0xCB]: DDCB/FDCB dispatch — displacement fetched BEFORE the final
+     * opcode, and that final byte is NOT an M1 fetch (only DD and CB tick R).
+     */
+    private wireCbDispatch;
+    /** main/mainIX/mainIY[0xED]: identical ED dispatch (a DD/FD before ED is ignored). */
+    private wireEdDispatch;
+}
+//# sourceMappingURL=DecoderZ80.d.ts.map

package/dist/cpu/z80/DecoderZ80.d.ts.map

@@ -0,0 +1 @@
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package/dist/cpu/z80/DecoderZ80.js

@@ -0,0 +1,107 @@
+import { HL_VIEW, IX_VIEW, IY_VIEW, sext8 } from './views.js';
+import { registerLoad } from './instructions/load.js';
+import { registerExchange } from './instructions/exchange.js';
+import { registerAlu8 } from './instructions/alu8.js';
+import { registerAlu16 } from './instructions/alu16.js';
+import { registerRotate } from './instructions/rotate.js';
+import { registerJump } from './instructions/jump.js';
+import { registerStack } from './instructions/stack.js';
+import { registerIO } from './instructions/io.js';
+import { registerControl } from './instructions/control.js';
+import { registerBits } from './instructions/bits.js';
+import { registerEd } from './instructions/ed.js';
+import { registerBlock } from './instructions/block.js';
+/** Build a 256-entry table pre-filled with a warn-on-execute stub. */
+function makeTable(name) {
+    return new Array(256).fill((_cpu) => 4).map((_, i) => {
+        return (_cpu) => {
+            console.warn(`[Z80] Unimplemented ${name} opcode: 0x${i.toString(16).padStart(2, '0')}`);
+            return 4;
+        };
+    });
+}
+function makeIdxCbTable() {
+    return new Array(256).fill((_c, _a) => 8).map((_, i) => {
+        return (_cpu, _addr) => {
+            console.warn(`[Z80] Unimplemented DDCB opcode: 0x${i.toString(16).padStart(2, '0')}`);
+            return 8;
+        };
+    });
+}
+/**
+ * The Z80 opcode tables. `main`/`mainIX`/`mainIY` are the three views of the
+ * unprefixed space; `cb` and `ed` are the CB- and ED-prefixed spaces; `idxCb`
+ * holds the DDCB/FDCB bodies (address precomputed by the dispatcher, shared
+ * between IX and IY).
+ */
+export class DecoderZ80 {
+    main = makeTable('main');
+    mainIX = makeTable('mainIX');
+    mainIY = makeTable('mainIY');
+    cb = makeTable('CB');
+    ed = makeTable('ED');
+    idxCb = makeIdxCbTable();
+    constructor() {
+        // Unassigned ED slots behave as NONI + NOP (8 T-states, no warning spam).
+        for (let i = 0; i < 256; i++) {
+            this.ed[i] = (_cpu) => 8;
+        }
+        // Build the three views of the main table.
+        this.buildMain(this.main, HL_VIEW);
+        this.buildMain(this.mainIX, IX_VIEW);
+        this.buildMain(this.mainIY, IY_VIEW);
+        // CB-prefixed space (shared) and its DDCB/FDCB bodies.
+        registerBits(this.cb, this.idxCb);
+        // ED-prefixed space (shared): misc + block ops.
+        registerEd(this.ed);
+        registerBlock(this.ed);
+        // Wire the prefix dispatchers into each main table.
+        this.wireCbDispatch();
+        this.wireEdDispatch();
+    }
+    buildMain(table, view) {
+        registerLoad(table, view);
+        registerExchange(table, view);
+        registerAlu8(table, view);
+        registerAlu16(table, view);
+        registerRotate(table, view);
+        registerJump(table, view);
+        registerStack(table, view);
+        registerIO(table, view);
+        registerControl(table, view);
+    }
+    /**
+     * main[0xCB]: plain CB dispatch (fetch op, R++, run cb table).
+     * mainIX/IY[0xCB]: DDCB/FDCB dispatch — displacement fetched BEFORE the final
+     * opcode, and that final byte is NOT an M1 fetch (only DD and CB tick R).
+     */
+    wireCbDispatch() {
+        this.main[0xcb] = (cpu) => {
+            const op = cpu.fetchByte();
+            cpu.regs.incR();
+            return this.cb[op](cpu);
+        };
+        const idxDispatch = (getPair) => (cpu) => {
+            const d = sext8(cpu.fetchByte());
+            cpu.regs.incR(); // the CB prefix byte
+            const addr = (getPair(cpu) + d) & 0xffff;
+            cpu.regs.wz = addr;
+            const op = cpu.fetchByte(); // final byte — not an M1 cycle
+            return this.idxCb[op](cpu, addr);
+        };
+        this.mainIX[0xcb] = idxDispatch((cpu) => cpu.regs.ix);
+        this.mainIY[0xcb] = idxDispatch((cpu) => cpu.regs.iy);
+    }
+    /** main/mainIX/mainIY[0xED]: identical ED dispatch (a DD/FD before ED is ignored). */
+    wireEdDispatch() {
+        const dispatch = (cpu) => {
+            const op = cpu.fetchByte();
+            cpu.regs.incR();
+            return this.ed[op](cpu);
+        };
+        this.main[0xed] = dispatch;
+        this.mainIX[0xed] = dispatch;
+        this.mainIY[0xed] = dispatch;
+    }
+}
+//# sourceMappingURL=DecoderZ80.js.map

package/dist/cpu/z80/DecoderZ80.js.map

@@ -0,0 +1 @@
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package/dist/cpu/z80/FlagsZ80.d.ts

@@ -0,0 +1,27 @@
+/**
+ * Zilog Z80 flags register (F).
+ *
+ * Byte layout: S Z Y H X PV N C  (bit 7 → bit 0)
+ *   S  (0x80) Sign
+ *   Z  (0x40) Zero
+ *   Y  (0x20) undocumented copy of result bit 5
+ *   H  (0x10) Half-carry
+ *   X  (0x08) undocumented copy of result bit 3
+ *   PV (0x04) Parity / overflow (context-dependent)
+ *   N  (0x02) Add/Subtract (set by subtractions)
+ *   C  (0x01) Carry
+ */
+export declare class FlagsZ80 {
+    s: boolean;
+    z: boolean;
+    y: boolean;
+    h: boolean;
+    x: boolean;
+    pv: boolean;
+    n: boolean;
+    c: boolean;
+    toByte(): number;
+    fromByte(b: number): void;
+    reset(): void;
+}
+//# sourceMappingURL=FlagsZ80.d.ts.map

package/dist/cpu/z80/FlagsZ80.d.ts.map

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