@joezilla/8sim 0.10.0

package/dist/cards/RtcCard.d.ts.map

@@ -0,0 +1 @@
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package/dist/cards/RtcCard.js

@@ -0,0 +1,61 @@
+import { u8 } from '../util/bits.js';
+/** Deterministic default when no host clock is wired (tests, headless builds). */
+const EPOCH_ZERO = () => new Date(0);
+const bcd = (n) => (((Math.floor(n / 10) % 10) << 4) | (n % 10)) & 0xff;
+/**
+ * National MM58167 real-time clock (Story 5.10). A 32-register clock/calendar
+ * chip on an I/O window: the counter registers (0x00–0x07) read the host wall
+ * clock as BCD, the rest (RAM / compare / interrupt / status) are plain storage.
+ *
+ * The host time comes from `ctx.services.clock` (a `() => Date`), so the machine
+ * reads real time while tests stay deterministic by injecting a fixed clock.
+ * Writes to the live counters are ignored — you can't set the host's clock.
+ */
+export class RtcCard {
+    id;
+    base;
+    now;
+    ram = new Uint8Array(0x20); // 0x08..0x1F are read/write storage
+    dev;
+    constructor(id = 'rtc', opts = {}, clock = EPOCH_ZERO) {
+        this.id = id;
+        this.base = (opts.base ?? 0x40) & 0xff;
+        this.now = clock;
+        const self = this;
+        const ports = [];
+        for (let i = 0; i < 0x20; i++)
+            ports.push((this.base + i) & 0xff);
+        this.dev = {
+            id: `${id}:io`,
+            basePorts: ports,
+            ioRead: (port) => self.readReg((port - self.base) & 0x1f),
+            ioWrite: (port, value) => self.writeReg((port - self.base) & 0x1f, value),
+            reset: () => self.ram.fill(0),
+        };
+    }
+    attach(bus) {
+        bus.attachIODevice(this.dev);
+    }
+    reset() {
+        this.ram.fill(0);
+    }
+    readReg(off) {
+        const d = this.now();
+        switch (off) {
+            case 0x00: return 0; //                     thousandths of a second
+            case 0x01: return bcd(Math.floor(d.getMilliseconds() / 10)); // hundredths
+            case 0x02: return bcd(d.getSeconds());
+            case 0x03: return bcd(d.getMinutes());
+            case 0x04: return bcd(d.getHours());
+            case 0x05: return bcd(d.getDay() + 1); //   day of week, 1–7
+            case 0x06: return bcd(d.getDate()); //      day of month
+            case 0x07: return bcd(d.getMonth() + 1); // month, 1–12
+            default: return this.ram[off] ?? 0; //      RAM / compare / status registers
+        }
+    }
+    writeReg(off, value) {
+        if (off > 0x07)
+            this.ram[off] = u8(value); // live counters are read-only
+    }
+}
+//# sourceMappingURL=RtcCard.js.map

package/dist/cards/RtcCard.js.map

@@ -0,0 +1 @@
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package/dist/cards/SerialCard.d.ts

@@ -0,0 +1,31 @@
+import type { IS100Card } from '../interfaces/IS100Card.js';
+import type { IIODevice } from '../interfaces/IIODevice.js';
+import type { Bus } from '../bus/Bus.js';
+/** The UART chip a serial card is built around. */
+export type SerialChip = 'i8251' | 'm6850';
+/** A serial channel: an I/O device that also streams characters. */
+interface SerialChannel extends IIODevice {
+    onTransmit(cb: (byte: number) => void): void;
+    enqueueRx(byte: number): void;
+    reset(): void;
+}
+export interface SerialCardOptions {
+    readonly dataPort?: number;
+    readonly ctrlPort?: number;
+    readonly chip?: SerialChip;
+}
+/**
+ * A single-channel serial (UART) card — the general console board authored
+ * serial cards resolve to (Story 5.7). Unlike a bare chip wrapped in
+ * `deviceCard`, it exposes its `channel` so the host wires it to the operator
+ * terminal (ConsoleHub looks for `.channel`). Backed by an 8251 or a 6850.
+ */
+export declare class SerialCard implements IS100Card {
+    readonly id: string;
+    readonly channel: SerialChannel;
+    constructor(id?: string, opts?: SerialCardOptions);
+    attach(bus: Bus): void;
+    reset(): void;
+}
+export {};
+//# sourceMappingURL=SerialCard.d.ts.map

package/dist/cards/SerialCard.d.ts.map

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package/dist/cards/SerialCard.js

@@ -0,0 +1,28 @@
+import { Usart8251 } from './Usart8251.js';
+import { Mc6850Acia } from './Mc6850Acia.js';
+/**
+ * A single-channel serial (UART) card — the general console board authored
+ * serial cards resolve to (Story 5.7). Unlike a bare chip wrapped in
+ * `deviceCard`, it exposes its `channel` so the host wires it to the operator
+ * terminal (ConsoleHub looks for `.channel`). Backed by an 8251 or a 6850.
+ */
+export class SerialCard {
+    id;
+    channel;
+    constructor(id = 'serial', opts = {}) {
+        const dataPort = opts.dataPort ?? 0x10;
+        const ctrlPort = opts.ctrlPort ?? 0x11;
+        this.id = id;
+        this.channel =
+            opts.chip === 'm6850'
+                ? new Mc6850Acia(`${id}:ch`, ctrlPort, dataPort) // 6850: status/ctrl port, data port
+                : new Usart8251(`${id}:ch`, dataPort, ctrlPort); // 8251: data port, ctrl port
+    }
+    attach(bus) {
+        bus.attachIODevice(this.channel);
+    }
+    reset() {
+        this.channel.reset();
+    }
+}
+//# sourceMappingURL=SerialCard.js.map

package/dist/cards/SerialCard.js.map

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package/dist/cards/Tr1602Uart.d.ts

@@ -0,0 +1,55 @@
+import type { IIODevice } from '../interfaces/IIODevice.js';
+type TransmitCallback = (byte: number) => void;
+type ControlCallback = (value: number) => void;
+/**
+ * TR1602B / TMS-6011 / AY-5-1013 / HD-6402 standalone UART, as used on the
+ * IMSAI MIO board. Unlike the Intel 8251 (see {@link Usart8251}), this chip has
+ * no software-writable mode/command registers — the data format is fixed by
+ * hardware jumpers. There is therefore no initialization sequence, and the
+ * transmitter is ready immediately after power-on. The UART itself has no CTS
+ * awareness: TxRDY (TBRE) is high whenever the transmit buffer is empty.
+ *
+ * Occupies two consecutive I/O ports:
+ *   dataPort   — read: received byte (clears Data-Received); write: transmit
+ *   statusPort — read: status flags; write: board control register (8212)
+ *
+ * Status byte (SIO-2-compatible wiring — the recommended MIO configuration):
+ *   bit0 TxRDY   (TBRE)  — 1 = ready to accept a byte to transmit (always 1)
+ *   bit1 RxRDY   (DR)    — 1 = a received byte is available
+ *   bit2 TxEMPTY (TRE)   — 1 = transmit shift register idle (always 1)
+ *   bit3 PE              — parity error on the last received byte
+ *   bit4 OE              — overrun (byte arrived before the previous was read)
+ *   bit5 FE              — framing error on the last received byte
+ *   bit6/7               — board-specific, unused here
+ */
+export declare class Tr1602Uart implements IIODevice {
+    private readonly dataPort;
+    private readonly statusPort;
+    readonly id: string;
+    readonly basePorts: ReadonlyArray<number>;
+    private errorFlags;
+    private rxQueue;
+    private controlReg;
+    private transmitCb;
+    private controlCb;
+    constructor(id: string, dataPort: number, statusPort: number);
+    ioRead(port: number): number;
+    ioWrite(port: number, value: number): void;
+    reset(): void;
+    /**
+     * Feed a received byte to the UART. Sets Data-Received (RxRDY). A byte
+     * arriving while the single-byte buffer is still full flags an overrun (OE),
+     * mirroring the TR1602's lack of a receive FIFO.
+     */
+    enqueueRx(byte: number): void;
+    onTransmit(cb: TransmitCallback): void;
+    /** Register a callback fired on writes to the board control register. */
+    onControl(cb: ControlCallback): void;
+    /** Last value written to the board control register (statusPort write). */
+    get control(): number;
+    /** Inject receive error flags (parity / overrun / framing) for the next read. */
+    setErrors(pe: boolean, oe: boolean, fe: boolean): void;
+    private buildStatus;
+}
+export {};
+//# sourceMappingURL=Tr1602Uart.d.ts.map

package/dist/cards/Tr1602Uart.d.ts.map

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package/dist/cards/Tr1602Uart.js

@@ -0,0 +1,102 @@
+import { u8 } from '../util/bits.js';
+/**
+ * TR1602B / TMS-6011 / AY-5-1013 / HD-6402 standalone UART, as used on the
+ * IMSAI MIO board. Unlike the Intel 8251 (see {@link Usart8251}), this chip has
+ * no software-writable mode/command registers — the data format is fixed by
+ * hardware jumpers. There is therefore no initialization sequence, and the
+ * transmitter is ready immediately after power-on. The UART itself has no CTS
+ * awareness: TxRDY (TBRE) is high whenever the transmit buffer is empty.
+ *
+ * Occupies two consecutive I/O ports:
+ *   dataPort   — read: received byte (clears Data-Received); write: transmit
+ *   statusPort — read: status flags; write: board control register (8212)
+ *
+ * Status byte (SIO-2-compatible wiring — the recommended MIO configuration):
+ *   bit0 TxRDY   (TBRE)  — 1 = ready to accept a byte to transmit (always 1)
+ *   bit1 RxRDY   (DR)    — 1 = a received byte is available
+ *   bit2 TxEMPTY (TRE)   — 1 = transmit shift register idle (always 1)
+ *   bit3 PE              — parity error on the last received byte
+ *   bit4 OE              — overrun (byte arrived before the previous was read)
+ *   bit5 FE              — framing error on the last received byte
+ *   bit6/7               — board-specific, unused here
+ */
+export class Tr1602Uart {
+    dataPort;
+    statusPort;
+    id;
+    basePorts;
+    // bit0=PE, bit1=OE, bit2=FE — positioned into status bits 3-5 when read.
+    errorFlags = 0;
+    rxQueue = [];
+    controlReg = 0;
+    transmitCb;
+    controlCb;
+    constructor(id, dataPort, statusPort) {
+        this.dataPort = dataPort;
+        this.statusPort = statusPort;
+        this.id = id;
+        this.basePorts = [dataPort, statusPort];
+    }
+    ioRead(port) {
+        if (port === this.statusPort) {
+            return this.buildStatus();
+        }
+        // Data port read: pull the received byte, clearing Data-Received (DR).
+        const byte = this.rxQueue.shift();
+        if (this.rxQueue.length === 0) {
+            this.errorFlags &= ~0x02; // overrun clears once the buffer drains
+        }
+        return byte !== undefined ? byte : 0xff;
+    }
+    ioWrite(port, value) {
+        if (port === this.statusPort) {
+            // Board control register (8212): DTR / RTS / cassette motor / etc.
+            this.controlReg = u8(value);
+            this.controlCb?.(this.controlReg);
+            return;
+        }
+        // Data port write: transmit immediately. The UART is always ready — no
+        // init sequence and no CTS gating.
+        this.transmitCb?.(u8(value));
+    }
+    reset() {
+        this.errorFlags = 0;
+        this.rxQueue = [];
+        this.controlReg = 0;
+        // transmitCb / controlCb survive reset — they are host wiring.
+    }
+    /**
+     * Feed a received byte to the UART. Sets Data-Received (RxRDY). A byte
+     * arriving while the single-byte buffer is still full flags an overrun (OE),
+     * mirroring the TR1602's lack of a receive FIFO.
+     */
+    enqueueRx(byte) {
+        if (this.rxQueue.length > 0) {
+            this.errorFlags |= 0x02; // OE: previous byte was not read in time
+        }
+        this.rxQueue.push(u8(byte));
+    }
+    onTransmit(cb) {
+        this.transmitCb = cb;
+    }
+    /** Register a callback fired on writes to the board control register. */
+    onControl(cb) {
+        this.controlCb = cb;
+    }
+    /** Last value written to the board control register (statusPort write). */
+    get control() {
+        return this.controlReg;
+    }
+    /** Inject receive error flags (parity / overrun / framing) for the next read. */
+    setErrors(pe, oe, fe) {
+        this.errorFlags = (pe ? 0x01 : 0) | (oe ? 0x02 : 0) | (fe ? 0x04 : 0);
+    }
+    buildStatus() {
+        const txRDY = 0x01; // transmit buffer always ready
+        const rxRDY = this.rxQueue.length > 0 ? 0x02 : 0;
+        const txEMPTY = 0x04; // transmit register always idle
+        const errors = (this.errorFlags & 0x07) << 3;
+        return txRDY | rxRDY | txEMPTY | errors;
+    }
+}
+//# sourceMappingURL=Tr1602Uart.js.map

package/dist/cards/Tr1602Uart.js.map

@@ -0,0 +1 @@
+{"version":3,"file":"Tr1602Uart.js","sourceRoot":"","sources":["../../src/cards/Tr1602Uart.ts"],"names":[],"mappings":"AACA,OAAO,EAAE,EAAE,EAAE,MAAM,iBAAiB,CAAC;AAKrC;;;;;;;;;;;;;;;;;;;;GAoBG;AACH,MAAM,OAAO,UAAU;IAWoB;IAAmC;IAVnE,EAAE,CAAS;IACX,SAAS,CAAwB;IAE1C,yEAAyE;IACjE,UAAU,GAAG,CAAC,CAAC;IACf,OAAO,GAAa,EAAE,CAAC;IACvB,UAAU,GAAG,CAAC,CAAC;IACf,UAAU,CAA+B;IACzC,SAAS,CAA8B;IAE/C,YAAY,EAAU,EAAmB,QAAgB,EAAmB,UAAkB;QAArD,aAAQ,GAAR,QAAQ,CAAQ;QAAmB,eAAU,GAAV,UAAU,CAAQ;QAC5F,IAAI,CAAC,EAAE,GAAG,EAAE,CAAC;QACb,IAAI,CAAC,SAAS,GAAG,CAAC,QAAQ,EAAE,UAAU,CAAC,CAAC;IAC1C,CAAC;IAED,MAAM,CAAC,IAAY;QACjB,IAAI,IAAI,KAAK,IAAI,CAAC,UAAU,EAAE,CAAC;YAC7B,OAAO,IAAI,CAAC,WAAW,EAAE,CAAC;QAC5B,CAAC;QACD,uEAAuE;QACvE,MAAM,IAAI,GAAG,IAAI,CAAC,OAAO,CAAC,KAAK,EAAE,CAAC;QAClC,IAAI,IAAI,CAAC,OAAO,CAAC,MAAM,KAAK,CAAC,EAAE,CAAC;YAC9B,IAAI,CAAC,UAAU,IAAI,CAAC,IAAI,CAAC,CAAC,wCAAwC;QACpE,CAAC;QACD,OAAO,IAAI,KAAK,SAAS,CAAC,CAAC,CAAC,IAAI,CAAC,CAAC,CAAC,IAAI,CAAC;IAC1C,CAAC;IAED,OAAO,CAAC,IAAY,EAAE,KAAa;QACjC,IAAI,IAAI,KAAK,IAAI,CAAC,UAAU,EAAE,CAAC;YAC7B,mEAAmE;YACnE,IAAI,CAAC,UAAU,GAAG,EAAE,CAAC,KAAK,CAAC,CAAC;YAC5B,IAAI,CAAC,SAAS,EAAE,CAAC,IAAI,CAAC,UAAU,CAAC,CAAC;YAClC,OAAO;QACT,CAAC;QACD,uEAAuE;QACvE,mCAAmC;QACnC,IAAI,CAAC,UAAU,EAAE,CAAC,EAAE,CAAC,KAAK,CAAC,CAAC,CAAC;IAC/B,CAAC;IAED,KAAK;QACH,IAAI,CAAC,UAAU,GAAG,CAAC,CAAC;QACpB,IAAI,CAAC,OAAO,GAAG,EAAE,CAAC;QAClB,IAAI,CAAC,UAAU,GAAG,CAAC,CAAC;QACpB,+DAA+D;IACjE,CAAC;IAED;;;;OAIG;IACH,SAAS,CAAC,IAAY;QACpB,IAAI,IAAI,CAAC,OAAO,CAAC,MAAM,GAAG,CAAC,EAAE,CAAC;YAC5B,IAAI,CAAC,UAAU,IAAI,IAAI,CAAC,CAAC,yCAAyC;QACpE,CAAC;QACD,IAAI,CAAC,OAAO,CAAC,IAAI,CAAC,EAAE,CAAC,IAAI,CAAC,CAAC,CAAC;IAC9B,CAAC;IAED,UAAU,CAAC,EAAoB;QAC7B,IAAI,CAAC,UAAU,GAAG,EAAE,CAAC;IACvB,CAAC;IAED,yEAAyE;IACzE,SAAS,CAAC,EAAmB;QAC3B,IAAI,CAAC,SAAS,GAAG,EAAE,CAAC;IACtB,CAAC;IAED,2EAA2E;IAC3E,IAAI,OAAO;QACT,OAAO,IAAI,CAAC,UAAU,CAAC;IACzB,CAAC;IAED,iFAAiF;IACjF,SAAS,CAAC,EAAW,EAAE,EAAW,EAAE,EAAW;QAC7C,IAAI,CAAC,UAAU,GAAG,CAAC,EAAE,CAAC,CAAC,CAAC,IAAI,CAAC,CAAC,CAAC,CAAC,CAAC,GAAG,CAAC,EAAE,CAAC,CAAC,CAAC,IAAI,CAAC,CAAC,CAAC,CAAC,CAAC,GAAG,CAAC,EAAE,CAAC,CAAC,CAAC,IAAI,CAAC,CAAC,CAAC,CAAC,CAAC,CAAC;IACxE,CAAC;IAEO,WAAW;QACjB,MAAM,KAAK,GAAG,IAAI,CAAC,CAAG,+BAA+B;QACrD,MAAM,KAAK,GAAG,IAAI,CAAC,OAAO,CAAC,MAAM,GAAG,CAAC,CAAC,CAAC,CAAC,IAAI,CAAC,CAAC,CAAC,CAAC,CAAC;QACjD,MAAM,OAAO,GAAG,IAAI,CAAC,CAAC,gCAAgC;QACtD,MAAM,MAAM,GAAG,CAAC,IAAI,CAAC,UAAU,GAAG,IAAI,CAAC,IAAI,CAAC,CAAC;QAC7C,OAAO,KAAK,GAAG,KAAK,GAAG,OAAO,GAAG,MAAM,CAAC;IAC1C,CAAC;CACF"}

package/dist/cards/Usart8251.d.ts

@@ -0,0 +1,28 @@
+import type { IIODevice } from '../interfaces/IIODevice.js';
+type TransmitCallback = (byte: number) => void;
+export declare class Usart8251 implements IIODevice {
+    private readonly dataPort;
+    private readonly ctrlPort;
+    readonly id: string;
+    readonly basePorts: ReadonlyArray<number>;
+    private phase;
+    private modeWord;
+    private txEnable;
+    private rxEnable;
+    private errorFlags;
+    private rxQueue;
+    private transmitCb;
+    private ctsActive;
+    private dsrActive;
+    constructor(id: string, dataPort: number, ctrlPort: number);
+    ioWrite(port: number, value: number): void;
+    ioRead(port: number): number;
+    reset(): void;
+    enqueueRx(byte: number): void;
+    onTransmit(cb: TransmitCallback): void;
+    setCts(active: boolean): void;
+    setDsr(active: boolean): void;
+    private buildStatus;
+}
+export {};
+//# sourceMappingURL=Usart8251.d.ts.map

package/dist/cards/Usart8251.d.ts.map

@@ -0,0 +1 @@
+{"version":3,"file":"Usart8251.d.ts","sourceRoot":"","sources":["../../src/cards/Usart8251.ts"],"names":[],"mappings":"AAAA,OAAO,KAAK,EAAE,SAAS,EAAE,MAAM,4BAA4B,CAAC;AAG5D,KAAK,gBAAgB,GAAG,CAAC,IAAI,EAAE,MAAM,KAAK,IAAI,CAAC;AAE/C,qBAAa,SAAU,YAAW,SAAS;IAejB,OAAO,CAAC,QAAQ,CAAC,QAAQ;IAAU,OAAO,CAAC,QAAQ,CAAC,QAAQ;IAdpF,QAAQ,CAAC,EAAE,EAAE,MAAM,CAAC;IACpB,QAAQ,CAAC,SAAS,EAAE,aAAa,CAAC,MAAM,CAAC,CAAC;IAE1C,OAAO,CAAC,KAAK,CAA8B;IAC3C,OAAO,CAAC,QAAQ,CAAK;IACrB,OAAO,CAAC,QAAQ,CAAS;IACzB,OAAO,CAAC,QAAQ,CAAS;IAEzB,OAAO,CAAC,UAAU,CAAK;IACvB,OAAO,CAAC,OAAO,CAAgB;IAC/B,OAAO,CAAC,UAAU,CAA+B;IACjD,OAAO,CAAC,SAAS,CAAQ;IACzB,OAAO,CAAC,SAAS,CAAQ;gBAEb,EAAE,EAAE,MAAM,EAAmB,QAAQ,EAAE,MAAM,EAAmB,QAAQ,EAAE,MAAM;IAK5F,OAAO,CAAC,IAAI,EAAE,MAAM,EAAE,KAAK,EAAE,MAAM,GAAG,IAAI;IA6B1C,MAAM,CAAC,IAAI,EAAE,MAAM,GAAG,MAAM;IAQ5B,KAAK,IAAI,IAAI;IAUb,SAAS,CAAC,IAAI,EAAE,MAAM,GAAG,IAAI;IAI7B,UAAU,CAAC,EAAE,EAAE,gBAAgB,GAAG,IAAI;IAItC,MAAM,CAAC,MAAM,EAAE,OAAO,GAAG,IAAI;IAI7B,MAAM,CAAC,MAAM,EAAE,OAAO,GAAG,IAAI;IAI7B,OAAO,CAAC,WAAW;CAQpB"}

package/dist/cards/Usart8251.js

@@ -0,0 +1,88 @@
+import { u8 } from '../util/bits.js';
+export class Usart8251 {
+    dataPort;
+    ctrlPort;
+    id;
+    basePorts;
+    phase = 'mode';
+    modeWord = 0;
+    txEnable = false;
+    rxEnable = false;
+    // 3-bit error field: bit0=PE, bit1=OE, bit2=FE — packed into status bits 3-5
+    errorFlags = 0;
+    rxQueue = [];
+    transmitCb;
+    ctsActive = true;
+    dsrActive = true;
+    constructor(id, dataPort, ctrlPort) {
+        this.dataPort = dataPort;
+        this.ctrlPort = ctrlPort;
+        this.id = id;
+        this.basePorts = [dataPort, ctrlPort];
+    }
+    ioWrite(port, value) {
+        if (port === this.ctrlPort) {
+            if (this.phase === 'mode') {
+                this.modeWord = value;
+                this.phase = 'command';
+                return;
+            }
+            if ((value & 0x40) !== 0) {
+                this.phase = 'mode';
+                this.txEnable = false;
+                this.rxEnable = false;
+                this.errorFlags = 0;
+                this.rxQueue = [];
+                return;
+            }
+            this.txEnable = (value & 0x01) !== 0;
+            this.rxEnable = (value & 0x04) !== 0;
+            if ((value & 0x10) !== 0) {
+                this.errorFlags = 0;
+            }
+            return;
+        }
+        if (port === this.dataPort) {
+            if (this.txEnable && this.ctsActive) {
+                this.transmitCb?.(u8(value));
+            }
+        }
+    }
+    ioRead(port) {
+        if (port === this.ctrlPort) {
+            return this.buildStatus();
+        }
+        const byte = this.rxQueue.shift();
+        return byte !== undefined ? byte : 0xff;
+    }
+    reset() {
+        this.phase = 'mode';
+        this.modeWord = 0;
+        this.txEnable = false;
+        this.rxEnable = false;
+        this.errorFlags = 0;
+        this.rxQueue = [];
+        // transmitCb, ctsActive, dsrActive survive reset — they are host wiring
+    }
+    enqueueRx(byte) {
+        this.rxQueue.push(u8(byte));
+    }
+    onTransmit(cb) {
+        this.transmitCb = cb;
+    }
+    setCts(active) {
+        this.ctsActive = active;
+    }
+    setDsr(active) {
+        this.dsrActive = active;
+    }
+    buildStatus() {
+        const txRDY = this.txEnable && this.ctsActive ? 0x01 : 0;
+        const rxRDY = this.rxEnable && this.rxQueue.length > 0 ? 0x02 : 0;
+        const txEMPTY = 0x04;
+        const errors = (this.errorFlags & 0x07) << 3;
+        const dsr = this.dsrActive ? 0x80 : 0;
+        return txRDY | rxRDY | txEMPTY | errors | dsr;
+    }
+}
+//# sourceMappingURL=Usart8251.js.map

package/dist/cards/Usart8251.js.map

@@ -0,0 +1 @@
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package/dist/cards/VdmCard.d.ts

@@ -0,0 +1,27 @@
+import type { IS100Card } from '../interfaces/IS100Card.js';
+import type { Bus } from '../bus/Bus.js';
+import type { DisplaySurface } from './DisplaySurface.js';
+export interface VdmCardOptions {
+    /** Video RAM base (the VDM-1 mapped its 1K at 0xCC00). */
+    readonly base?: number;
+}
+/**
+ * Processor Technology VDM-1 memory-mapped character display (Story 5.9).
+ *
+ * A passive display: 1 KB of video RAM the CPU writes ASCII into; a character
+ * generator turns each byte into a glyph (bit 7 = inverse). The card owns no
+ * memory of its own — its video RAM is a declared `MachineSpec.memory` region
+ * (so it's overlap-validated and shows on the memory-map ribbon), and the card
+ * reads it back through the bus each frame for the host to render.
+ */
+export declare class VdmCard implements IS100Card {
+    readonly id: string;
+    readonly display: DisplaySurface;
+    private readonly base;
+    private bus?;
+    constructor(id?: string, opts?: VdmCardOptions);
+    attach(bus: Bus): void;
+    reset(): void;
+    private readVram;
+}
+//# sourceMappingURL=VdmCard.d.ts.map

package/dist/cards/VdmCard.d.ts.map

@@ -0,0 +1 @@
+{"version":3,"file":"VdmCard.d.ts","sourceRoot":"","sources":["../../src/cards/VdmCard.ts"],"names":[],"mappings":"AAAA,OAAO,KAAK,EAAE,SAAS,EAAE,MAAM,4BAA4B,CAAC;AAC5D,OAAO,KAAK,EAAE,GAAG,EAAE,MAAM,eAAe,CAAC;AACzC,OAAO,KAAK,EAAE,cAAc,EAAE,MAAM,qBAAqB,CAAC;AAO1D,MAAM,WAAW,cAAc;IAC7B,0DAA0D;IAC1D,QAAQ,CAAC,IAAI,CAAC,EAAE,MAAM,CAAC;CACxB;AAED;;;;;;;;GAQG;AACH,qBAAa,OAAQ,YAAW,SAAS;IACvC,QAAQ,CAAC,EAAE,EAAE,MAAM,CAAC;IACpB,QAAQ,CAAC,OAAO,EAAE,cAAc,CAAC;IACjC,OAAO,CAAC,QAAQ,CAAC,IAAI,CAAS;IAC9B,OAAO,CAAC,GAAG,CAAC,CAAM;gBAEN,EAAE,SAAQ,EAAE,IAAI,GAAE,cAAmB;IASjD,MAAM,CAAC,GAAG,EAAE,GAAG,GAAG,IAAI;IAItB,KAAK,IAAI,IAAI;IAEb,OAAO,CAAC,QAAQ;CAMjB"}

package/dist/cards/VdmCard.js

@@ -0,0 +1,40 @@
+/** Processor Technology VDM-1: 16 lines × 64 characters = 1024 bytes. */
+const COLS = 64;
+const ROWS = 16;
+const SIZE = COLS * ROWS;
+/**
+ * Processor Technology VDM-1 memory-mapped character display (Story 5.9).
+ *
+ * A passive display: 1 KB of video RAM the CPU writes ASCII into; a character
+ * generator turns each byte into a glyph (bit 7 = inverse). The card owns no
+ * memory of its own — its video RAM is a declared `MachineSpec.memory` region
+ * (so it's overlap-validated and shows on the memory-map ribbon), and the card
+ * reads it back through the bus each frame for the host to render.
+ */
+export class VdmCard {
+    id;
+    display;
+    base;
+    bus;
+    constructor(id = 'vdm', opts = {}) {
+        this.id = id;
+        this.base = (opts.base ?? 0xcc00) & 0xffff;
+        this.display = {
+            descriptor: { mode: 'charGrid', cols: COLS, rows: ROWS, font: 'vdm', attrBit: 7 },
+            frame: () => ({ bytes: this.readVram(), state: {} }),
+        };
+    }
+    attach(bus) {
+        this.bus = bus; // the video RAM is a separate MachineSpec.memory region
+    }
+    reset() { }
+    readVram() {
+        const out = new Uint8Array(SIZE);
+        const bus = this.bus;
+        if (bus)
+            for (let i = 0; i < SIZE; i++)
+                out[i] = bus.read((this.base + i) & 0xffff) & 0xff;
+        return out;
+    }
+}
+//# sourceMappingURL=VdmCard.js.map

package/dist/cards/VdmCard.js.map

@@ -0,0 +1 @@
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package/dist/clock/ImmediateClock.d.ts

@@ -0,0 +1,8 @@
+import type { IClock } from '../interfaces/IClock.js';
+export declare class ImmediateClock implements IClock {
+    private elapsed;
+    addCycles(cycles: number): void;
+    getElapsedCycles(): bigint;
+    reset(): void;
+}
+//# sourceMappingURL=ImmediateClock.d.ts.map

package/dist/clock/ImmediateClock.d.ts.map

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package/dist/clock/ImmediateClock.js

@@ -0,0 +1,13 @@
+export class ImmediateClock {
+    elapsed = 0n;
+    addCycles(cycles) {
+        this.elapsed += BigInt(cycles);
+    }
+    getElapsedCycles() {
+        return this.elapsed;
+    }
+    reset() {
+        this.elapsed = 0n;
+    }
+}
+//# sourceMappingURL=ImmediateClock.js.map

package/dist/clock/ImmediateClock.js.map

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package/dist/clock/SystemClock.d.ts

@@ -0,0 +1,45 @@
+import type { IClock } from '../interfaces/IClock.js';
+/**
+ * A real-time clock that tracks how far the simulation has run relative to a
+ * target CPU frequency. Uses performance.now() for timing — works in Node 16+,
+ * all browsers, Deno, Bun. Uses setTimeout(fn, 0) for yielding — no
+ * setImmediate or process.* dependencies.
+ *
+ * Drift accounting is absolute (cycles vs. wall time since the last baseline),
+ * so oversleeping or scheduler jitter self-corrects instead of accumulating.
+ */
+export declare class SystemClock implements IClock {
+    private elapsed;
+    private hz;
+    private startTime;
+    private cyclesAtStart;
+    private readonly now;
+    constructor(hz?: number, now?: () => number);
+    addCycles(cycles: number): void;
+    getElapsedCycles(): bigint;
+    reset(): void;
+    get targetHz(): number;
+    /**
+     * Change the target frequency. Re-baselines so the new rate applies from
+     * this moment — cycles already executed are not retroactively repriced.
+     */
+    setHz(hz: number): void;
+    /**
+     * Forfeit any accumulated drift and restart pacing from "now". Used after
+     * host stalls (GC pause, suspended tab) so the simulation doesn't sprint to
+     * catch up on lost wall time.
+     */
+    resync(): void;
+    /**
+     * Returns a promise that resolves after yielding to the event loop.
+     * Callers should await this periodically to avoid blocking.
+     */
+    yield(): Promise<void>;
+    /**
+     * How far ahead (in ms) the simulation is relative to wall time.
+     * Positive = running too fast (should sleep); negative = behind.
+     */
+    getAheadMs(): number;
+    private rebaseline;
+}
+//# sourceMappingURL=SystemClock.d.ts.map

package/dist/clock/SystemClock.d.ts.map

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