@joezilla/8sim 0.10.0

package/dist/cards/Mc6850Acia.js.map

@@ -0,0 +1 @@
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package/dist/cards/Mits2SioCard.d.ts

@@ -0,0 +1,27 @@
+import type { IS100Card } from '../interfaces/IS100Card.js';
+import type { Bus } from '../bus/Bus.js';
+import { Mc6850Acia } from './Mc6850Acia.js';
+export interface Sio2CardOptions {
+    readonly basePort?: number;
+}
+/**
+ * MITS Altair 88-2SIO dual serial card — two Motorola MC6850 ACIAs. Consumes
+ * four consecutive I/O addresses; the standard MITS base is 0x10:
+ *
+ *   base+0 / base+1   Port 0  — control/status (0x10) + data (0x11)
+ *   base+2 / base+3   Port 1  — control/status (0x12) + data (0x13)
+ *
+ * Port 0 is the conventional console. The 88-2SIO is the assumed serial board
+ * for nearly all MITS software (Altair BASIC, Altair DOS, and most CP/M BIOS
+ * implementations), so this is the card to attach when booting Altair CP/M.
+ */
+export declare class Mits2SioCard implements IS100Card {
+    readonly id: string;
+    readonly port0: Mc6850Acia;
+    readonly port1: Mc6850Acia;
+    constructor(id?: string, options?: Sio2CardOptions);
+    attach(bus: Bus): void;
+    wireToConsole(): void;
+    reset(): void;
+}
+//# sourceMappingURL=Mits2SioCard.d.ts.map

package/dist/cards/Mits2SioCard.d.ts.map

@@ -0,0 +1 @@
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package/dist/cards/Mits2SioCard.js

@@ -0,0 +1,36 @@
+import { Mc6850Acia } from './Mc6850Acia.js';
+import { writeHostStdout } from '../util/hostConsole.js';
+/**
+ * MITS Altair 88-2SIO dual serial card — two Motorola MC6850 ACIAs. Consumes
+ * four consecutive I/O addresses; the standard MITS base is 0x10:
+ *
+ *   base+0 / base+1   Port 0  — control/status (0x10) + data (0x11)
+ *   base+2 / base+3   Port 1  — control/status (0x12) + data (0x13)
+ *
+ * Port 0 is the conventional console. The 88-2SIO is the assumed serial board
+ * for nearly all MITS software (Altair BASIC, Altair DOS, and most CP/M BIOS
+ * implementations), so this is the card to attach when booting Altair CP/M.
+ */
+export class Mits2SioCard {
+    id;
+    port0;
+    port1;
+    constructor(id = '2sio', options = {}) {
+        const base = options.basePort ?? 0x10;
+        this.id = id;
+        this.port0 = new Mc6850Acia(`${id}:port0`, base + 0, base + 1);
+        this.port1 = new Mc6850Acia(`${id}:port1`, base + 2, base + 3);
+    }
+    attach(bus) {
+        bus.attachIODevice(this.port0);
+        bus.attachIODevice(this.port1);
+    }
+    wireToConsole() {
+        this.port0.onTransmit((byte) => writeHostStdout(String.fromCharCode(byte & 0x7f)));
+    }
+    reset() {
+        this.port0.reset();
+        this.port1.reset();
+    }
+}
+//# sourceMappingURL=Mits2SioCard.js.map

package/dist/cards/Mits2SioCard.js.map

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package/dist/cards/MitsDcddCard.d.ts

@@ -0,0 +1,52 @@
+import type { IS100Card } from '../interfaces/IS100Card.js';
+import type { IIODevice } from '../interfaces/IIODevice.js';
+import type { Bus } from '../bus/Bus.js';
+import { type WebSocketLike } from './FdcPlusClient.js';
+export interface DcddOptions {
+    readonly basePort?: number;
+}
+export declare class MitsDcddCard implements IS100Card, IIODevice {
+    readonly id: string;
+    readonly basePorts: ReadonlyArray<number>;
+    private readonly fdcClient;
+    private readonly p1;
+    private readonly p2;
+    private readonly p3;
+    private selectedDrive;
+    private readonly driveTrack;
+    private headLoaded;
+    private writeEnabled;
+    private fetchPending;
+    private trackData;
+    private writeBuffer;
+    private writtenSectors;
+    private writeDirty;
+    private lastSector;
+    private byteInSector;
+    private cacheDrive;
+    /** Head position of the currently selected drive (0 when none selected). */
+    private get currentTrack();
+    private set currentTrack(value);
+    constructor(id: string, ws: WebSocketLike, options?: DcddOptions);
+    attach(bus: Bus): void;
+    ioRead(port: number): number;
+    ioWrite(port: number, value: number): void;
+    reset(): void;
+    private readStatus;
+    private writeDriveSelect;
+    private readSector;
+    private writeCommand;
+    private readData;
+    private writeData;
+    /**
+     * Start fetching the current track if the head is loaded, a drive is
+     * selected, we don't already have the data, and no fetch is in flight. Safe
+     * to call from any read/command path — it converges on caching the track the
+     * head is currently over.
+     */
+    private ensureTrack;
+    private fetchTrack;
+    private flushWrite;
+    private issueStep;
+}
+//# sourceMappingURL=MitsDcddCard.d.ts.map

package/dist/cards/MitsDcddCard.d.ts.map

@@ -0,0 +1 @@
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package/dist/cards/MitsDcddCard.js

@@ -0,0 +1,294 @@
+import { FdcPlusClient } from './FdcPlusClient.js';
+const TRACK_LEN = 137 * 32; // 4384 bytes — one full 8-inch track
+const BYTES_PER_SECTOR = 137;
+const MAX_TRACK = 76;
+export class MitsDcddCard {
+    id;
+    basePorts;
+    fdcClient;
+    p1;
+    p2;
+    p3;
+    selectedDrive = 0xFF;
+    // Head position is PER-DRIVE state: each drive's arm stays where it was
+    // left. The BIOS seeks relatively from a per-drive track table in RAM, so a
+    // single shared counter desyncs the moment two drives interleave seeks
+    // (e.g. PIP copying between disks) and lands reads/writes on wrong tracks.
+    driveTrack = new Array(16).fill(0);
+    headLoaded = false;
+    writeEnabled = false;
+    fetchPending = false;
+    trackData = null;
+    writeBuffer = null;
+    writtenSectors = new Set(); // sectors touched since Write Enable
+    writeDirty = false;
+    lastSector = -1;
+    byteInSector = 0;
+    cacheDrive = 0xFF; // which drive the cached trackData belongs to
+    /** Head position of the currently selected drive (0 when none selected). */
+    get currentTrack() {
+        return this.selectedDrive === 0xFF ? 0 : (this.driveTrack[this.selectedDrive] ?? 0);
+    }
+    set currentTrack(track) {
+        if (this.selectedDrive !== 0xFF)
+            this.driveTrack[this.selectedDrive] = track;
+    }
+    constructor(id, ws, options = {}) {
+        this.id = id;
+        const base = options.basePort ?? 0x08;
+        this.p1 = base;
+        this.p2 = base + 1;
+        this.p3 = base + 2;
+        this.basePorts = [this.p1, this.p2, this.p3];
+        this.fdcClient = new FdcPlusClient(ws);
+    }
+    attach(bus) {
+        bus.attachIODevice(this);
+    }
+    ioRead(port) {
+        if (port === this.p1)
+            return this.readStatus();
+        if (port === this.p2)
+            return this.readSector();
+        if (port === this.p3)
+            return this.readData();
+        return 0xff;
+    }
+    ioWrite(port, value) {
+        if (port === this.p1) {
+            this.writeDriveSelect(value);
+            return;
+        }
+        if (port === this.p2) {
+            this.writeCommand(value);
+            return;
+        }
+        if (port === this.p3) {
+            this.writeData(value);
+            return;
+        }
+    }
+    reset() {
+        this.flushWrite();
+        this.selectedDrive = 0xFF;
+        this.driveTrack.fill(0);
+        this.headLoaded = false;
+        this.writeEnabled = false;
+        this.fetchPending = false;
+        this.trackData = null;
+        this.writeBuffer = null;
+        this.writtenSectors.clear();
+        this.writeDirty = false;
+        this.lastSector = -1;
+        this.byteInSector = 0;
+        this.cacheDrive = 0xFF;
+    }
+    // --- Port 1: status (READ) / drive select (WRITE) ---
+    readStatus() {
+        this.ensureTrack(); // lazily (re)start a fetch if the current track isn't cached
+        // 88-DCDD status register, all bits active-low (0 = condition true):
+        //   bit7 NRDA   — new read data available
+        //   bit6 TRK0   — head at track 0
+        //   bit3 DRVRDY — drive ready (a drive is selected and its disk is present)
+        //   bit2 HDSTAT — head loaded / positioning valid
+        //   bit1 MVHEAD — head movement complete (instantaneous in emulation)
+        //   bit0 ENWDAT — ready to accept write data
+        const nrda = (!this.headLoaded || !this.trackData || this.fetchPending) ? 0x80 : 0;
+        const trk0 = this.currentTrack === 0 ? 0x00 : 0x40;
+        const drvrdy = this.selectedDrive !== 0xFF ? 0x00 : 0x08;
+        const hdstat = this.headLoaded ? 0x00 : 0x04;
+        const mvhd = 0x00;
+        const enwd = this.writeEnabled ? 0x00 : 0x01;
+        return nrda | trk0 | drvrdy | hdstat | mvhd | enwd;
+    }
+    writeDriveSelect(value) {
+        if ((value & 0x80) !== 0) {
+            // Disable/deselect the drive. On real hardware this drops the drive-enable
+            // line but the head-load solenoid and the data already under the head are
+            // physical state that persists — the drive can be reselected with the head
+            // still loaded. The MITS multi-stage boot relies on exactly this (it
+            // reselects the drive and expects HEDLD to already be active). Only an
+            // explicit Head Unload command (Port 2 bit 3) lifts the head.
+            this.flushWrite();
+            this.selectedDrive = 0xFF;
+            this.writeEnabled = false;
+            return;
+        }
+        const drive = value & 0x0F;
+        // A dirty write buffer belongs to the drive we're switching away from —
+        // flush it before the selection changes, or it lands on the new drive.
+        if (drive !== this.selectedDrive)
+            this.flushWrite();
+        this.selectedDrive = drive;
+        // Selecting a different drive invalidates the cached track (different disk).
+        if (drive !== this.cacheDrive) {
+            this.trackData = null;
+        }
+        this.ensureTrack();
+        this.fdcClient
+            .stat(this.selectedDrive, this.headLoaded, this.currentTrack)
+            .catch(() => { });
+    }
+    // --- Port 2: sector position (READ) / command (WRITE) ---
+    readSector() {
+        const revMs = 166.667;
+        const secMs = revMs / 32;
+        const pos = performance.now() % revMs;
+        const sector = Math.floor(pos / secMs) & 0x1F;
+        const offset = pos % secMs;
+        // Sector True (bit 0) pulses LOW for first 1 ms of each sector window
+        const sectorTrue = offset < 1.0 ? 0 : 1;
+        if (sector !== this.lastSector || sectorTrue === 0) {
+            // New sector under the head, or the start-of-sector pulse. Sector True
+            // marks the beginning of the sector: software that samples it here (the
+            // BIOS waits for it before every transfer) expects the byte stream to
+            // start at byte 0 — even when re-targeting the sector it just finished,
+            // where the sector number alone wouldn't change.
+            this.lastSector = sector;
+            this.byteInSector = 0;
+        }
+        return 0xC0 | ((sector & 0x1F) << 1) | sectorTrue;
+    }
+    writeCommand(value) {
+        // Process all command bits; multiple may be set simultaneously
+        if ((value & 0x80) !== 0) { // Write Enable
+            // The BIOS issues Write Enable once per sector write. On real hardware
+            // each sector hits the disk immediately; here writes accumulate in the
+            // track buffer until flush, so Write Enable must NOT discard sectors
+            // buffered by earlier enables — only ensure a buffer exists.
+            this.writeEnabled = true;
+            if (!this.writeBuffer)
+                this.writeBuffer = new Uint8Array(TRACK_LEN);
+        }
+        if ((value & 0x08) !== 0) { // Head Unload
+            this.flushWrite();
+            this.headLoaded = false;
+            this.trackData = null;
+        }
+        if ((value & 0x04) !== 0) { // Head Load
+            this.headLoaded = true;
+            this.ensureTrack();
+        }
+        if ((value & 0x02) !== 0)
+            this.issueStep('out'); // Step Out
+        if ((value & 0x01) !== 0)
+            this.issueStep('in'); // Step In
+    }
+    // --- Port 3: data (READ/WRITE) ---
+    readData() {
+        if (!this.headLoaded || !this.trackData || this.fetchPending)
+            return 0xff;
+        // Past the 137th byte the head is over the inter-sector gap — nothing to
+        // read until the sector counter advances (which resets byteInSector).
+        if (this.byteInSector >= BYTES_PER_SECTOR)
+            return 0xff;
+        const sector = this.lastSector < 0 ? 0 : this.lastSector;
+        const offset = sector * BYTES_PER_SECTOR + this.byteInSector;
+        // A sector rewritten since Write Enable reads back its new contents.
+        const source = (this.writeBuffer && this.writtenSectors.has(sector))
+            ? this.writeBuffer
+            : this.trackData;
+        if (offset >= source.length)
+            return 0xff;
+        const byte = source[offset] ?? 0xff;
+        this.byteInSector++;
+        return byte;
+    }
+    writeData(value) {
+        if (!this.writeEnabled || !this.writeBuffer)
+            return;
+        // The BIOS pads its 137-byte sector burst with trailing bytes; on real
+        // hardware they land in the inter-sector gap. Discard them — wrapping
+        // around would overwrite the start of the sector (the track-marker byte),
+        // corrupting it.
+        if (this.byteInSector >= BYTES_PER_SECTOR)
+            return;
+        const sector = this.lastSector < 0 ? 0 : this.lastSector;
+        const offset = sector * BYTES_PER_SECTOR + this.byteInSector;
+        if (offset < this.writeBuffer.length) {
+            this.writeBuffer[offset] = value & 0xff;
+            this.writtenSectors.add(sector);
+            this.writeDirty = true;
+        }
+        this.byteInSector++;
+    }
+    // --- Private helpers ---
+    /**
+     * Start fetching the current track if the head is loaded, a drive is
+     * selected, we don't already have the data, and no fetch is in flight. Safe
+     * to call from any read/command path — it converges on caching the track the
+     * head is currently over.
+     */
+    ensureTrack() {
+        if (!this.headLoaded || this.selectedDrive === 0xFF)
+            return;
+        if (this.trackData || this.fetchPending)
+            return;
+        this.fetchTrack();
+    }
+    fetchTrack() {
+        if (this.selectedDrive === 0xFF || !this.headLoaded || this.fetchPending)
+            return;
+        this.fetchPending = true;
+        const drive = this.selectedDrive;
+        const track = this.currentTrack;
+        this.fdcClient
+            .readTrack(drive, track, TRACK_LEN)
+            .then((data) => {
+            // Only install the data if the head hasn't moved (and the same drive is
+            // still selected) since the fetch began — otherwise it belongs to a
+            // track we're no longer over and would corrupt the next read. A cache
+            // that appeared meanwhile is a flushed write image, which is fresher
+            // than what we just fetched — keep it.
+            if (track === this.currentTrack && drive === this.selectedDrive && !this.trackData) {
+                this.trackData = data;
+                this.cacheDrive = drive;
+            }
+        })
+            .catch(() => { })
+            .finally(() => {
+            this.fetchPending = false;
+            // If the head moved during the fetch, chase the track it's now over.
+            this.ensureTrack();
+        });
+    }
+    flushWrite() {
+        if (!this.writeDirty || !this.writeBuffer || this.selectedDrive === 0xFF)
+            return;
+        // WRIT replaces the whole track on the server, but the program only wrote
+        // some sectors — merge those over the cached track image so the rest keep
+        // their contents.
+        const image = this.trackData ? new Uint8Array(this.trackData) : new Uint8Array(TRACK_LEN);
+        for (const sector of this.writtenSectors) {
+            const off = sector * BYTES_PER_SECTOR;
+            image.set(this.writeBuffer.subarray(off, off + BYTES_PER_SECTOR), off);
+        }
+        const drive = this.selectedDrive;
+        const track = this.currentTrack;
+        this.writeBuffer = null;
+        this.writtenSectors.clear();
+        this.writeDirty = false;
+        this.writeEnabled = false;
+        // The merged image is now the freshest copy of the track — reads must see
+        // the written data, not the pre-write cache.
+        this.trackData = image;
+        this.cacheDrive = drive;
+        this.fdcClient.writeTrack(drive, track, image).catch((e) => {
+            console.error(`[${this.id}] track write failed (drive ${drive}, track ${track}): ${String(e)}`);
+        });
+    }
+    issueStep(dir) {
+        // Seeks are instantaneous in emulation. A real-time settle delay would
+        // desync from the emulated CPU (which the software paces itself), and
+        // dropping "too-fast" step pulses would lose track position entirely.
+        this.flushWrite(); // a dirty buffer belongs to the track we're leaving
+        if (dir === 'in')
+            this.currentTrack = Math.min(MAX_TRACK, this.currentTrack + 1);
+        else
+            this.currentTrack = Math.max(0, this.currentTrack - 1);
+        this.trackData = null; // head moved; cached track is no longer under it
+        this.writeEnabled = false;
+        this.ensureTrack(); // begin fetching the new track
+    }
+}
+//# sourceMappingURL=MitsDcddCard.js.map

package/dist/cards/MitsDcddCard.js.map

@@ -0,0 +1 @@
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package/dist/cards/ParallelCard.d.ts

@@ -0,0 +1,35 @@
+import type { IS100Card } from '../interfaces/IS100Card.js';
+import type { Bus } from '../bus/Bus.js';
+/** Data direction of a parallel port from the operator's peripheral view. */
+export type PortDirection = 'out' | 'in' | 'inout';
+export interface ParallelCardOptions {
+    readonly port?: number;
+    readonly direction?: PortDirection;
+}
+/** The host-side surface a GPIO peripheral (LEDs / switches / printer) binds to. */
+export interface GpioPort {
+    readonly direction: PortDirection;
+    /** The byte the CPU last latched on the output pins (drive LEDs / a printer). */
+    read(): number;
+    /** Drive the input pins — the value the CPU reads (sense switches). */
+    setInput(byte: number): void;
+    /** Fired whenever the CPU writes the output latch. */
+    onOutput(cb: (byte: number) => void): void;
+}
+/**
+ * A single 8-bit parallel I/O card (Story 5.8) — an 8212-style latched port the
+ * general GPIO cards resolve to. A CPU write latches the output byte; a CPU read
+ * returns the input pins. It exposes a `gpio` surface so the host wires it to a
+ * peripheral — an LED bank, sense switches, a printer, or real hardware GPIO.
+ * `direction` is a hint for the peripheral viewer (the 8212 is bidirectional).
+ */
+export declare class ParallelCard implements IS100Card {
+    readonly id: string;
+    readonly direction: PortDirection;
+    readonly gpio: GpioPort;
+    private readonly dev;
+    constructor(id?: string, opts?: ParallelCardOptions);
+    attach(bus: Bus): void;
+    reset(): void;
+}
+//# sourceMappingURL=ParallelCard.d.ts.map

package/dist/cards/ParallelCard.d.ts.map

@@ -0,0 +1 @@
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package/dist/cards/ParallelCard.js

@@ -0,0 +1,32 @@
+import { Port8212 } from './Port8212.js';
+/**
+ * A single 8-bit parallel I/O card (Story 5.8) — an 8212-style latched port the
+ * general GPIO cards resolve to. A CPU write latches the output byte; a CPU read
+ * returns the input pins. It exposes a `gpio` surface so the host wires it to a
+ * peripheral — an LED bank, sense switches, a printer, or real hardware GPIO.
+ * `direction` is a hint for the peripheral viewer (the 8212 is bidirectional).
+ */
+export class ParallelCard {
+    id;
+    direction;
+    gpio;
+    dev;
+    constructor(id = 'parallel', opts = {}) {
+        this.id = id;
+        this.direction = opts.direction ?? 'out';
+        this.dev = new Port8212(`${id}:port`, opts.port ?? 0x00);
+        this.gpio = {
+            direction: this.direction,
+            read: () => this.dev.output,
+            setInput: (byte) => this.dev.setInput(byte),
+            onOutput: (cb) => this.dev.onWrite(cb),
+        };
+    }
+    attach(bus) {
+        bus.attachIODevice(this.dev);
+    }
+    reset() {
+        this.dev.reset();
+    }
+}
+//# sourceMappingURL=ParallelCard.js.map

package/dist/cards/ParallelCard.js.map

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package/dist/cards/Port8212.d.ts

@@ -0,0 +1,31 @@
+import type { IIODevice } from '../interfaces/IIODevice.js';
+type PortWriteCallback = (value: number) => void;
+/**
+ * Intel / AMD 8212 eight-bit latched I/O port, as used for the IMSAI MIO
+ * board's two parallel ports. A CPU write latches the output byte (held on the
+ * output pins); a CPU read returns whatever is currently presented on the input
+ * pins. Output and input are independent, modelling a bidirectional 8212 port.
+ *
+ * The host drives the input pins with {@link setInput} and observes the latched
+ * output via {@link output} or an {@link onWrite} callback — this is how a
+ * printer, LED bank, switch bank, or other peripheral is wired to the port.
+ */
+export declare class Port8212 implements IIODevice {
+    readonly id: string;
+    readonly basePorts: ReadonlyArray<number>;
+    private outputLatch;
+    private inputLatch;
+    private writeCb;
+    constructor(id: string, port: number);
+    ioRead(_port: number): number;
+    ioWrite(_port: number, value: number): void;
+    reset(): void;
+    /** Drive the port's input pins — the value the CPU reads from this port. */
+    setInput(value: number): void;
+    /** The byte currently latched on the output pins. */
+    get output(): number;
+    /** Register a callback fired whenever the CPU writes the output latch. */
+    onWrite(cb: PortWriteCallback): void;
+}
+export {};
+//# sourceMappingURL=Port8212.d.ts.map

package/dist/cards/Port8212.d.ts.map

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package/dist/cards/Port8212.js

@@ -0,0 +1,47 @@
+import { u8 } from '../util/bits.js';
+/**
+ * Intel / AMD 8212 eight-bit latched I/O port, as used for the IMSAI MIO
+ * board's two parallel ports. A CPU write latches the output byte (held on the
+ * output pins); a CPU read returns whatever is currently presented on the input
+ * pins. Output and input are independent, modelling a bidirectional 8212 port.
+ *
+ * The host drives the input pins with {@link setInput} and observes the latched
+ * output via {@link output} or an {@link onWrite} callback — this is how a
+ * printer, LED bank, switch bank, or other peripheral is wired to the port.
+ */
+export class Port8212 {
+    id;
+    basePorts;
+    outputLatch = 0;
+    inputLatch = 0xff; // unconnected TTL inputs float high
+    writeCb;
+    constructor(id, port) {
+        this.id = id;
+        this.basePorts = [port];
+    }
+    ioRead(_port) {
+        return this.inputLatch;
+    }
+    ioWrite(_port, value) {
+        this.outputLatch = u8(value);
+        this.writeCb?.(this.outputLatch);
+    }
+    reset() {
+        this.outputLatch = 0;
+        this.inputLatch = 0xff;
+        // writeCb survives reset — it is host wiring.
+    }
+    /** Drive the port's input pins — the value the CPU reads from this port. */
+    setInput(value) {
+        this.inputLatch = u8(value);
+    }
+    /** The byte currently latched on the output pins. */
+    get output() {
+        return this.outputLatch;
+    }
+    /** Register a callback fired whenever the CPU writes the output latch. */
+    onWrite(cb) {
+        this.writeCb = cb;
+    }
+}
+//# sourceMappingURL=Port8212.js.map

package/dist/cards/Port8212.js.map

@@ -0,0 +1 @@
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package/dist/cards/RtcCard.d.ts

@@ -0,0 +1,30 @@
+import type { IS100Card } from '../interfaces/IS100Card.js';
+import type { Bus } from '../bus/Bus.js';
+/** Host time source injected via CardContext.services.clock. */
+export type RtcClock = () => Date;
+export interface RtcCardOptions {
+    /** Base I/O port; the chip occupies base..base+0x1F (32 registers). */
+    readonly base?: number;
+}
+/**
+ * National MM58167 real-time clock (Story 5.10). A 32-register clock/calendar
+ * chip on an I/O window: the counter registers (0x00–0x07) read the host wall
+ * clock as BCD, the rest (RAM / compare / interrupt / status) are plain storage.
+ *
+ * The host time comes from `ctx.services.clock` (a `() => Date`), so the machine
+ * reads real time while tests stay deterministic by injecting a fixed clock.
+ * Writes to the live counters are ignored — you can't set the host's clock.
+ */
+export declare class RtcCard implements IS100Card {
+    readonly id: string;
+    private readonly base;
+    private readonly now;
+    private readonly ram;
+    private readonly dev;
+    constructor(id?: string, opts?: RtcCardOptions, clock?: RtcClock);
+    attach(bus: Bus): void;
+    reset(): void;
+    private readReg;
+    private writeReg;
+}
+//# sourceMappingURL=RtcCard.d.ts.map