@joezilla/8sim 0.10.0

package/dist/8sim.browser.js

@@ -0,0 +1,4728 @@
+// src/cpu/Registers.ts
+var Registers = class {
+  a = 0;
+  b = 0;
+  c = 0;
+  d = 0;
+  e = 0;
+  h = 0;
+  l = 0;
+  sp = 0;
+  pc = 0;
+  /** BC register pair */
+  get bc() {
+    return this.b << 8 | this.c;
+  }
+  set bc(v) {
+    this.b = v >> 8 & 255;
+    this.c = v & 255;
+  }
+  /** DE register pair */
+  get de() {
+    return this.d << 8 | this.e;
+  }
+  set de(v) {
+    this.d = v >> 8 & 255;
+    this.e = v & 255;
+  }
+  /** HL register pair */
+  get hl() {
+    return this.h << 8 | this.l;
+  }
+  set hl(v) {
+    this.h = v >> 8 & 255;
+    this.l = v & 255;
+  }
+  reset() {
+    this.a = this.b = this.c = this.d = this.e = this.h = this.l = 0;
+    this.sp = 0;
+    this.pc = 0;
+  }
+};
+
+// src/cpu/Flags.ts
+var Flags = class {
+  s = false;
+  // Sign
+  z = false;
+  // Zero
+  ac = false;
+  // Auxiliary Carry (half-carry)
+  p = false;
+  // Parity (even)
+  cy = false;
+  // Carry
+  /** Serialize to PSW byte */
+  toByte() {
+    return (this.s ? 128 : 0) | (this.z ? 64 : 0) | (this.ac ? 16 : 0) | (this.p ? 4 : 0) | 2 | // bit 1 always 1
+    (this.cy ? 1 : 0);
+  }
+  /** Deserialize from PSW byte */
+  fromByte(b) {
+    this.s = (b & 128) !== 0;
+    this.z = (b & 64) !== 0;
+    this.ac = (b & 16) !== 0;
+    this.p = (b & 4) !== 0;
+    this.cy = (b & 1) !== 0;
+  }
+  reset() {
+    this.s = this.z = this.ac = this.p = this.cy = false;
+  }
+};
+
+// src/cpu/Decoder.ts
+var Decoder = class {
+  table;
+  constructor() {
+    this.table = new Array(256).fill(void 0).map((_, i) => {
+      return (_regs, _flags, _bus) => {
+        console.warn(`Unimplemented opcode: 0x${i.toString(16).padStart(2, "0")}`);
+        return 4;
+      };
+    });
+  }
+  register(opcode, handler) {
+    this.table[opcode] = handler;
+  }
+  registerMany(opcodes, handler) {
+    for (const op of opcodes) {
+      this.register(op, handler);
+    }
+  }
+  decode(opcode) {
+    return this.table[opcode & 255];
+  }
+};
+
+// src/cpu/status8080.ts
+var STATUS = {
+  INTA: 1,
+  // interrupt acknowledge
+  WO: 2,
+  //   write/output — active LOW (set = a read cycle)
+  STACK: 4,
+  // stack access
+  HLTA: 8,
+  // halt acknowledge
+  OUT: 16,
+  //  output write
+  M1: 32,
+  //   first machine cycle (opcode fetch)
+  INP: 64,
+  //  input read
+  MEMR: 128
+  // memory read
+};
+var isRst = (op) => (op & 199) === 199;
+var writesMemory = (op) => op === 50 || // STA
+op === 34 || // SHLD
+op === 2 || op === 18 || // STAX B/D
+op === 54 || // MVI M,d8
+op >= 112 && op <= 119 && op !== 118 || // MOV M,r
+op === 197 || op === 213 || op === 229 || op === 245 || // PUSH
+op === 205 || op === 196 || op === 204 || op === 212 || op === 220 || op === 228 || op === 236 || op === 244 || op === 252 || // CALL (all)
+op === 227 || // XTHL
+isRst(op);
+var touchesStack = (op) => op === 197 || op === 213 || op === 229 || op === 245 || // PUSH
+op === 193 || op === 209 || op === 225 || op === 241 || // POP
+op === 205 || op === 196 || op === 204 || op === 212 || op === 220 || op === 228 || op === 236 || op === 244 || op === 252 || // CALL (all)
+op === 201 || op === 192 || op === 200 || op === 208 || op === 216 || op === 224 || op === 232 || op === 240 || op === 248 || // RET (all)
+op === 227 || // XTHL
+isRst(op);
+function statusByteForOpcode(op) {
+  let s = STATUS.M1 | STATUS.MEMR | STATUS.WO;
+  if (op === 118) return s | STATUS.HLTA;
+  if (op === 219) s |= STATUS.INP;
+  if (op === 211) s = (s | STATUS.OUT) & ~STATUS.WO;
+  if (touchesStack(op)) s |= STATUS.STACK;
+  if (writesMemory(op)) s &= ~STATUS.WO;
+  return s;
+}
+function buildStatusTable() {
+  const t = new Uint8Array(256);
+  for (let op = 0; op < 256; op++) t[op] = statusByteForOpcode(op);
+  return t;
+}
+var INTA_STATUS = STATUS.INTA | STATUS.M1 | STATUS.WO;
+var FETCH_STATUS = STATUS.M1 | STATUS.MEMR | STATUS.WO;
+
+// src/cpu/instructions/control.ts
+function registerControl(decoder) {
+  decoder.register(0, (_regs, _flags, _bus) => 4);
+  decoder.register(118, (_regs, _flags, _bus) => 7);
+  decoder.register(251, (_regs, _flags, _bus) => 4);
+  decoder.register(243, (_regs, _flags, _bus) => 4);
+}
+
+// src/util/bits.ts
+function u8(v) {
+  return v & 255;
+}
+function u16(v) {
+  return v & 65535;
+}
+function signBit(v) {
+  return (v & 128) !== 0;
+}
+function zeroFlag(v) {
+  return (v & 255) === 0;
+}
+function parityFlag(v) {
+  let x = v & 255;
+  x ^= x >> 4;
+  x ^= x >> 2;
+  x ^= x >> 1;
+  return (x & 1) === 0;
+}
+function auxCarryAdd(a, b, carry = 0) {
+  return (a & 15) + (b & 15) + carry > 15;
+}
+function auxCarrySub(a, b, borrow = 0) {
+  return (a & 15) - (b & 15) - borrow < 0;
+}
+function toWord(hi2, lo2) {
+  return (hi2 & 255) << 8 | lo2 & 255;
+}
+function hi(w) {
+  return w >> 8 & 255;
+}
+function lo(w) {
+  return w & 255;
+}
+
+// src/cpu/instructions/data.ts
+var REG_ORDER = ["b", "c", "d", "e", "h", "l", "M", "a"];
+function getReg(regs, r, bus) {
+  if (r === "M") return bus.read(regs.hl);
+  return regs[r];
+}
+function setReg(regs, r, val, bus) {
+  if (r === "M") {
+    bus.write(regs.hl, u8(val));
+    return;
+  }
+  regs[r] = u8(val);
+}
+function registerData(decoder) {
+  for (let dst = 0; dst < 8; dst++) {
+    for (let src = 0; src < 8; src++) {
+      const opcode = 64 | dst << 3 | src;
+      if (opcode === 118) continue;
+      const dstReg = REG_ORDER[dst];
+      const srcReg = REG_ORDER[src];
+      const cycles = dstReg === "M" || srcReg === "M" ? 7 : 5;
+      decoder.register(opcode, (regs, _flags, bus) => {
+        const val = getReg(regs, srcReg, bus);
+        setReg(regs, dstReg, val, bus);
+        return cycles;
+      });
+    }
+  }
+  for (let r = 0; r < 8; r++) {
+    const opcode = 6 | r << 3;
+    const reg = REG_ORDER[r];
+    const cycles = reg === "M" ? 10 : 7;
+    decoder.register(opcode, (regs, _flags, bus) => {
+      const imm = bus.read(regs.pc);
+      regs.pc = u16(regs.pc + 1);
+      setReg(regs, reg, imm, bus);
+      return cycles;
+    });
+  }
+  decoder.register(1, (regs, _flags, bus) => {
+    regs.c = bus.read(regs.pc);
+    regs.b = bus.read(u16(regs.pc + 1));
+    regs.pc = u16(regs.pc + 2);
+    return 10;
+  });
+  decoder.register(17, (regs, _flags, bus) => {
+    regs.e = bus.read(regs.pc);
+    regs.d = bus.read(u16(regs.pc + 1));
+    regs.pc = u16(regs.pc + 2);
+    return 10;
+  });
+  decoder.register(33, (regs, _flags, bus) => {
+    regs.l = bus.read(regs.pc);
+    regs.h = bus.read(u16(regs.pc + 1));
+    regs.pc = u16(regs.pc + 2);
+    return 10;
+  });
+  decoder.register(49, (regs, _flags, bus) => {
+    const lo_ = bus.read(regs.pc);
+    const hi_ = bus.read(u16(regs.pc + 1));
+    regs.sp = u16(toWord(hi_, lo_));
+    regs.pc = u16(regs.pc + 2);
+    return 10;
+  });
+  decoder.register(58, (regs, _flags, bus) => {
+    const lo_ = bus.read(regs.pc);
+    const hi_ = bus.read(u16(regs.pc + 1));
+    regs.pc = u16(regs.pc + 2);
+    regs.a = bus.read(toWord(hi_, lo_));
+    return 13;
+  });
+  decoder.register(50, (regs, _flags, bus) => {
+    const lo_ = bus.read(regs.pc);
+    const hi_ = bus.read(u16(regs.pc + 1));
+    regs.pc = u16(regs.pc + 2);
+    bus.write(toWord(hi_, lo_), regs.a);
+    return 13;
+  });
+  decoder.register(42, (regs, _flags, bus) => {
+    const lo_ = bus.read(regs.pc);
+    const hi_ = bus.read(u16(regs.pc + 1));
+    regs.pc = u16(regs.pc + 2);
+    const addr = toWord(hi_, lo_);
+    regs.l = bus.read(addr);
+    regs.h = bus.read(u16(addr + 1));
+    return 16;
+  });
+  decoder.register(34, (regs, _flags, bus) => {
+    const lo_ = bus.read(regs.pc);
+    const hi_ = bus.read(u16(regs.pc + 1));
+    regs.pc = u16(regs.pc + 2);
+    const addr = toWord(hi_, lo_);
+    bus.write(addr, regs.l);
+    bus.write(u16(addr + 1), regs.h);
+    return 16;
+  });
+  decoder.register(10, (regs, _flags, bus) => {
+    regs.a = bus.read(regs.bc);
+    return 7;
+  });
+  decoder.register(26, (regs, _flags, bus) => {
+    regs.a = bus.read(regs.de);
+    return 7;
+  });
+  decoder.register(2, (regs, _flags, bus) => {
+    bus.write(regs.bc, regs.a);
+    return 7;
+  });
+  decoder.register(18, (regs, _flags, bus) => {
+    bus.write(regs.de, regs.a);
+    return 7;
+  });
+  decoder.register(235, (regs, _flags, _bus) => {
+    const tmp = regs.hl;
+    regs.hl = regs.de;
+    regs.de = tmp;
+    return 5;
+  });
+}
+
+// src/cpu/instructions/alu.ts
+var REG_ORDER2 = ["b", "c", "d", "e", "h", "l", "M", "a"];
+function getReg2(regs, r, bus) {
+  if (r === "M") return bus.read(regs.hl);
+  return regs[r];
+}
+function setArithFlags(flags, result, ac) {
+  const r8 = u8(result);
+  flags.s = signBit(r8);
+  flags.z = zeroFlag(r8);
+  flags.ac = ac;
+  flags.p = parityFlag(r8);
+}
+function registerAlu(decoder) {
+  for (let r = 0; r < 8; r++) {
+    const opcode = 128 | r;
+    const reg = REG_ORDER2[r];
+    const cycles = reg === "M" ? 7 : 4;
+    decoder.register(opcode, (regs, flags, bus) => {
+      const a = regs.a;
+      const b = getReg2(regs, reg, bus);
+      const result = a + b;
+      flags.cy = result > 255;
+      flags.ac = auxCarryAdd(a, b);
+      setArithFlags(flags, result, flags.ac);
+      regs.a = u8(result);
+      return cycles;
+    });
+  }
+  for (let r = 0; r < 8; r++) {
+    const opcode = 136 | r;
+    const reg = REG_ORDER2[r];
+    const cycles = reg === "M" ? 7 : 4;
+    decoder.register(opcode, (regs, flags, bus) => {
+      const a = regs.a;
+      const b = getReg2(regs, reg, bus);
+      const cy = flags.cy ? 1 : 0;
+      const result = a + b + cy;
+      flags.cy = result > 255;
+      flags.ac = auxCarryAdd(a, b, cy);
+      setArithFlags(flags, result, flags.ac);
+      regs.a = u8(result);
+      return cycles;
+    });
+  }
+  for (let r = 0; r < 8; r++) {
+    const opcode = 144 | r;
+    const reg = REG_ORDER2[r];
+    const cycles = reg === "M" ? 7 : 4;
+    decoder.register(opcode, (regs, flags, bus) => {
+      const a = regs.a;
+      const b = getReg2(regs, reg, bus);
+      const result = a - b;
+      flags.cy = result < 0;
+      flags.ac = auxCarrySub(a, b);
+      setArithFlags(flags, result, flags.ac);
+      regs.a = u8(result);
+      return cycles;
+    });
+  }
+  for (let r = 0; r < 8; r++) {
+    const opcode = 152 | r;
+    const reg = REG_ORDER2[r];
+    const cycles = reg === "M" ? 7 : 4;
+    decoder.register(opcode, (regs, flags, bus) => {
+      const a = regs.a;
+      const b = getReg2(regs, reg, bus);
+      const borrow = flags.cy ? 1 : 0;
+      const result = a - b - borrow;
+      flags.cy = result < 0;
+      flags.ac = auxCarrySub(a, b, borrow);
+      setArithFlags(flags, result, flags.ac);
+      regs.a = u8(result);
+      return cycles;
+    });
+  }
+  decoder.register(198, (regs, flags, bus) => {
+    const a = regs.a;
+    const b = bus.read(regs.pc);
+    regs.pc = u16(regs.pc + 1);
+    const result = a + b;
+    flags.cy = result > 255;
+    flags.ac = auxCarryAdd(a, b);
+    setArithFlags(flags, result, flags.ac);
+    regs.a = u8(result);
+    return 7;
+  });
+  decoder.register(206, (regs, flags, bus) => {
+    const a = regs.a;
+    const b = bus.read(regs.pc);
+    regs.pc = u16(regs.pc + 1);
+    const cy = flags.cy ? 1 : 0;
+    const result = a + b + cy;
+    flags.cy = result > 255;
+    flags.ac = auxCarryAdd(a, b, cy);
+    setArithFlags(flags, result, flags.ac);
+    regs.a = u8(result);
+    return 7;
+  });
+  decoder.register(214, (regs, flags, bus) => {
+    const a = regs.a;
+    const b = bus.read(regs.pc);
+    regs.pc = u16(regs.pc + 1);
+    const result = a - b;
+    flags.cy = result < 0;
+    flags.ac = auxCarrySub(a, b);
+    setArithFlags(flags, result, flags.ac);
+    regs.a = u8(result);
+    return 7;
+  });
+  decoder.register(222, (regs, flags, bus) => {
+    const a = regs.a;
+    const b = bus.read(regs.pc);
+    regs.pc = u16(regs.pc + 1);
+    const borrow = flags.cy ? 1 : 0;
+    const result = a - b - borrow;
+    flags.cy = result < 0;
+    flags.ac = auxCarrySub(a, b, borrow);
+    setArithFlags(flags, result, flags.ac);
+    regs.a = u8(result);
+    return 7;
+  });
+  for (let r = 0; r < 8; r++) {
+    const opcode = 4 | r << 3;
+    const reg = REG_ORDER2[r];
+    const cycles = reg === "M" ? 10 : 5;
+    decoder.register(opcode, (regs, flags, bus) => {
+      const old = getReg2(regs, reg, bus);
+      const result = old + 1;
+      flags.ac = auxCarryAdd(old, 1);
+      flags.s = signBit(u8(result));
+      flags.z = zeroFlag(u8(result));
+      flags.p = parityFlag(u8(result));
+      if (reg === "M") {
+        bus.write(regs.hl, u8(result));
+      } else {
+        regs[reg] = u8(result);
+      }
+      return cycles;
+    });
+  }
+  for (let r = 0; r < 8; r++) {
+    const opcode = 5 | r << 3;
+    const reg = REG_ORDER2[r];
+    const cycles = reg === "M" ? 10 : 5;
+    decoder.register(opcode, (regs, flags, bus) => {
+      const old = getReg2(regs, reg, bus);
+      const result = old - 1;
+      flags.ac = auxCarrySub(old, 1);
+      flags.s = signBit(u8(result));
+      flags.z = zeroFlag(u8(result));
+      flags.p = parityFlag(u8(result));
+      if (reg === "M") {
+        bus.write(regs.hl, u8(result));
+      } else {
+        regs[reg] = u8(result);
+      }
+      return cycles;
+    });
+  }
+  decoder.register(3, (regs, _flags, _bus) => {
+    regs.bc = u16(regs.bc + 1);
+    return 5;
+  });
+  decoder.register(19, (regs, _flags, _bus) => {
+    regs.de = u16(regs.de + 1);
+    return 5;
+  });
+  decoder.register(35, (regs, _flags, _bus) => {
+    regs.hl = u16(regs.hl + 1);
+    return 5;
+  });
+  decoder.register(51, (regs, _flags, _bus) => {
+    regs.sp = u16(regs.sp + 1);
+    return 5;
+  });
+  decoder.register(11, (regs, _flags, _bus) => {
+    regs.bc = u16(regs.bc - 1);
+    return 5;
+  });
+  decoder.register(27, (regs, _flags, _bus) => {
+    regs.de = u16(regs.de - 1);
+    return 5;
+  });
+  decoder.register(43, (regs, _flags, _bus) => {
+    regs.hl = u16(regs.hl - 1);
+    return 5;
+  });
+  decoder.register(59, (regs, _flags, _bus) => {
+    regs.sp = u16(regs.sp - 1);
+    return 5;
+  });
+  function dad(regs, flags, rp) {
+    const result = regs.hl + rp;
+    flags.cy = result > 65535;
+    regs.hl = u16(result);
+    return 10;
+  }
+  decoder.register(9, (regs, flags, _bus) => dad(regs, flags, regs.bc));
+  decoder.register(25, (regs, flags, _bus) => dad(regs, flags, regs.de));
+  decoder.register(41, (regs, flags, _bus) => dad(regs, flags, regs.hl));
+  decoder.register(57, (regs, flags, _bus) => dad(regs, flags, regs.sp));
+  decoder.register(39, (regs, flags, _bus) => {
+    let a = regs.a;
+    let correction = 0;
+    let setCY = false;
+    if (flags.ac || (a & 15) > 9) {
+      correction |= 6;
+    }
+    if (flags.cy || a > 153) {
+      correction |= 96;
+      setCY = true;
+    }
+    const result = a + correction;
+    flags.ac = auxCarryAdd(a, correction);
+    flags.cy = setCY;
+    a = u8(result);
+    flags.s = signBit(a);
+    flags.z = zeroFlag(a);
+    flags.p = parityFlag(a);
+    regs.a = a;
+    return 4;
+  });
+}
+
+// src/cpu/instructions/logical.ts
+var REG_ORDER3 = ["b", "c", "d", "e", "h", "l", "M", "a"];
+function getReg3(regs, r, bus) {
+  if (r === "M") return bus.read(regs.hl);
+  return regs[r];
+}
+function setLogicFlags(flags, result) {
+  const r8 = u8(result);
+  flags.s = signBit(r8);
+  flags.z = zeroFlag(r8);
+  flags.p = parityFlag(r8);
+  flags.cy = false;
+}
+function registerLogical(decoder) {
+  for (let r = 0; r < 8; r++) {
+    const opcode = 160 | r;
+    const reg = REG_ORDER3[r];
+    const cycles = reg === "M" ? 7 : 4;
+    decoder.register(opcode, (regs, flags, bus) => {
+      const result = regs.a & getReg3(regs, reg, bus);
+      flags.ac = ((regs.a | getReg3(regs, reg, bus)) & 8) !== 0;
+      setLogicFlags(flags, result);
+      regs.a = u8(result);
+      return cycles;
+    });
+  }
+  decoder.register(230, (regs, flags, bus) => {
+    const imm = bus.read(regs.pc);
+    regs.pc = u16(regs.pc + 1);
+    flags.ac = ((regs.a | imm) & 8) !== 0;
+    const result = regs.a & imm;
+    setLogicFlags(flags, result);
+    regs.a = u8(result);
+    return 7;
+  });
+  for (let r = 0; r < 8; r++) {
+    const opcode = 176 | r;
+    const reg = REG_ORDER3[r];
+    const cycles = reg === "M" ? 7 : 4;
+    decoder.register(opcode, (regs, flags, bus) => {
+      const result = regs.a | getReg3(regs, reg, bus);
+      flags.ac = false;
+      setLogicFlags(flags, result);
+      regs.a = u8(result);
+      return cycles;
+    });
+  }
+  decoder.register(246, (regs, flags, bus) => {
+    const imm = bus.read(regs.pc);
+    regs.pc = u16(regs.pc + 1);
+    flags.ac = false;
+    const result = regs.a | imm;
+    setLogicFlags(flags, result);
+    regs.a = u8(result);
+    return 7;
+  });
+  for (let r = 0; r < 8; r++) {
+    const opcode = 168 | r;
+    const reg = REG_ORDER3[r];
+    const cycles = reg === "M" ? 7 : 4;
+    decoder.register(opcode, (regs, flags, bus) => {
+      const result = regs.a ^ getReg3(regs, reg, bus);
+      flags.ac = false;
+      setLogicFlags(flags, result);
+      regs.a = u8(result);
+      return cycles;
+    });
+  }
+  decoder.register(238, (regs, flags, bus) => {
+    const imm = bus.read(regs.pc);
+    regs.pc = u16(regs.pc + 1);
+    flags.ac = false;
+    const result = regs.a ^ imm;
+    setLogicFlags(flags, result);
+    regs.a = u8(result);
+    return 7;
+  });
+  for (let r = 0; r < 8; r++) {
+    const opcode = 184 | r;
+    const reg = REG_ORDER3[r];
+    const cycles = reg === "M" ? 7 : 4;
+    decoder.register(opcode, (regs, flags, bus) => {
+      const a = regs.a;
+      const b = getReg3(regs, reg, bus);
+      const result = a - b;
+      flags.cy = result < 0;
+      flags.ac = (a & 15) - (b & 15) < 0;
+      setLogicFlags(flags, result);
+      flags.cy = a < b;
+      return cycles;
+    });
+  }
+  decoder.register(254, (regs, flags, bus) => {
+    const a = regs.a;
+    const b = bus.read(regs.pc);
+    regs.pc = u16(regs.pc + 1);
+    const result = a - b;
+    flags.cy = a < b;
+    flags.ac = (a & 15) - (b & 15) < 0;
+    setLogicFlags(flags, result);
+    flags.cy = a < b;
+    return 7;
+  });
+  decoder.register(47, (regs, _flags, _bus) => {
+    regs.a = u8(~regs.a);
+    return 4;
+  });
+  decoder.register(63, (_regs, flags, _bus) => {
+    flags.cy = !flags.cy;
+    return 4;
+  });
+  decoder.register(55, (_regs, flags, _bus) => {
+    flags.cy = true;
+    return 4;
+  });
+}
+
+// src/cpu/instructions/rotate.ts
+function registerRotate(decoder) {
+  decoder.register(7, (regs, flags, _bus) => {
+    const a = regs.a;
+    flags.cy = (a & 128) !== 0;
+    regs.a = u8(a << 1 | (flags.cy ? 1 : 0));
+    return 4;
+  });
+  decoder.register(15, (regs, flags, _bus) => {
+    const a = regs.a;
+    flags.cy = (a & 1) !== 0;
+    regs.a = u8(a >> 1 | (flags.cy ? 128 : 0));
+    return 4;
+  });
+  decoder.register(23, (regs, flags, _bus) => {
+    const a = regs.a;
+    const newCY = (a & 128) !== 0;
+    regs.a = u8(a << 1 | (flags.cy ? 1 : 0));
+    flags.cy = newCY;
+    return 4;
+  });
+  decoder.register(31, (regs, flags, _bus) => {
+    const a = regs.a;
+    const newCY = (a & 1) !== 0;
+    regs.a = u8(a >> 1 | (flags.cy ? 128 : 0));
+    flags.cy = newCY;
+    return 4;
+  });
+}
+
+// src/cpu/instructions/branch.ts
+function readAddr(regs, bus) {
+  const lo2 = bus.read(regs.pc);
+  const hi2 = bus.read(u16(regs.pc + 1));
+  regs.pc = u16(regs.pc + 2);
+  return toWord(hi2, lo2);
+}
+function registerBranch(decoder) {
+  decoder.register(195, (regs, _flags, bus) => {
+    regs.pc = readAddr(regs, bus);
+    return 10;
+  });
+  const jccTable = [
+    [194, (f) => !f.z],
+    // JNZ
+    [202, (f) => f.z],
+    // JZ
+    [210, (f) => !f.cy],
+    // JNC
+    [218, (f) => f.cy],
+    // JC
+    [226, (f) => !f.p],
+    // JPO (parity odd)
+    [234, (f) => f.p],
+    // JPE (parity even)
+    [242, (f) => !f.s],
+    // JP (positive)
+    [250, (f) => f.s]
+    // JM (minus)
+  ];
+  for (const [opcode, cond2] of jccTable) {
+    decoder.register(opcode, (regs, flags, bus) => {
+      const addr = readAddr(regs, bus);
+      if (cond2(flags)) regs.pc = addr;
+      return 10;
+    });
+  }
+  decoder.register(205, (regs, _flags, bus) => {
+    const addr = readAddr(regs, bus);
+    regs.sp = u16(regs.sp - 1);
+    bus.write(regs.sp, regs.pc >> 8 & 255);
+    regs.sp = u16(regs.sp - 1);
+    bus.write(regs.sp, regs.pc & 255);
+    regs.pc = addr;
+    return 17;
+  });
+  const callTable = [
+    [196, (f) => !f.z],
+    // CNZ
+    [204, (f) => f.z],
+    // CZ
+    [212, (f) => !f.cy],
+    // CNC
+    [220, (f) => f.cy],
+    // CC
+    [228, (f) => !f.p],
+    // CPO
+    [236, (f) => f.p],
+    // CPE
+    [244, (f) => !f.s],
+    // CP
+    [252, (f) => f.s]
+    // CM
+  ];
+  for (const [opcode, cond2] of callTable) {
+    decoder.register(opcode, (regs, flags, bus) => {
+      const addr = readAddr(regs, bus);
+      if (cond2(flags)) {
+        regs.sp = u16(regs.sp - 1);
+        bus.write(regs.sp, regs.pc >> 8 & 255);
+        regs.sp = u16(regs.sp - 1);
+        bus.write(regs.sp, regs.pc & 255);
+        regs.pc = addr;
+        return 17;
+      }
+      return 11;
+    });
+  }
+  decoder.register(201, (regs, _flags, bus) => {
+    const lo2 = bus.read(regs.sp);
+    const hi2 = bus.read(u16(regs.sp + 1));
+    regs.sp = u16(regs.sp + 2);
+    regs.pc = toWord(hi2, lo2);
+    return 10;
+  });
+  const retTable = [
+    [192, (f) => !f.z],
+    // RNZ
+    [200, (f) => f.z],
+    // RZ
+    [208, (f) => !f.cy],
+    // RNC
+    [216, (f) => f.cy],
+    // RC
+    [224, (f) => !f.p],
+    // RPO
+    [232, (f) => f.p],
+    // RPE
+    [240, (f) => !f.s],
+    // RP
+    [248, (f) => f.s]
+    // RM
+  ];
+  for (const [opcode, cond2] of retTable) {
+    decoder.register(opcode, (regs, flags, bus) => {
+      if (cond2(flags)) {
+        const lo2 = bus.read(regs.sp);
+        const hi2 = bus.read(u16(regs.sp + 1));
+        regs.sp = u16(regs.sp + 2);
+        regs.pc = toWord(hi2, lo2);
+        return 11;
+      }
+      return 5;
+    });
+  }
+  for (let n = 0; n < 8; n++) {
+    const opcode = 199 | n << 3;
+    decoder.register(opcode, (regs, _flags, bus) => {
+      regs.sp = u16(regs.sp - 1);
+      bus.write(regs.sp, regs.pc >> 8 & 255);
+      regs.sp = u16(regs.sp - 1);
+      bus.write(regs.sp, regs.pc & 255);
+      regs.pc = n * 8;
+      return 11;
+    });
+  }
+  decoder.register(233, (regs, _flags, _bus) => {
+    regs.pc = regs.hl;
+    return 5;
+  });
+}
+
+// src/cpu/instructions/stack.ts
+function registerStack(decoder) {
+  decoder.register(197, (regs, _flags, bus) => {
+    regs.sp = u16(regs.sp - 1);
+    bus.write(regs.sp, regs.b);
+    regs.sp = u16(regs.sp - 1);
+    bus.write(regs.sp, regs.c);
+    return 11;
+  });
+  decoder.register(213, (regs, _flags, bus) => {
+    regs.sp = u16(regs.sp - 1);
+    bus.write(regs.sp, regs.d);
+    regs.sp = u16(regs.sp - 1);
+    bus.write(regs.sp, regs.e);
+    return 11;
+  });
+  decoder.register(229, (regs, _flags, bus) => {
+    regs.sp = u16(regs.sp - 1);
+    bus.write(regs.sp, regs.h);
+    regs.sp = u16(regs.sp - 1);
+    bus.write(regs.sp, regs.l);
+    return 11;
+  });
+  decoder.register(245, (regs, flags, bus) => {
+    regs.sp = u16(regs.sp - 1);
+    bus.write(regs.sp, regs.a);
+    regs.sp = u16(regs.sp - 1);
+    bus.write(regs.sp, flags.toByte());
+    return 11;
+  });
+  decoder.register(193, (regs, _flags, bus) => {
+    regs.c = bus.read(regs.sp);
+    regs.sp = u16(regs.sp + 1);
+    regs.b = bus.read(regs.sp);
+    regs.sp = u16(regs.sp + 1);
+    return 10;
+  });
+  decoder.register(209, (regs, _flags, bus) => {
+    regs.e = bus.read(regs.sp);
+    regs.sp = u16(regs.sp + 1);
+    regs.d = bus.read(regs.sp);
+    regs.sp = u16(regs.sp + 1);
+    return 10;
+  });
+  decoder.register(225, (regs, _flags, bus) => {
+    regs.l = bus.read(regs.sp);
+    regs.sp = u16(regs.sp + 1);
+    regs.h = bus.read(regs.sp);
+    regs.sp = u16(regs.sp + 1);
+    return 10;
+  });
+  decoder.register(241, (regs, flags, bus) => {
+    const psw = bus.read(regs.sp);
+    regs.sp = u16(regs.sp + 1);
+    regs.a = bus.read(regs.sp);
+    regs.sp = u16(regs.sp + 1);
+    flags.fromByte(psw);
+    return 10;
+  });
+  decoder.register(227, (regs, _flags, bus) => {
+    const lo2 = bus.read(regs.sp);
+    const hi2 = bus.read(u16(regs.sp + 1));
+    bus.write(regs.sp, regs.l);
+    bus.write(u16(regs.sp + 1), regs.h);
+    regs.l = lo2;
+    regs.h = hi2;
+    return 18;
+  });
+  decoder.register(249, (regs, _flags, _bus) => {
+    regs.sp = regs.hl;
+    return 5;
+  });
+}
+
+// src/cpu/instructions/io.ts
+function registerIO(decoder) {
+  decoder.register(219, (regs, _flags, bus) => {
+    const port = bus.read(regs.pc);
+    regs.pc = u16(regs.pc + 1);
+    regs.a = bus.ioRead(port);
+    return 10;
+  });
+  decoder.register(211, (regs, _flags, bus) => {
+    const port = bus.read(regs.pc);
+    regs.pc = u16(regs.pc + 1);
+    bus.ioWrite(port, regs.a);
+    return 10;
+  });
+}
+
+// src/cpu/Cpu8080.ts
+var Cpu8080 = class {
+  registers;
+  flags;
+  bus;
+  pic;
+  decoder;
+  inte = false;
+  pendingEI = false;
+  halted = false;
+  /** Front-panel status byte of the last instruction (Bitsby8 cockpit). */
+  lastStatus = FETCH_STATUS;
+  statusTable = buildStatusTable();
+  /** Program counter accessor (ICpu); proxies the register file. */
+  get pc() {
+    return this.registers.pc;
+  }
+  set pc(v) {
+    this.registers.pc = u16(v);
+  }
+  /** Uniform register/flags snapshot for introspection (ICpu). */
+  state() {
+    const r = this.registers;
+    return { pc: r.pc, sp: r.sp, a: r.a, f: this.flags.toByte(), b: r.b, c: r.c, d: r.d, e: r.e, h: r.h, l: r.l, halted: this.halted, inte: this.inte, intPending: this.pic.hasPendingInterrupt(), status: this.lastStatus };
+  }
+  constructor(bus, pic) {
+    this.bus = bus;
+    this.pic = pic;
+    this.registers = new Registers();
+    this.flags = new Flags();
+    this.decoder = new Decoder();
+    this.buildDecoder();
+  }
+  buildDecoder() {
+    registerControl(this.decoder);
+    registerData(this.decoder);
+    registerAlu(this.decoder);
+    registerLogical(this.decoder);
+    registerRotate(this.decoder);
+    registerBranch(this.decoder);
+    registerStack(this.decoder);
+    registerIO(this.decoder);
+  }
+  reset() {
+    this.registers.reset();
+    this.flags.reset();
+    this.inte = false;
+    this.pendingEI = false;
+    this.halted = false;
+    this.lastStatus = FETCH_STATUS;
+  }
+  step() {
+    const regs = this.registers;
+    if (this.halted) {
+      if (this.inte && this.pic.hasPendingInterrupt()) {
+        this.handleInterrupt();
+        return 11;
+      }
+      return 4;
+    }
+    if (this.pendingEI) {
+      this.inte = true;
+      this.pendingEI = false;
+    }
+    if (this.inte && this.pic.hasPendingInterrupt()) {
+      this.handleInterrupt();
+      return 11;
+    }
+    const opcode = this.bus.read(regs.pc);
+    regs.pc = u16(regs.pc + 1);
+    this.lastStatus = this.statusTable[opcode];
+    if (opcode === 118) {
+      this.halted = true;
+      return 7;
+    }
+    if (opcode === 251) {
+      this.pendingEI = true;
+      return 4;
+    }
+    if (opcode === 243) {
+      this.inte = false;
+      this.pendingEI = false;
+      return 4;
+    }
+    const handler = this.decoder.decode(opcode);
+    return handler(regs, this.flags, this.bus);
+  }
+  handleInterrupt() {
+    this.inte = false;
+    this.halted = false;
+    this.lastStatus = INTA_STATUS;
+    const rstByte = this.bus.acknowledgeInterrupt();
+    const regs = this.registers;
+    regs.sp = u16(regs.sp - 1);
+    this.bus.write(regs.sp, regs.pc >> 8 & 255);
+    regs.sp = u16(regs.sp - 1);
+    this.bus.write(regs.sp, regs.pc & 255);
+    regs.pc = rstByte & 56;
+  }
+  /**
+   * Run until halted or maxCycles exceeded.
+   * Returns total T-states executed.
+   */
+  run(maxCycles = Infinity) {
+    let total = 0n;
+    while (!this.halted && total < BigInt(maxCycles)) {
+      total += BigInt(this.step());
+    }
+    return total;
+  }
+};
+
+// src/cpu/z80/RegistersZ80.ts
+var RegistersZ80 = class {
+  a = 0;
+  b = 0;
+  c = 0;
+  d = 0;
+  e = 0;
+  h = 0;
+  l = 0;
+  // Shadow set (swapped by EXX / EX AF,AF'). F' is a raw PSW byte.
+  a2 = 0;
+  f2 = 0;
+  b2 = 0;
+  c2 = 0;
+  d2 = 0;
+  e2 = 0;
+  h2 = 0;
+  l2 = 0;
+  ix = 0;
+  iy = 0;
+  sp = 0;
+  pc = 0;
+  i = 0;
+  // interrupt vector base
+  r = 0;
+  // refresh counter (bit 7 preserved across increments)
+  wz = 0;
+  // MEMPTR — internal 16-bit temp
+  /** BC register pair */
+  get bc() {
+    return this.b << 8 | this.c;
+  }
+  set bc(v) {
+    this.b = v >> 8 & 255;
+    this.c = v & 255;
+  }
+  /** DE register pair */
+  get de() {
+    return this.d << 8 | this.e;
+  }
+  set de(v) {
+    this.d = v >> 8 & 255;
+    this.e = v & 255;
+  }
+  /** HL register pair */
+  get hl() {
+    return this.h << 8 | this.l;
+  }
+  set hl(v) {
+    this.h = v >> 8 & 255;
+    this.l = v & 255;
+  }
+  /** IX high/low bytes (undocumented IXH/IXL) */
+  get ixh() {
+    return this.ix >> 8 & 255;
+  }
+  set ixh(v) {
+    this.ix = (v & 255) << 8 | this.ix & 255;
+  }
+  get ixl() {
+    return this.ix & 255;
+  }
+  set ixl(v) {
+    this.ix = this.ix & 65280 | v & 255;
+  }
+  /** IY high/low bytes (undocumented IYH/IYL) */
+  get iyh() {
+    return this.iy >> 8 & 255;
+  }
+  set iyh(v) {
+    this.iy = (v & 255) << 8 | this.iy & 255;
+  }
+  get iyl() {
+    return this.iy & 255;
+  }
+  set iyl(v) {
+    this.iy = this.iy & 65280 | v & 255;
+  }
+  /** M1 refresh tick: low 7 bits increment, bit 7 preserved. */
+  incR() {
+    this.r = this.r & 128 | this.r + 1 & 127;
+  }
+  /** EXX: swap BC/DE/HL with their shadows (AF is separate, via EX AF,AF'). */
+  exx() {
+    let t = this.b;
+    this.b = this.b2;
+    this.b2 = t;
+    t = this.c;
+    this.c = this.c2;
+    this.c2 = t;
+    t = this.d;
+    this.d = this.d2;
+    this.d2 = t;
+    t = this.e;
+    this.e = this.e2;
+    this.e2 = t;
+    t = this.h;
+    this.h = this.h2;
+    this.h2 = t;
+    t = this.l;
+    this.l = this.l2;
+    this.l2 = t;
+  }
+  reset() {
+    this.a = this.b = this.c = this.d = this.e = this.h = this.l = 0;
+    this.a2 = this.f2 = this.b2 = this.c2 = this.d2 = this.e2 = this.h2 = this.l2 = 0;
+    this.ix = this.iy = 0;
+    this.sp = 0;
+    this.pc = 0;
+    this.i = this.r = 0;
+    this.wz = 0;
+  }
+};
+
+// src/cpu/z80/FlagsZ80.ts
+var FlagsZ80 = class {
+  s = false;
+  z = false;
+  y = false;
+  h = false;
+  x = false;
+  pv = false;
+  n = false;
+  c = false;
+  toByte() {
+    return (this.s ? 128 : 0) | (this.z ? 64 : 0) | (this.y ? 32 : 0) | (this.h ? 16 : 0) | (this.x ? 8 : 0) | (this.pv ? 4 : 0) | (this.n ? 2 : 0) | (this.c ? 1 : 0);
+  }
+  fromByte(b) {
+    this.s = (b & 128) !== 0;
+    this.z = (b & 64) !== 0;
+    this.y = (b & 32) !== 0;
+    this.h = (b & 16) !== 0;
+    this.x = (b & 8) !== 0;
+    this.pv = (b & 4) !== 0;
+    this.n = (b & 2) !== 0;
+    this.c = (b & 1) !== 0;
+  }
+  reset() {
+    this.s = this.z = this.y = this.h = this.x = this.pv = this.n = this.c = false;
+  }
+};
+
+// src/cpu/z80/views.ts
+function sext8(b) {
+  return (b & 128) !== 0 ? (b & 255) - 256 : b & 255;
+}
+var HL_VIEW = {
+  kind: "hl",
+  indexed: false,
+  memExtra: 0,
+  getPair: (r) => r.hl,
+  setPair: (r, v) => {
+    r.hl = v & 65535;
+  },
+  getHi: (r) => r.h,
+  setHi: (r, v) => {
+    r.h = v & 255;
+  },
+  getLo: (r) => r.l,
+  setLo: (r, v) => {
+    r.l = v & 255;
+  },
+  // Plain (HL) access does not touch WZ.
+  memAddr: (cpu) => cpu.regs.hl
+};
+function makeIndexView(kind, getReg4, setReg2, getH, setH, getL, setL) {
+  return {
+    kind,
+    indexed: true,
+    memExtra: 8,
+    // 3 T to read d + 5 T internal add
+    getPair: getReg4,
+    setPair: setReg2,
+    getHi: getH,
+    setHi: setH,
+    getLo: getL,
+    setLo: setL,
+    memAddr: (cpu) => {
+      const d = sext8(cpu.fetchByte());
+      const addr = getReg4(cpu.regs) + d & 65535;
+      cpu.regs.wz = addr;
+      return addr;
+    }
+  };
+}
+var IX_VIEW = makeIndexView(
+  "ix",
+  (r) => r.ix,
+  (r, v) => {
+    r.ix = v & 65535;
+  },
+  (r) => r.ixh,
+  (r, v) => {
+    r.ixh = v;
+  },
+  (r) => r.ixl,
+  (r, v) => {
+    r.ixl = v;
+  }
+);
+var IY_VIEW = makeIndexView(
+  "iy",
+  (r) => r.iy,
+  (r, v) => {
+    r.iy = v & 65535;
+  },
+  (r) => r.iyh,
+  (r, v) => {
+    r.iyh = v;
+  },
+  (r) => r.iyl,
+  (r, v) => {
+    r.iyl = v;
+  }
+);
+
+// src/cpu/z80/regcodes.ts
+function getR(regs, view, code) {
+  switch (code) {
+    case 0:
+      return regs.b;
+    case 1:
+      return regs.c;
+    case 2:
+      return regs.d;
+    case 3:
+      return regs.e;
+    case 4:
+      return view.getHi(regs);
+    case 5:
+      return view.getLo(regs);
+    case 7:
+      return regs.a;
+    default:
+      return 0;
+  }
+}
+function setR(regs, view, code, v) {
+  const b = v & 255;
+  switch (code) {
+    case 0:
+      regs.b = b;
+      break;
+    case 1:
+      regs.c = b;
+      break;
+    case 2:
+      regs.d = b;
+      break;
+    case 3:
+      regs.e = b;
+      break;
+    case 4:
+      view.setHi(regs, b);
+      break;
+    case 5:
+      view.setLo(regs, b);
+      break;
+    case 7:
+      regs.a = b;
+      break;
+  }
+}
+function getRealR(regs, code) {
+  switch (code) {
+    case 0:
+      return regs.b;
+    case 1:
+      return regs.c;
+    case 2:
+      return regs.d;
+    case 3:
+      return regs.e;
+    case 4:
+      return regs.h;
+    case 5:
+      return regs.l;
+    case 7:
+      return regs.a;
+    default:
+      return 0;
+  }
+}
+function setRealR(regs, code, v) {
+  const b = v & 255;
+  switch (code) {
+    case 0:
+      regs.b = b;
+      break;
+    case 1:
+      regs.c = b;
+      break;
+    case 2:
+      regs.d = b;
+      break;
+    case 3:
+      regs.e = b;
+      break;
+    case 4:
+      regs.h = b;
+      break;
+    case 5:
+      regs.l = b;
+      break;
+    case 7:
+      regs.a = b;
+      break;
+  }
+}
+
+// src/cpu/z80/instructions/load.ts
+function read16(cpu, addr) {
+  const lo2 = cpu.bus.read(addr);
+  const hi2 = cpu.bus.read(u16(addr + 1));
+  return hi2 << 8 | lo2;
+}
+function write16(cpu, addr, v) {
+  cpu.bus.write(addr, v & 255);
+  cpu.bus.write(u16(addr + 1), v >> 8 & 255);
+}
+function registerLoad(table, view) {
+  for (let op = 64; op <= 127; op++) {
+    if (op === 118) continue;
+    const dst = op >> 3 & 7;
+    const src = op & 7;
+    if (src === 6) {
+      table[op] = (cpu) => {
+        const addr = view.memAddr(cpu);
+        setRealR(cpu.regs, dst, cpu.bus.read(addr));
+        return 7 + view.memExtra;
+      };
+    } else if (dst === 6) {
+      table[op] = (cpu) => {
+        const addr = view.memAddr(cpu);
+        cpu.bus.write(addr, getRealR(cpu.regs, src));
+        return 7 + view.memExtra;
+      };
+    } else {
+      table[op] = (cpu) => {
+        setR(cpu.regs, view, dst, getR(cpu.regs, view, src));
+        return 4;
+      };
+    }
+  }
+  for (let r = 0; r < 8; r++) {
+    const op = 6 | r << 3;
+    if (r === 6) {
+      table[op] = (cpu) => {
+        const addr = view.memAddr(cpu);
+        cpu.bus.write(addr, cpu.fetchByte());
+        return view.indexed ? 15 : 10;
+      };
+    } else {
+      table[op] = (cpu) => {
+        setR(cpu.regs, view, r, cpu.fetchByte());
+        return 7;
+      };
+    }
+  }
+  table[10] = (cpu) => {
+    const a = cpu.regs.bc;
+    cpu.regs.a = cpu.bus.read(a);
+    cpu.regs.wz = u16(a + 1);
+    return 7;
+  };
+  table[26] = (cpu) => {
+    const a = cpu.regs.de;
+    cpu.regs.a = cpu.bus.read(a);
+    cpu.regs.wz = u16(a + 1);
+    return 7;
+  };
+  table[58] = (cpu) => {
+    const nn = cpu.fetchWord();
+    cpu.regs.a = cpu.bus.read(nn);
+    cpu.regs.wz = u16(nn + 1);
+    return 13;
+  };
+  table[2] = (cpu) => {
+    const a = cpu.regs.bc;
+    cpu.bus.write(a, cpu.regs.a);
+    cpu.regs.wz = (cpu.regs.a << 8 | a + 1 & 255) & 65535;
+    return 7;
+  };
+  table[18] = (cpu) => {
+    const a = cpu.regs.de;
+    cpu.bus.write(a, cpu.regs.a);
+    cpu.regs.wz = (cpu.regs.a << 8 | a + 1 & 255) & 65535;
+    return 7;
+  };
+  table[50] = (cpu) => {
+    const nn = cpu.fetchWord();
+    cpu.bus.write(nn, cpu.regs.a);
+    cpu.regs.wz = (cpu.regs.a << 8 | nn + 1 & 255) & 65535;
+    return 13;
+  };
+  table[1] = (cpu) => {
+    cpu.regs.bc = cpu.fetchWord();
+    return 10;
+  };
+  table[17] = (cpu) => {
+    cpu.regs.de = cpu.fetchWord();
+    return 10;
+  };
+  table[33] = (cpu) => {
+    view.setPair(cpu.regs, cpu.fetchWord());
+    return 10;
+  };
+  table[49] = (cpu) => {
+    cpu.regs.sp = cpu.fetchWord();
+    return 10;
+  };
+  table[34] = (cpu) => {
+    const nn = cpu.fetchWord();
+    write16(cpu, nn, view.getPair(cpu.regs));
+    cpu.regs.wz = u16(nn + 1);
+    return 16;
+  };
+  table[42] = (cpu) => {
+    const nn = cpu.fetchWord();
+    view.setPair(cpu.regs, read16(cpu, nn));
+    cpu.regs.wz = u16(nn + 1);
+    return 16;
+  };
+  table[249] = (cpu) => {
+    cpu.regs.sp = view.getPair(cpu.regs);
+    return 6;
+  };
+}
+
+// src/cpu/z80/instructions/exchange.ts
+function registerExchange(table, view) {
+  table[235] = (cpu) => {
+    const de = cpu.regs.de;
+    cpu.regs.de = cpu.regs.hl;
+    cpu.regs.hl = de;
+    return 4;
+  };
+  table[8] = (cpu) => {
+    const a = cpu.regs.a;
+    const f = cpu.flags.toByte();
+    cpu.regs.a = cpu.regs.a2;
+    cpu.flags.fromByte(cpu.regs.f2);
+    cpu.regs.a2 = a;
+    cpu.regs.f2 = f;
+    return 4;
+  };
+  table[217] = (cpu) => {
+    cpu.regs.exx();
+    return 4;
+  };
+  table[227] = (cpu) => {
+    const sp = cpu.regs.sp;
+    const lo2 = cpu.bus.read(sp);
+    const hi2 = cpu.bus.read(u16(sp + 1));
+    const val = view.getPair(cpu.regs);
+    cpu.bus.write(sp, val & 255);
+    cpu.bus.write(u16(sp + 1), val >> 8 & 255);
+    const swapped = hi2 << 8 | lo2;
+    view.setPair(cpu.regs, swapped);
+    cpu.regs.wz = swapped;
+    return 19;
+  };
+}
+
+// src/cpu/z80/flagHelpers.ts
+var PARITY = (() => {
+  const t = new Array(256);
+  for (let v = 0; v < 256; v++) {
+    let x = v;
+    x ^= x >> 4;
+    x ^= x >> 2;
+    x ^= x >> 1;
+    t[v] = (x & 1) === 0;
+  }
+  return t;
+})();
+function parityEven(v) {
+  return PARITY[v & 255];
+}
+function setSzyx(f, r) {
+  f.s = (r & 128) !== 0;
+  f.z = (r & 255) === 0;
+  f.y = (r & 32) !== 0;
+  f.x = (r & 8) !== 0;
+}
+function setSzyxp(f, r) {
+  setSzyx(f, r);
+  f.pv = PARITY[r & 255];
+}
+function add8(f, a, b, cIn) {
+  const sum = a + b + cIn;
+  const r = sum & 255;
+  setSzyx(f, r);
+  f.h = (a & 15) + (b & 15) + cIn > 15;
+  f.pv = (~(a ^ b) & (a ^ r) & 128) !== 0;
+  f.n = false;
+  f.c = sum > 255;
+  return r;
+}
+function sub8(f, a, b, cIn) {
+  const diff = a - b - cIn;
+  const r = diff & 255;
+  setSzyx(f, r);
+  f.h = (a & 15) - (b & 15) - cIn < 0;
+  f.pv = ((a ^ b) & (a ^ r) & 128) !== 0;
+  f.n = true;
+  f.c = diff < 0;
+  return r;
+}
+function cp8(f, a, b) {
+  const diff = a - b;
+  const r = diff & 255;
+  f.s = (r & 128) !== 0;
+  f.z = r === 0;
+  f.y = (b & 32) !== 0;
+  f.x = (b & 8) !== 0;
+  f.h = (a & 15) - (b & 15) < 0;
+  f.pv = ((a ^ b) & (a ^ r) & 128) !== 0;
+  f.n = true;
+  f.c = diff < 0;
+}
+function inc8(f, v) {
+  const r = v + 1 & 255;
+  setSzyx(f, r);
+  f.h = (v & 15) === 15;
+  f.pv = v === 127;
+  f.n = false;
+  return r;
+}
+function dec8(f, v) {
+  const r = v - 1 & 255;
+  setSzyx(f, r);
+  f.h = (v & 15) === 0;
+  f.pv = v === 128;
+  f.n = true;
+  return r;
+}
+function setLogicFlags2(f, r, hVal) {
+  setSzyxp(f, r);
+  f.h = hVal;
+  f.n = false;
+  f.c = false;
+}
+function add16(f, a, b) {
+  const sum = a + b;
+  const r = sum & 65535;
+  f.h = (a & 4095) + (b & 4095) > 4095;
+  f.n = false;
+  f.c = sum > 65535;
+  f.y = (r & 8192) !== 0;
+  f.x = (r & 2048) !== 0;
+  return r;
+}
+function adc16(f, a, b, cIn) {
+  const sum = a + b + cIn;
+  const r = sum & 65535;
+  f.s = (r & 32768) !== 0;
+  f.z = r === 0;
+  f.h = (a & 4095) + (b & 4095) + cIn > 4095;
+  f.pv = (~(a ^ b) & (a ^ r) & 32768) !== 0;
+  f.n = false;
+  f.c = sum > 65535;
+  f.y = (r & 8192) !== 0;
+  f.x = (r & 2048) !== 0;
+  return r;
+}
+function sbc16(f, a, b, cIn) {
+  const diff = a - b - cIn;
+  const r = diff & 65535;
+  f.s = (r & 32768) !== 0;
+  f.z = r === 0;
+  f.h = (a & 4095) - (b & 4095) - cIn < 0;
+  f.pv = ((a ^ b) & (a ^ r) & 32768) !== 0;
+  f.n = true;
+  f.c = diff < 0;
+  f.y = (r & 8192) !== 0;
+  f.x = (r & 2048) !== 0;
+  return r;
+}
+
+// src/cpu/z80/instructions/alu8.ts
+function applyAlu(cpu, kind, v) {
+  const f = cpu.flags;
+  const regs = cpu.regs;
+  switch (kind) {
+    case 0:
+      regs.a = add8(f, regs.a, v, 0);
+      break;
+    // ADD
+    case 1:
+      regs.a = add8(f, regs.a, v, f.c ? 1 : 0);
+      break;
+    // ADC
+    case 2:
+      regs.a = sub8(f, regs.a, v, 0);
+      break;
+    // SUB
+    case 3:
+      regs.a = sub8(f, regs.a, v, f.c ? 1 : 0);
+      break;
+    // SBC
+    case 4:
+      regs.a = regs.a & v;
+      setLogicFlags2(f, regs.a, true);
+      break;
+    // AND
+    case 5:
+      regs.a = regs.a ^ v;
+      setLogicFlags2(f, regs.a, false);
+      break;
+    // XOR
+    case 6:
+      regs.a = regs.a | v;
+      setLogicFlags2(f, regs.a, false);
+      break;
+    // OR
+    case 7:
+      cp8(f, regs.a, v);
+      break;
+  }
+}
+function registerAlu8(table, view) {
+  for (let op = 128; op <= 191; op++) {
+    const kind = op >> 3 & 7;
+    const reg = op & 7;
+    if (reg === 6) {
+      table[op] = (cpu) => {
+        const addr = view.memAddr(cpu);
+        applyAlu(cpu, kind, cpu.bus.read(addr));
+        return 7 + view.memExtra;
+      };
+    } else {
+      table[op] = (cpu) => {
+        applyAlu(cpu, kind, getR(cpu.regs, view, reg));
+        return 4;
+      };
+    }
+  }
+  for (const op of [198, 206, 214, 222, 230, 238, 246, 254]) {
+    const kind = op >> 3 & 7;
+    table[op] = (cpu) => {
+      applyAlu(cpu, kind, cpu.fetchByte());
+      return 7;
+    };
+  }
+  for (let r = 0; r < 8; r++) {
+    const op = 4 | r << 3;
+    if (r === 6) {
+      table[op] = (cpu) => {
+        const addr = view.memAddr(cpu);
+        cpu.bus.write(addr, inc8(cpu.flags, cpu.bus.read(addr)));
+        return 11 + view.memExtra;
+      };
+    } else {
+      table[op] = (cpu) => {
+        setR(cpu.regs, view, r, inc8(cpu.flags, getR(cpu.regs, view, r)));
+        return 4;
+      };
+    }
+  }
+  for (let r = 0; r < 8; r++) {
+    const op = 5 | r << 3;
+    if (r === 6) {
+      table[op] = (cpu) => {
+        const addr = view.memAddr(cpu);
+        cpu.bus.write(addr, dec8(cpu.flags, cpu.bus.read(addr)));
+        return 11 + view.memExtra;
+      };
+    } else {
+      table[op] = (cpu) => {
+        setR(cpu.regs, view, r, dec8(cpu.flags, getR(cpu.regs, view, r)));
+        return 4;
+      };
+    }
+  }
+}
+
+// src/cpu/z80/instructions/alu16.ts
+function registerAlu16(table, view) {
+  table[3] = (cpu) => {
+    cpu.regs.bc = u16(cpu.regs.bc + 1);
+    return 6;
+  };
+  table[19] = (cpu) => {
+    cpu.regs.de = u16(cpu.regs.de + 1);
+    return 6;
+  };
+  table[35] = (cpu) => {
+    view.setPair(cpu.regs, u16(view.getPair(cpu.regs) + 1));
+    return 6;
+  };
+  table[51] = (cpu) => {
+    cpu.regs.sp = u16(cpu.regs.sp + 1);
+    return 6;
+  };
+  table[11] = (cpu) => {
+    cpu.regs.bc = u16(cpu.regs.bc - 1);
+    return 6;
+  };
+  table[27] = (cpu) => {
+    cpu.regs.de = u16(cpu.regs.de - 1);
+    return 6;
+  };
+  table[43] = (cpu) => {
+    view.setPair(cpu.regs, u16(view.getPair(cpu.regs) - 1));
+    return 6;
+  };
+  table[59] = (cpu) => {
+    cpu.regs.sp = u16(cpu.regs.sp - 1);
+    return 6;
+  };
+  const addHl = (getOperand) => (cpu) => {
+    const hl = view.getPair(cpu.regs);
+    cpu.regs.wz = u16(hl + 1);
+    view.setPair(cpu.regs, add16(cpu.flags, hl, getOperand(cpu)));
+    return 11;
+  };
+  table[9] = addHl((cpu) => cpu.regs.bc);
+  table[25] = addHl((cpu) => cpu.regs.de);
+  table[41] = addHl((cpu) => view.getPair(cpu.regs));
+  table[57] = addHl((cpu) => cpu.regs.sp);
+}
+
+// src/cpu/z80/instructions/rotate.ts
+function registerRotate2(table, _view) {
+  const finish = (f, a, carry) => {
+    f.c = carry !== 0;
+    f.h = false;
+    f.n = false;
+    f.y = (a & 32) !== 0;
+    f.x = (a & 8) !== 0;
+  };
+  table[7] = (cpu) => {
+    const a = cpu.regs.a;
+    const c = a >> 7 & 1;
+    cpu.regs.a = (a << 1 | c) & 255;
+    finish(cpu.flags, cpu.regs.a, c);
+    return 4;
+  };
+  table[15] = (cpu) => {
+    const a = cpu.regs.a;
+    const c = a & 1;
+    cpu.regs.a = (a >> 1 | c << 7) & 255;
+    finish(cpu.flags, cpu.regs.a, c);
+    return 4;
+  };
+  table[23] = (cpu) => {
+    const a = cpu.regs.a;
+    const c = a >> 7 & 1;
+    cpu.regs.a = (a << 1 | (cpu.flags.c ? 1 : 0)) & 255;
+    finish(cpu.flags, cpu.regs.a, c);
+    return 4;
+  };
+  table[31] = (cpu) => {
+    const a = cpu.regs.a;
+    const c = a & 1;
+    cpu.regs.a = (a >> 1 | (cpu.flags.c ? 128 : 0)) & 255;
+    finish(cpu.flags, cpu.regs.a, c);
+    return 4;
+  };
+}
+
+// src/cpu/z80/instructions/jump.ts
+function cond(f, cc) {
+  switch (cc) {
+    case 0:
+      return !f.z;
+    case 1:
+      return f.z;
+    case 2:
+      return !f.c;
+    case 3:
+      return f.c;
+    case 4:
+      return !f.pv;
+    case 5:
+      return f.pv;
+    case 6:
+      return !f.s;
+    default:
+      return f.s;
+  }
+}
+function registerJump(table, view) {
+  table[195] = (cpu) => {
+    const nn = cpu.fetchWord();
+    cpu.regs.pc = nn;
+    cpu.regs.wz = nn;
+    return 10;
+  };
+  for (let cc = 0; cc < 8; cc++) {
+    const op = 194 | cc << 3;
+    table[op] = (cpu) => {
+      const nn = cpu.fetchWord();
+      cpu.regs.wz = nn;
+      if (cond(cpu.flags, cc)) cpu.regs.pc = nn;
+      return 10;
+    };
+  }
+  table[24] = (cpu) => {
+    const e = sext8(cpu.fetchByte());
+    cpu.regs.pc = u16(cpu.regs.pc + e);
+    cpu.regs.wz = cpu.regs.pc;
+    return 12;
+  };
+  for (let cc = 0; cc < 4; cc++) {
+    const op = 32 | cc << 3;
+    table[op] = (cpu) => {
+      const e = sext8(cpu.fetchByte());
+      if (cond(cpu.flags, cc)) {
+        cpu.regs.pc = u16(cpu.regs.pc + e);
+        cpu.regs.wz = cpu.regs.pc;
+        return 12;
+      }
+      return 7;
+    };
+  }
+  table[16] = (cpu) => {
+    const e = sext8(cpu.fetchByte());
+    cpu.regs.b = cpu.regs.b - 1 & 255;
+    if (cpu.regs.b !== 0) {
+      cpu.regs.pc = u16(cpu.regs.pc + e);
+      cpu.regs.wz = cpu.regs.pc;
+      return 13;
+    }
+    return 8;
+  };
+  table[205] = (cpu) => {
+    const nn = cpu.fetchWord();
+    cpu.regs.wz = nn;
+    cpu.push16(cpu.regs.pc);
+    cpu.regs.pc = nn;
+    return 17;
+  };
+  for (let cc = 0; cc < 8; cc++) {
+    const op = 196 | cc << 3;
+    table[op] = (cpu) => {
+      const nn = cpu.fetchWord();
+      cpu.regs.wz = nn;
+      if (cond(cpu.flags, cc)) {
+        cpu.push16(cpu.regs.pc);
+        cpu.regs.pc = nn;
+        return 17;
+      }
+      return 10;
+    };
+  }
+  table[201] = (cpu) => {
+    const pc = cpu.pop16();
+    cpu.regs.pc = pc;
+    cpu.regs.wz = pc;
+    return 10;
+  };
+  for (let cc = 0; cc < 8; cc++) {
+    const op = 192 | cc << 3;
+    table[op] = (cpu) => {
+      if (cond(cpu.flags, cc)) {
+        const pc = cpu.pop16();
+        cpu.regs.pc = pc;
+        cpu.regs.wz = pc;
+        return 11;
+      }
+      return 5;
+    };
+  }
+  for (let n = 0; n < 8; n++) {
+    const op = 199 | n << 3;
+    const target = n << 3;
+    table[op] = (cpu) => {
+      cpu.push16(cpu.regs.pc);
+      cpu.regs.pc = target;
+      cpu.regs.wz = target;
+      return 11;
+    };
+  }
+  table[233] = (cpu) => {
+    cpu.regs.pc = view.getPair(cpu.regs);
+    return 4;
+  };
+}
+
+// src/cpu/z80/instructions/stack.ts
+function registerStack2(table, view) {
+  table[197] = (cpu) => {
+    cpu.push16(cpu.regs.bc);
+    return 11;
+  };
+  table[213] = (cpu) => {
+    cpu.push16(cpu.regs.de);
+    return 11;
+  };
+  table[229] = (cpu) => {
+    cpu.push16(view.getPair(cpu.regs));
+    return 11;
+  };
+  table[245] = (cpu) => {
+    cpu.push16(cpu.regs.a << 8 | cpu.flags.toByte());
+    return 11;
+  };
+  table[193] = (cpu) => {
+    cpu.regs.bc = cpu.pop16();
+    return 10;
+  };
+  table[209] = (cpu) => {
+    cpu.regs.de = cpu.pop16();
+    return 10;
+  };
+  table[225] = (cpu) => {
+    view.setPair(cpu.regs, cpu.pop16());
+    return 10;
+  };
+  table[241] = (cpu) => {
+    const v = cpu.pop16();
+    cpu.regs.a = v >> 8 & 255;
+    cpu.flags.fromByte(v & 255);
+    return 10;
+  };
+}
+
+// src/cpu/z80/instructions/io.ts
+function registerIO2(table, _view) {
+  table[219] = (cpu) => {
+    const n = cpu.fetchByte();
+    cpu.regs.wz = (cpu.regs.a << 8 | n) + 1 & 65535;
+    cpu.regs.a = cpu.bus.ioRead(n) & 255;
+    return 11;
+  };
+  table[211] = (cpu) => {
+    const n = cpu.fetchByte();
+    cpu.bus.ioWrite(n, cpu.regs.a);
+    cpu.regs.wz = (cpu.regs.a << 8 | n + 1 & 255) & 65535;
+    return 11;
+  };
+}
+
+// src/cpu/z80/instructions/control.ts
+function registerControl2(table, _view) {
+  table[0] = (_cpu) => 4;
+  table[118] = (cpu) => {
+    cpu.halted = true;
+    return 4;
+  };
+  table[243] = (cpu) => {
+    cpu.iff1 = false;
+    cpu.iff2 = false;
+    cpu.pendingEI = false;
+    return 4;
+  };
+  table[251] = (cpu) => {
+    cpu.pendingEI = true;
+    return 4;
+  };
+  table[39] = (cpu) => {
+    const f = cpu.flags;
+    const a0 = cpu.regs.a;
+    let corr = 0;
+    let carry = false;
+    if (f.h || (a0 & 15) > 9) corr |= 6;
+    if (f.c || a0 > 153) {
+      corr |= 96;
+      carry = true;
+    }
+    const a = (f.n ? a0 - corr : a0 + corr) & 255;
+    cpu.regs.a = a;
+    f.c = carry;
+    f.h = ((a0 ^ a) & 16) !== 0;
+    setSzyxp(f, a);
+    return 4;
+  };
+  table[47] = (cpu) => {
+    const f = cpu.flags;
+    cpu.regs.a = ~cpu.regs.a & 255;
+    f.h = true;
+    f.n = true;
+    f.y = (cpu.regs.a & 32) !== 0;
+    f.x = (cpu.regs.a & 8) !== 0;
+    return 4;
+  };
+  table[55] = (cpu) => {
+    const f = cpu.flags;
+    f.c = true;
+    f.h = false;
+    f.n = false;
+    f.y = (cpu.regs.a & 32) !== 0;
+    f.x = (cpu.regs.a & 8) !== 0;
+    return 4;
+  };
+  table[63] = (cpu) => {
+    const f = cpu.flags;
+    f.h = f.c;
+    f.c = !f.c;
+    f.n = false;
+    f.y = (cpu.regs.a & 32) !== 0;
+    f.x = (cpu.regs.a & 8) !== 0;
+    return 4;
+  };
+}
+
+// src/cpu/z80/instructions/bits.ts
+function rotShift(f, kind, v) {
+  let c = 0;
+  let r = 0;
+  switch (kind) {
+    case 0:
+      c = v >> 7 & 1;
+      r = (v << 1 | c) & 255;
+      break;
+    // RLC
+    case 1:
+      c = v & 1;
+      r = (v >> 1 | c << 7) & 255;
+      break;
+    // RRC
+    case 2:
+      c = v >> 7 & 1;
+      r = (v << 1 | (f.c ? 1 : 0)) & 255;
+      break;
+    // RL
+    case 3:
+      c = v & 1;
+      r = (v >> 1 | (f.c ? 128 : 0)) & 255;
+      break;
+    // RR
+    case 4:
+      c = v >> 7 & 1;
+      r = v << 1 & 255;
+      break;
+    // SLA
+    case 5:
+      c = v & 1;
+      r = (v >> 1 | v & 128) & 255;
+      break;
+    // SRA
+    case 6:
+      c = v >> 7 & 1;
+      r = (v << 1 | 1) & 255;
+      break;
+    // SLL (undocumented)
+    case 7:
+      c = v & 1;
+      r = v >> 1 & 255;
+      break;
+  }
+  setSzyxp(f, r);
+  f.h = false;
+  f.n = false;
+  f.c = c === 1;
+  return r;
+}
+function bitTest(f, b, v, xySource) {
+  const bit = v & 1 << b;
+  f.z = bit === 0;
+  f.pv = f.z;
+  f.s = b === 7 && bit !== 0;
+  f.h = true;
+  f.n = false;
+  f.y = (xySource & 32) !== 0;
+  f.x = (xySource & 8) !== 0;
+}
+function registerBits(cb, idxCb) {
+  for (let op = 0; op < 64; op++) {
+    const kind = op >> 3 & 7;
+    const reg = op & 7;
+    if (reg === 6) {
+      cb[op] = (cpu) => {
+        const addr = cpu.regs.hl;
+        cpu.bus.write(addr, rotShift(cpu.flags, kind, cpu.bus.read(addr)));
+        return 15;
+      };
+    } else {
+      cb[op] = (cpu) => {
+        setRealR(cpu.regs, reg, rotShift(cpu.flags, kind, getRealR(cpu.regs, reg)));
+        return 8;
+      };
+    }
+  }
+  for (let op = 64; op <= 127; op++) {
+    const b = op >> 3 & 7;
+    const reg = op & 7;
+    if (reg === 6) {
+      cb[op] = (cpu) => {
+        bitTest(cpu.flags, b, cpu.bus.read(cpu.regs.hl), cpu.regs.wz >> 8);
+        return 12;
+      };
+    } else {
+      cb[op] = (cpu) => {
+        const v = getRealR(cpu.regs, reg);
+        bitTest(cpu.flags, b, v, v);
+        return 8;
+      };
+    }
+  }
+  for (let op = 128; op <= 255; op++) {
+    const b = op >> 3 & 7;
+    const reg = op & 7;
+    const set = op >= 192;
+    const mask = 1 << b;
+    if (reg === 6) {
+      cb[op] = (cpu) => {
+        const addr = cpu.regs.hl;
+        const v = cpu.bus.read(addr);
+        cpu.bus.write(addr, set ? v | mask : v & ~mask);
+        return 15;
+      };
+    } else {
+      cb[op] = (cpu) => {
+        const v = getRealR(cpu.regs, reg);
+        setRealR(cpu.regs, reg, set ? v | mask : v & ~mask);
+        return 8;
+      };
+    }
+  }
+  for (let op = 0; op < 64; op++) {
+    const kind = op >> 3 & 7;
+    const reg = op & 7;
+    idxCb[op] = (cpu, addr) => {
+      const r = rotShift(cpu.flags, kind, cpu.bus.read(addr));
+      cpu.bus.write(addr, r);
+      if (reg !== 6) setRealR(cpu.regs, reg, r);
+      return 19;
+    };
+  }
+  for (let op = 64; op <= 127; op++) {
+    const b = op >> 3 & 7;
+    idxCb[op] = (cpu, addr) => {
+      bitTest(cpu.flags, b, cpu.bus.read(addr), addr >> 8);
+      return 16;
+    };
+  }
+  for (let op = 128; op <= 255; op++) {
+    const b = op >> 3 & 7;
+    const reg = op & 7;
+    const set = op >= 192;
+    const mask = 1 << b;
+    idxCb[op] = (cpu, addr) => {
+      const v = cpu.bus.read(addr);
+      const r = set ? v | mask : v & ~mask;
+      cpu.bus.write(addr, r);
+      if (reg !== 6) setRealR(cpu.regs, reg, r);
+      return 19;
+    };
+  }
+}
+
+// src/cpu/z80/instructions/ed.ts
+function read162(cpu, addr) {
+  return cpu.bus.read(addr) | cpu.bus.read(u16(addr + 1)) << 8;
+}
+function write162(cpu, addr, v) {
+  cpu.bus.write(addr, v & 255);
+  cpu.bus.write(u16(addr + 1), v >> 8 & 255);
+}
+function ldAToIR(cpu, v) {
+  const f = cpu.flags;
+  cpu.regs.a = v & 255;
+  f.s = (v & 128) !== 0;
+  f.z = (v & 255) === 0;
+  f.y = (v & 32) !== 0;
+  f.x = (v & 8) !== 0;
+  f.h = false;
+  f.n = false;
+  f.pv = cpu.iff2;
+}
+function registerEd(ed) {
+  const pairGet = {
+    0: (cpu) => cpu.regs.bc,
+    1: (cpu) => cpu.regs.de,
+    2: (cpu) => cpu.regs.hl,
+    3: (cpu) => cpu.regs.sp
+  };
+  const pairSet = {
+    0: (cpu, v) => {
+      cpu.regs.bc = v;
+    },
+    1: (cpu, v) => {
+      cpu.regs.de = v;
+    },
+    2: (cpu, v) => {
+      cpu.regs.hl = v;
+    },
+    3: (cpu, v) => {
+      cpu.regs.sp = v;
+    }
+  };
+  for (let p = 0; p < 4; p++) {
+    ed[66 | p << 4] = (cpu) => {
+      const hl = cpu.regs.hl;
+      cpu.regs.wz = u16(hl + 1);
+      cpu.regs.hl = sbc16(cpu.flags, hl, pairGet[p](cpu), cpu.flags.c ? 1 : 0);
+      return 15;
+    };
+    ed[74 | p << 4] = (cpu) => {
+      const hl = cpu.regs.hl;
+      cpu.regs.wz = u16(hl + 1);
+      cpu.regs.hl = adc16(cpu.flags, hl, pairGet[p](cpu), cpu.flags.c ? 1 : 0);
+      return 15;
+    };
+    ed[67 | p << 4] = (cpu) => {
+      const nn = cpu.fetchWord();
+      write162(cpu, nn, pairGet[p](cpu));
+      cpu.regs.wz = u16(nn + 1);
+      return 20;
+    };
+    ed[75 | p << 4] = (cpu) => {
+      const nn = cpu.fetchWord();
+      pairSet[p](cpu, read162(cpu, nn));
+      cpu.regs.wz = u16(nn + 1);
+      return 20;
+    };
+  }
+  const neg = (cpu) => {
+    cpu.regs.a = sub8(cpu.flags, 0, cpu.regs.a, 0);
+    return 8;
+  };
+  for (const op of [68, 76, 84, 92, 100, 108, 116, 124]) ed[op] = neg;
+  const retn = (cpu) => {
+    cpu.iff1 = cpu.iff2;
+    const pc = cpu.pop16();
+    cpu.regs.pc = pc;
+    cpu.regs.wz = pc;
+    return 14;
+  };
+  for (const op of [69, 85, 93, 101, 109, 117, 125]) ed[op] = retn;
+  ed[77] = retn;
+  const setIm = (mode) => (cpu) => {
+    cpu.im = mode;
+    return 8;
+  };
+  ed[70] = setIm(0);
+  ed[78] = setIm(0);
+  ed[102] = setIm(0);
+  ed[110] = setIm(0);
+  ed[86] = setIm(1);
+  ed[118] = setIm(1);
+  ed[94] = setIm(2);
+  ed[126] = setIm(2);
+  ed[71] = (cpu) => {
+    cpu.regs.i = cpu.regs.a;
+    return 9;
+  };
+  ed[79] = (cpu) => {
+    cpu.regs.r = cpu.regs.a;
+    return 9;
+  };
+  ed[87] = (cpu) => {
+    ldAToIR(cpu, cpu.regs.i);
+    return 9;
+  };
+  ed[95] = (cpu) => {
+    ldAToIR(cpu, cpu.regs.r);
+    return 9;
+  };
+  ed[103] = (cpu) => {
+    const hl = cpu.regs.hl;
+    const m = cpu.bus.read(hl);
+    const a = cpu.regs.a;
+    cpu.bus.write(hl, (a << 4 | m >> 4) & 255);
+    cpu.regs.a = a & 240 | m & 15;
+    setSzyxp(cpu.flags, cpu.regs.a);
+    cpu.flags.h = false;
+    cpu.flags.n = false;
+    cpu.regs.wz = u16(hl + 1);
+    return 18;
+  };
+  ed[111] = (cpu) => {
+    const hl = cpu.regs.hl;
+    const m = cpu.bus.read(hl);
+    const a = cpu.regs.a;
+    cpu.bus.write(hl, (m << 4 | a & 15) & 255);
+    cpu.regs.a = a & 240 | m >> 4 & 15;
+    setSzyxp(cpu.flags, cpu.regs.a);
+    cpu.flags.h = false;
+    cpu.flags.n = false;
+    cpu.regs.wz = u16(hl + 1);
+    return 18;
+  };
+  for (let r = 0; r < 8; r++) {
+    ed[64 | r << 3] = (cpu) => {
+      const v = cpu.bus.ioRead(cpu.regs.c) & 255;
+      if (r !== 6) setRealR(cpu.regs, r, v);
+      setSzyxp(cpu.flags, v);
+      cpu.flags.h = false;
+      cpu.flags.n = false;
+      cpu.regs.wz = u16(cpu.regs.bc + 1);
+      return 12;
+    };
+  }
+  for (let r = 0; r < 8; r++) {
+    ed[65 | r << 3] = (cpu) => {
+      const v = r === 6 ? 0 : getRealR(cpu.regs, r);
+      cpu.bus.ioWrite(cpu.regs.c, v);
+      cpu.regs.wz = u16(cpu.regs.bc + 1);
+      return 12;
+    };
+  }
+}
+
+// src/cpu/z80/instructions/block.ts
+function registerBlock(ed) {
+  const ld = (dir) => {
+    const v = (cpu) => {
+      const byte = cpu.bus.read(cpu.regs.hl);
+      cpu.bus.write(cpu.regs.de, byte);
+      cpu.regs.hl = u16(cpu.regs.hl + dir);
+      cpu.regs.de = u16(cpu.regs.de + dir);
+      cpu.regs.bc = u16(cpu.regs.bc - 1);
+      const n = byte + cpu.regs.a & 255;
+      const f = cpu.flags;
+      f.h = false;
+      f.n = false;
+      f.pv = cpu.regs.bc !== 0;
+      f.y = (n & 2) !== 0;
+      f.x = (n & 8) !== 0;
+    };
+    ed[dir === 1 ? 160 : 168] = (cpu) => {
+      v(cpu);
+      return 16;
+    };
+    ed[dir === 1 ? 176 : 184] = (cpu) => {
+      v(cpu);
+      if (cpu.regs.bc !== 0) {
+        cpu.regs.pc = u16(cpu.regs.pc - 2);
+        cpu.regs.wz = u16(cpu.regs.pc + 1);
+        return 21;
+      }
+      return 16;
+    };
+  };
+  ld(1);
+  ld(-1);
+  const cp = (dir) => {
+    const one = (cpu) => {
+      const a = cpu.regs.a;
+      const val = cpu.bus.read(cpu.regs.hl);
+      const result = a - val & 255;
+      cpu.regs.hl = u16(cpu.regs.hl + dir);
+      cpu.regs.bc = u16(cpu.regs.bc - 1);
+      cpu.regs.wz = u16(cpu.regs.wz + dir);
+      const f = cpu.flags;
+      f.n = true;
+      f.h = (a & 15) - (val & 15) < 0;
+      const n = result - (f.h ? 1 : 0) & 255;
+      f.s = (result & 128) !== 0;
+      f.z = result === 0;
+      f.pv = cpu.regs.bc !== 0;
+      f.y = (n & 2) !== 0;
+      f.x = (n & 8) !== 0;
+    };
+    ed[dir === 1 ? 161 : 169] = (cpu) => {
+      one(cpu);
+      return 16;
+    };
+    ed[dir === 1 ? 177 : 185] = (cpu) => {
+      one(cpu);
+      if (cpu.regs.bc !== 0 && !cpu.flags.z) {
+        cpu.regs.pc = u16(cpu.regs.pc - 2);
+        cpu.regs.wz = u16(cpu.regs.pc + 1);
+        return 21;
+      }
+      return 16;
+    };
+  };
+  cp(1);
+  cp(-1);
+  const ini = (dir) => {
+    const one = (cpu) => {
+      const f = cpu.flags;
+      cpu.regs.wz = u16(cpu.regs.bc + dir);
+      const val = cpu.bus.ioRead(cpu.regs.c) & 255;
+      cpu.bus.write(cpu.regs.hl, val);
+      cpu.regs.hl = u16(cpu.regs.hl + dir);
+      cpu.regs.b = cpu.regs.b - 1 & 255;
+      const b = cpu.regs.b;
+      f.n = (val & 128) !== 0;
+      f.s = (b & 128) !== 0;
+      f.z = b === 0;
+      f.y = (b & 32) !== 0;
+      f.x = (b & 8) !== 0;
+      const k = val + (cpu.regs.c + dir & 255);
+      f.h = k > 255;
+      f.c = k > 255;
+      f.pv = parityEven(k & 7 ^ b);
+    };
+    ed[dir === 1 ? 162 : 170] = (cpu) => {
+      one(cpu);
+      return 16;
+    };
+    ed[dir === 1 ? 178 : 186] = (cpu) => {
+      one(cpu);
+      if (cpu.regs.b !== 0) {
+        cpu.regs.pc = u16(cpu.regs.pc - 2);
+        return 21;
+      }
+      return 16;
+    };
+  };
+  ini(1);
+  ini(-1);
+  const outi = (dir) => {
+    const one = (cpu) => {
+      const f = cpu.flags;
+      const val = cpu.bus.read(cpu.regs.hl);
+      cpu.regs.b = cpu.regs.b - 1 & 255;
+      const b = cpu.regs.b;
+      cpu.bus.ioWrite(cpu.regs.c, val);
+      cpu.regs.hl = u16(cpu.regs.hl + dir);
+      cpu.regs.wz = u16(cpu.regs.bc + dir);
+      f.n = (val & 128) !== 0;
+      f.s = (b & 128) !== 0;
+      f.z = b === 0;
+      f.y = (b & 32) !== 0;
+      f.x = (b & 8) !== 0;
+      const k = val + cpu.regs.l;
+      f.h = k > 255;
+      f.c = k > 255;
+      f.pv = parityEven(k & 7 ^ b);
+    };
+    ed[dir === 1 ? 163 : 171] = (cpu) => {
+      one(cpu);
+      return 16;
+    };
+    ed[dir === 1 ? 179 : 187] = (cpu) => {
+      one(cpu);
+      if (cpu.regs.b !== 0) {
+        cpu.regs.pc = u16(cpu.regs.pc - 2);
+        return 21;
+      }
+      return 16;
+    };
+  };
+  outi(1);
+  outi(-1);
+}
+
+// src/cpu/z80/DecoderZ80.ts
+function makeTable(name) {
+  return new Array(256).fill((_cpu) => 4).map((_, i) => {
+    return (_cpu) => {
+      console.warn(`[Z80] Unimplemented ${name} opcode: 0x${i.toString(16).padStart(2, "0")}`);
+      return 4;
+    };
+  });
+}
+function makeIdxCbTable() {
+  return new Array(256).fill((_c, _a) => 8).map((_, i) => {
+    return (_cpu, _addr) => {
+      console.warn(`[Z80] Unimplemented DDCB opcode: 0x${i.toString(16).padStart(2, "0")}`);
+      return 8;
+    };
+  });
+}
+var DecoderZ80 = class {
+  main = makeTable("main");
+  mainIX = makeTable("mainIX");
+  mainIY = makeTable("mainIY");
+  cb = makeTable("CB");
+  ed = makeTable("ED");
+  idxCb = makeIdxCbTable();
+  constructor() {
+    for (let i = 0; i < 256; i++) {
+      this.ed[i] = (_cpu) => 8;
+    }
+    this.buildMain(this.main, HL_VIEW);
+    this.buildMain(this.mainIX, IX_VIEW);
+    this.buildMain(this.mainIY, IY_VIEW);
+    registerBits(this.cb, this.idxCb);
+    registerEd(this.ed);
+    registerBlock(this.ed);
+    this.wireCbDispatch();
+    this.wireEdDispatch();
+  }
+  buildMain(table, view) {
+    registerLoad(table, view);
+    registerExchange(table, view);
+    registerAlu8(table, view);
+    registerAlu16(table, view);
+    registerRotate2(table, view);
+    registerJump(table, view);
+    registerStack2(table, view);
+    registerIO2(table, view);
+    registerControl2(table, view);
+  }
+  /**
+   * main[0xCB]: plain CB dispatch (fetch op, R++, run cb table).
+   * mainIX/IY[0xCB]: DDCB/FDCB dispatch — displacement fetched BEFORE the final
+   * opcode, and that final byte is NOT an M1 fetch (only DD and CB tick R).
+   */
+  wireCbDispatch() {
+    this.main[203] = (cpu) => {
+      const op = cpu.fetchByte();
+      cpu.regs.incR();
+      return this.cb[op](cpu);
+    };
+    const idxDispatch = (getPair) => (cpu) => {
+      const d = sext8(cpu.fetchByte());
+      cpu.regs.incR();
+      const addr = getPair(cpu) + d & 65535;
+      cpu.regs.wz = addr;
+      const op = cpu.fetchByte();
+      return this.idxCb[op](cpu, addr);
+    };
+    this.mainIX[203] = idxDispatch((cpu) => cpu.regs.ix);
+    this.mainIY[203] = idxDispatch((cpu) => cpu.regs.iy);
+  }
+  /** main/mainIX/mainIY[0xED]: identical ED dispatch (a DD/FD before ED is ignored). */
+  wireEdDispatch() {
+    const dispatch = (cpu) => {
+      const op = cpu.fetchByte();
+      cpu.regs.incR();
+      return this.ed[op](cpu);
+    };
+    this.main[237] = dispatch;
+    this.mainIX[237] = dispatch;
+    this.mainIY[237] = dispatch;
+  }
+};
+
+// src/cpu/z80/CpuZ80.ts
+var CpuZ80 = class {
+  regs = new RegistersZ80();
+  flags = new FlagsZ80();
+  bus;
+  pic;
+  dec;
+  iff1 = false;
+  iff2 = false;
+  im = 0;
+  pendingEI = false;
+  halted = false;
+  pendingNMI = false;
+  /** Front-panel status byte of the last instruction (8080-style approximation). */
+  lastStatus = FETCH_STATUS;
+  statusTable = buildStatusTable();
+  constructor(bus, pic) {
+    this.bus = bus;
+    this.pic = pic;
+    this.dec = new DecoderZ80();
+  }
+  /** Program counter accessor (ICpu). */
+  get pc() {
+    return this.regs.pc;
+  }
+  set pc(v) {
+    this.regs.pc = u16(v);
+  }
+  /** Uniform register/flags snapshot for introspection (ICpu). */
+  state() {
+    const r = this.regs;
+    return { pc: r.pc, sp: r.sp, a: r.a, f: this.flags.toByte(), b: r.b, c: r.c, d: r.d, e: r.e, h: r.h, l: r.l, halted: this.halted, inte: this.iff1, intPending: this.pic.hasPendingInterrupt(), status: this.lastStatus };
+  }
+  /** Assert a non-maskable interrupt (edge-triggered latch; serviced next step). */
+  triggerNMI() {
+    this.pendingNMI = true;
+  }
+  // --- Z80Core memory/stack helpers ---
+  fetchByte() {
+    const b = this.bus.read(this.regs.pc);
+    this.regs.pc = u16(this.regs.pc + 1);
+    return b;
+  }
+  fetchWord() {
+    const lo2 = this.fetchByte();
+    const hi2 = this.fetchByte();
+    return hi2 << 8 | lo2;
+  }
+  push16(v) {
+    this.regs.sp = u16(this.regs.sp - 1);
+    this.bus.write(this.regs.sp, v >> 8 & 255);
+    this.regs.sp = u16(this.regs.sp - 1);
+    this.bus.write(this.regs.sp, v & 255);
+  }
+  pop16() {
+    const lo2 = this.bus.read(this.regs.sp);
+    this.regs.sp = u16(this.regs.sp + 1);
+    const hi2 = this.bus.read(this.regs.sp);
+    this.regs.sp = u16(this.regs.sp + 1);
+    return hi2 << 8 | lo2;
+  }
+  reset() {
+    this.regs.reset();
+    this.flags.reset();
+    this.iff1 = false;
+    this.iff2 = false;
+    this.im = 0;
+    this.pendingEI = false;
+    this.halted = false;
+    this.pendingNMI = false;
+    this.lastStatus = FETCH_STATUS;
+  }
+  step() {
+    if (this.pendingNMI) return this.serviceNMI();
+    const eiJustCommitted = this.pendingEI;
+    if (this.pendingEI) {
+      this.iff1 = true;
+      this.iff2 = true;
+      this.pendingEI = false;
+    }
+    if (this.iff1 && !eiJustCommitted && this.pic.hasPendingInterrupt()) {
+      return this.serviceINT();
+    }
+    if (this.halted) {
+      this.regs.incR();
+      return 4;
+    }
+    let op = this.fetchByte();
+    this.regs.incR();
+    let table = this.dec.main;
+    let prefixT = 0;
+    while (op === 221 || op === 253) {
+      table = op === 221 ? this.dec.mainIX : this.dec.mainIY;
+      prefixT += 4;
+      op = this.fetchByte();
+      this.regs.incR();
+    }
+    this.lastStatus = this.statusTable[op];
+    return prefixT + table[op](this);
+  }
+  serviceINT() {
+    this.iff1 = false;
+    this.iff2 = false;
+    this.halted = false;
+    this.lastStatus = INTA_STATUS;
+    this.regs.incR();
+    const ackByte = this.bus.acknowledgeInterrupt();
+    switch (this.im) {
+      case 0: {
+        return 2 + this.dec.main[ackByte & 255](this);
+      }
+      case 1:
+        this.push16(this.regs.pc);
+        this.regs.pc = 56;
+        this.regs.wz = 56;
+        return 13;
+      case 2: {
+        const vector = (this.regs.i << 8 | ackByte & 255) & 65535;
+        this.push16(this.regs.pc);
+        const lo2 = this.bus.read(vector);
+        const hi2 = this.bus.read(u16(vector + 1));
+        this.regs.pc = hi2 << 8 | lo2;
+        this.regs.wz = this.regs.pc;
+        return 19;
+      }
+    }
+  }
+  serviceNMI() {
+    this.pendingNMI = false;
+    this.halted = false;
+    this.iff1 = false;
+    this.regs.incR();
+    this.push16(this.regs.pc);
+    this.regs.pc = 102;
+    this.regs.wz = 102;
+    return 11;
+  }
+  /** Run until halted or `maxCycles` T-states elapse; returns total T-states. */
+  run(maxCycles = Infinity) {
+    let total = 0n;
+    while (!this.halted && total < BigInt(maxCycles)) {
+      total += BigInt(this.step());
+    }
+    return total;
+  }
+};
+
+// src/bus/BusRegion.ts
+function createRegion(module) {
+  return {
+    start: module.baseAddress,
+    end: module.baseAddress + module.size - 1,
+    module
+  };
+}
+
+// src/io/IoSpace.ts
+var IoSpace = class {
+  devices = /* @__PURE__ */ new Map();
+  register(dev) {
+    for (const port of dev.basePorts) {
+      this.devices.set(port & 255, dev);
+    }
+  }
+  read(port) {
+    const dev = this.devices.get(port & 255);
+    if (dev === void 0) return 255;
+    return dev.ioRead(port & 255);
+  }
+  write(port, value) {
+    const dev = this.devices.get(port & 255);
+    if (dev === void 0) return;
+    dev.ioWrite(port & 255, value & 255);
+  }
+  reset() {
+    const seen = /* @__PURE__ */ new Set();
+    for (const dev of this.devices.values()) {
+      if (!seen.has(dev)) {
+        seen.add(dev);
+        dev.reset();
+      }
+    }
+  }
+};
+
+// src/bus/Bus.ts
+var Bus = class {
+  regions = [];
+  ioSpace;
+  pic;
+  constructor(pic) {
+    this.pic = pic;
+    this.ioSpace = new IoSpace();
+  }
+  attachMemory(mem) {
+    this.regions.push(createRegion(mem));
+    this.regions.sort((a, b) => a.start - b.start);
+  }
+  attachIODevice(dev) {
+    this.ioSpace.register(dev);
+  }
+  read(address) {
+    const addr = address & 65535;
+    const region = this.findRegion(addr);
+    if (region === void 0) return 255;
+    return region.module.read(addr - region.start);
+  }
+  write(address, value) {
+    const addr = address & 65535;
+    const region = this.findRegion(addr);
+    if (region === void 0) return;
+    if (region.module.readOnly) return;
+    region.module.write(addr - region.start, value);
+  }
+  ioRead(port) {
+    return this.ioSpace.read(port & 255);
+  }
+  ioWrite(port, value) {
+    this.ioSpace.write(port & 255, value & 255);
+  }
+  acknowledgeInterrupt() {
+    return this.pic.acknowledge();
+  }
+  getPic() {
+    return this.pic;
+  }
+  reset() {
+    for (const region of this.regions) {
+      region.module.reset();
+    }
+    this.ioSpace.reset();
+    this.pic.reset();
+  }
+  findRegion(addr) {
+    for (const region of this.regions) {
+      if (addr >= region.start && addr <= region.end) {
+        return region;
+      }
+    }
+    return void 0;
+  }
+};
+
+// src/bus/SnoopBus.ts
+var SnoopBus = class {
+  constructor(inner) {
+    this.inner = inner;
+  }
+  observers = [];
+  attach(observer) {
+    this.observers.push(observer);
+  }
+  detach(observer) {
+    const i = this.observers.indexOf(observer);
+    if (i !== -1) this.observers.splice(i, 1);
+  }
+  read(address) {
+    const value = this.inner.read(address);
+    for (const obs of this.observers) obs.onMemRead?.(address & 65535, value);
+    return value;
+  }
+  write(address, value) {
+    this.inner.write(address, value);
+    for (const obs of this.observers) obs.onMemWrite?.(address & 65535, value & 255);
+  }
+  ioRead(port) {
+    const value = this.inner.ioRead(port);
+    for (const obs of this.observers) obs.onIoRead?.(port & 255, value);
+    return value;
+  }
+  ioWrite(port, value) {
+    this.inner.ioWrite(port, value);
+    for (const obs of this.observers) obs.onIoWrite?.(port & 255, value & 255);
+  }
+  acknowledgeInterrupt() {
+    return this.inner.acknowledgeInterrupt();
+  }
+};
+
+// src/memory/Ram.ts
+var Ram = class {
+  id;
+  baseAddress;
+  size;
+  readOnly = false;
+  data;
+  constructor(id, baseAddress, size) {
+    this.id = id;
+    this.baseAddress = baseAddress & 65535;
+    this.size = size;
+    this.data = new Uint8Array(size);
+  }
+  read(offset) {
+    if (offset < 0 || offset >= this.size) return 255;
+    return this.data[offset] ?? 255;
+  }
+  write(offset, value) {
+    if (offset < 0 || offset >= this.size) return;
+    this.data[offset] = u8(value);
+  }
+  reset() {
+    this.data.fill(0);
+  }
+  /** Load bytes into RAM starting at offset */
+  load(data, offset = 0) {
+    this.data.set(data, offset);
+  }
+  /** Direct access for testing */
+  getBytes() {
+    return this.data;
+  }
+};
+
+// src/memory/Rom.ts
+var Rom = class {
+  id;
+  baseAddress;
+  size;
+  readOnly = true;
+  data;
+  constructor(id, baseAddress, data) {
+    this.id = id;
+    this.baseAddress = baseAddress & 65535;
+    this.size = data.length;
+    this.data = new Uint8Array(data);
+  }
+  read(offset) {
+    if (offset < 0 || offset >= this.size) return 255;
+    return this.data[offset] ?? 255;
+  }
+  write(_offset, _value) {
+  }
+  reset() {
+  }
+};
+
+// src/memory/MemoryMappedIOAdapter.ts
+var MemoryMappedIOAdapter = class {
+  id;
+  baseAddress;
+  size;
+  readOnly = false;
+  device;
+  constructor(baseAddress, size, device) {
+    this.id = `mmio:${device.id}`;
+    this.baseAddress = baseAddress & 65535;
+    this.size = size;
+    this.device = device;
+  }
+  read(offset) {
+    return this.device.ioRead(offset);
+  }
+  write(offset, value) {
+    this.device.ioWrite(offset, value);
+  }
+  reset() {
+    this.device.reset();
+  }
+};
+
+// src/interrupt/InterruptController.ts
+var InterruptController = class {
+  id = "pic";
+  pending = 0;
+  // bitmask of pending IRQ lines
+  lines;
+  constructor(lines = 8) {
+    this.lines = lines;
+  }
+  hasPendingInterrupt() {
+    return this.pending !== 0;
+  }
+  acknowledge() {
+    for (let i = 0; i < this.lines; i++) {
+      if ((this.pending & 1 << i) !== 0) {
+        this.pending &= ~(1 << i);
+        return 199 | i << 3;
+      }
+    }
+    return 255;
+  }
+  assertIRQ(line) {
+    if (line >= 0 && line < this.lines) {
+      this.pending |= 1 << line;
+    }
+  }
+  clearIRQ(line) {
+    if (line >= 0 && line < this.lines) {
+      this.pending &= ~(1 << line);
+    }
+  }
+  reset() {
+    this.pending = 0;
+  }
+};
+
+// src/clock/ImmediateClock.ts
+var ImmediateClock = class {
+  elapsed = 0n;
+  addCycles(cycles) {
+    this.elapsed += BigInt(cycles);
+  }
+  getElapsedCycles() {
+    return this.elapsed;
+  }
+  reset() {
+    this.elapsed = 0n;
+  }
+};
+
+// src/clock/SystemClock.ts
+var SystemClock = class {
+  elapsed = 0n;
+  hz;
+  startTime;
+  cyclesAtStart = 0n;
+  now;
+  constructor(hz = 2e6, now = () => performance.now()) {
+    this.hz = hz;
+    this.now = now;
+    this.startTime = now();
+  }
+  addCycles(cycles) {
+    this.elapsed += BigInt(cycles);
+  }
+  getElapsedCycles() {
+    return this.elapsed;
+  }
+  reset() {
+    this.elapsed = 0n;
+    this.rebaseline();
+  }
+  get targetHz() {
+    return this.hz;
+  }
+  /**
+   * Change the target frequency. Re-baselines so the new rate applies from
+   * this moment — cycles already executed are not retroactively repriced.
+   */
+  setHz(hz) {
+    this.rebaseline();
+    this.hz = hz;
+  }
+  /**
+   * Forfeit any accumulated drift and restart pacing from "now". Used after
+   * host stalls (GC pause, suspended tab) so the simulation doesn't sprint to
+   * catch up on lost wall time.
+   */
+  resync() {
+    this.rebaseline();
+  }
+  /**
+   * Returns a promise that resolves after yielding to the event loop.
+   * Callers should await this periodically to avoid blocking.
+   */
+  yield() {
+    return new Promise((resolve) => setTimeout(resolve, 0));
+  }
+  /**
+   * How far ahead (in ms) the simulation is relative to wall time.
+   * Positive = running too fast (should sleep); negative = behind.
+   */
+  getAheadMs() {
+    const wallMs = this.now() - this.startTime;
+    const simMs = Number(this.elapsed - this.cyclesAtStart) / this.hz * 1e3;
+    return simMs - wallMs;
+  }
+  rebaseline() {
+    this.cyclesAtStart = this.elapsed;
+    this.startTime = this.now();
+  }
+};
+
+// src/machine/MachineRunner.ts
+var MAX_SPEED_BATCH = 4e4;
+var MAX_SLICE_MS = 20;
+var RESYNC_BEHIND_MS = 250;
+var MachineRunner = class {
+  constructor(cpu, options = {}) {
+    this.cpu = cpu;
+    this.hz = options.hz ?? 2e6;
+    this.now = options.now ?? (() => performance.now());
+    this.clock = new SystemClock(typeof this.hz === "number" ? this.hz : 2e6, this.now);
+    this.schedule = options.schedule ?? ((fn, ms) => setTimeout(fn, ms));
+    this.onError = options.onError ?? ((err) => {
+      console.error("[MachineRunner]", err);
+    });
+  }
+  hz;
+  clock;
+  schedule;
+  onError;
+  now;
+  running = false;
+  startedAt = 0;
+  cyclesAtStart = 0n;
+  get targetHz() {
+    return this.hz;
+  }
+  /** Measured average speed in Hz since start() — for status displays. */
+  get effectiveHz() {
+    const wallSec = (this.now() - this.startedAt) / 1e3;
+    if (!this.running || wallSec <= 0) return 0;
+    return Number(this.clock.getElapsedCycles() - this.cyclesAtStart) / wallSec;
+  }
+  get isRunning() {
+    return this.running;
+  }
+  /** Total simulated T-states executed across the runner's lifetime. */
+  get elapsedCycles() {
+    return this.clock.getElapsedCycles();
+  }
+  start() {
+    if (this.running) return;
+    this.running = true;
+    this.startedAt = this.now();
+    this.cyclesAtStart = this.clock.getElapsedCycles();
+    this.clock.resync();
+    this.schedule(this.tick, 0);
+  }
+  stop() {
+    this.running = false;
+  }
+  /** Change speed while running; pacing restarts from this moment. */
+  setHz(hz) {
+    this.hz = hz;
+    this.clock.setHz(typeof hz === "number" ? hz : this.clock.targetHz);
+  }
+  tick = () => {
+    if (!this.running) return;
+    try {
+      if (this.hz === "max") {
+        for (let i = 0; i < MAX_SPEED_BATCH; i++) this.clock.addCycles(this.cpu.step());
+        this.schedule(this.tick, 0);
+        return;
+      }
+      if (this.clock.getAheadMs() < -RESYNC_BEHIND_MS) this.clock.resync();
+      const chunk = Math.max(1, Math.floor(this.hz / 1e3));
+      const sliceStart = this.now();
+      do {
+        let cycles = 0;
+        while (cycles < chunk) cycles += this.cpu.step();
+        this.clock.addCycles(cycles);
+      } while (this.clock.getAheadMs() < 0 && this.now() - sliceStart < MAX_SLICE_MS);
+      const aheadMs = this.clock.getAheadMs();
+      this.schedule(this.tick, aheadMs > 1 ? Math.floor(aheadMs) : 0);
+    } catch (err) {
+      this.running = false;
+      this.onError(err);
+    }
+  };
+};
+
+// src/machine/MachineSpec.ts
+var MachineSpecError = class extends Error {
+  constructor(message) {
+    super(message);
+    this.name = "MachineSpecError";
+  }
+};
+
+// src/machine/buildMachine.ts
+var inU16 = (n) => Number.isInteger(n) && n >= 0 && n <= 65535;
+var regionEnd = (r) => r.base + r.size - 1;
+function buildMachine(spec, opts = {}) {
+  validate(spec);
+  const pic = new InterruptController();
+  const bus = new Bus(pic);
+  for (const region of spec.memory) {
+    if (region.kind === "rom") {
+      bus.attachMemory(new Rom(region.id, region.base, region.image));
+    } else {
+      const ram = new Ram(region.id, region.base, region.size);
+      if (region.image) {
+        for (let i = 0; i < region.image.length; i++) ram.write(i, region.image[i]);
+      }
+      bus.attachMemory(ram);
+    }
+  }
+  const ctx = {
+    pic,
+    log: opts.log ?? (() => {
+    }),
+    services: opts.services ?? {}
+  };
+  const cards = [];
+  for (const card of spec.cards) {
+    const built = card.factory(card.id, card.config ?? {}, ctx);
+    built.attach(bus);
+    cards.push(built);
+  }
+  const cpu = spec.cpuKind === "z80" ? new CpuZ80(bus, pic) : new Cpu8080(bus, pic);
+  cpu.reset();
+  cpu.pc = spec.resetVector;
+  const runner = new MachineRunner(cpu, { hz: spec.clock === "max" ? "max" : spec.clock.hz });
+  return { cpu, bus, pic, cards, runner, spec };
+}
+function validate(spec) {
+  if (spec.cpuKind !== "i8080" && spec.cpuKind !== "z80") {
+    throw new MachineSpecError(`cpuKind must be "i8080" or "z80", got ${JSON.stringify(spec.cpuKind)}`);
+  }
+  if (spec.clock !== "max" && !(typeof spec.clock === "object" && spec.clock.hz > 0)) {
+    throw new MachineSpecError(`clock must be "max" or { hz: >0 }, got ${JSON.stringify(spec.clock)}`);
+  }
+  if (!inU16(spec.resetVector)) {
+    throw new MachineSpecError(`resetVector must be an integer in 0x0000..0xFFFF, got ${spec.resetVector}`);
+  }
+  for (const r of spec.memory) {
+    if (r.kind === "mmio") {
+      throw new MachineSpecError(
+        `memory region "${r.id}": kind "mmio" is not supported by buildMachine (memory-mapped I/O is provided by cards)`
+      );
+    }
+    if (!inU16(r.base) || !Number.isInteger(r.size) || r.size < 1 || r.base + r.size > 65536) {
+      throw new MachineSpecError(
+        `memory region "${r.id}": invalid base/size (base=${r.base}, size=${r.size}); must fit within 0x0000..0xFFFF`
+      );
+    }
+    if (r.kind === "rom" && (!r.image || r.image.length !== r.size)) {
+      throw new MachineSpecError(
+        `memory region "${r.id}": rom requires an image whose length (${r.image?.length ?? 0}) equals size (${r.size})`
+      );
+    }
+    if (r.kind === "ram" && r.image && r.image.length > r.size) {
+      throw new MachineSpecError(
+        `memory region "${r.id}": ram image length (${r.image.length}) exceeds size (${r.size})`
+      );
+    }
+  }
+  const sorted = [...spec.memory].sort((a, b) => a.base - b.base);
+  for (let i = 0; i + 1 < sorted.length; i++) {
+    const a = sorted[i];
+    const b = sorted[i + 1];
+    if (regionEnd(a) >= b.base) {
+      throw new MachineSpecError(
+        `memory regions overlap: "${a.id}" (0x${a.base.toString(16)}-0x${regionEnd(a).toString(16)}) and "${b.id}" (0x${b.base.toString(16)}-0x${regionEnd(b).toString(16)})`
+      );
+    }
+  }
+  const portOwner = /* @__PURE__ */ new Map();
+  for (const card of spec.cards) {
+    for (const port of card.claims?.ports ?? []) {
+      const prev = portOwner.get(port & 255);
+      if (prev !== void 0) {
+        throw new MachineSpecError(
+          `I/O port 0x${(port & 255).toString(16)} claimed by both "${prev}" and "${card.id}"`
+        );
+      }
+      portOwner.set(port & 255, card.id);
+    }
+  }
+  const irqOwner = /* @__PURE__ */ new Map();
+  for (const card of spec.cards) {
+    const irq = card.claims?.irq;
+    if (irq === void 0 || irq === null) continue;
+    const prev = irqOwner.get(irq);
+    if (prev !== void 0) {
+      throw new MachineSpecError(`IRQ line ${irq} claimed by both "${prev}" and "${card.id}"`);
+    }
+    irqOwner.set(irq, card.id);
+  }
+}
+
+// src/bundles/CardBundle.ts
+var CardConfigError = class extends Error {
+  constructor(message) {
+    super(message);
+    this.name = "CardConfigError";
+  }
+};
+function withDefaults(manifest, config = {}) {
+  const out = {};
+  for (const [key, spec] of Object.entries(manifest.configSchema)) {
+    const value = key in config ? config[key] : spec.default;
+    validateParam(manifest.name, key, spec, value);
+    out[key] = value;
+  }
+  return out;
+}
+function validateParam(card, key, spec, value) {
+  const where = `card "${card}" config "${key}"`;
+  if (spec.type === "enum") {
+    if (!spec.enum || !spec.enum.includes(value)) {
+      throw new CardConfigError(`${where}: ${JSON.stringify(value)} is not one of ${JSON.stringify(spec.enum ?? [])}`);
+    }
+    return;
+  }
+  const hi2 = spec.max ?? (spec.type === "u16" ? 65535 : 255);
+  const lo2 = spec.min ?? 0;
+  if (typeof value !== "number" || !Number.isInteger(value) || value < lo2 || value > hi2) {
+    throw new CardConfigError(`${where}: ${JSON.stringify(value)} must be an integer in ${lo2}..${hi2}`);
+  }
+}
+
+// src/cards/Usart8251.ts
+var Usart8251 = class {
+  constructor(id, dataPort, ctrlPort) {
+    this.dataPort = dataPort;
+    this.ctrlPort = ctrlPort;
+    this.id = id;
+    this.basePorts = [dataPort, ctrlPort];
+  }
+  id;
+  basePorts;
+  phase = "mode";
+  modeWord = 0;
+  txEnable = false;
+  rxEnable = false;
+  // 3-bit error field: bit0=PE, bit1=OE, bit2=FE — packed into status bits 3-5
+  errorFlags = 0;
+  rxQueue = [];
+  transmitCb;
+  ctsActive = true;
+  dsrActive = true;
+  ioWrite(port, value) {
+    if (port === this.ctrlPort) {
+      if (this.phase === "mode") {
+        this.modeWord = value;
+        this.phase = "command";
+        return;
+      }
+      if ((value & 64) !== 0) {
+        this.phase = "mode";
+        this.txEnable = false;
+        this.rxEnable = false;
+        this.errorFlags = 0;
+        this.rxQueue = [];
+        return;
+      }
+      this.txEnable = (value & 1) !== 0;
+      this.rxEnable = (value & 4) !== 0;
+      if ((value & 16) !== 0) {
+        this.errorFlags = 0;
+      }
+      return;
+    }
+    if (port === this.dataPort) {
+      if (this.txEnable && this.ctsActive) {
+        this.transmitCb?.(u8(value));
+      }
+    }
+  }
+  ioRead(port) {
+    if (port === this.ctrlPort) {
+      return this.buildStatus();
+    }
+    const byte = this.rxQueue.shift();
+    return byte !== void 0 ? byte : 255;
+  }
+  reset() {
+    this.phase = "mode";
+    this.modeWord = 0;
+    this.txEnable = false;
+    this.rxEnable = false;
+    this.errorFlags = 0;
+    this.rxQueue = [];
+  }
+  enqueueRx(byte) {
+    this.rxQueue.push(u8(byte));
+  }
+  onTransmit(cb) {
+    this.transmitCb = cb;
+  }
+  setCts(active) {
+    this.ctsActive = active;
+  }
+  setDsr(active) {
+    this.dsrActive = active;
+  }
+  buildStatus() {
+    const txRDY = this.txEnable && this.ctsActive ? 1 : 0;
+    const rxRDY = this.rxEnable && this.rxQueue.length > 0 ? 2 : 0;
+    const txEMPTY = 4;
+    const errors = (this.errorFlags & 7) << 3;
+    const dsr = this.dsrActive ? 128 : 0;
+    return txRDY | rxRDY | txEMPTY | errors | dsr;
+  }
+};
+
+// src/util/hostConsole.ts
+function writeHostStdout(text) {
+  globalThis.process?.stdout?.write(text);
+}
+
+// src/cards/ImsaiSioCard.ts
+var SioBoardCtrl = class {
+  constructor(id, port, a, b) {
+    this.a = a;
+    this.b = b;
+    this.id = id;
+    this.basePorts = [port];
+  }
+  id;
+  basePorts;
+  ioRead(_port) {
+    return 255;
+  }
+  ioWrite(_port, value) {
+    if ((value & 3) !== 0) this.a.reset();
+    if ((value & 12) !== 0) this.b.reset();
+  }
+  reset() {
+  }
+};
+var ImsaiSioCard = class {
+  id;
+  channelA;
+  channelB;
+  boardCtrl;
+  constructor(id = "sio2", options = {}) {
+    const portA = options.basePortA ?? 2;
+    const portB = options.basePortB ?? 4;
+    const ctrlPort = options.boardCtrlPort ?? 8;
+    this.id = id;
+    this.channelA = new Usart8251(`${id}:a`, portA, portA + 1);
+    this.channelB = new Usart8251(`${id}:b`, portB, portB + 1);
+    this.boardCtrl = new SioBoardCtrl(`${id}:ctrl`, ctrlPort, this.channelA, this.channelB);
+  }
+  attach(bus) {
+    bus.attachIODevice(this.channelA);
+    bus.attachIODevice(this.channelB);
+    bus.attachIODevice(this.boardCtrl);
+  }
+  wireToConsole() {
+    const write = (byte) => writeHostStdout(String.fromCharCode(byte));
+    this.channelA.onTransmit(write);
+    this.channelB.onTransmit(write);
+  }
+  reset() {
+    this.channelA.reset();
+    this.channelB.reset();
+  }
+};
+
+// src/cards/Mc6850Acia.ts
+var Mc6850Acia = class {
+  constructor(id, statusPort, dataPort) {
+    this.statusPort = statusPort;
+    this.dataPort = dataPort;
+    this.id = id;
+    this.basePorts = [statusPort, dataPort];
+  }
+  id;
+  basePorts;
+  controlReg = 0;
+  rxQueue = [];
+  // bit0=FE, bit1=OVRN, bit2=PE — positioned into status bits 4-6 when read.
+  errorFlags = 0;
+  rxIntEnable = false;
+  txIntEnable = false;
+  ctsClear = true;
+  // CTS input grounded → clear to send
+  carrierPresent = true;
+  // DCD input grounded → carrier present
+  transmitCb;
+  ioRead(port) {
+    if (port === this.statusPort) {
+      return this.buildStatus();
+    }
+    const byte = this.rxQueue.shift();
+    if (this.rxQueue.length === 0) {
+      this.errorFlags &= ~2;
+    }
+    return byte !== void 0 ? byte : 255;
+  }
+  ioWrite(port, value) {
+    if (port === this.statusPort) {
+      this.writeControl(u8(value));
+      return;
+    }
+    if (this.ctsClear) {
+      this.transmitCb?.(u8(value));
+    }
+  }
+  reset() {
+    this.masterReset();
+    this.controlReg = 0;
+  }
+  /**
+   * Feed a received byte to the ACIA. Sets RDRF; a byte arriving while the
+   * previous one has not been read flags an overrun (OVRN).
+   */
+  enqueueRx(byte) {
+    if (this.rxQueue.length > 0) {
+      this.errorFlags |= 2;
+    }
+    this.rxQueue.push(u8(byte));
+  }
+  onTransmit(cb) {
+    this.transmitCb = cb;
+  }
+  /** Drive the CTS input: true = clear to send (grounded), false = inhibited. */
+  setCts(clear) {
+    this.ctsClear = clear;
+  }
+  /** Drive the DCD input: true = carrier present (grounded), false = lost. */
+  setDcd(carrierPresent) {
+    this.carrierPresent = carrierPresent;
+  }
+  /** Inject receive error flags (framing / overrun / parity) for the next read. */
+  setErrors(fe, ovrn, pe) {
+    this.errorFlags = (fe ? 1 : 0) | (ovrn ? 2 : 0) | (pe ? 4 : 0);
+  }
+  /** Last value written to the control register. */
+  get control() {
+    return this.controlReg;
+  }
+  writeControl(value) {
+    this.controlReg = value;
+    if ((value & 3) === 3) {
+      this.masterReset();
+      return;
+    }
+    this.rxIntEnable = (value & 128) !== 0;
+    this.txIntEnable = (value & 96) === 32;
+  }
+  masterReset() {
+    this.rxQueue = [];
+    this.errorFlags = 0;
+    this.rxIntEnable = false;
+    this.txIntEnable = false;
+  }
+  buildStatus() {
+    const rdrf = this.rxQueue.length > 0 && this.carrierPresent ? 1 : 0;
+    const tdre = this.ctsClear ? 2 : 0;
+    const dcd = this.carrierPresent ? 0 : 4;
+    const cts = this.ctsClear ? 0 : 8;
+    const errs = (this.errorFlags & 7) << 4;
+    const irq = this.rxIntEnable && rdrf !== 0 || this.txIntEnable && tdre !== 0 ? 128 : 0;
+    return rdrf | tdre | dcd | cts | errs | irq;
+  }
+};
+
+// src/cards/Mits2SioCard.ts
+var Mits2SioCard = class {
+  id;
+  port0;
+  port1;
+  constructor(id = "2sio", options = {}) {
+    const base = options.basePort ?? 16;
+    this.id = id;
+    this.port0 = new Mc6850Acia(`${id}:port0`, base + 0, base + 1);
+    this.port1 = new Mc6850Acia(`${id}:port1`, base + 2, base + 3);
+  }
+  attach(bus) {
+    bus.attachIODevice(this.port0);
+    bus.attachIODevice(this.port1);
+  }
+  wireToConsole() {
+    this.port0.onTransmit((byte) => writeHostStdout(String.fromCharCode(byte & 127)));
+  }
+  reset() {
+    this.port0.reset();
+    this.port1.reset();
+  }
+};
+
+// src/cards/Tr1602Uart.ts
+var Tr1602Uart = class {
+  constructor(id, dataPort, statusPort) {
+    this.dataPort = dataPort;
+    this.statusPort = statusPort;
+    this.id = id;
+    this.basePorts = [dataPort, statusPort];
+  }
+  id;
+  basePorts;
+  // bit0=PE, bit1=OE, bit2=FE — positioned into status bits 3-5 when read.
+  errorFlags = 0;
+  rxQueue = [];
+  controlReg = 0;
+  transmitCb;
+  controlCb;
+  ioRead(port) {
+    if (port === this.statusPort) {
+      return this.buildStatus();
+    }
+    const byte = this.rxQueue.shift();
+    if (this.rxQueue.length === 0) {
+      this.errorFlags &= ~2;
+    }
+    return byte !== void 0 ? byte : 255;
+  }
+  ioWrite(port, value) {
+    if (port === this.statusPort) {
+      this.controlReg = u8(value);
+      this.controlCb?.(this.controlReg);
+      return;
+    }
+    this.transmitCb?.(u8(value));
+  }
+  reset() {
+    this.errorFlags = 0;
+    this.rxQueue = [];
+    this.controlReg = 0;
+  }
+  /**
+   * Feed a received byte to the UART. Sets Data-Received (RxRDY). A byte
+   * arriving while the single-byte buffer is still full flags an overrun (OE),
+   * mirroring the TR1602's lack of a receive FIFO.
+   */
+  enqueueRx(byte) {
+    if (this.rxQueue.length > 0) {
+      this.errorFlags |= 2;
+    }
+    this.rxQueue.push(u8(byte));
+  }
+  onTransmit(cb) {
+    this.transmitCb = cb;
+  }
+  /** Register a callback fired on writes to the board control register. */
+  onControl(cb) {
+    this.controlCb = cb;
+  }
+  /** Last value written to the board control register (statusPort write). */
+  get control() {
+    return this.controlReg;
+  }
+  /** Inject receive error flags (parity / overrun / framing) for the next read. */
+  setErrors(pe, oe, fe) {
+    this.errorFlags = (pe ? 1 : 0) | (oe ? 2 : 0) | (fe ? 4 : 0);
+  }
+  buildStatus() {
+    const txRDY = 1;
+    const rxRDY = this.rxQueue.length > 0 ? 2 : 0;
+    const txEMPTY = 4;
+    const errors = (this.errorFlags & 7) << 3;
+    return txRDY | rxRDY | txEMPTY | errors;
+  }
+};
+
+// src/cards/Port8212.ts
+var Port8212 = class {
+  id;
+  basePorts;
+  outputLatch = 0;
+  inputLatch = 255;
+  // unconnected TTL inputs float high
+  writeCb;
+  constructor(id, port) {
+    this.id = id;
+    this.basePorts = [port];
+  }
+  ioRead(_port) {
+    return this.inputLatch;
+  }
+  ioWrite(_port, value) {
+    this.outputLatch = u8(value);
+    this.writeCb?.(this.outputLatch);
+  }
+  reset() {
+    this.outputLatch = 0;
+    this.inputLatch = 255;
+  }
+  /** Drive the port's input pins — the value the CPU reads from this port. */
+  setInput(value) {
+    this.inputLatch = u8(value);
+  }
+  /** The byte currently latched on the output pins. */
+  get output() {
+    return this.outputLatch;
+  }
+  /** Register a callback fired whenever the CPU writes the output latch. */
+  onWrite(cb) {
+    this.writeCb = cb;
+  }
+};
+
+// src/cards/ImsaiMioCard.ts
+var ImsaiMioCard = class {
+  id;
+  portA;
+  portB;
+  uart;
+  constructor(id = "mio", options = {}) {
+    const base = options.basePort ?? 16;
+    this.id = id;
+    this.portA = new Port8212(`${id}:portA`, base + 0);
+    this.portB = new Port8212(`${id}:portB`, base + 1);
+    this.uart = new Tr1602Uart(`${id}:uart`, base + 2, base + 3);
+  }
+  attach(bus) {
+    bus.attachIODevice(this.portA);
+    bus.attachIODevice(this.portB);
+    bus.attachIODevice(this.uart);
+  }
+  wireToConsole() {
+    this.uart.onTransmit((byte) => writeHostStdout(String.fromCharCode(byte & 127)));
+  }
+  reset() {
+    this.portA.reset();
+    this.portB.reset();
+    this.uart.reset();
+  }
+};
+
+// src/cards/FdcPlusClient.ts
+var FdcPlusClient = class {
+  constructor(ws) {
+    this.ws = ws;
+    ws.onmessage = (ev) => {
+      const chunk = ev.data instanceof ArrayBuffer ? new Uint8Array(ev.data) : ev.data;
+      this.rxBuf.push(chunk);
+      this.rxTotal += chunk.length;
+      this.drain();
+    };
+    ws.onerror = () => this.rejectAll(new Error("WebSocket error"));
+    ws.onclose = () => this.rejectAll(new Error("WebSocket closed"));
+  }
+  rxBuf = [];
+  rxTotal = 0;
+  pending = [];
+  // Wire mutex. The protocol is strictly request/response, and WRIT is a
+  // multi-frame exchange (header → ack → raw data → status): any frame another
+  // op sends mid-exchange is consumed by the server as track data, and the
+  // tail of the real payload spills out as garbage commands, permanently
+  // desyncing the stream. Null when the wire is idle.
+  chainTail = null;
+  stat(drive, headLoad, track) {
+    return this.exchange(() => {
+      const p1 = (headLoad ? 1 : 0) << 8 | drive & 255;
+      this.ws.send(this.makeCmd("STAT", p1, track & 65535));
+      return this.enqueue(8).then((buf) => this.parseCmd(buf).p2);
+    });
+  }
+  readTrack(drive, track, length) {
+    return this.exchange(() => {
+      const p1 = (drive & 15) << 12 | track & 4095;
+      this.ws.send(this.makeCmd("READ", p1, length));
+      return this.enqueue(length);
+    });
+  }
+  writeTrack(drive, track, data) {
+    return this.exchange(() => {
+      const p1 = (drive & 15) << 12 | track & 4095;
+      this.ws.send(this.makeCmd("WRIT", p1, data.length));
+      return this.enqueue(8).then((ackBuf) => {
+        const ack = this.parseCmd(ackBuf);
+        if (ack.p1 !== 0) throw new Error(`WRIT rejected: status ${ack.p1}`);
+        this.ws.send(data);
+        return this.enqueue(8).then((wstaBuf) => {
+          const wsta = this.parseCmd(wstaBuf);
+          if (wsta.p1 !== 0) throw new Error(`WSTA error: status ${wsta.p1}`);
+        });
+      });
+    });
+  }
+  /**
+   * Run one full request/response exchange with exclusive use of the wire.
+   * Starts synchronously when the wire is idle (device registers depend on the
+   * command going out on the same tick); queues behind the in-flight exchange
+   * otherwise. A failed exchange never blocks the queue.
+   */
+  exchange(op) {
+    const run = this.chainTail ? this.chainTail.then(op, op) : op();
+    const tail = run.then(() => void 0, () => void 0);
+    this.chainTail = tail;
+    void tail.then(() => {
+      if (this.chainTail === tail) this.chainTail = null;
+    });
+    return run;
+  }
+  makeCmd(mnemonic, p1, p2) {
+    const buf = new Uint8Array(8);
+    for (let i = 0; i < 4; i++) buf[i] = mnemonic.charCodeAt(i) & 255;
+    buf[4] = p1 & 255;
+    buf[5] = p1 >> 8 & 255;
+    buf[6] = p2 & 255;
+    buf[7] = p2 >> 8 & 255;
+    return buf;
+  }
+  parseCmd(buf) {
+    const cmd = String.fromCharCode(
+      buf[0] ?? 0,
+      buf[1] ?? 0,
+      buf[2] ?? 0,
+      buf[3] ?? 0
+    );
+    const p1 = (buf[4] ?? 0) | (buf[5] ?? 0) << 8;
+    const p2 = (buf[6] ?? 0) | (buf[7] ?? 0) << 8;
+    return { cmd, p1, p2 };
+  }
+  enqueue(bytesExpected) {
+    return new Promise((resolve, reject) => {
+      this.pending.push({ resolve, reject, bytesExpected });
+      this.drain();
+    });
+  }
+  drain() {
+    while (this.pending.length > 0) {
+      const head = this.pending[0];
+      if (!head || this.rxTotal < head.bytesExpected) break;
+      this.pending.shift();
+      head.resolve(this.collect(head.bytesExpected));
+    }
+  }
+  collect(n) {
+    const out = new Uint8Array(n);
+    let written = 0;
+    while (written < n) {
+      const chunk = this.rxBuf[0];
+      if (!chunk) break;
+      const needed = n - written;
+      if (chunk.length <= needed) {
+        out.set(chunk, written);
+        written += chunk.length;
+        this.rxBuf.shift();
+        this.rxTotal -= chunk.length;
+      } else {
+        out.set(chunk.subarray(0, needed), written);
+        this.rxBuf[0] = chunk.subarray(needed);
+        this.rxTotal -= needed;
+        written = n;
+      }
+    }
+    return out;
+  }
+  rejectAll(err) {
+    const entries = this.pending.splice(0);
+    for (const e of entries) e.reject(err);
+  }
+};
+
+// src/cards/MitsDcddCard.ts
+var TRACK_LEN = 137 * 32;
+var BYTES_PER_SECTOR = 137;
+var MAX_TRACK = 76;
+var MitsDcddCard = class {
+  id;
+  basePorts;
+  fdcClient;
+  p1;
+  p2;
+  p3;
+  selectedDrive = 255;
+  // Head position is PER-DRIVE state: each drive's arm stays where it was
+  // left. The BIOS seeks relatively from a per-drive track table in RAM, so a
+  // single shared counter desyncs the moment two drives interleave seeks
+  // (e.g. PIP copying between disks) and lands reads/writes on wrong tracks.
+  driveTrack = new Array(16).fill(0);
+  headLoaded = false;
+  writeEnabled = false;
+  fetchPending = false;
+  trackData = null;
+  writeBuffer = null;
+  writtenSectors = /* @__PURE__ */ new Set();
+  // sectors touched since Write Enable
+  writeDirty = false;
+  lastSector = -1;
+  byteInSector = 0;
+  cacheDrive = 255;
+  // which drive the cached trackData belongs to
+  /** Head position of the currently selected drive (0 when none selected). */
+  get currentTrack() {
+    return this.selectedDrive === 255 ? 0 : this.driveTrack[this.selectedDrive] ?? 0;
+  }
+  set currentTrack(track) {
+    if (this.selectedDrive !== 255) this.driveTrack[this.selectedDrive] = track;
+  }
+  constructor(id, ws, options = {}) {
+    this.id = id;
+    const base = options.basePort ?? 8;
+    this.p1 = base;
+    this.p2 = base + 1;
+    this.p3 = base + 2;
+    this.basePorts = [this.p1, this.p2, this.p3];
+    this.fdcClient = new FdcPlusClient(ws);
+  }
+  attach(bus) {
+    bus.attachIODevice(this);
+  }
+  ioRead(port) {
+    if (port === this.p1) return this.readStatus();
+    if (port === this.p2) return this.readSector();
+    if (port === this.p3) return this.readData();
+    return 255;
+  }
+  ioWrite(port, value) {
+    if (port === this.p1) {
+      this.writeDriveSelect(value);
+      return;
+    }
+    if (port === this.p2) {
+      this.writeCommand(value);
+      return;
+    }
+    if (port === this.p3) {
+      this.writeData(value);
+      return;
+    }
+  }
+  reset() {
+    this.flushWrite();
+    this.selectedDrive = 255;
+    this.driveTrack.fill(0);
+    this.headLoaded = false;
+    this.writeEnabled = false;
+    this.fetchPending = false;
+    this.trackData = null;
+    this.writeBuffer = null;
+    this.writtenSectors.clear();
+    this.writeDirty = false;
+    this.lastSector = -1;
+    this.byteInSector = 0;
+    this.cacheDrive = 255;
+  }
+  // --- Port 1: status (READ) / drive select (WRITE) ---
+  readStatus() {
+    this.ensureTrack();
+    const nrda = !this.headLoaded || !this.trackData || this.fetchPending ? 128 : 0;
+    const trk0 = this.currentTrack === 0 ? 0 : 64;
+    const drvrdy = this.selectedDrive !== 255 ? 0 : 8;
+    const hdstat = this.headLoaded ? 0 : 4;
+    const mvhd = 0;
+    const enwd = this.writeEnabled ? 0 : 1;
+    return nrda | trk0 | drvrdy | hdstat | mvhd | enwd;
+  }
+  writeDriveSelect(value) {
+    if ((value & 128) !== 0) {
+      this.flushWrite();
+      this.selectedDrive = 255;
+      this.writeEnabled = false;
+      return;
+    }
+    const drive = value & 15;
+    if (drive !== this.selectedDrive) this.flushWrite();
+    this.selectedDrive = drive;
+    if (drive !== this.cacheDrive) {
+      this.trackData = null;
+    }
+    this.ensureTrack();
+    this.fdcClient.stat(this.selectedDrive, this.headLoaded, this.currentTrack).catch(() => {
+    });
+  }
+  // --- Port 2: sector position (READ) / command (WRITE) ---
+  readSector() {
+    const revMs = 166.667;
+    const secMs = revMs / 32;
+    const pos = performance.now() % revMs;
+    const sector = Math.floor(pos / secMs) & 31;
+    const offset = pos % secMs;
+    const sectorTrue = offset < 1 ? 0 : 1;
+    if (sector !== this.lastSector || sectorTrue === 0) {
+      this.lastSector = sector;
+      this.byteInSector = 0;
+    }
+    return 192 | (sector & 31) << 1 | sectorTrue;
+  }
+  writeCommand(value) {
+    if ((value & 128) !== 0) {
+      this.writeEnabled = true;
+      if (!this.writeBuffer) this.writeBuffer = new Uint8Array(TRACK_LEN);
+    }
+    if ((value & 8) !== 0) {
+      this.flushWrite();
+      this.headLoaded = false;
+      this.trackData = null;
+    }
+    if ((value & 4) !== 0) {
+      this.headLoaded = true;
+      this.ensureTrack();
+    }
+    if ((value & 2) !== 0) this.issueStep("out");
+    if ((value & 1) !== 0) this.issueStep("in");
+  }
+  // --- Port 3: data (READ/WRITE) ---
+  readData() {
+    if (!this.headLoaded || !this.trackData || this.fetchPending) return 255;
+    if (this.byteInSector >= BYTES_PER_SECTOR) return 255;
+    const sector = this.lastSector < 0 ? 0 : this.lastSector;
+    const offset = sector * BYTES_PER_SECTOR + this.byteInSector;
+    const source = this.writeBuffer && this.writtenSectors.has(sector) ? this.writeBuffer : this.trackData;
+    if (offset >= source.length) return 255;
+    const byte = source[offset] ?? 255;
+    this.byteInSector++;
+    return byte;
+  }
+  writeData(value) {
+    if (!this.writeEnabled || !this.writeBuffer) return;
+    if (this.byteInSector >= BYTES_PER_SECTOR) return;
+    const sector = this.lastSector < 0 ? 0 : this.lastSector;
+    const offset = sector * BYTES_PER_SECTOR + this.byteInSector;
+    if (offset < this.writeBuffer.length) {
+      this.writeBuffer[offset] = value & 255;
+      this.writtenSectors.add(sector);
+      this.writeDirty = true;
+    }
+    this.byteInSector++;
+  }
+  // --- Private helpers ---
+  /**
+   * Start fetching the current track if the head is loaded, a drive is
+   * selected, we don't already have the data, and no fetch is in flight. Safe
+   * to call from any read/command path — it converges on caching the track the
+   * head is currently over.
+   */
+  ensureTrack() {
+    if (!this.headLoaded || this.selectedDrive === 255) return;
+    if (this.trackData || this.fetchPending) return;
+    this.fetchTrack();
+  }
+  fetchTrack() {
+    if (this.selectedDrive === 255 || !this.headLoaded || this.fetchPending) return;
+    this.fetchPending = true;
+    const drive = this.selectedDrive;
+    const track = this.currentTrack;
+    this.fdcClient.readTrack(drive, track, TRACK_LEN).then((data) => {
+      if (track === this.currentTrack && drive === this.selectedDrive && !this.trackData) {
+        this.trackData = data;
+        this.cacheDrive = drive;
+      }
+    }).catch(() => {
+    }).finally(() => {
+      this.fetchPending = false;
+      this.ensureTrack();
+    });
+  }
+  flushWrite() {
+    if (!this.writeDirty || !this.writeBuffer || this.selectedDrive === 255) return;
+    const image = this.trackData ? new Uint8Array(this.trackData) : new Uint8Array(TRACK_LEN);
+    for (const sector of this.writtenSectors) {
+      const off = sector * BYTES_PER_SECTOR;
+      image.set(this.writeBuffer.subarray(off, off + BYTES_PER_SECTOR), off);
+    }
+    const drive = this.selectedDrive;
+    const track = this.currentTrack;
+    this.writeBuffer = null;
+    this.writtenSectors.clear();
+    this.writeDirty = false;
+    this.writeEnabled = false;
+    this.trackData = image;
+    this.cacheDrive = drive;
+    this.fdcClient.writeTrack(drive, track, image).catch((e) => {
+      console.error(`[${this.id}] track write failed (drive ${drive}, track ${track}): ${String(e)}`);
+    });
+  }
+  issueStep(dir) {
+    this.flushWrite();
+    if (dir === "in") this.currentTrack = Math.min(MAX_TRACK, this.currentTrack + 1);
+    else this.currentTrack = Math.max(0, this.currentTrack - 1);
+    this.trackData = null;
+    this.writeEnabled = false;
+    this.ensureTrack();
+  }
+};
+
+// src/bundles/seed/index.ts
+var u82 = (v, fallback) => typeof v === "number" ? v & 255 : fallback;
+var u162 = (v, fallback) => typeof v === "number" ? v & 65535 : fallback;
+var deviceCard = (id, dev) => ({
+  id,
+  reset: () => dev.reset(),
+  attach: (bus) => bus.attachIODevice(dev)
+});
+var memoryCard = (id) => ({
+  id,
+  reset: () => {
+  },
+  attach: () => {
+  }
+});
+var cpuCard = (id) => ({
+  id,
+  reset: () => {
+  },
+  attach: () => {
+  }
+});
+var mits2SioBundle = {
+  manifest: {
+    name: "mits-88-2sio",
+    version: "1.0.0",
+    type: "serial",
+    kind: "card",
+    maker: "MITS",
+    summary: "MITS 88-2SIO dual serial interface (2\xD7 6850 ACIA).",
+    configSchema: { basePort: { type: "u8", default: 16, min: 0, max: 252, description: "Base I/O port (claims base..base+3)" } }
+  },
+  cardFactory: (id, cfg) => new Mits2SioCard(id, { basePort: u82(cfg.basePort, 16) }),
+  claims: (cfg) => {
+    const b = u82(cfg.basePort, 16);
+    return { ports: [b, b + 1, b + 2, b + 3] };
+  }
+};
+var imsaiSioBundle = {
+  manifest: {
+    name: "imsai-sio2",
+    version: "1.0.0",
+    type: "serial",
+    kind: "card",
+    maker: "IMSAI",
+    summary: "IMSAI SIO-2 dual 8251 serial card with a board-control port.",
+    configSchema: {
+      basePortA: { type: "u8", default: 2, min: 0, max: 254 },
+      basePortB: { type: "u8", default: 4, min: 0, max: 254 },
+      boardCtrlPort: { type: "u8", default: 8, min: 0, max: 255 }
+    }
+  },
+  cardFactory: (id, cfg) => new ImsaiSioCard(id, {
+    basePortA: u82(cfg.basePortA, 2),
+    basePortB: u82(cfg.basePortB, 4),
+    boardCtrlPort: u82(cfg.boardCtrlPort, 8)
+  }),
+  claims: (cfg) => {
+    const a = u82(cfg.basePortA, 2);
+    const b = u82(cfg.basePortB, 4);
+    const c = u82(cfg.boardCtrlPort, 8);
+    return { ports: [a, a + 1, b, b + 1, c] };
+  }
+};
+var imsaiMioBundle = {
+  manifest: {
+    name: "imsai-mio",
+    version: "1.0.0",
+    type: "serial",
+    kind: "card",
+    maker: "IMSAI",
+    summary: "IMSAI MIO multi-I/O card: two 8212 parallel ports (base+0/+1) and a TR1602 UART (base+2/+3).",
+    configSchema: { basePort: { type: "u8", default: 16, min: 0, max: 252 } }
+  },
+  cardFactory: (id, cfg) => new ImsaiMioCard(id, { basePort: u82(cfg.basePort, 16) }),
+  // Registers 4 consecutive ports: portA(base), portB(base+1), UART(base+2/+3).
+  claims: (cfg) => {
+    const b = u82(cfg.basePort, 16);
+    return { ports: [b, b + 1, b + 2, b + 3] };
+  }
+};
+var mitsDcddBundle = {
+  manifest: {
+    name: "mits-88-dcdd",
+    version: "1.0.0",
+    type: "floppy",
+    kind: "card",
+    maker: "MITS",
+    summary: "MITS 88-DCDD 8-inch floppy controller; disk I/O over the FDC channel.",
+    configSchema: { basePort: { type: "u8", default: 8, min: 0, max: 253 } }
+  },
+  cardFactory: (id, cfg, ctx) => {
+    const ws = ctx.services.fdc;
+    if (!ws) {
+      throw new MachineSpecError(
+        `card "${id}" (mits-88-dcdd) requires an FDC channel in ctx.services.fdc`
+      );
+    }
+    return new MitsDcddCard(id, ws, { basePort: u82(cfg.basePort, 8) });
+  },
+  claims: (cfg) => {
+    const b = u82(cfg.basePort, 8);
+    return { ports: [b, b + 1, b + 2] };
+  }
+};
+var usart8251Bundle = {
+  manifest: {
+    name: "intel-8251",
+    version: "1.0.0",
+    type: "serial",
+    kind: "chip",
+    maker: "Intel",
+    summary: "Intel 8251 USART (data + control port).",
+    configSchema: {
+      dataPort: { type: "u8", default: 16, min: 0, max: 255 },
+      ctrlPort: { type: "u8", default: 17, min: 0, max: 255 }
+    }
+  },
+  cardFactory: (id, cfg) => deviceCard(id, new Usart8251(id, u82(cfg.dataPort, 16), u82(cfg.ctrlPort, 17))),
+  claims: (cfg) => ({ ports: [u82(cfg.dataPort, 16), u82(cfg.ctrlPort, 17)] })
+};
+var mc6850Bundle = {
+  manifest: {
+    name: "motorola-6850",
+    version: "1.0.0",
+    type: "serial",
+    kind: "chip",
+    maker: "Motorola",
+    summary: "Motorola 6850 ACIA (status + data port).",
+    configSchema: {
+      statusPort: { type: "u8", default: 16, min: 0, max: 255 },
+      dataPort: { type: "u8", default: 17, min: 0, max: 255 }
+    }
+  },
+  cardFactory: (id, cfg) => deviceCard(id, new Mc6850Acia(id, u82(cfg.statusPort, 16), u82(cfg.dataPort, 17))),
+  claims: (cfg) => ({ ports: [u82(cfg.statusPort, 16), u82(cfg.dataPort, 17)] })
+};
+var port8212Bundle = {
+  manifest: {
+    name: "intel-8212",
+    version: "1.0.0",
+    type: "other",
+    kind: "chip",
+    maker: "Intel",
+    summary: "Intel 8212 8-bit I/O port.",
+    configSchema: { port: { type: "u8", default: 255, min: 0, max: 255 } }
+  },
+  cardFactory: (id, cfg) => deviceCard(id, new Port8212(id, u82(cfg.port, 255))),
+  claims: (cfg) => ({ ports: [u82(cfg.port, 255)] })
+};
+var tr1602Bundle = {
+  manifest: {
+    name: "tr1602-uart",
+    version: "1.0.0",
+    type: "serial",
+    kind: "chip",
+    maker: "Western Digital",
+    summary: "TR1602 UART (data + status port).",
+    configSchema: {
+      dataPort: { type: "u8", default: 0, min: 0, max: 255 },
+      statusPort: { type: "u8", default: 1, min: 0, max: 255 }
+    }
+  },
+  cardFactory: (id, cfg) => deviceCard(id, new Tr1602Uart(id, u82(cfg.dataPort, 0), u82(cfg.statusPort, 1))),
+  claims: (cfg) => ({ ports: [u82(cfg.dataPort, 0), u82(cfg.statusPort, 1)] })
+};
+var ramCardBundle = {
+  manifest: {
+    name: "ram-card",
+    version: "1.0.0",
+    type: "memory",
+    kind: "card",
+    maker: "generic",
+    summary: "Static RAM board \u2014 maps read/write RAM at a configurable base address.",
+    configSchema: {
+      base: { type: "u16", default: 0, min: 0, max: 65535, description: "Start address" },
+      size: { type: "u16", default: 16384, min: 1, max: 65535, description: "Bytes of RAM" }
+    }
+  },
+  cardFactory: (id) => memoryCard(id),
+  claims: () => ({ ports: [] }),
+  memory: (cfg) => [{ id: "ram", base: u162(cfg.base, 0), size: u162(cfg.size, 16384), kind: "ram" }]
+};
+var epromCardBundle = {
+  manifest: {
+    name: "eprom-card",
+    version: "1.0.0",
+    type: "memory",
+    kind: "card",
+    maker: "generic",
+    summary: "EPROM board \u2014 maps a read-only region at a base address; burn a .bin/Intel-HEX image into it.",
+    configSchema: {
+      base: { type: "u16", default: 61440, min: 0, max: 65535, description: "Start address" },
+      size: { type: "u16", default: 2048, min: 1, max: 65535, description: "EPROM size in bytes" }
+    }
+  },
+  cardFactory: (id) => memoryCard(id),
+  claims: () => ({ ports: [] }),
+  memory: (cfg) => {
+    const base = u162(cfg.base, 61440);
+    const size = u162(cfg.size, 2048);
+    return [{ id: "rom", base, size, kind: "rom", image: new Uint8Array(size) }];
+  }
+};
+var i8080CpuBundle = {
+  manifest: {
+    name: "i8080-cpu",
+    version: "1.0.0",
+    type: "cpu",
+    kind: "card",
+    maker: "Intel",
+    summary: "Intel 8080 CPU board \u2014 the bus master; sets the power-on jump address.",
+    configSchema: {
+      resetVector: { type: "u16", default: 0, min: 0, max: 65535, description: "Power-on jump (program counter at reset)" }
+    }
+  },
+  cardFactory: (id) => cpuCard(id),
+  claims: () => ({ ports: [] }),
+  cpu: (cfg) => ({ kind: "i8080", resetVector: u162(cfg.resetVector, 0) })
+};
+var z80CpuBundle = {
+  manifest: {
+    name: "z80-cpu",
+    version: "1.0.0",
+    type: "cpu",
+    kind: "card",
+    maker: "Zilog",
+    summary: "Zilog Z80 CPU board \u2014 the bus master; sets the power-on jump address.",
+    configSchema: {
+      resetVector: { type: "u16", default: 0, min: 0, max: 65535, description: "Power-on jump (program counter at reset)" }
+    }
+  },
+  cardFactory: (id) => cpuCard(id),
+  claims: () => ({ ports: [] }),
+  cpu: (cfg) => ({ kind: "z80", resetVector: u162(cfg.resetVector, 0) })
+};
+var seedBundles = [
+  i8080CpuBundle,
+  z80CpuBundle,
+  mits2SioBundle,
+  imsaiSioBundle,
+  imsaiMioBundle,
+  mitsDcddBundle,
+  usart8251Bundle,
+  mc6850Bundle,
+  port8212Bundle,
+  tr1602Bundle,
+  ramCardBundle,
+  epromCardBundle
+];
+var seedBundleByName = (name) => seedBundles.find((b) => b.manifest.name === name);
+
+// src/cards/SerialCard.ts
+var SerialCard = class {
+  id;
+  channel;
+  constructor(id = "serial", opts = {}) {
+    const dataPort = opts.dataPort ?? 16;
+    const ctrlPort = opts.ctrlPort ?? 17;
+    this.id = id;
+    this.channel = opts.chip === "m6850" ? new Mc6850Acia(`${id}:ch`, ctrlPort, dataPort) : new Usart8251(`${id}:ch`, dataPort, ctrlPort);
+  }
+  attach(bus) {
+    bus.attachIODevice(this.channel);
+  }
+  reset() {
+    this.channel.reset();
+  }
+};
+
+// src/cards/ParallelCard.ts
+var ParallelCard = class {
+  id;
+  direction;
+  gpio;
+  dev;
+  constructor(id = "parallel", opts = {}) {
+    this.id = id;
+    this.direction = opts.direction ?? "out";
+    this.dev = new Port8212(`${id}:port`, opts.port ?? 0);
+    this.gpio = {
+      direction: this.direction,
+      read: () => this.dev.output,
+      setInput: (byte) => this.dev.setInput(byte),
+      onOutput: (cb) => this.dev.onWrite(cb)
+    };
+  }
+  attach(bus) {
+    bus.attachIODevice(this.dev);
+  }
+  reset() {
+    this.dev.reset();
+  }
+};
+
+// src/cards/KeyboardCard.ts
+var KeyboardDevice = class {
+  id;
+  basePorts;
+  dataPort;
+  statusPort;
+  readyMask;
+  queue = [];
+  constructor(id, dataPort, statusPort, readyMask) {
+    this.id = id;
+    this.dataPort = u8(dataPort);
+    this.statusPort = u8(statusPort);
+    this.readyMask = u8(readyMask);
+    this.basePorts = this.dataPort === this.statusPort ? [this.dataPort] : [this.dataPort, this.statusPort];
+  }
+  ioRead(port) {
+    const p = u8(port);
+    if (p === this.dataPort) return this.queue.shift() ?? 0;
+    if (p === this.statusPort) return this.queue.length > 0 ? this.readyMask : 0;
+    return 0;
+  }
+  ioWrite() {
+  }
+  reset() {
+    this.queue.length = 0;
+  }
+  press(byte) {
+    this.queue.push(u8(byte));
+  }
+  get pending() {
+    return this.queue.length;
+  }
+};
+var KeyboardCard = class {
+  id;
+  keyboard;
+  dev;
+  constructor(id = "keyboard", opts = {}) {
+    this.id = id;
+    this.dev = new KeyboardDevice(
+      `${id}:kbd`,
+      opts.dataPort ?? 1,
+      opts.statusPort ?? 0,
+      opts.readyMask ?? 1
+    );
+    const dev = this.dev;
+    this.keyboard = {
+      press: (byte) => dev.press(byte),
+      type: (text) => {
+        for (let i = 0; i < text.length; i++) dev.press(text.charCodeAt(i));
+      },
+      get pending() {
+        return dev.pending;
+      }
+    };
+  }
+  attach(bus) {
+    bus.attachIODevice(this.dev);
+  }
+  reset() {
+    this.dev.reset();
+  }
+};
+
+// src/cards/VdmCard.ts
+var COLS = 64;
+var ROWS = 16;
+var SIZE = COLS * ROWS;
+var VdmCard = class {
+  id;
+  display;
+  base;
+  bus;
+  constructor(id = "vdm", opts = {}) {
+    this.id = id;
+    this.base = (opts.base ?? 52224) & 65535;
+    this.display = {
+      descriptor: { mode: "charGrid", cols: COLS, rows: ROWS, font: "vdm", attrBit: 7 },
+      frame: () => ({ bytes: this.readVram(), state: {} })
+    };
+  }
+  attach(bus) {
+    this.bus = bus;
+  }
+  reset() {
+  }
+  readVram() {
+    const out = new Uint8Array(SIZE);
+    const bus = this.bus;
+    if (bus) for (let i = 0; i < SIZE; i++) out[i] = bus.read(this.base + i & 65535) & 255;
+    return out;
+  }
+};
+
+// src/cards/DazzlerCard.ts
+var MAX_BUFFER = 2048;
+var DazzlerCard = class {
+  id;
+  display;
+  controlPort;
+  formatPort;
+  control = 0;
+  // D7 = on, D0–D6 = page
+  format = 0;
+  // resolution / colour / size
+  frameFlip = 0;
+  // toggling sync bit for control-port reads
+  bus;
+  dev;
+  constructor(id = "dazzler", opts = {}) {
+    this.id = id;
+    this.controlPort = (opts.controlPort ?? 14) & 255;
+    this.formatPort = (opts.formatPort ?? 15) & 255;
+    const self = this;
+    this.dev = {
+      id: `${id}:io`,
+      basePorts: this.controlPort === this.formatPort ? [this.controlPort] : [this.controlPort, this.formatPort],
+      ioRead(port) {
+        if ((port & 255) === self.controlPort) {
+          self.frameFlip ^= 64;
+          return self.frameFlip;
+        }
+        return 0;
+      },
+      ioWrite(port, value) {
+        if ((port & 255) === self.controlPort) self.control = value & 255;
+        else if ((port & 255) === self.formatPort) self.format = value & 255;
+      },
+      reset() {
+        self.control = 0;
+        self.format = 0;
+        self.frameFlip = 0;
+      }
+    };
+    this.display = {
+      descriptor: { mode: "bitmap", width: 128, height: 128, format: "dazzler" },
+      frame: () => ({
+        bytes: this.dma(),
+        state: { on: this.control >> 7 & 1, format: this.format, control: this.control }
+      })
+    };
+  }
+  attach(bus) {
+    this.bus = bus;
+    bus.attachIODevice(this.dev);
+  }
+  reset() {
+    this.dev.reset();
+  }
+  /** DMA the display buffer out of system RAM at the current page. */
+  dma() {
+    const out = new Uint8Array(MAX_BUFFER);
+    const bus = this.bus;
+    if (!bus) return out;
+    const base = (this.control & 127) << 9;
+    for (let i = 0; i < MAX_BUFFER; i++) out[i] = bus.read(base + i & 65535) & 255;
+    return out;
+  }
+};
+
+// src/cards/RtcCard.ts
+var EPOCH_ZERO = () => /* @__PURE__ */ new Date(0);
+var bcd = (n) => (Math.floor(n / 10) % 10 << 4 | n % 10) & 255;
+var RtcCard = class {
+  id;
+  base;
+  now;
+  ram = new Uint8Array(32);
+  // 0x08..0x1F are read/write storage
+  dev;
+  constructor(id = "rtc", opts = {}, clock = EPOCH_ZERO) {
+    this.id = id;
+    this.base = (opts.base ?? 64) & 255;
+    this.now = clock;
+    const self = this;
+    const ports = [];
+    for (let i = 0; i < 32; i++) ports.push(this.base + i & 255);
+    this.dev = {
+      id: `${id}:io`,
+      basePorts: ports,
+      ioRead: (port) => self.readReg(port - self.base & 31),
+      ioWrite: (port, value) => self.writeReg(port - self.base & 31, value),
+      reset: () => self.ram.fill(0)
+    };
+  }
+  attach(bus) {
+    bus.attachIODevice(this.dev);
+  }
+  reset() {
+    this.ram.fill(0);
+  }
+  readReg(off) {
+    const d = this.now();
+    switch (off) {
+      case 0:
+        return 0;
+      //                     thousandths of a second
+      case 1:
+        return bcd(Math.floor(d.getMilliseconds() / 10));
+      // hundredths
+      case 2:
+        return bcd(d.getSeconds());
+      case 3:
+        return bcd(d.getMinutes());
+      case 4:
+        return bcd(d.getHours());
+      case 5:
+        return bcd(d.getDay() + 1);
+      //   day of week, 1–7
+      case 6:
+        return bcd(d.getDate());
+      //      day of month
+      case 7:
+        return bcd(d.getMonth() + 1);
+      // month, 1–12
+      default:
+        return this.ram[off] ?? 0;
+    }
+  }
+  writeReg(off, value) {
+    if (off > 7) this.ram[off] = u8(value);
+  }
+};
+
+// src/cards/BankRamCard.ts
+var BankRamCard = class {
+  id;
+  banks;
+  selectPort;
+  current = 0;
+  mem;
+  dev;
+  constructor(id = "bankram", opts = {}) {
+    this.id = id;
+    const window = (opts.window ?? 49152) & 65535;
+    const size = Math.max(1, Math.min(65536, opts.size ?? 16384));
+    const bankCount = Math.max(1, Math.min(256, opts.banks ?? 4));
+    this.selectPort = (opts.selectPort ?? 64) & 255;
+    this.banks = Array.from({ length: bankCount }, () => new Uint8Array(size));
+    const self = this;
+    this.mem = {
+      id: `${id}:ram`,
+      baseAddress: window,
+      size,
+      readOnly: false,
+      read: (offset) => self.banks[self.current][offset] ?? 255,
+      write: (offset, value) => {
+        self.banks[self.current][offset] = u8(value);
+      },
+      reset: () => {
+        for (const b of self.banks) b.fill(0);
+        self.current = 0;
+      }
+    };
+    this.dev = {
+      id: `${id}:sel`,
+      basePorts: [this.selectPort],
+      ioRead: () => self.current & 255,
+      ioWrite: (_port, value) => {
+        self.current = (value & 255) % self.banks.length;
+      },
+      reset: () => {
+        self.current = 0;
+      }
+    };
+  }
+  attach(bus) {
+    bus.attachMemory(this.mem);
+    bus.attachIODevice(this.dev);
+  }
+  reset() {
+    for (const b of this.banks) b.fill(0);
+    this.current = 0;
+  }
+};
+
+// src/bundles/kernels.ts
+var u83 = (v, fallback) => typeof v === "number" ? v & 255 : fallback;
+var u163 = (v, fallback) => typeof v === "number" ? v & 65535 : fallback;
+var serialKernel = {
+  id: "serial",
+  label: "Serial UART (console)",
+  type: "serial",
+  binding: "terminal",
+  configSchema: {
+    dataPort: { type: "u8", default: 16, min: 0, max: 255, description: "Data register port" },
+    ctrlPort: { type: "u8", default: 17, min: 0, max: 255, description: "Status/control port" },
+    chip: { type: "enum", default: "i8251", enum: ["i8251", "m6850"], description: "UART chip" }
+  },
+  create: (id, cfg) => new SerialCard(id, {
+    dataPort: u83(cfg.dataPort, 16),
+    ctrlPort: u83(cfg.ctrlPort, 17),
+    chip: cfg.chip ?? "i8251"
+  }),
+  claims: (cfg) => ({ ports: [u83(cfg.dataPort, 16), u83(cfg.ctrlPort, 17)] })
+};
+var parallelKernel = {
+  id: "parallel",
+  label: "Parallel I/O port",
+  type: "parallel",
+  binding: "gpio",
+  configSchema: {
+    port: { type: "u8", default: 0, min: 0, max: 255, description: "I/O port" },
+    direction: { type: "enum", default: "out", enum: ["out", "in", "inout"], description: "Data direction" }
+  },
+  create: (id, cfg) => new ParallelCard(id, { port: u83(cfg.port, 0), direction: cfg.direction ?? "out" }),
+  claims: (cfg) => ({ ports: [u83(cfg.port, 0)] })
+};
+var keyboardKernel = {
+  id: "keyboard",
+  label: "Keyboard input port (ASCII)",
+  type: "keyboard",
+  binding: "keyboard",
+  configSchema: {
+    dataPort: { type: "u8", default: 1, min: 0, max: 255, description: "Key data register port" },
+    statusPort: { type: "u8", default: 0, min: 0, max: 255, description: "Key-ready status port" },
+    readyMask: { type: "u8", default: 1, min: 0, max: 255, description: "Status bits set while a key waits" }
+  },
+  create: (id, cfg) => new KeyboardCard(id, {
+    dataPort: u83(cfg.dataPort, 1),
+    statusPort: u83(cfg.statusPort, 0),
+    readyMask: u83(cfg.readyMask, 1)
+  }),
+  claims: (cfg) => ({ ports: [u83(cfg.dataPort, 1), u83(cfg.statusPort, 0)] })
+};
+var vdmKernel = {
+  id: "vdm-video",
+  label: "VDM-1 video (64\xD716 characters)",
+  type: "video",
+  binding: "display",
+  configSchema: {
+    base: { type: "u16", default: 52224, min: 0, max: 65535, description: "Video RAM base" }
+  },
+  create: (id, cfg) => new VdmCard(id, { base: u163(cfg.base, 52224) }),
+  claims: () => ({ ports: [] }),
+  memory: (cfg) => [{ id: "vram", base: u163(cfg.base, 52224), size: 1024, kind: "ram" }]
+};
+var dazzlerKernel = {
+  id: "dazzler-video",
+  label: "Cromemco Dazzler (colour graphics)",
+  type: "video",
+  binding: "display",
+  configSchema: {
+    controlPort: { type: "u8", default: 14, min: 0, max: 255, description: "Control port (picture on + buffer page)" },
+    formatPort: { type: "u8", default: 15, min: 0, max: 255, description: "Format port (resolution / colour)" }
+  },
+  create: (id, cfg) => new DazzlerCard(id, { controlPort: u83(cfg.controlPort, 14), formatPort: u83(cfg.formatPort, 15) }),
+  claims: (cfg) => ({ ports: [u83(cfg.controlPort, 14), u83(cfg.formatPort, 15)] })
+  // No `memory`: the Dazzler DMAs ordinary system RAM, so it declares no region.
+};
+var rtcKernel = {
+  id: "mm58167-rtc",
+  label: "MM58167 real-time clock",
+  type: "rtc",
+  binding: "clock",
+  configSchema: {
+    base: { type: "u8", default: 64, min: 0, max: 224, description: "Base I/O port (occupies base..base+0x1F)" }
+  },
+  create: (id, cfg, ctx) => new RtcCard(id, { base: u83(cfg.base, 64) }, ctx.services.clock),
+  // 32 consecutive registers.
+  claims: (cfg) => {
+    const b = u83(cfg.base, 64);
+    return { ports: Array.from({ length: 32 }, (_v, i) => b + i & 255) };
+  }
+};
+var bankRamKernel = {
+  id: "bank-ram",
+  label: "Bank-switching RAM (MMU)",
+  type: "memory",
+  configSchema: {
+    window: { type: "u16", default: 49152, min: 0, max: 65535, description: "Switched window base address" },
+    size: { type: "u16", default: 16384, min: 1, max: 65535, description: "Bytes visible per bank" },
+    banks: { type: "u8", default: 4, min: 1, max: 255, description: "Number of RAM banks" },
+    selectPort: { type: "u8", default: 64, min: 0, max: 255, description: "Bank-select I/O port" }
+  },
+  create: (id, cfg) => new BankRamCard(id, {
+    window: u163(cfg.window, 49152),
+    size: u163(cfg.size, 16384),
+    banks: u83(cfg.banks, 4),
+    selectPort: u83(cfg.selectPort, 64)
+  }),
+  claims: (cfg) => ({ ports: [u83(cfg.selectPort, 64)] })
+};
+var kernels = [
+  serialKernel,
+  parallelKernel,
+  keyboardKernel,
+  vdmKernel,
+  dazzlerKernel,
+  rtcKernel,
+  bankRamKernel
+];
+var kernelById = (id) => kernels.find((k) => k.id === id);
+export {
+  BankRamCard,
+  Bus,
+  CardConfigError,
+  Cpu8080,
+  CpuZ80,
+  DazzlerCard,
+  FdcPlusClient,
+  Flags,
+  FlagsZ80,
+  ImmediateClock,
+  ImsaiMioCard,
+  ImsaiSioCard,
+  InterruptController,
+  IoSpace,
+  KeyboardCard,
+  MachineRunner,
+  MachineSpecError,
+  Mc6850Acia,
+  MemoryMappedIOAdapter,
+  Mits2SioCard,
+  MitsDcddCard,
+  ParallelCard,
+  Port8212,
+  Ram,
+  Registers,
+  RegistersZ80,
+  Rom,
+  RtcCard,
+  SerialCard,
+  SnoopBus,
+  SystemClock,
+  Tr1602Uart,
+  Usart8251,
+  VdmCard,
+  auxCarryAdd,
+  auxCarrySub,
+  bankRamKernel,
+  buildMachine,
+  dazzlerKernel,
+  hi,
+  kernelById,
+  kernels,
+  keyboardKernel,
+  lo,
+  parallelKernel,
+  parityFlag,
+  rtcKernel,
+  seedBundleByName,
+  seedBundles,
+  serialKernel,
+  signBit,
+  toWord,
+  u16,
+  u8,
+  vdmKernel,
+  withDefaults,
+  zeroFlag
+};