@joezilla/8sim 0.10.0

package/dist/cpu/z80/FlagsZ80.js

@@ -0,0 +1,47 @@
+/**
+ * Zilog Z80 flags register (F).
+ *
+ * Byte layout: S Z Y H X PV N C  (bit 7 → bit 0)
+ *   S  (0x80) Sign
+ *   Z  (0x40) Zero
+ *   Y  (0x20) undocumented copy of result bit 5
+ *   H  (0x10) Half-carry
+ *   X  (0x08) undocumented copy of result bit 3
+ *   PV (0x04) Parity / overflow (context-dependent)
+ *   N  (0x02) Add/Subtract (set by subtractions)
+ *   C  (0x01) Carry
+ */
+export class FlagsZ80 {
+    s = false;
+    z = false;
+    y = false;
+    h = false;
+    x = false;
+    pv = false;
+    n = false;
+    c = false;
+    toByte() {
+        return ((this.s ? 0x80 : 0) |
+            (this.z ? 0x40 : 0) |
+            (this.y ? 0x20 : 0) |
+            (this.h ? 0x10 : 0) |
+            (this.x ? 0x08 : 0) |
+            (this.pv ? 0x04 : 0) |
+            (this.n ? 0x02 : 0) |
+            (this.c ? 0x01 : 0));
+    }
+    fromByte(b) {
+        this.s = (b & 0x80) !== 0;
+        this.z = (b & 0x40) !== 0;
+        this.y = (b & 0x20) !== 0;
+        this.h = (b & 0x10) !== 0;
+        this.x = (b & 0x08) !== 0;
+        this.pv = (b & 0x04) !== 0;
+        this.n = (b & 0x02) !== 0;
+        this.c = (b & 0x01) !== 0;
+    }
+    reset() {
+        this.s = this.z = this.y = this.h = this.x = this.pv = this.n = this.c = false;
+    }
+}
+//# sourceMappingURL=FlagsZ80.js.map

package/dist/cpu/z80/FlagsZ80.js.map

@@ -0,0 +1 @@
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package/dist/cpu/z80/RegistersZ80.d.ts

@@ -0,0 +1,60 @@
+/**
+ * Zilog Z80 register file.
+ *
+ * Main 8-bit registers A,B,C,D,E,H,L plus the flags register F (held separately
+ * in {@link FlagsZ80}). The shadow set (A',F',B',C',D',E',H',L') is stored as raw
+ * bytes here — F' as a byte since it is only ever bulk-swapped by EX AF,AF'.
+ * Index registers IX/IY are 16-bit with byte accessors for the undocumented
+ * IXH/IXL/IYH/IYL operations. I is the interrupt vector base; R the refresh
+ * counter (bit 7 sticky). WZ is the internal MEMPTR register, observable only
+ * through the X/Y flags of `BIT n,(HL)` and a few other quirks.
+ */
+export declare class RegistersZ80 {
+    a: number;
+    b: number;
+    c: number;
+    d: number;
+    e: number;
+    h: number;
+    l: number;
+    a2: number;
+    f2: number;
+    b2: number;
+    c2: number;
+    d2: number;
+    e2: number;
+    h2: number;
+    l2: number;
+    ix: number;
+    iy: number;
+    sp: number;
+    pc: number;
+    i: number;
+    r: number;
+    wz: number;
+    /** BC register pair */
+    get bc(): number;
+    set bc(v: number);
+    /** DE register pair */
+    get de(): number;
+    set de(v: number);
+    /** HL register pair */
+    get hl(): number;
+    set hl(v: number);
+    /** IX high/low bytes (undocumented IXH/IXL) */
+    get ixh(): number;
+    set ixh(v: number);
+    get ixl(): number;
+    set ixl(v: number);
+    /** IY high/low bytes (undocumented IYH/IYL) */
+    get iyh(): number;
+    set iyh(v: number);
+    get iyl(): number;
+    set iyl(v: number);
+    /** M1 refresh tick: low 7 bits increment, bit 7 preserved. */
+    incR(): void;
+    /** EXX: swap BC/DE/HL with their shadows (AF is separate, via EX AF,AF'). */
+    exx(): void;
+    reset(): void;
+}
+//# sourceMappingURL=RegistersZ80.d.ts.map

package/dist/cpu/z80/RegistersZ80.d.ts.map

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package/dist/cpu/z80/RegistersZ80.js

@@ -0,0 +1,90 @@
+/**
+ * Zilog Z80 register file.
+ *
+ * Main 8-bit registers A,B,C,D,E,H,L plus the flags register F (held separately
+ * in {@link FlagsZ80}). The shadow set (A',F',B',C',D',E',H',L') is stored as raw
+ * bytes here — F' as a byte since it is only ever bulk-swapped by EX AF,AF'.
+ * Index registers IX/IY are 16-bit with byte accessors for the undocumented
+ * IXH/IXL/IYH/IYL operations. I is the interrupt vector base; R the refresh
+ * counter (bit 7 sticky). WZ is the internal MEMPTR register, observable only
+ * through the X/Y flags of `BIT n,(HL)` and a few other quirks.
+ */
+export class RegistersZ80 {
+    a = 0;
+    b = 0;
+    c = 0;
+    d = 0;
+    e = 0;
+    h = 0;
+    l = 0;
+    // Shadow set (swapped by EXX / EX AF,AF'). F' is a raw PSW byte.
+    a2 = 0;
+    f2 = 0;
+    b2 = 0;
+    c2 = 0;
+    d2 = 0;
+    e2 = 0;
+    h2 = 0;
+    l2 = 0;
+    ix = 0;
+    iy = 0;
+    sp = 0;
+    pc = 0;
+    i = 0; // interrupt vector base
+    r = 0; // refresh counter (bit 7 preserved across increments)
+    wz = 0; // MEMPTR — internal 16-bit temp
+    /** BC register pair */
+    get bc() { return (this.b << 8) | this.c; }
+    set bc(v) { this.b = (v >> 8) & 0xff; this.c = v & 0xff; }
+    /** DE register pair */
+    get de() { return (this.d << 8) | this.e; }
+    set de(v) { this.d = (v >> 8) & 0xff; this.e = v & 0xff; }
+    /** HL register pair */
+    get hl() { return (this.h << 8) | this.l; }
+    set hl(v) { this.h = (v >> 8) & 0xff; this.l = v & 0xff; }
+    /** IX high/low bytes (undocumented IXH/IXL) */
+    get ixh() { return (this.ix >> 8) & 0xff; }
+    set ixh(v) { this.ix = ((v & 0xff) << 8) | (this.ix & 0xff); }
+    get ixl() { return this.ix & 0xff; }
+    set ixl(v) { this.ix = (this.ix & 0xff00) | (v & 0xff); }
+    /** IY high/low bytes (undocumented IYH/IYL) */
+    get iyh() { return (this.iy >> 8) & 0xff; }
+    set iyh(v) { this.iy = ((v & 0xff) << 8) | (this.iy & 0xff); }
+    get iyl() { return this.iy & 0xff; }
+    set iyl(v) { this.iy = (this.iy & 0xff00) | (v & 0xff); }
+    /** M1 refresh tick: low 7 bits increment, bit 7 preserved. */
+    incR() {
+        this.r = (this.r & 0x80) | ((this.r + 1) & 0x7f);
+    }
+    /** EXX: swap BC/DE/HL with their shadows (AF is separate, via EX AF,AF'). */
+    exx() {
+        let t = this.b;
+        this.b = this.b2;
+        this.b2 = t;
+        t = this.c;
+        this.c = this.c2;
+        this.c2 = t;
+        t = this.d;
+        this.d = this.d2;
+        this.d2 = t;
+        t = this.e;
+        this.e = this.e2;
+        this.e2 = t;
+        t = this.h;
+        this.h = this.h2;
+        this.h2 = t;
+        t = this.l;
+        this.l = this.l2;
+        this.l2 = t;
+    }
+    reset() {
+        this.a = this.b = this.c = this.d = this.e = this.h = this.l = 0;
+        this.a2 = this.f2 = this.b2 = this.c2 = this.d2 = this.e2 = this.h2 = this.l2 = 0;
+        this.ix = this.iy = 0;
+        this.sp = 0;
+        this.pc = 0;
+        this.i = this.r = 0;
+        this.wz = 0;
+    }
+}
+//# sourceMappingURL=RegistersZ80.js.map

package/dist/cpu/z80/RegistersZ80.js.map

@@ -0,0 +1 @@
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package/dist/cpu/z80/flagHelpers.d.ts

@@ -0,0 +1,25 @@
+import type { FlagsZ80 } from './FlagsZ80.js';
+export declare function parityEven(v: number): boolean;
+/** Set S, Z, Y, X from a result byte (PV/H/N/C left to the caller). */
+export declare function setSzyx(f: FlagsZ80, r: number): void;
+/** Set S, Z, Y, X, PV(parity) from a result byte — the "logic/rotate" flag shape. */
+export declare function setSzyxp(f: FlagsZ80, r: number): void;
+/** 8-bit ADD / ADC. Returns the truncated result. */
+export declare function add8(f: FlagsZ80, a: number, b: number, cIn: 0 | 1): number;
+/** 8-bit SUB / SBC. `cIn` is the incoming borrow. Returns the truncated result. */
+export declare function sub8(f: FlagsZ80, a: number, b: number, cIn: 0 | 1): number;
+/** CP: like SUB but the result is discarded and X/Y come from the operand, not the result. */
+export declare function cp8(f: FlagsZ80, a: number, b: number): void;
+/** INC r: C is preserved, so it is not touched here. */
+export declare function inc8(f: FlagsZ80, v: number): number;
+/** DEC r: C is preserved, so it is not touched here. */
+export declare function dec8(f: FlagsZ80, v: number): number;
+/** AND/OR/XOR result flags. `hVal` is true for AND (H=1), false for OR/XOR (H=0). */
+export declare function setLogicFlags(f: FlagsZ80, r: number, hVal: boolean): void;
+/** ADD HL,rr (and ADD IX/IY,rr): affects H, N, C, X, Y only. Returns 16-bit result. */
+export declare function add16(f: FlagsZ80, a: number, b: number): number;
+/** ADC HL,rr: full flags; Z from the whole 16-bit result. */
+export declare function adc16(f: FlagsZ80, a: number, b: number, cIn: 0 | 1): number;
+/** SBC HL,rr: full flags; `cIn` is incoming borrow. */
+export declare function sbc16(f: FlagsZ80, a: number, b: number, cIn: 0 | 1): number;
+//# sourceMappingURL=flagHelpers.d.ts.map

package/dist/cpu/z80/flagHelpers.d.ts.map

@@ -0,0 +1 @@
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package/dist/cpu/z80/flagHelpers.js

@@ -0,0 +1,136 @@
+/**
+ * Shared Z80 flag computations. Every arithmetic/logic result funnels through
+ * one of these so the undocumented X (bit 3) and Y (bit 5) flags — copied from
+ * the result byte — are handled uniformly.
+ *
+ * Conventions: `cIn` is the incoming carry (0|1) for adds and the incoming
+ * borrow (0|1) for subtracts. Signed-overflow (PV) uses the classic
+ * `(~(a^b) & (a^r))` for adds and `((a^b) & (a^r))` for subtracts.
+ */
+/** Precomputed even-parity table (true = even number of set bits). */
+const PARITY = (() => {
+    const t = new Array(256);
+    for (let v = 0; v < 256; v++) {
+        let x = v;
+        x ^= x >> 4;
+        x ^= x >> 2;
+        x ^= x >> 1;
+        t[v] = (x & 1) === 0;
+    }
+    return t;
+})();
+export function parityEven(v) {
+    return PARITY[v & 0xff];
+}
+/** Set S, Z, Y, X from a result byte (PV/H/N/C left to the caller). */
+export function setSzyx(f, r) {
+    f.s = (r & 0x80) !== 0;
+    f.z = (r & 0xff) === 0;
+    f.y = (r & 0x20) !== 0;
+    f.x = (r & 0x08) !== 0;
+}
+/** Set S, Z, Y, X, PV(parity) from a result byte — the "logic/rotate" flag shape. */
+export function setSzyxp(f, r) {
+    setSzyx(f, r);
+    f.pv = PARITY[r & 0xff];
+}
+/** 8-bit ADD / ADC. Returns the truncated result. */
+export function add8(f, a, b, cIn) {
+    const sum = a + b + cIn;
+    const r = sum & 0xff;
+    setSzyx(f, r);
+    f.h = ((a & 0xf) + (b & 0xf) + cIn) > 0xf;
+    f.pv = (~(a ^ b) & (a ^ r) & 0x80) !== 0;
+    f.n = false;
+    f.c = sum > 0xff;
+    return r;
+}
+/** 8-bit SUB / SBC. `cIn` is the incoming borrow. Returns the truncated result. */
+export function sub8(f, a, b, cIn) {
+    const diff = a - b - cIn;
+    const r = diff & 0xff;
+    setSzyx(f, r);
+    f.h = ((a & 0xf) - (b & 0xf) - cIn) < 0;
+    f.pv = ((a ^ b) & (a ^ r) & 0x80) !== 0;
+    f.n = true;
+    f.c = diff < 0;
+    return r;
+}
+/** CP: like SUB but the result is discarded and X/Y come from the operand, not the result. */
+export function cp8(f, a, b) {
+    const diff = a - b;
+    const r = diff & 0xff;
+    f.s = (r & 0x80) !== 0;
+    f.z = r === 0;
+    f.y = (b & 0x20) !== 0;
+    f.x = (b & 0x08) !== 0;
+    f.h = ((a & 0xf) - (b & 0xf)) < 0;
+    f.pv = ((a ^ b) & (a ^ r) & 0x80) !== 0;
+    f.n = true;
+    f.c = diff < 0;
+}
+/** INC r: C is preserved, so it is not touched here. */
+export function inc8(f, v) {
+    const r = (v + 1) & 0xff;
+    setSzyx(f, r);
+    f.h = (v & 0xf) === 0xf;
+    f.pv = v === 0x7f;
+    f.n = false;
+    return r;
+}
+/** DEC r: C is preserved, so it is not touched here. */
+export function dec8(f, v) {
+    const r = (v - 1) & 0xff;
+    setSzyx(f, r);
+    f.h = (v & 0xf) === 0;
+    f.pv = v === 0x80;
+    f.n = true;
+    return r;
+}
+/** AND/OR/XOR result flags. `hVal` is true for AND (H=1), false for OR/XOR (H=0). */
+export function setLogicFlags(f, r, hVal) {
+    setSzyxp(f, r);
+    f.h = hVal;
+    f.n = false;
+    f.c = false;
+}
+/** ADD HL,rr (and ADD IX/IY,rr): affects H, N, C, X, Y only. Returns 16-bit result. */
+export function add16(f, a, b) {
+    const sum = a + b;
+    const r = sum & 0xffff;
+    f.h = ((a & 0xfff) + (b & 0xfff)) > 0xfff;
+    f.n = false;
+    f.c = sum > 0xffff;
+    f.y = (r & 0x2000) !== 0; // bit 13 = bit 5 of high byte
+    f.x = (r & 0x0800) !== 0; // bit 11 = bit 3 of high byte
+    return r;
+}
+/** ADC HL,rr: full flags; Z from the whole 16-bit result. */
+export function adc16(f, a, b, cIn) {
+    const sum = a + b + cIn;
+    const r = sum & 0xffff;
+    f.s = (r & 0x8000) !== 0;
+    f.z = r === 0;
+    f.h = ((a & 0xfff) + (b & 0xfff) + cIn) > 0xfff;
+    f.pv = (~(a ^ b) & (a ^ r) & 0x8000) !== 0;
+    f.n = false;
+    f.c = sum > 0xffff;
+    f.y = (r & 0x2000) !== 0;
+    f.x = (r & 0x0800) !== 0;
+    return r;
+}
+/** SBC HL,rr: full flags; `cIn` is incoming borrow. */
+export function sbc16(f, a, b, cIn) {
+    const diff = a - b - cIn;
+    const r = diff & 0xffff;
+    f.s = (r & 0x8000) !== 0;
+    f.z = r === 0;
+    f.h = ((a & 0xfff) - (b & 0xfff) - cIn) < 0;
+    f.pv = ((a ^ b) & (a ^ r) & 0x8000) !== 0;
+    f.n = true;
+    f.c = diff < 0;
+    f.y = (r & 0x2000) !== 0;
+    f.x = (r & 0x0800) !== 0;
+    return r;
+}
+//# sourceMappingURL=flagHelpers.js.map

package/dist/cpu/z80/flagHelpers.js.map

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package/dist/cpu/z80/instructions/alu16.d.ts

@@ -0,0 +1,4 @@
+import type { Z80Handler, IndexView } from '../types.js';
+/** 16-bit INC/DEC and ADD HL,rr in the main table (view-parameterized). */
+export declare function registerAlu16(table: Z80Handler[], view: IndexView): void;
+//# sourceMappingURL=alu16.d.ts.map

package/dist/cpu/z80/instructions/alu16.d.ts.map

@@ -0,0 +1 @@
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package/dist/cpu/z80/instructions/alu16.js

@@ -0,0 +1,27 @@
+import { add16 } from '../flagHelpers.js';
+import { u16 } from '../../../util/bits.js';
+/** 16-bit INC/DEC and ADD HL,rr in the main table (view-parameterized). */
+export function registerAlu16(table, view) {
+    // INC rr
+    table[0x03] = (cpu) => { cpu.regs.bc = u16(cpu.regs.bc + 1); return 6; };
+    table[0x13] = (cpu) => { cpu.regs.de = u16(cpu.regs.de + 1); return 6; };
+    table[0x23] = (cpu) => { view.setPair(cpu.regs, u16(view.getPair(cpu.regs) + 1)); return 6; };
+    table[0x33] = (cpu) => { cpu.regs.sp = u16(cpu.regs.sp + 1); return 6; };
+    // DEC rr
+    table[0x0b] = (cpu) => { cpu.regs.bc = u16(cpu.regs.bc - 1); return 6; };
+    table[0x1b] = (cpu) => { cpu.regs.de = u16(cpu.regs.de - 1); return 6; };
+    table[0x2b] = (cpu) => { view.setPair(cpu.regs, u16(view.getPair(cpu.regs) - 1)); return 6; };
+    table[0x3b] = (cpu) => { cpu.regs.sp = u16(cpu.regs.sp - 1); return 6; };
+    // ADD HL,rr  (ADD IX,rr / ADD IY,rr) — WZ = HL(before) + 1
+    const addHl = (getOperand) => (cpu) => {
+        const hl = view.getPair(cpu.regs);
+        cpu.regs.wz = u16(hl + 1);
+        view.setPair(cpu.regs, add16(cpu.flags, hl, getOperand(cpu)));
+        return 11;
+    };
+    table[0x09] = addHl((cpu) => cpu.regs.bc);
+    table[0x19] = addHl((cpu) => cpu.regs.de);
+    table[0x29] = addHl((cpu) => view.getPair(cpu.regs));
+    table[0x39] = addHl((cpu) => cpu.regs.sp);
+}
+//# sourceMappingURL=alu16.js.map

package/dist/cpu/z80/instructions/alu16.js.map

@@ -0,0 +1 @@
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package/dist/cpu/z80/instructions/alu8.d.ts

@@ -0,0 +1,4 @@
+import type { Z80Handler, IndexView } from '../types.js';
+/** 8-bit arithmetic/logic and INC/DEC r in the main table (view-parameterized). */
+export declare function registerAlu8(table: Z80Handler[], view: IndexView): void;
+//# sourceMappingURL=alu8.d.ts.map

package/dist/cpu/z80/instructions/alu8.d.ts.map

@@ -0,0 +1 @@
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package/dist/cpu/z80/instructions/alu8.js

@@ -0,0 +1,100 @@
+import { getR, setR } from '../regcodes.js';
+import { add8, sub8, cp8, setLogicFlags, inc8, dec8 } from '../flagHelpers.js';
+/** Apply ALU operation `kind` (0=ADD..7=CP) of `v` onto the accumulator. */
+function applyAlu(cpu, kind, v) {
+    const f = cpu.flags;
+    const regs = cpu.regs;
+    switch (kind) {
+        case 0:
+            regs.a = add8(f, regs.a, v, 0);
+            break; // ADD
+        case 1:
+            regs.a = add8(f, regs.a, v, f.c ? 1 : 0);
+            break; // ADC
+        case 2:
+            regs.a = sub8(f, regs.a, v, 0);
+            break; // SUB
+        case 3:
+            regs.a = sub8(f, regs.a, v, f.c ? 1 : 0);
+            break; // SBC
+        case 4:
+            regs.a = regs.a & v;
+            setLogicFlags(f, regs.a, true);
+            break; // AND
+        case 5:
+            regs.a = regs.a ^ v;
+            setLogicFlags(f, regs.a, false);
+            break; // XOR
+        case 6:
+            regs.a = regs.a | v;
+            setLogicFlags(f, regs.a, false);
+            break; // OR
+        case 7:
+            cp8(f, regs.a, v);
+            break; // CP
+    }
+}
+/** 8-bit arithmetic/logic and INC/DEC r in the main table (view-parameterized). */
+export function registerAlu8(table, view) {
+    // ALU A,r / ALU A,(HL)  (0x80..0xBF)
+    for (let op = 0x80; op <= 0xbf; op++) {
+        const kind = (op >> 3) & 7;
+        const reg = op & 7;
+        if (reg === 6) {
+            table[op] = (cpu) => {
+                const addr = view.memAddr(cpu);
+                applyAlu(cpu, kind, cpu.bus.read(addr));
+                return 7 + view.memExtra;
+            };
+        }
+        else {
+            table[op] = (cpu) => {
+                applyAlu(cpu, kind, getR(cpu.regs, view, reg));
+                return 4;
+            };
+        }
+    }
+    // ALU A,n  (0xC6,0xCE,0xD6,0xDE,0xE6,0xEE,0xF6,0xFE)
+    for (const op of [0xc6, 0xce, 0xd6, 0xde, 0xe6, 0xee, 0xf6, 0xfe]) {
+        const kind = (op >> 3) & 7;
+        table[op] = (cpu) => {
+            applyAlu(cpu, kind, cpu.fetchByte());
+            return 7;
+        };
+    }
+    // INC r  (0x04|r<<3)
+    for (let r = 0; r < 8; r++) {
+        const op = 0x04 | (r << 3);
+        if (r === 6) {
+            table[op] = (cpu) => {
+                const addr = view.memAddr(cpu);
+                cpu.bus.write(addr, inc8(cpu.flags, cpu.bus.read(addr)));
+                return 11 + view.memExtra;
+            };
+        }
+        else {
+            table[op] = (cpu) => {
+                setR(cpu.regs, view, r, inc8(cpu.flags, getR(cpu.regs, view, r)));
+                return 4;
+            };
+        }
+    }
+    // DEC r  (0x05|r<<3)
+    for (let r = 0; r < 8; r++) {
+        const op = 0x05 | (r << 3);
+        if (r === 6) {
+            table[op] = (cpu) => {
+                const addr = view.memAddr(cpu);
+                cpu.bus.write(addr, dec8(cpu.flags, cpu.bus.read(addr)));
+                return 11 + view.memExtra;
+            };
+        }
+        else {
+            table[op] = (cpu) => {
+                setR(cpu.regs, view, r, dec8(cpu.flags, getR(cpu.regs, view, r)));
+                return 4;
+            };
+        }
+    }
+}
+//# sourceMappingURL=alu8.js.map

package/dist/cpu/z80/instructions/alu8.js.map

@@ -0,0 +1 @@
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package/dist/cpu/z80/instructions/bits.d.ts

@@ -0,0 +1,10 @@
+import type { Z80Handler, Z80IndexedCbHandler } from '../types.js';
+/**
+ * Registers the plain CB table and the DDCB/FDCB (indexed) bodies.
+ *
+ * Plain CB handlers return the FULL T-state count (the CB dispatcher does not add
+ * the prefix). Indexed handlers return the count minus the DD/FD prefix (which
+ * step() adds): rot/shift/res/set = 19 (→23), BIT = 16 (→20).
+ */
+export declare function registerBits(cb: Z80Handler[], idxCb: Z80IndexedCbHandler[]): void;
+//# sourceMappingURL=bits.d.ts.map

package/dist/cpu/z80/instructions/bits.d.ts.map

@@ -0,0 +1 @@
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