@joezilla/8sim 0.10.0

package/dist/cards/FdcPlusClient.js

@@ -0,0 +1,130 @@
+export class FdcPlusClient {
+    ws;
+    rxBuf = [];
+    rxTotal = 0;
+    pending = [];
+    // Wire mutex. The protocol is strictly request/response, and WRIT is a
+    // multi-frame exchange (header → ack → raw data → status): any frame another
+    // op sends mid-exchange is consumed by the server as track data, and the
+    // tail of the real payload spills out as garbage commands, permanently
+    // desyncing the stream. Null when the wire is idle.
+    chainTail = null;
+    constructor(ws) {
+        this.ws = ws;
+        ws.onmessage = (ev) => {
+            const chunk = ev.data instanceof ArrayBuffer
+                ? new Uint8Array(ev.data)
+                : ev.data;
+            this.rxBuf.push(chunk);
+            this.rxTotal += chunk.length;
+            this.drain();
+        };
+        ws.onerror = () => this.rejectAll(new Error('WebSocket error'));
+        ws.onclose = () => this.rejectAll(new Error('WebSocket closed'));
+    }
+    stat(drive, headLoad, track) {
+        return this.exchange(() => {
+            const p1 = ((headLoad ? 1 : 0) << 8) | (drive & 0xff);
+            this.ws.send(this.makeCmd('STAT', p1, track & 0xffff));
+            return this.enqueue(8).then(buf => this.parseCmd(buf).p2);
+        });
+    }
+    readTrack(drive, track, length) {
+        return this.exchange(() => {
+            const p1 = ((drive & 0xf) << 12) | (track & 0xfff);
+            this.ws.send(this.makeCmd('READ', p1, length));
+            return this.enqueue(length);
+        });
+    }
+    writeTrack(drive, track, data) {
+        return this.exchange(() => {
+            const p1 = ((drive & 0xf) << 12) | (track & 0xfff);
+            this.ws.send(this.makeCmd('WRIT', p1, data.length));
+            return this.enqueue(8).then(ackBuf => {
+                const ack = this.parseCmd(ackBuf);
+                if (ack.p1 !== 0)
+                    throw new Error(`WRIT rejected: status ${ack.p1}`);
+                this.ws.send(data);
+                return this.enqueue(8).then(wstaBuf => {
+                    const wsta = this.parseCmd(wstaBuf);
+                    if (wsta.p1 !== 0)
+                        throw new Error(`WSTA error: status ${wsta.p1}`);
+                });
+            });
+        });
+    }
+    /**
+     * Run one full request/response exchange with exclusive use of the wire.
+     * Starts synchronously when the wire is idle (device registers depend on the
+     * command going out on the same tick); queues behind the in-flight exchange
+     * otherwise. A failed exchange never blocks the queue.
+     */
+    exchange(op) {
+        const run = this.chainTail ? this.chainTail.then(op, op) : op();
+        const tail = run.then(() => undefined, () => undefined);
+        this.chainTail = tail;
+        void tail.then(() => { if (this.chainTail === tail)
+            this.chainTail = null; });
+        return run;
+    }
+    makeCmd(mnemonic, p1, p2) {
+        const buf = new Uint8Array(8);
+        for (let i = 0; i < 4; i++)
+            buf[i] = mnemonic.charCodeAt(i) & 0xff;
+        buf[4] = p1 & 0xff;
+        buf[5] = (p1 >> 8) & 0xff;
+        buf[6] = p2 & 0xff;
+        buf[7] = (p2 >> 8) & 0xff;
+        return buf;
+    }
+    parseCmd(buf) {
+        const cmd = String.fromCharCode(buf[0] ?? 0, buf[1] ?? 0, buf[2] ?? 0, buf[3] ?? 0);
+        const p1 = (buf[4] ?? 0) | ((buf[5] ?? 0) << 8);
+        const p2 = (buf[6] ?? 0) | ((buf[7] ?? 0) << 8);
+        return { cmd, p1, p2 };
+    }
+    enqueue(bytesExpected) {
+        return new Promise((resolve, reject) => {
+            this.pending.push({ resolve, reject, bytesExpected });
+            this.drain();
+        });
+    }
+    drain() {
+        while (this.pending.length > 0) {
+            const head = this.pending[0];
+            if (!head || this.rxTotal < head.bytesExpected)
+                break;
+            this.pending.shift();
+            head.resolve(this.collect(head.bytesExpected));
+        }
+    }
+    collect(n) {
+        const out = new Uint8Array(n);
+        let written = 0;
+        while (written < n) {
+            const chunk = this.rxBuf[0];
+            if (!chunk)
+                break;
+            const needed = n - written;
+            if (chunk.length <= needed) {
+                out.set(chunk, written);
+                written += chunk.length;
+                this.rxBuf.shift();
+                this.rxTotal -= chunk.length;
+            }
+            else {
+                out.set(chunk.subarray(0, needed), written);
+                this.rxBuf[0] = chunk.subarray(needed);
+                this.rxTotal -= needed;
+                written = n;
+            }
+        }
+        return out;
+    }
+    rejectAll(err) {
+        const entries = this.pending.splice(0);
+        for (const e of entries)
+            e.reject(err);
+    }
+}
+//# sourceMappingURL=FdcPlusClient.js.map

package/dist/cards/FdcPlusClient.js.map

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package/dist/cards/ImsaiMioCard.d.ts

@@ -0,0 +1,36 @@
+import type { IS100Card } from '../interfaces/IS100Card.js';
+import type { Bus } from '../bus/Bus.js';
+import { Tr1602Uart } from './Tr1602Uart.js';
+import { Port8212 } from './Port8212.js';
+export interface MioCardOptions {
+    readonly basePort?: number;
+}
+/**
+ * IMSAI MIO (Multiple Input/Output) S-100 card (1977). A multifunction I/O
+ * board combining a TR1602 UART serial port, two 8212 parallel ports, and a
+ * board control register, on four consecutive I/O addresses:
+ *
+ *   base+0  Port A  — 8212 parallel I/O
+ *   base+1  Port B  — 8212 parallel I/O
+ *   base+2  serial data     (read: RX / write: TX)
+ *   base+3  serial status   (read) / board control (write)
+ *
+ * The base address is jumper-selectable on real hardware. The default of 0x10
+ * places the serial port at 0x12/0x13 (the standard MIO layout). Use
+ * `basePort: 0x00` to relocate the serial port to 0x02/0x03 for SIO-2-
+ * compatible console duty.
+ *
+ * Unlike {@link ImsaiSioCard} (Intel 8251), the MIO's TR1602 UART needs no
+ * initialization and is always transmit-ready.
+ */
+export declare class ImsaiMioCard implements IS100Card {
+    readonly id: string;
+    readonly portA: Port8212;
+    readonly portB: Port8212;
+    readonly uart: Tr1602Uart;
+    constructor(id?: string, options?: MioCardOptions);
+    attach(bus: Bus): void;
+    wireToConsole(): void;
+    reset(): void;
+}
+//# sourceMappingURL=ImsaiMioCard.d.ts.map

package/dist/cards/ImsaiMioCard.d.ts.map

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package/dist/cards/ImsaiMioCard.js

@@ -0,0 +1,48 @@
+import { Tr1602Uart } from './Tr1602Uart.js';
+import { Port8212 } from './Port8212.js';
+import { writeHostStdout } from '../util/hostConsole.js';
+/**
+ * IMSAI MIO (Multiple Input/Output) S-100 card (1977). A multifunction I/O
+ * board combining a TR1602 UART serial port, two 8212 parallel ports, and a
+ * board control register, on four consecutive I/O addresses:
+ *
+ *   base+0  Port A  — 8212 parallel I/O
+ *   base+1  Port B  — 8212 parallel I/O
+ *   base+2  serial data     (read: RX / write: TX)
+ *   base+3  serial status   (read) / board control (write)
+ *
+ * The base address is jumper-selectable on real hardware. The default of 0x10
+ * places the serial port at 0x12/0x13 (the standard MIO layout). Use
+ * `basePort: 0x00` to relocate the serial port to 0x02/0x03 for SIO-2-
+ * compatible console duty.
+ *
+ * Unlike {@link ImsaiSioCard} (Intel 8251), the MIO's TR1602 UART needs no
+ * initialization and is always transmit-ready.
+ */
+export class ImsaiMioCard {
+    id;
+    portA;
+    portB;
+    uart;
+    constructor(id = 'mio', options = {}) {
+        const base = options.basePort ?? 0x10;
+        this.id = id;
+        this.portA = new Port8212(`${id}:portA`, base + 0);
+        this.portB = new Port8212(`${id}:portB`, base + 1);
+        this.uart = new Tr1602Uart(`${id}:uart`, base + 2, base + 3);
+    }
+    attach(bus) {
+        bus.attachIODevice(this.portA);
+        bus.attachIODevice(this.portB);
+        bus.attachIODevice(this.uart);
+    }
+    wireToConsole() {
+        this.uart.onTransmit((byte) => writeHostStdout(String.fromCharCode(byte & 0x7f)));
+    }
+    reset() {
+        this.portA.reset();
+        this.portB.reset();
+        this.uart.reset();
+    }
+}
+//# sourceMappingURL=ImsaiMioCard.js.map

package/dist/cards/ImsaiMioCard.js.map

@@ -0,0 +1 @@
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package/dist/cards/ImsaiSioCard.d.ts

@@ -0,0 +1,19 @@
+import type { IS100Card } from '../interfaces/IS100Card.js';
+import type { Bus } from '../bus/Bus.js';
+import { Usart8251 } from './Usart8251.js';
+export interface SioCardOptions {
+    readonly basePortA?: number;
+    readonly basePortB?: number;
+    readonly boardCtrlPort?: number;
+}
+export declare class ImsaiSioCard implements IS100Card {
+    readonly id: string;
+    readonly channelA: Usart8251;
+    readonly channelB: Usart8251;
+    private readonly boardCtrl;
+    constructor(id?: string, options?: SioCardOptions);
+    attach(bus: Bus): void;
+    wireToConsole(): void;
+    reset(): void;
+}
+//# sourceMappingURL=ImsaiSioCard.d.ts.map

package/dist/cards/ImsaiSioCard.d.ts.map

@@ -0,0 +1 @@
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package/dist/cards/ImsaiSioCard.js

@@ -0,0 +1,54 @@
+import { Usart8251 } from './Usart8251.js';
+import { writeHostStdout } from '../util/hostConsole.js';
+class SioBoardCtrl {
+    a;
+    b;
+    id;
+    basePorts;
+    constructor(id, port, a, b) {
+        this.a = a;
+        this.b = b;
+        this.id = id;
+        this.basePorts = [port];
+    }
+    ioRead(_port) {
+        return 0xff;
+    }
+    ioWrite(_port, value) {
+        if ((value & 0x03) !== 0)
+            this.a.reset();
+        if ((value & 0x0c) !== 0)
+            this.b.reset();
+    }
+    reset() { }
+}
+export class ImsaiSioCard {
+    id;
+    channelA;
+    channelB;
+    boardCtrl;
+    constructor(id = 'sio2', options = {}) {
+        const portA = options.basePortA ?? 0x02;
+        const portB = options.basePortB ?? 0x04;
+        const ctrlPort = options.boardCtrlPort ?? 0x08;
+        this.id = id;
+        this.channelA = new Usart8251(`${id}:a`, portA, portA + 1);
+        this.channelB = new Usart8251(`${id}:b`, portB, portB + 1);
+        this.boardCtrl = new SioBoardCtrl(`${id}:ctrl`, ctrlPort, this.channelA, this.channelB);
+    }
+    attach(bus) {
+        bus.attachIODevice(this.channelA);
+        bus.attachIODevice(this.channelB);
+        bus.attachIODevice(this.boardCtrl);
+    }
+    wireToConsole() {
+        const write = (byte) => writeHostStdout(String.fromCharCode(byte));
+        this.channelA.onTransmit(write);
+        this.channelB.onTransmit(write);
+    }
+    reset() {
+        this.channelA.reset();
+        this.channelB.reset();
+    }
+}
+//# sourceMappingURL=ImsaiSioCard.js.map

package/dist/cards/ImsaiSioCard.js.map

@@ -0,0 +1 @@
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package/dist/cards/KeyboardCard.d.ts

@@ -0,0 +1,37 @@
+import type { IS100Card } from '../interfaces/IS100Card.js';
+import type { Bus } from '../bus/Bus.js';
+/**
+ * The host-side surface a keyboard peripheral binds to (Story 5.9). The host
+ * (fdcplus-web) drives key presses in from a real keyboard; the guest reads
+ * them from the card's data port. This is the input counterpart to
+ * {@link SerialCard.channel} / {@link ParallelCard.gpio} / {@link VdmCard.display}.
+ */
+export interface KeyboardPort {
+    /** Queue a single key (ASCII/byte) for the guest to read from the data port. */
+    press(byte: number): void;
+    /** Queue each character of a string — convenience for a host paste. */
+    type(text: string): void;
+    /** How many keys are waiting to be read. */
+    readonly pending: number;
+}
+export interface KeyboardCardOptions {
+    readonly dataPort?: number;
+    readonly statusPort?: number;
+    /** Bits asserted on the status port while a key is waiting (default 0x01). */
+    readonly readyMask?: number;
+}
+/**
+ * A keyboard input card — the general ASCII-keyboard board that authored
+ * keyboard cards resolve to (Story 5.9). It exposes a `keyboard` surface so the
+ * host wires it to the operator's real keyboard, mirroring how SerialCard
+ * exposes `channel` and VdmCard exposes `display`.
+ */
+export declare class KeyboardCard implements IS100Card {
+    readonly id: string;
+    readonly keyboard: KeyboardPort;
+    private readonly dev;
+    constructor(id?: string, opts?: KeyboardCardOptions);
+    attach(bus: Bus): void;
+    reset(): void;
+}
+//# sourceMappingURL=KeyboardCard.d.ts.map

package/dist/cards/KeyboardCard.d.ts.map

@@ -0,0 +1 @@
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package/dist/cards/KeyboardCard.js

@@ -0,0 +1,79 @@
+import { u8 } from '../util/bits.js';
+/**
+ * Input-only keyboard port device — a FIFO of key bytes behind a data + status
+ * port, the classic parallel-ASCII keyboard interface of a VDM-1 / Dazzler
+ * video terminal (no serial line). The guest polls the status port for the
+ * ready bit(s), then reads the data port to take the next key (which
+ * acknowledges it). Writes are ignored — a keyboard is read-only on the bus.
+ */
+class KeyboardDevice {
+    id;
+    basePorts;
+    dataPort;
+    statusPort;
+    readyMask;
+    queue = [];
+    constructor(id, dataPort, statusPort, readyMask) {
+        this.id = id;
+        this.dataPort = u8(dataPort);
+        this.statusPort = u8(statusPort);
+        this.readyMask = u8(readyMask);
+        // A single-port keyboard (data === status) collapses to one claim; the data
+        // read wins the dispatch below so the guest can still take keys.
+        this.basePorts =
+            this.dataPort === this.statusPort ? [this.dataPort] : [this.dataPort, this.statusPort];
+    }
+    ioRead(port) {
+        const p = u8(port);
+        if (p === this.dataPort)
+            return this.queue.shift() ?? 0; // take next key, acknowledge
+        if (p === this.statusPort)
+            return this.queue.length > 0 ? this.readyMask : 0;
+        return 0;
+    }
+    ioWrite() {
+        // input-only: a keyboard doesn't respond to CPU writes
+    }
+    reset() {
+        this.queue.length = 0;
+    }
+    press(byte) {
+        this.queue.push(u8(byte));
+    }
+    get pending() {
+        return this.queue.length;
+    }
+}
+/**
+ * A keyboard input card — the general ASCII-keyboard board that authored
+ * keyboard cards resolve to (Story 5.9). It exposes a `keyboard` surface so the
+ * host wires it to the operator's real keyboard, mirroring how SerialCard
+ * exposes `channel` and VdmCard exposes `display`.
+ */
+export class KeyboardCard {
+    id;
+    keyboard;
+    dev;
+    constructor(id = 'keyboard', opts = {}) {
+        this.id = id;
+        this.dev = new KeyboardDevice(`${id}:kbd`, opts.dataPort ?? 0x01, opts.statusPort ?? 0x00, opts.readyMask ?? 0x01);
+        const dev = this.dev;
+        this.keyboard = {
+            press: (byte) => dev.press(byte),
+            type: (text) => {
+                for (let i = 0; i < text.length; i++)
+                    dev.press(text.charCodeAt(i));
+            },
+            get pending() {
+                return dev.pending;
+            },
+        };
+    }
+    attach(bus) {
+        bus.attachIODevice(this.dev);
+    }
+    reset() {
+        this.dev.reset();
+    }
+}
+//# sourceMappingURL=KeyboardCard.js.map

package/dist/cards/KeyboardCard.js.map

@@ -0,0 +1 @@
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package/dist/cards/Mc6850Acia.d.ts

@@ -0,0 +1,68 @@
+import type { IIODevice } from '../interfaces/IIODevice.js';
+type TransmitCallback = (byte: number) => void;
+/**
+ * Motorola MC6850 ACIA, as used (×2) on the MITS Altair 88-2SIO board.
+ *
+ * Occupies two consecutive I/O ports — note the order is the OPPOSITE of the
+ * Intel 8251 / TR1602 (which put data at the lower address):
+ *   statusPort (base+0) — read: status register; write: control register
+ *   dataPort   (base+1) — read: received byte;   write: transmit byte
+ *
+ * Status register:
+ *   bit0 RDRF  — receive data register full (1 = byte available)
+ *   bit1 TDRE  — transmit data register empty (1 = ready to accept a byte)
+ *   bit2 DCD   — data carrier detect (1 = carrier lost)
+ *   bit3 CTS   — clear-to-send input (1 = NOT clear to send)
+ *   bit4 FE    — framing error
+ *   bit5 OVRN  — receiver overrun
+ *   bit6 PE    — parity error
+ *   bit7 IRQ   — interrupt request pending
+ *
+ * Control register (write):
+ *   bits1-0  counter divide / master reset (11 = master reset)
+ *   bits4-2  word select (data bits / parity / stop bits — cosmetic here)
+ *   bits6-5  transmit control (RTS state + TX interrupt enable)
+ *   bit7     receive interrupt enable
+ *
+ * DCD and CTS default to their grounded (active) state — carrier present and
+ * clear-to-send — matching a board jumpered for direct terminal use. With DCD
+ * lost, RDRF is clamped to 0; with CTS not clear, TDRE is inhibited (the two
+ * classic "my 2SIO doesn't work" failure modes).
+ */
+export declare class Mc6850Acia implements IIODevice {
+    private readonly statusPort;
+    private readonly dataPort;
+    readonly id: string;
+    readonly basePorts: ReadonlyArray<number>;
+    private controlReg;
+    private rxQueue;
+    private errorFlags;
+    private rxIntEnable;
+    private txIntEnable;
+    private ctsClear;
+    private carrierPresent;
+    private transmitCb;
+    constructor(id: string, statusPort: number, dataPort: number);
+    ioRead(port: number): number;
+    ioWrite(port: number, value: number): void;
+    reset(): void;
+    /**
+     * Feed a received byte to the ACIA. Sets RDRF; a byte arriving while the
+     * previous one has not been read flags an overrun (OVRN).
+     */
+    enqueueRx(byte: number): void;
+    onTransmit(cb: TransmitCallback): void;
+    /** Drive the CTS input: true = clear to send (grounded), false = inhibited. */
+    setCts(clear: boolean): void;
+    /** Drive the DCD input: true = carrier present (grounded), false = lost. */
+    setDcd(carrierPresent: boolean): void;
+    /** Inject receive error flags (framing / overrun / parity) for the next read. */
+    setErrors(fe: boolean, ovrn: boolean, pe: boolean): void;
+    /** Last value written to the control register. */
+    get control(): number;
+    private writeControl;
+    private masterReset;
+    private buildStatus;
+}
+export {};
+//# sourceMappingURL=Mc6850Acia.d.ts.map

package/dist/cards/Mc6850Acia.d.ts.map

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package/dist/cards/Mc6850Acia.js

@@ -0,0 +1,132 @@
+import { u8 } from '../util/bits.js';
+/**
+ * Motorola MC6850 ACIA, as used (×2) on the MITS Altair 88-2SIO board.
+ *
+ * Occupies two consecutive I/O ports — note the order is the OPPOSITE of the
+ * Intel 8251 / TR1602 (which put data at the lower address):
+ *   statusPort (base+0) — read: status register; write: control register
+ *   dataPort   (base+1) — read: received byte;   write: transmit byte
+ *
+ * Status register:
+ *   bit0 RDRF  — receive data register full (1 = byte available)
+ *   bit1 TDRE  — transmit data register empty (1 = ready to accept a byte)
+ *   bit2 DCD   — data carrier detect (1 = carrier lost)
+ *   bit3 CTS   — clear-to-send input (1 = NOT clear to send)
+ *   bit4 FE    — framing error
+ *   bit5 OVRN  — receiver overrun
+ *   bit6 PE    — parity error
+ *   bit7 IRQ   — interrupt request pending
+ *
+ * Control register (write):
+ *   bits1-0  counter divide / master reset (11 = master reset)
+ *   bits4-2  word select (data bits / parity / stop bits — cosmetic here)
+ *   bits6-5  transmit control (RTS state + TX interrupt enable)
+ *   bit7     receive interrupt enable
+ *
+ * DCD and CTS default to their grounded (active) state — carrier present and
+ * clear-to-send — matching a board jumpered for direct terminal use. With DCD
+ * lost, RDRF is clamped to 0; with CTS not clear, TDRE is inhibited (the two
+ * classic "my 2SIO doesn't work" failure modes).
+ */
+export class Mc6850Acia {
+    statusPort;
+    dataPort;
+    id;
+    basePorts;
+    controlReg = 0;
+    rxQueue = [];
+    // bit0=FE, bit1=OVRN, bit2=PE — positioned into status bits 4-6 when read.
+    errorFlags = 0;
+    rxIntEnable = false;
+    txIntEnable = false;
+    ctsClear = true; // CTS input grounded → clear to send
+    carrierPresent = true; // DCD input grounded → carrier present
+    transmitCb;
+    constructor(id, statusPort, dataPort) {
+        this.statusPort = statusPort;
+        this.dataPort = dataPort;
+        this.id = id;
+        this.basePorts = [statusPort, dataPort];
+    }
+    ioRead(port) {
+        if (port === this.statusPort) {
+            return this.buildStatus();
+        }
+        // Data port read: pull the received byte, clearing RDRF (and overrun once
+        // the buffer drains).
+        const byte = this.rxQueue.shift();
+        if (this.rxQueue.length === 0) {
+            this.errorFlags &= ~0x02;
+        }
+        return byte !== undefined ? byte : 0xff;
+    }
+    ioWrite(port, value) {
+        if (port === this.statusPort) {
+            this.writeControl(u8(value));
+            return;
+        }
+        // Data port write: transmit, unless CTS says the peer is not ready.
+        if (this.ctsClear) {
+            this.transmitCb?.(u8(value));
+        }
+    }
+    reset() {
+        this.masterReset();
+        this.controlReg = 0;
+        // cts/dcd inputs and transmitCb survive reset — they are host wiring.
+    }
+    /**
+     * Feed a received byte to the ACIA. Sets RDRF; a byte arriving while the
+     * previous one has not been read flags an overrun (OVRN).
+     */
+    enqueueRx(byte) {
+        if (this.rxQueue.length > 0) {
+            this.errorFlags |= 0x02; // OVRN
+        }
+        this.rxQueue.push(u8(byte));
+    }
+    onTransmit(cb) {
+        this.transmitCb = cb;
+    }
+    /** Drive the CTS input: true = clear to send (grounded), false = inhibited. */
+    setCts(clear) {
+        this.ctsClear = clear;
+    }
+    /** Drive the DCD input: true = carrier present (grounded), false = lost. */
+    setDcd(carrierPresent) {
+        this.carrierPresent = carrierPresent;
+    }
+    /** Inject receive error flags (framing / overrun / parity) for the next read. */
+    setErrors(fe, ovrn, pe) {
+        this.errorFlags = (fe ? 0x01 : 0) | (ovrn ? 0x02 : 0) | (pe ? 0x04 : 0);
+    }
+    /** Last value written to the control register. */
+    get control() {
+        return this.controlReg;
+    }
+    writeControl(value) {
+        this.controlReg = value;
+        if ((value & 0x03) === 0x03) {
+            this.masterReset();
+            return;
+        }
+        this.rxIntEnable = (value & 0x80) !== 0;
+        this.txIntEnable = (value & 0x60) === 0x20; // bits 6-5 == 01
+    }
+    masterReset() {
+        this.rxQueue = [];
+        this.errorFlags = 0;
+        this.rxIntEnable = false;
+        this.txIntEnable = false;
+    }
+    buildStatus() {
+        const rdrf = this.rxQueue.length > 0 && this.carrierPresent ? 0x01 : 0;
+        const tdre = this.ctsClear ? 0x02 : 0;
+        const dcd = this.carrierPresent ? 0 : 0x04;
+        const cts = this.ctsClear ? 0 : 0x08;
+        const errs = (this.errorFlags & 0x07) << 4; // FE=bit4, OVRN=bit5, PE=bit6
+        const irq = (this.rxIntEnable && rdrf !== 0) || (this.txIntEnable && tdre !== 0) ? 0x80 : 0;
+        return rdrf | tdre | dcd | cts | errs | irq;
+    }
+}
+//# sourceMappingURL=Mc6850Acia.js.map