@joezilla/8sim 0.10.0

package/dist/cpu/instructions/alu.js.map

@@ -0,0 +1 @@
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package/dist/cpu/instructions/branch.d.ts

@@ -0,0 +1,3 @@
+import type { Decoder } from '../Decoder.js';
+export declare function registerBranch(decoder: Decoder): void;
+//# sourceMappingURL=branch.d.ts.map

package/dist/cpu/instructions/branch.d.ts.map

@@ -0,0 +1 @@
+{"version":3,"file":"branch.d.ts","sourceRoot":"","sources":["../../../src/cpu/instructions/branch.ts"],"names":[],"mappings":"AAAA,OAAO,KAAK,EAAE,OAAO,EAAE,MAAM,eAAe,CAAC;AAW7C,wBAAgB,cAAc,CAAC,OAAO,EAAE,OAAO,GAAG,IAAI,CAqHrD"}

package/dist/cpu/instructions/branch.js

@@ -0,0 +1,117 @@
+import { u16, toWord } from '../../util/bits.js';
+function readAddr(regs, bus) {
+    const lo = bus.read(regs.pc);
+    const hi = bus.read(u16(regs.pc + 1));
+    regs.pc = u16(regs.pc + 2);
+    return toWord(hi, lo);
+}
+export function registerBranch(decoder) {
+    // JMP addr (0xC3) — unconditional
+    decoder.register(0xc3, (regs, _flags, bus) => {
+        regs.pc = readAddr(regs, bus);
+        return 10;
+    });
+    // Conditional JMPs
+    const jccTable = [
+        [0xc2, f => !f.z], // JNZ
+        [0xca, f => f.z], // JZ
+        [0xd2, f => !f.cy], // JNC
+        [0xda, f => f.cy], // JC
+        [0xe2, f => !f.p], // JPO (parity odd)
+        [0xea, f => f.p], // JPE (parity even)
+        [0xf2, f => !f.s], // JP (positive)
+        [0xfa, f => f.s], // JM (minus)
+    ];
+    for (const [opcode, cond] of jccTable) {
+        decoder.register(opcode, (regs, flags, bus) => {
+            const addr = readAddr(regs, bus);
+            if (cond(flags))
+                regs.pc = addr;
+            return 10;
+        });
+    }
+    // CALL addr (0xCD)
+    decoder.register(0xcd, (regs, _flags, bus) => {
+        const addr = readAddr(regs, bus);
+        regs.sp = u16(regs.sp - 1);
+        bus.write(regs.sp, (regs.pc >> 8) & 0xff);
+        regs.sp = u16(regs.sp - 1);
+        bus.write(regs.sp, regs.pc & 0xff);
+        regs.pc = addr;
+        return 17;
+    });
+    // Conditional CALLs
+    const callTable = [
+        [0xc4, f => !f.z], // CNZ
+        [0xcc, f => f.z], // CZ
+        [0xd4, f => !f.cy], // CNC
+        [0xdc, f => f.cy], // CC
+        [0xe4, f => !f.p], // CPO
+        [0xec, f => f.p], // CPE
+        [0xf4, f => !f.s], // CP
+        [0xfc, f => f.s], // CM
+    ];
+    for (const [opcode, cond] of callTable) {
+        decoder.register(opcode, (regs, flags, bus) => {
+            const addr = readAddr(regs, bus);
+            if (cond(flags)) {
+                regs.sp = u16(regs.sp - 1);
+                bus.write(regs.sp, (regs.pc >> 8) & 0xff);
+                regs.sp = u16(regs.sp - 1);
+                bus.write(regs.sp, regs.pc & 0xff);
+                regs.pc = addr;
+                return 17;
+            }
+            return 11;
+        });
+    }
+    // RET (0xC9)
+    decoder.register(0xc9, (regs, _flags, bus) => {
+        const lo = bus.read(regs.sp);
+        const hi = bus.read(u16(regs.sp + 1));
+        regs.sp = u16(regs.sp + 2);
+        regs.pc = toWord(hi, lo);
+        return 10;
+    });
+    // Conditional RETs
+    const retTable = [
+        [0xc0, f => !f.z], // RNZ
+        [0xc8, f => f.z], // RZ
+        [0xd0, f => !f.cy], // RNC
+        [0xd8, f => f.cy], // RC
+        [0xe0, f => !f.p], // RPO
+        [0xe8, f => f.p], // RPE
+        [0xf0, f => !f.s], // RP
+        [0xf8, f => f.s], // RM
+    ];
+    for (const [opcode, cond] of retTable) {
+        decoder.register(opcode, (regs, flags, bus) => {
+            if (cond(flags)) {
+                const lo = bus.read(regs.sp);
+                const hi = bus.read(u16(regs.sp + 1));
+                regs.sp = u16(regs.sp + 2);
+                regs.pc = toWord(hi, lo);
+                return 11;
+            }
+            return 5;
+        });
+    }
+    // RST 0..7 (0xC7, 0xCF, 0xD7, 0xDF, 0xE7, 0xEF, 0xF7, 0xFF)
+    for (let n = 0; n < 8; n++) {
+        const opcode = 0xc7 | (n << 3);
+        decoder.register(opcode, (regs, _flags, bus) => {
+            regs.sp = u16(regs.sp - 1);
+            bus.write(regs.sp, (regs.pc >> 8) & 0xff);
+            regs.sp = u16(regs.sp - 1);
+            bus.write(regs.sp, regs.pc & 0xff);
+            regs.pc = n * 8;
+            return 11;
+        });
+    }
+    // PCHL (0xE9) — Jump to HL
+    decoder.register(0xe9, (regs, _flags, _bus) => {
+        regs.pc = regs.hl;
+        return 5;
+    });
+}
+//# sourceMappingURL=branch.js.map

package/dist/cpu/instructions/branch.js.map

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package/dist/cpu/instructions/control.d.ts

@@ -0,0 +1,3 @@
+import type { Decoder } from '../Decoder.js';
+export declare function registerControl(decoder: Decoder): void;
+//# sourceMappingURL=control.d.ts.map

package/dist/cpu/instructions/control.d.ts.map

@@ -0,0 +1 @@
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package/dist/cpu/instructions/control.js

@@ -0,0 +1,12 @@
+export function registerControl(decoder) {
+    // NOP
+    decoder.register(0x00, (_regs, _flags, _bus) => 4);
+    // HLT — CPU halts; handled specially in Cpu8080.step(), but we register it
+    // The Cpu8080 checks for HLT before decoding so this is a fallback
+    decoder.register(0x76, (_regs, _flags, _bus) => 7);
+    // EI — handled in Cpu8080.step() via pendingEI flag
+    decoder.register(0xfb, (_regs, _flags, _bus) => 4);
+    // DI — handled in Cpu8080.step()
+    decoder.register(0xf3, (_regs, _flags, _bus) => 4);
+}
+//# sourceMappingURL=control.js.map

package/dist/cpu/instructions/control.js.map

@@ -0,0 +1 @@
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package/dist/cpu/instructions/data.d.ts

@@ -0,0 +1,3 @@
+import type { Decoder } from '../Decoder.js';
+export declare function registerData(decoder: Decoder): void;
+//# sourceMappingURL=data.d.ts.map

package/dist/cpu/instructions/data.d.ts.map

@@ -0,0 +1 @@
+{"version":3,"file":"data.d.ts","sourceRoot":"","sources":["../../../src/cpu/instructions/data.ts"],"names":[],"mappings":"AAAA,OAAO,KAAK,EAAE,OAAO,EAAE,MAAM,eAAe,CAAC;AAmB7C,wBAAgB,YAAY,CAAC,OAAO,EAAE,OAAO,GAAG,IAAI,CAsInD"}

package/dist/cpu/instructions/data.js

@@ -0,0 +1,137 @@
+import { u8, u16, toWord } from '../../util/bits.js';
+const REG_ORDER = ['b', 'c', 'd', 'e', 'h', 'l', 'M', 'a'];
+function getReg(regs, r, bus) {
+    if (r === 'M')
+        return bus.read(regs.hl);
+    return regs[r];
+}
+function setReg(regs, r, val, bus) {
+    if (r === 'M') {
+        bus.write(regs.hl, u8(val));
+        return;
+    }
+    regs[r] = u8(val);
+}
+export function registerData(decoder) {
+    // MOV r1, r2 (0x40..0x7F, except 0x76 which is HLT)
+    for (let dst = 0; dst < 8; dst++) {
+        for (let src = 0; src < 8; src++) {
+            const opcode = 0x40 | (dst << 3) | src;
+            if (opcode === 0x76)
+                continue; // HLT
+            const dstReg = REG_ORDER[dst];
+            const srcReg = REG_ORDER[src];
+            const cycles = (dstReg === 'M' || srcReg === 'M') ? 7 : 5;
+            decoder.register(opcode, (regs, _flags, bus) => {
+                const val = getReg(regs, srcReg, bus);
+                setReg(regs, dstReg, val, bus);
+                return cycles;
+            });
+        }
+    }
+    // MVI r, d8 (0x06, 0x0E, 0x16, 0x1E, 0x26, 0x2E, 0x36, 0x3E)
+    for (let r = 0; r < 8; r++) {
+        const opcode = 0x06 | (r << 3);
+        const reg = REG_ORDER[r];
+        const cycles = reg === 'M' ? 10 : 7;
+        decoder.register(opcode, (regs, _flags, bus) => {
+            const imm = bus.read(regs.pc);
+            regs.pc = u16(regs.pc + 1);
+            setReg(regs, reg, imm, bus);
+            return cycles;
+        });
+    }
+    // LXI B, d16 (0x01)
+    decoder.register(0x01, (regs, _flags, bus) => {
+        regs.c = bus.read(regs.pc);
+        regs.b = bus.read(u16(regs.pc + 1));
+        regs.pc = u16(regs.pc + 2);
+        return 10;
+    });
+    // LXI D, d16 (0x11)
+    decoder.register(0x11, (regs, _flags, bus) => {
+        regs.e = bus.read(regs.pc);
+        regs.d = bus.read(u16(regs.pc + 1));
+        regs.pc = u16(regs.pc + 2);
+        return 10;
+    });
+    // LXI H, d16 (0x21)
+    decoder.register(0x21, (regs, _flags, bus) => {
+        regs.l = bus.read(regs.pc);
+        regs.h = bus.read(u16(regs.pc + 1));
+        regs.pc = u16(regs.pc + 2);
+        return 10;
+    });
+    // LXI SP, d16 (0x31)
+    decoder.register(0x31, (regs, _flags, bus) => {
+        const lo_ = bus.read(regs.pc);
+        const hi_ = bus.read(u16(regs.pc + 1));
+        regs.sp = u16(toWord(hi_, lo_));
+        regs.pc = u16(regs.pc + 2);
+        return 10;
+    });
+    // LDA addr (0x3A)
+    decoder.register(0x3a, (regs, _flags, bus) => {
+        const lo_ = bus.read(regs.pc);
+        const hi_ = bus.read(u16(regs.pc + 1));
+        regs.pc = u16(regs.pc + 2);
+        regs.a = bus.read(toWord(hi_, lo_));
+        return 13;
+    });
+    // STA addr (0x32)
+    decoder.register(0x32, (regs, _flags, bus) => {
+        const lo_ = bus.read(regs.pc);
+        const hi_ = bus.read(u16(regs.pc + 1));
+        regs.pc = u16(regs.pc + 2);
+        bus.write(toWord(hi_, lo_), regs.a);
+        return 13;
+    });
+    // LHLD addr (0x2A)
+    decoder.register(0x2a, (regs, _flags, bus) => {
+        const lo_ = bus.read(regs.pc);
+        const hi_ = bus.read(u16(regs.pc + 1));
+        regs.pc = u16(regs.pc + 2);
+        const addr = toWord(hi_, lo_);
+        regs.l = bus.read(addr);
+        regs.h = bus.read(u16(addr + 1));
+        return 16;
+    });
+    // SHLD addr (0x22)
+    decoder.register(0x22, (regs, _flags, bus) => {
+        const lo_ = bus.read(regs.pc);
+        const hi_ = bus.read(u16(regs.pc + 1));
+        regs.pc = u16(regs.pc + 2);
+        const addr = toWord(hi_, lo_);
+        bus.write(addr, regs.l);
+        bus.write(u16(addr + 1), regs.h);
+        return 16;
+    });
+    // LDAX B (0x0A)
+    decoder.register(0x0a, (regs, _flags, bus) => {
+        regs.a = bus.read(regs.bc);
+        return 7;
+    });
+    // LDAX D (0x1A)
+    decoder.register(0x1a, (regs, _flags, bus) => {
+        regs.a = bus.read(regs.de);
+        return 7;
+    });
+    // STAX B (0x02)
+    decoder.register(0x02, (regs, _flags, bus) => {
+        bus.write(regs.bc, regs.a);
+        return 7;
+    });
+    // STAX D (0x12)
+    decoder.register(0x12, (regs, _flags, bus) => {
+        bus.write(regs.de, regs.a);
+        return 7;
+    });
+    // XCHG (0xEB) — exchange HL and DE
+    decoder.register(0xeb, (regs, _flags, _bus) => {
+        const tmp = regs.hl;
+        regs.hl = regs.de;
+        regs.de = tmp;
+        return 5;
+    });
+}
+//# sourceMappingURL=data.js.map

package/dist/cpu/instructions/data.js.map

@@ -0,0 +1 @@
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package/dist/cpu/instructions/io.d.ts

@@ -0,0 +1,3 @@
+import type { Decoder } from '../Decoder.js';
+export declare function registerIO(decoder: Decoder): void;
+//# sourceMappingURL=io.d.ts.map

package/dist/cpu/instructions/io.d.ts.map

@@ -0,0 +1 @@
+{"version":3,"file":"io.d.ts","sourceRoot":"","sources":["../../../src/cpu/instructions/io.ts"],"names":[],"mappings":"AAAA,OAAO,KAAK,EAAE,OAAO,EAAE,MAAM,eAAe,CAAC;AAG7C,wBAAgB,UAAU,CAAC,OAAO,EAAE,OAAO,GAAG,IAAI,CAgBjD"}

package/dist/cpu/instructions/io.js

@@ -0,0 +1,18 @@
+import { u16 } from '../../util/bits.js';
+export function registerIO(decoder) {
+    // IN port (0xDB)
+    decoder.register(0xdb, (regs, _flags, bus) => {
+        const port = bus.read(regs.pc);
+        regs.pc = u16(regs.pc + 1);
+        regs.a = bus.ioRead(port);
+        return 10;
+    });
+    // OUT port (0xD3)
+    decoder.register(0xd3, (regs, _flags, bus) => {
+        const port = bus.read(regs.pc);
+        regs.pc = u16(regs.pc + 1);
+        bus.ioWrite(port, regs.a);
+        return 10;
+    });
+}
+//# sourceMappingURL=io.js.map

package/dist/cpu/instructions/io.js.map

@@ -0,0 +1 @@
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package/dist/cpu/instructions/logical.d.ts

@@ -0,0 +1,3 @@
+import type { Decoder } from '../Decoder.js';
+export declare function registerLogical(decoder: Decoder): void;
+//# sourceMappingURL=logical.d.ts.map

package/dist/cpu/instructions/logical.d.ts.map

@@ -0,0 +1 @@
+{"version":3,"file":"logical.d.ts","sourceRoot":"","sources":["../../../src/cpu/instructions/logical.ts"],"names":[],"mappings":"AAAA,OAAO,KAAK,EAAE,OAAO,EAAE,MAAM,eAAe,CAAC;AAsB7C,wBAAgB,eAAe,CAAC,OAAO,EAAE,OAAO,GAAG,IAAI,CA2HtD"}

package/dist/cpu/instructions/logical.js

@@ -0,0 +1,129 @@
+import { u8, u16, signBit, zeroFlag, parityFlag } from '../../util/bits.js';
+const REG_ORDER = ['b', 'c', 'd', 'e', 'h', 'l', 'M', 'a'];
+function getReg(regs, r, bus) {
+    if (r === 'M')
+        return bus.read(regs.hl);
+    return regs[r];
+}
+function setLogicFlags(flags, result) {
+    const r8 = u8(result);
+    flags.s = signBit(r8);
+    flags.z = zeroFlag(r8);
+    flags.p = parityFlag(r8);
+    flags.cy = false;
+}
+export function registerLogical(decoder) {
+    // ANA r / ANA M (0xA0..0xA7)
+    for (let r = 0; r < 8; r++) {
+        const opcode = 0xa0 | r;
+        const reg = REG_ORDER[r];
+        const cycles = reg === 'M' ? 7 : 4;
+        decoder.register(opcode, (regs, flags, bus) => {
+            const result = regs.a & getReg(regs, reg, bus);
+            flags.ac = ((regs.a | getReg(regs, reg, bus)) & 0x08) !== 0;
+            setLogicFlags(flags, result);
+            regs.a = u8(result);
+            return cycles;
+        });
+    }
+    // ANI d8 (0xE6)
+    decoder.register(0xe6, (regs, flags, bus) => {
+        const imm = bus.read(regs.pc);
+        regs.pc = u16(regs.pc + 1);
+        flags.ac = ((regs.a | imm) & 0x08) !== 0;
+        const result = regs.a & imm;
+        setLogicFlags(flags, result);
+        regs.a = u8(result);
+        return 7;
+    });
+    // ORA r / ORA M (0xB0..0xB7)
+    for (let r = 0; r < 8; r++) {
+        const opcode = 0xb0 | r;
+        const reg = REG_ORDER[r];
+        const cycles = reg === 'M' ? 7 : 4;
+        decoder.register(opcode, (regs, flags, bus) => {
+            const result = regs.a | getReg(regs, reg, bus);
+            flags.ac = false;
+            setLogicFlags(flags, result);
+            regs.a = u8(result);
+            return cycles;
+        });
+    }
+    // ORI d8 (0xF6)
+    decoder.register(0xf6, (regs, flags, bus) => {
+        const imm = bus.read(regs.pc);
+        regs.pc = u16(regs.pc + 1);
+        flags.ac = false;
+        const result = regs.a | imm;
+        setLogicFlags(flags, result);
+        regs.a = u8(result);
+        return 7;
+    });
+    // XRA r / XRA M (0xA8..0xAF)
+    for (let r = 0; r < 8; r++) {
+        const opcode = 0xa8 | r;
+        const reg = REG_ORDER[r];
+        const cycles = reg === 'M' ? 7 : 4;
+        decoder.register(opcode, (regs, flags, bus) => {
+            const result = regs.a ^ getReg(regs, reg, bus);
+            flags.ac = false;
+            setLogicFlags(flags, result);
+            regs.a = u8(result);
+            return cycles;
+        });
+    }
+    // XRI d8 (0xEE)
+    decoder.register(0xee, (regs, flags, bus) => {
+        const imm = bus.read(regs.pc);
+        regs.pc = u16(regs.pc + 1);
+        flags.ac = false;
+        const result = regs.a ^ imm;
+        setLogicFlags(flags, result);
+        regs.a = u8(result);
+        return 7;
+    });
+    // CMP r / CMP M (0xB8..0xBF)
+    for (let r = 0; r < 8; r++) {
+        const opcode = 0xb8 | r;
+        const reg = REG_ORDER[r];
+        const cycles = reg === 'M' ? 7 : 4;
+        decoder.register(opcode, (regs, flags, bus) => {
+            const a = regs.a;
+            const b = getReg(regs, reg, bus);
+            const result = a - b;
+            flags.cy = result < 0;
+            flags.ac = ((a & 0xf) - (b & 0xf)) < 0;
+            setLogicFlags(flags, result);
+            flags.cy = a < b;
+            return cycles;
+        });
+    }
+    // CPI d8 (0xFE)
+    decoder.register(0xfe, (regs, flags, bus) => {
+        const a = regs.a;
+        const b = bus.read(regs.pc);
+        regs.pc = u16(regs.pc + 1);
+        const result = a - b;
+        flags.cy = a < b;
+        flags.ac = ((a & 0xf) - (b & 0xf)) < 0;
+        setLogicFlags(flags, result);
+        flags.cy = a < b;
+        return 7;
+    });
+    // CMA (0x2F) — Complement A
+    decoder.register(0x2f, (regs, _flags, _bus) => {
+        regs.a = u8(~regs.a);
+        return 4;
+    });
+    // CMC (0x3F) — Complement Carry
+    decoder.register(0x3f, (_regs, flags, _bus) => {
+        flags.cy = !flags.cy;
+        return 4;
+    });
+    // STC (0x37) — Set Carry
+    decoder.register(0x37, (_regs, flags, _bus) => {
+        flags.cy = true;
+        return 4;
+    });
+}
+//# sourceMappingURL=logical.js.map

package/dist/cpu/instructions/logical.js.map

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package/dist/cpu/instructions/rotate.d.ts

@@ -0,0 +1,3 @@
+import type { Decoder } from '../Decoder.js';
+export declare function registerRotate(decoder: Decoder): void;
+//# sourceMappingURL=rotate.d.ts.map

package/dist/cpu/instructions/rotate.d.ts.map

@@ -0,0 +1 @@
+{"version":3,"file":"rotate.d.ts","sourceRoot":"","sources":["../../../src/cpu/instructions/rotate.ts"],"names":[],"mappings":"AAAA,OAAO,KAAK,EAAE,OAAO,EAAE,MAAM,eAAe,CAAC;AAG7C,wBAAgB,cAAc,CAAC,OAAO,EAAE,OAAO,GAAG,IAAI,CAkCrD"}

package/dist/cpu/instructions/rotate.js

@@ -0,0 +1,34 @@
+import { u8 } from '../../util/bits.js';
+export function registerRotate(decoder) {
+    // RLC (0x07) — Rotate A left; CY = bit7
+    decoder.register(0x07, (regs, flags, _bus) => {
+        const a = regs.a;
+        flags.cy = (a & 0x80) !== 0;
+        regs.a = u8((a << 1) | (flags.cy ? 1 : 0));
+        return 4;
+    });
+    // RRC (0x0F) — Rotate A right; CY = bit0
+    decoder.register(0x0f, (regs, flags, _bus) => {
+        const a = regs.a;
+        flags.cy = (a & 0x01) !== 0;
+        regs.a = u8((a >> 1) | (flags.cy ? 0x80 : 0));
+        return 4;
+    });
+    // RAL (0x17) — Rotate A left through carry
+    decoder.register(0x17, (regs, flags, _bus) => {
+        const a = regs.a;
+        const newCY = (a & 0x80) !== 0;
+        regs.a = u8((a << 1) | (flags.cy ? 1 : 0));
+        flags.cy = newCY;
+        return 4;
+    });
+    // RAR (0x1F) — Rotate A right through carry
+    decoder.register(0x1f, (regs, flags, _bus) => {
+        const a = regs.a;
+        const newCY = (a & 0x01) !== 0;
+        regs.a = u8((a >> 1) | (flags.cy ? 0x80 : 0));
+        flags.cy = newCY;
+        return 4;
+    });
+}
+//# sourceMappingURL=rotate.js.map

package/dist/cpu/instructions/rotate.js.map

@@ -0,0 +1 @@
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package/dist/cpu/instructions/stack.d.ts

@@ -0,0 +1,3 @@
+import type { Decoder } from '../Decoder.js';
+export declare function registerStack(decoder: Decoder): void;
+//# sourceMappingURL=stack.d.ts.map

package/dist/cpu/instructions/stack.d.ts.map

@@ -0,0 +1 @@
+{"version":3,"file":"stack.d.ts","sourceRoot":"","sources":["../../../src/cpu/instructions/stack.ts"],"names":[],"mappings":"AAAA,OAAO,KAAK,EAAE,OAAO,EAAE,MAAM,eAAe,CAAC;AAG7C,wBAAgB,aAAa,CAAC,OAAO,EAAE,OAAO,GAAG,IAAI,CA0EpD"}