wasmtime 21.0.1 → 22.0.0
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- checksums.yaml +4 -4
- data/Cargo.lock +80 -87
- data/ext/Cargo.toml +4 -4
- data/ext/cargo-vendor/cranelift-bforest-0.109.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-bforest-0.109.0/Cargo.toml +41 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/Cargo.toml +193 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/context.rs +384 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/dominator_tree.rs +727 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/egraph.rs +835 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/inst_predicates.rs +230 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/ir/dfg.rs +1777 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/ir/extfunc.rs +402 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/ir/immediates.rs +1612 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/ir/stackslot.rs +208 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/ir/types.rs +627 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/aarch64/abi.rs +1556 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/aarch64/inst/args.rs +711 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/aarch64/inst/emit.rs +3584 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/aarch64/inst/emit_tests.rs +7901 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/aarch64/inst/imms.rs +1213 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/aarch64/inst/mod.rs +3060 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/aarch64/inst/regs.rs +269 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/aarch64/inst/unwind/systemv.rs +174 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/aarch64/inst.isle +4218 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/aarch64/pcc.rs +568 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/riscv64/abi.rs +1029 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/riscv64/inst/args.rs +2054 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/riscv64/inst/emit.rs +2682 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/riscv64/inst/emit_tests.rs +2215 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/riscv64/inst/encode.rs +675 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/riscv64/inst/imms.rs +374 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/riscv64/inst/mod.rs +1938 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/riscv64/inst/unwind/systemv.rs +170 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/riscv64/inst/vector.rs +1150 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/riscv64/inst.isle +3127 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/riscv64/inst_vector.isle +1907 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/riscv64/lower/isle.rs +649 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/riscv64/lower.isle +2923 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/riscv64/mod.rs +260 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/s390x/abi.rs +1016 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/s390x/inst/args.rs +298 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/s390x/inst/emit.rs +3401 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/s390x/inst/emit_tests.rs +13388 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/s390x/inst/imms.rs +202 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/s390x/inst/mod.rs +3401 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/s390x/inst/regs.rs +169 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/s390x/inst/unwind/systemv.rs +212 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/s390x/inst.isle +5028 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/s390x/lower.isle +3995 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/x64/abi.rs +1390 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/x64/inst/args.rs +2240 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/x64/inst/emit.rs +4287 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/x64/inst/emit_state.rs +52 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/x64/inst/emit_tests.rs +5171 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/x64/inst/mod.rs +2821 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/x64/inst/regs.rs +275 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/x64/inst/unwind/systemv.rs +198 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/x64/inst.isle +5289 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/x64/lower.isle +4810 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/x64/pcc.rs +1014 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isle_prelude.rs +986 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/lib.rs +106 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/machinst/abi.rs +2419 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/machinst/blockorder.rs +465 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/machinst/buffer.rs +2508 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/machinst/isle.rs +909 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/machinst/lower.rs +1432 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/machinst/mod.rs +551 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/machinst/reg.rs +479 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/machinst/valueregs.rs +138 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/machinst/vcode.rs +1741 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/opts/cprop.isle +297 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/opts/shifts.isle +307 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/prelude.isle +664 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/prelude_lower.isle +1073 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/timing.rs +296 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/traversals.rs +216 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/verifier/mod.rs +1957 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/write.rs +638 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.109.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.109.0/Cargo.toml +36 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.109.0/src/cdsl/types.rs +496 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.109.0/src/isa/riscv64.rs +174 -0
- data/ext/cargo-vendor/cranelift-codegen-shared-0.109.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-codegen-shared-0.109.0/Cargo.toml +22 -0
- data/ext/cargo-vendor/cranelift-codegen-shared-0.109.0/src/constants.rs +28 -0
- data/ext/cargo-vendor/cranelift-control-0.109.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-control-0.109.0/Cargo.toml +30 -0
- data/ext/cargo-vendor/cranelift-entity-0.109.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-entity-0.109.0/Cargo.toml +53 -0
- data/ext/cargo-vendor/cranelift-entity-0.109.0/src/set.rs +290 -0
- data/ext/cargo-vendor/cranelift-frontend-0.109.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-frontend-0.109.0/Cargo.toml +68 -0
- data/ext/cargo-vendor/cranelift-frontend-0.109.0/src/frontend.rs +1857 -0
- data/ext/cargo-vendor/cranelift-frontend-0.109.0/src/lib.rs +187 -0
- data/ext/cargo-vendor/cranelift-frontend-0.109.0/src/ssa.rs +1328 -0
- data/ext/cargo-vendor/cranelift-isle-0.109.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-isle-0.109.0/Cargo.toml +47 -0
- data/ext/cargo-vendor/cranelift-isle-0.109.0/src/sema.rs +2492 -0
- data/ext/cargo-vendor/cranelift-native-0.109.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-native-0.109.0/Cargo.toml +43 -0
- data/ext/cargo-vendor/cranelift-native-0.109.0/src/lib.rs +188 -0
- data/ext/cargo-vendor/cranelift-native-0.109.0/src/riscv.rs +128 -0
- data/ext/cargo-vendor/cranelift-wasm-0.109.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-wasm-0.109.0/Cargo.toml +110 -0
- data/ext/cargo-vendor/cranelift-wasm-0.109.0/src/code_translator.rs +3695 -0
- data/ext/cargo-vendor/cranelift-wasm-0.109.0/src/func_translator.rs +296 -0
- data/ext/cargo-vendor/cranelift-wasm-0.109.0/src/module_translator.rs +120 -0
- data/ext/cargo-vendor/cranelift-wasm-0.109.0/src/sections_translator.rs +343 -0
- data/ext/cargo-vendor/cranelift-wasm-0.109.0/src/state.rs +522 -0
- data/ext/cargo-vendor/object-0.36.3/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/object-0.36.3/CHANGELOG.md +1028 -0
- data/ext/cargo-vendor/object-0.36.3/Cargo.toml +180 -0
- data/ext/cargo-vendor/object-0.36.3/README.md +60 -0
- data/ext/cargo-vendor/object-0.36.3/src/build/bytes.rs +146 -0
- data/ext/cargo-vendor/object-0.36.3/src/build/elf.rs +3113 -0
- data/ext/cargo-vendor/object-0.36.3/src/common.rs +590 -0
- data/ext/cargo-vendor/object-0.36.3/src/elf.rs +6303 -0
- data/ext/cargo-vendor/object-0.36.3/src/endian.rs +831 -0
- data/ext/cargo-vendor/object-0.36.3/src/macho.rs +3303 -0
- data/ext/cargo-vendor/object-0.36.3/src/pod.rs +281 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/any.rs +1334 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/archive.rs +1133 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/coff/comdat.rs +220 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/coff/file.rs +381 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/coff/relocation.rs +113 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/coff/section.rs +619 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/coff/symbol.rs +669 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/elf/attributes.rs +340 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/elf/comdat.rs +186 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/elf/file.rs +959 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/elf/hash.rs +236 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/elf/note.rs +302 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/elf/relocation.rs +661 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/elf/section.rs +1241 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/elf/segment.rs +365 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/elf/symbol.rs +654 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/elf/version.rs +513 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/gnu_compression.rs +36 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/macho/dyld_cache.rs +384 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/macho/file.rs +779 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/macho/load_command.rs +404 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/macho/section.rs +420 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/macho/segment.rs +317 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/macho/symbol.rs +532 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/mod.rs +1018 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/pe/file.rs +1033 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/pe/import.rs +381 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/pe/relocation.rs +109 -0
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- data/ext/cargo-vendor/object-0.36.3/src/read/read_cache.rs +261 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/traits.rs +589 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/wasm.rs +983 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/xcoff/file.rs +716 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/xcoff/relocation.rs +138 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/xcoff/section.rs +452 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/xcoff/symbol.rs +836 -0
- data/ext/cargo-vendor/object-0.36.3/src/write/coff/object.rs +681 -0
- data/ext/cargo-vendor/object-0.36.3/src/write/coff/writer.rs +520 -0
- data/ext/cargo-vendor/object-0.36.3/src/write/elf/object.rs +897 -0
- data/ext/cargo-vendor/object-0.36.3/src/write/elf/writer.rs +2361 -0
- data/ext/cargo-vendor/object-0.36.3/src/write/macho.rs +1124 -0
- data/ext/cargo-vendor/object-0.36.3/src/write/mod.rs +1023 -0
- data/ext/cargo-vendor/object-0.36.3/src/write/pe.rs +849 -0
- data/ext/cargo-vendor/object-0.36.3/src/write/xcoff.rs +588 -0
- data/ext/cargo-vendor/object-0.36.3/tests/build/elf.rs +254 -0
- data/ext/cargo-vendor/object-0.36.3/tests/build/mod.rs +3 -0
- data/ext/cargo-vendor/object-0.36.3/tests/integration.rs +3 -0
- data/ext/cargo-vendor/object-0.36.3/tests/read/macho.rs +49 -0
- data/ext/cargo-vendor/object-0.36.3/tests/read/mod.rs +5 -0
- data/ext/cargo-vendor/object-0.36.3/tests/round_trip/bss.rs +244 -0
- data/ext/cargo-vendor/object-0.36.3/tests/round_trip/comdat.rs +217 -0
- data/ext/cargo-vendor/object-0.36.3/tests/round_trip/common.rs +241 -0
- data/ext/cargo-vendor/object-0.36.3/tests/round_trip/elf.rs +302 -0
- data/ext/cargo-vendor/object-0.36.3/tests/round_trip/mod.rs +682 -0
- data/ext/cargo-vendor/object-0.36.3/tests/round_trip/section_flags.rs +89 -0
- data/ext/cargo-vendor/object-0.36.3/tests/round_trip/tls.rs +308 -0
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- data/ext/cargo-vendor/wasi-common-22.0.0/src/snapshots/preview_0.rs +1080 -0
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- data/ext/cargo-vendor/wasi-common-22.0.0/src/string_array.rs +75 -0
- data/ext/cargo-vendor/wasi-common-22.0.0/src/sync/sched/windows.rs +221 -0
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- /data/ext/cargo-vendor/{wit-parser-0.207.0 → wit-parser-0.209.1}/tests/ui/wasi.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.207.0 → wit-parser-0.209.1}/tests/ui/wasi.wit.json +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.207.0 → wit-parser-0.209.1}/tests/ui/world-diamond.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.207.0 → wit-parser-0.209.1}/tests/ui/world-iface-no-collide.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.207.0 → wit-parser-0.209.1}/tests/ui/world-implicit-import1.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.207.0 → wit-parser-0.209.1}/tests/ui/world-implicit-import2.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.207.0 → wit-parser-0.209.1}/tests/ui/world-implicit-import3.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.207.0 → wit-parser-0.209.1}/tests/ui/world-same-fields4.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.207.0 → wit-parser-0.209.1}/tests/ui/world-top-level-funcs.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.207.0 → wit-parser-0.209.1}/tests/ui/world-top-level-funcs.wit.json +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.207.0 → wit-parser-0.209.1}/tests/ui/world-top-level-resources.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.207.0 → wit-parser-0.209.1}/tests/ui/worlds-union-dedup.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.207.0 → wit-parser-0.209.1}/tests/ui/worlds-with-types.wit +0 -0
@@ -1,258 +0,0 @@
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use crate::{
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abi::{align_to, ABIOperand, ABISig, LocalSlot, ABI},
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masm::MacroAssembler,
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};
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use anyhow::Result;
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use smallvec::SmallVec;
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use std::ops::Range;
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use wasmparser::{BinaryReader, FuncValidator, ValidatorResources};
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use wasmtime_environ::{TypeConvert, WasmValType};
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// TODO:
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// SpiderMonkey's implementation uses 16;
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// (ref: https://searchfox.org/mozilla-central/source/js/src/wasm/WasmBCFrame.h#585)
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// during instrumentation we should measure to verify if this is a good default.
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pub(crate) type Locals = SmallVec<[LocalSlot; 16]>;
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/// Function defined locals start and end in the frame.
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pub(crate) struct DefinedLocalsRange(Range<u32>);
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impl DefinedLocalsRange {
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/// Get a reference to the inner range.
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pub fn as_range(&self) -> &Range<u32> {
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&self.0
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}
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}
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/// An abstraction to read the defined locals from the Wasm binary for a function.
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#[derive(Default)]
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pub(crate) struct DefinedLocals {
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/// The defined locals for a function.
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pub defined_locals: Locals,
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/// The size of the defined locals.
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pub stack_size: u32,
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}
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impl DefinedLocals {
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/// Compute the local slots for a Wasm function.
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pub fn new<A: ABI>(
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types: &impl TypeConvert,
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reader: &mut BinaryReader<'_>,
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validator: &mut FuncValidator<ValidatorResources>,
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) -> Result<Self> {
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let mut next_stack: u32 = 0;
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// The first 32 bits of a Wasm binary function describe the number of locals.
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let local_count = reader.read_var_u32()?;
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let mut slots: Locals = Default::default();
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for _ in 0..local_count {
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let position = reader.original_position();
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let count = reader.read_var_u32()?;
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let ty = reader.read()?;
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validator.define_locals(position, count, ty)?;
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let ty = types.convert_valtype(ty);
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for _ in 0..count {
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let ty_size = <A as ABI>::sizeof(&ty);
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next_stack = align_to(next_stack, ty_size as u32) + (ty_size as u32);
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slots.push(LocalSlot::new(ty, next_stack));
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}
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}
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Ok(Self {
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defined_locals: slots,
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stack_size: next_stack,
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})
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}
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}
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/// Frame handler abstraction.
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pub(crate) struct Frame {
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/// The size of the entire local area; the arguments plus the function defined locals.
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pub locals_size: u32,
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/// The range in the frame corresponding to the defined locals range.
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pub defined_locals_range: DefinedLocalsRange,
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/// The local slots for the current function.
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///
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/// Locals get calculated when allocating a frame and are readonly
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/// through the function compilation lifetime.
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locals: Locals,
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/// The offset to the slot containing the `VMContext`.
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pub vmctx_slot: LocalSlot,
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/// The slot holding the address of the results area.
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pub results_base_slot: Option<LocalSlot>,
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}
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impl Frame {
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/// Allocate a new [`Frame`].
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pub fn new<A: ABI>(sig: &ABISig, defined_locals: &DefinedLocals) -> Result<Self> {
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let (mut locals, defined_locals_start) = Self::compute_arg_slots::<A>(sig)?;
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// The defined locals have a zero-based offset by default
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// so we need to add the defined locals start to the offset.
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locals.extend(
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defined_locals
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.defined_locals
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.iter()
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.map(|l| LocalSlot::new(l.ty, l.offset + defined_locals_start)),
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);
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let stack_align = <A as ABI>::stack_align();
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let defined_locals_end = align_to(
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defined_locals_start + defined_locals.stack_size,
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stack_align as u32,
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);
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// Handle the results base slot for multi value returns.
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let (results_base_slot, locals_size) = if sig.params.has_retptr() {
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match sig.params.unwrap_results_area_operand() {
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// If the results operand is a stack argument, ensure the
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// offset is correctly calculated, that is, that it includes the
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// argument base offset.
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// In this case, the locals size, remains untouched as we don't
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// need to create an extra slot for it.
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ABIOperand::Stack { ty, offset, .. } => (
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Some(LocalSlot::stack_arg(
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*ty,
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*offset + (<A as ABI>::arg_base_offset() as u32),
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)),
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defined_locals_end,
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),
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// If the resuls operand is a register, we give this register
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// the same treatment as all the other argument registers and
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// spill it, therefore, we need to increase the locals size by
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// one slot.
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ABIOperand::Reg { ty, size, .. } => {
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let offs = align_to(defined_locals_end, *size) + *size;
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(
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Some(LocalSlot::new(*ty, offs)),
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align_to(offs, <A as ABI>::stack_align().into()),
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)
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}
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}
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} else {
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(None, defined_locals_end)
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};
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let vmctx_slot = *locals.get(0).expect("LocalSlot for VMContext");
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Ok(Self {
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locals,
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locals_size,
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vmctx_slot,
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defined_locals_range: DefinedLocalsRange(
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defined_locals_start..(defined_locals_start + defined_locals.stack_size),
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),
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results_base_slot,
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})
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}
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// Winch's ABI uses two extra parameters to store the callee and caller
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// VMContext pointers.
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// These arguments are spilled and treated as frame locals, but not
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// WebAssembly locals.
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const WASM_LOCALS_OFFSET: usize = 2;
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/// Get the [LocalSlot] for a WebAssembly local.
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/// This method assumes that the index is bound to u32::MAX, representing
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/// the index space for WebAssembly locals.
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///
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/// # Panics
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/// This method panics if the index is not associated to a valid WebAssembly
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/// local.
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pub fn get_wasm_local(&self, index: u32) -> &LocalSlot {
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let local_index = Self::WASM_LOCALS_OFFSET + index as usize;
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self.locals
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.get(local_index)
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.unwrap_or_else(|| panic!(" Expected WebAssembly local at slot: {index}"))
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}
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/// Get the [LocalSlot] for a frame local.
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/// This method doesn't make any asumptions about the local index passed in,
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/// and simply delegates the [LocalSlot] retrieval to the underlying locals
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/// vector.
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///
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/// # Panics
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/// This method panics if the index is not associated to a valid WebAssembly
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/// local.
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pub fn get_frame_local(&self, index: usize) -> &LocalSlot {
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self.locals
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.get(index)
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.unwrap_or_else(|| panic!(" Expected Frame local at slot: {index}"))
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}
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/// Returns the address of the local at the given index.
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///
|
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/// # Panics
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190
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/// This function panics if the the index is not associated to a local.
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191
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pub fn get_local_address<M: MacroAssembler>(
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192
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&self,
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193
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index: u32,
|
194
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masm: &mut M,
|
195
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) -> (WasmValType, M::Address) {
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196
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let slot = self.get_wasm_local(index);
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197
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(slot.ty, masm.local_address(&slot))
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198
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}
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199
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|
200
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fn compute_arg_slots<A: ABI>(sig: &ABISig) -> Result<(Locals, u32)> {
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201
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// Go over the function ABI-signature and
|
202
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// calculate the stack slots.
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203
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//
|
204
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// for each parameter p; when p
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205
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//
|
206
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// Stack =>
|
207
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// The slot offset is calculated from the ABIOperand offset
|
208
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// relative the to the frame pointer (and its inclusions, e.g.
|
209
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// return address).
|
210
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//
|
211
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// Register =>
|
212
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// The slot is calculated by accumulating into the `next_frame_size`
|
213
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// the size + alignment of the type that the register is holding.
|
214
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//
|
215
|
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// NOTE
|
216
|
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// This implementation takes inspiration from SpiderMonkey's implementation
|
217
|
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// to calculate local slots for function arguments
|
218
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// (https://searchfox.org/mozilla-central/source/js/src/wasm/WasmBCFrame.cpp#83).
|
219
|
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// The main difference is that SpiderMonkey's implementation
|
220
|
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// doesn't append any sort of metadata to the locals regarding stack
|
221
|
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// addressing mode (stack pointer or frame pointer), the offset is
|
222
|
-
// declared negative if the local belongs to a stack argument;
|
223
|
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// that's enough to later calculate address of the local later on.
|
224
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//
|
225
|
-
// Winch appends an addressing mode to each slot, in the end
|
226
|
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// we want positive addressing from the stack pointer
|
227
|
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// for both locals and stack arguments.
|
228
|
-
|
229
|
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let arg_base_offset = <A as ABI>::arg_base_offset().into();
|
230
|
-
let mut next_stack = 0u32;
|
231
|
-
|
232
|
-
// Skip the results base param; if present, the [Frame] will create
|
233
|
-
// a dedicated slot for it.
|
234
|
-
let slots: Locals = sig
|
235
|
-
.params_without_retptr()
|
236
|
-
.into_iter()
|
237
|
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.map(|arg| Self::abi_arg_slot(&arg, &mut next_stack, arg_base_offset))
|
238
|
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.collect();
|
239
|
-
|
240
|
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Ok((slots, next_stack))
|
241
|
-
}
|
242
|
-
|
243
|
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fn abi_arg_slot(arg: &ABIOperand, next_stack: &mut u32, arg_base_offset: u32) -> LocalSlot {
|
244
|
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match arg {
|
245
|
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// Create a local slot, for input register spilling,
|
246
|
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// with type-size aligned access.
|
247
|
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ABIOperand::Reg { ty, size, .. } => {
|
248
|
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*next_stack = align_to(*next_stack, *size) + *size;
|
249
|
-
LocalSlot::new(*ty, *next_stack)
|
250
|
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}
|
251
|
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// Create a local slot, with an offset from the arguments base in
|
252
|
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// the stack; which is the frame pointer + return address.
|
253
|
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ABIOperand::Stack { ty, offset, .. } => {
|
254
|
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LocalSlot::stack_arg(*ty, offset + arg_base_offset)
|
255
|
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}
|
256
|
-
}
|
257
|
-
}
|
258
|
-
}
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@@ -1,380 +0,0 @@
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1
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-
//! Assembler library implementation for Aarch64.
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2
|
-
|
3
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use super::{address::Address, regs};
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4
|
-
use crate::masm::RoundingMode;
|
5
|
-
use crate::{masm::OperandSize, reg::Reg};
|
6
|
-
use cranelift_codegen::isa::aarch64::inst::{FPUOp1, FPUOp2, FpuRoundMode, ScalarSize};
|
7
|
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use cranelift_codegen::{
|
8
|
-
ir::{MemFlags, SourceLoc},
|
9
|
-
isa::aarch64::inst::{
|
10
|
-
self,
|
11
|
-
emit::{EmitInfo, EmitState},
|
12
|
-
ALUOp, ALUOp3, AMode, ExtendOp, Imm12, Inst, PairAMode,
|
13
|
-
},
|
14
|
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settings, Final, MachBuffer, MachBufferFinalized, MachInstEmit, MachInstEmitState, MachLabel,
|
15
|
-
Writable,
|
16
|
-
};
|
17
|
-
|
18
|
-
impl From<OperandSize> for inst::OperandSize {
|
19
|
-
fn from(size: OperandSize) -> Self {
|
20
|
-
match size {
|
21
|
-
OperandSize::S32 => Self::Size32,
|
22
|
-
OperandSize::S64 => Self::Size64,
|
23
|
-
s => panic!("Invalid operand size {:?}", s),
|
24
|
-
}
|
25
|
-
}
|
26
|
-
}
|
27
|
-
impl Into<ScalarSize> for OperandSize {
|
28
|
-
fn into(self) -> ScalarSize {
|
29
|
-
match self {
|
30
|
-
OperandSize::S8 => ScalarSize::Size8,
|
31
|
-
OperandSize::S16 => ScalarSize::Size16,
|
32
|
-
OperandSize::S32 => ScalarSize::Size32,
|
33
|
-
OperandSize::S64 => ScalarSize::Size64,
|
34
|
-
OperandSize::S128 => ScalarSize::Size128,
|
35
|
-
}
|
36
|
-
}
|
37
|
-
}
|
38
|
-
|
39
|
-
/// Low level assembler implementation for Aarch64.
|
40
|
-
pub(crate) struct Assembler {
|
41
|
-
/// The machine instruction buffer.
|
42
|
-
buffer: MachBuffer<Inst>,
|
43
|
-
/// Constant emission information.
|
44
|
-
emit_info: EmitInfo,
|
45
|
-
/// Emission state.
|
46
|
-
emit_state: EmitState,
|
47
|
-
}
|
48
|
-
|
49
|
-
impl Assembler {
|
50
|
-
/// Create a new Aarch64 assembler.
|
51
|
-
pub fn new(shared_flags: settings::Flags) -> Self {
|
52
|
-
Self {
|
53
|
-
buffer: MachBuffer::<Inst>::new(),
|
54
|
-
emit_state: Default::default(),
|
55
|
-
emit_info: EmitInfo::new(shared_flags),
|
56
|
-
}
|
57
|
-
}
|
58
|
-
}
|
59
|
-
|
60
|
-
impl Assembler {
|
61
|
-
/// Return the emitted code.
|
62
|
-
pub fn finalize(mut self, loc: Option<SourceLoc>) -> MachBufferFinalized<Final> {
|
63
|
-
let constants = Default::default();
|
64
|
-
let stencil = self
|
65
|
-
.buffer
|
66
|
-
.finish(&constants, self.emit_state.ctrl_plane_mut());
|
67
|
-
stencil.apply_base_srcloc(loc.unwrap_or_default())
|
68
|
-
}
|
69
|
-
|
70
|
-
fn emit(&mut self, inst: Inst) {
|
71
|
-
inst.emit(&[], &mut self.buffer, &self.emit_info, &mut self.emit_state);
|
72
|
-
}
|
73
|
-
|
74
|
-
/// Load a constant into a register.
|
75
|
-
pub fn load_constant(&mut self, imm: u64, rd: Reg) {
|
76
|
-
let writable = Writable::from_reg(rd.into());
|
77
|
-
Inst::load_constant(writable, imm, &mut |_| writable)
|
78
|
-
.into_iter()
|
79
|
-
.for_each(|i| self.emit(i));
|
80
|
-
}
|
81
|
-
|
82
|
-
/// Store a pair of registers.
|
83
|
-
pub fn stp(&mut self, xt1: Reg, xt2: Reg, addr: Address) {
|
84
|
-
let mem: PairAMode = addr.try_into().unwrap();
|
85
|
-
self.emit(Inst::StoreP64 {
|
86
|
-
rt: xt1.into(),
|
87
|
-
rt2: xt2.into(),
|
88
|
-
mem,
|
89
|
-
flags: MemFlags::trusted(),
|
90
|
-
});
|
91
|
-
}
|
92
|
-
|
93
|
-
/// Store a register.
|
94
|
-
pub fn str(&mut self, reg: Reg, addr: Address, size: OperandSize) {
|
95
|
-
let mem: AMode = addr.try_into().unwrap();
|
96
|
-
let flags = MemFlags::trusted();
|
97
|
-
|
98
|
-
use OperandSize::*;
|
99
|
-
let inst = match size {
|
100
|
-
S64 => Inst::Store64 {
|
101
|
-
rd: reg.into(),
|
102
|
-
mem,
|
103
|
-
flags,
|
104
|
-
},
|
105
|
-
S32 => Inst::Store32 {
|
106
|
-
rd: reg.into(),
|
107
|
-
mem,
|
108
|
-
flags,
|
109
|
-
},
|
110
|
-
|
111
|
-
_ => unreachable!(),
|
112
|
-
};
|
113
|
-
|
114
|
-
self.emit(inst);
|
115
|
-
}
|
116
|
-
|
117
|
-
/// Load a register.
|
118
|
-
pub fn ldr(&mut self, addr: Address, rd: Reg, size: OperandSize) {
|
119
|
-
use OperandSize::*;
|
120
|
-
let writable_reg = Writable::from_reg(rd.into());
|
121
|
-
let mem: AMode = addr.try_into().unwrap();
|
122
|
-
let flags = MemFlags::trusted();
|
123
|
-
|
124
|
-
let inst = match size {
|
125
|
-
S64 => Inst::ULoad64 {
|
126
|
-
rd: writable_reg,
|
127
|
-
mem,
|
128
|
-
flags,
|
129
|
-
},
|
130
|
-
S32 => Inst::ULoad32 {
|
131
|
-
rd: writable_reg,
|
132
|
-
mem,
|
133
|
-
flags,
|
134
|
-
},
|
135
|
-
_ => unreachable!(),
|
136
|
-
};
|
137
|
-
|
138
|
-
self.emit(inst);
|
139
|
-
}
|
140
|
-
|
141
|
-
/// Load a pair of registers.
|
142
|
-
pub fn ldp(&mut self, xt1: Reg, xt2: Reg, addr: Address) {
|
143
|
-
let writable_xt1 = Writable::from_reg(xt1.into());
|
144
|
-
let writable_xt2 = Writable::from_reg(xt2.into());
|
145
|
-
let mem = addr.try_into().unwrap();
|
146
|
-
|
147
|
-
self.emit(Inst::LoadP64 {
|
148
|
-
rt: writable_xt1,
|
149
|
-
rt2: writable_xt2,
|
150
|
-
mem,
|
151
|
-
flags: MemFlags::trusted(),
|
152
|
-
});
|
153
|
-
}
|
154
|
-
|
155
|
-
/// Register to register move.
|
156
|
-
pub fn mov_rr(&mut self, rm: Reg, rd: Reg, size: OperandSize) {
|
157
|
-
let writable_rd = Writable::from_reg(rd.into());
|
158
|
-
self.emit(Inst::Mov {
|
159
|
-
size: size.into(),
|
160
|
-
rd: writable_rd,
|
161
|
-
rm: rm.into(),
|
162
|
-
});
|
163
|
-
}
|
164
|
-
|
165
|
-
/// Floating point register to register move.
|
166
|
-
pub fn fmov_rr(&mut self, rn: Reg, rd: Reg, size: OperandSize) {
|
167
|
-
let writable = Writable::from_reg(rd.into());
|
168
|
-
let inst = match size {
|
169
|
-
OperandSize::S32 => Inst::FpuMove32 {
|
170
|
-
rd: writable,
|
171
|
-
rn: rn.into(),
|
172
|
-
},
|
173
|
-
OperandSize::S64 => Inst::FpuMove64 {
|
174
|
-
rd: writable,
|
175
|
-
rn: rn.into(),
|
176
|
-
},
|
177
|
-
_ => unreachable!(),
|
178
|
-
};
|
179
|
-
|
180
|
-
self.emit(inst);
|
181
|
-
}
|
182
|
-
|
183
|
-
pub fn mov_to_fpu(&mut self, rn: Reg, rd: Reg, size: OperandSize) {
|
184
|
-
let writable_rd = Writable::from_reg(rd.into());
|
185
|
-
self.emit(Inst::MovToFpu {
|
186
|
-
size: size.into(),
|
187
|
-
rd: writable_rd,
|
188
|
-
rn: rn.into(),
|
189
|
-
});
|
190
|
-
}
|
191
|
-
|
192
|
-
/// Add with three registers.
|
193
|
-
pub fn add_rrr(&mut self, rm: Reg, rn: Reg, rd: Reg, size: OperandSize) {
|
194
|
-
self.emit_alu_rrr_extend(ALUOp::Add, rm, rn, rd, size);
|
195
|
-
}
|
196
|
-
|
197
|
-
/// Add immediate and register.
|
198
|
-
pub fn add_ir(&mut self, imm: u64, rn: Reg, rd: Reg, size: OperandSize) {
|
199
|
-
let alu_op = ALUOp::Add;
|
200
|
-
if let Some(imm) = Imm12::maybe_from_u64(imm) {
|
201
|
-
self.emit_alu_rri(alu_op, imm, rn, rd, size);
|
202
|
-
} else {
|
203
|
-
let scratch = regs::scratch();
|
204
|
-
self.load_constant(imm, scratch);
|
205
|
-
self.emit_alu_rrr_extend(alu_op, scratch, rn, rd, size);
|
206
|
-
}
|
207
|
-
}
|
208
|
-
|
209
|
-
/// Substract with three registers.
|
210
|
-
pub fn sub_rrr(&mut self, rm: Reg, rn: Reg, rd: Reg, size: OperandSize) {
|
211
|
-
self.emit_alu_rrr_extend(ALUOp::Sub, rm, rn, rd, size);
|
212
|
-
}
|
213
|
-
|
214
|
-
/// Subtract immediate and register.
|
215
|
-
pub fn sub_ir(&mut self, imm: u64, rn: Reg, rd: Reg, size: OperandSize) {
|
216
|
-
let alu_op = ALUOp::Sub;
|
217
|
-
if let Some(imm) = Imm12::maybe_from_u64(imm) {
|
218
|
-
self.emit_alu_rri(alu_op, imm, rn, rd, size);
|
219
|
-
} else {
|
220
|
-
let scratch = regs::scratch();
|
221
|
-
self.load_constant(imm, scratch);
|
222
|
-
self.emit_alu_rrr_extend(alu_op, scratch, rn, rd, size);
|
223
|
-
}
|
224
|
-
}
|
225
|
-
|
226
|
-
/// Multiply with three registers.
|
227
|
-
pub fn mul_rrr(&mut self, rm: Reg, rn: Reg, rd: Reg, size: OperandSize) {
|
228
|
-
self.emit_alu_rrrr(ALUOp3::MAdd, rm, rn, rd, regs::zero(), size);
|
229
|
-
}
|
230
|
-
|
231
|
-
/// Multiply immediate and register.
|
232
|
-
pub fn mul_ir(&mut self, imm: u64, rn: Reg, rd: Reg, size: OperandSize) {
|
233
|
-
let scratch = regs::scratch();
|
234
|
-
self.load_constant(imm, scratch);
|
235
|
-
self.emit_alu_rrrr(ALUOp3::MAdd, scratch, rn, rd, regs::zero(), size);
|
236
|
-
}
|
237
|
-
|
238
|
-
/// Float add with three registers.
|
239
|
-
pub fn fadd_rrr(&mut self, rm: Reg, rn: Reg, rd: Reg, size: OperandSize) {
|
240
|
-
self.emit_fpu_rrr(FPUOp2::Add, rm, rn, rd, size);
|
241
|
-
}
|
242
|
-
|
243
|
-
/// Float sub with three registers.
|
244
|
-
pub fn fsub_rrr(&mut self, rm: Reg, rn: Reg, rd: Reg, size: OperandSize) {
|
245
|
-
self.emit_fpu_rrr(FPUOp2::Sub, rm, rn, rd, size);
|
246
|
-
}
|
247
|
-
|
248
|
-
/// Float multiply with three registers.
|
249
|
-
pub fn fmul_rrr(&mut self, rm: Reg, rn: Reg, rd: Reg, size: OperandSize) {
|
250
|
-
self.emit_fpu_rrr(FPUOp2::Mul, rm, rn, rd, size);
|
251
|
-
}
|
252
|
-
|
253
|
-
/// Float division with three registers.
|
254
|
-
pub fn fdiv_rrr(&mut self, rm: Reg, rn: Reg, rd: Reg, size: OperandSize) {
|
255
|
-
self.emit_fpu_rrr(FPUOp2::Div, rm, rn, rd, size);
|
256
|
-
}
|
257
|
-
|
258
|
-
/// Float max with three registers.
|
259
|
-
pub fn fmax_rrr(&mut self, rm: Reg, rn: Reg, rd: Reg, size: OperandSize) {
|
260
|
-
self.emit_fpu_rrr(FPUOp2::Max, rm, rn, rd, size);
|
261
|
-
}
|
262
|
-
|
263
|
-
/// Float min with three registers.
|
264
|
-
pub fn fmin_rrr(&mut self, rm: Reg, rn: Reg, rd: Reg, size: OperandSize) {
|
265
|
-
self.emit_fpu_rrr(FPUOp2::Min, rm, rn, rd, size);
|
266
|
-
}
|
267
|
-
|
268
|
-
/// Float neg with two registers.
|
269
|
-
pub fn fneg_rr(&mut self, rn: Reg, rd: Reg, size: OperandSize) {
|
270
|
-
self.emit_fpu_rr(FPUOp1::Neg, rn, rd, size);
|
271
|
-
}
|
272
|
-
|
273
|
-
/// Float abs with two registers.
|
274
|
-
pub fn fabs_rr(&mut self, rn: Reg, rd: Reg, size: OperandSize) {
|
275
|
-
self.emit_fpu_rr(FPUOp1::Abs, rn, rd, size);
|
276
|
-
}
|
277
|
-
|
278
|
-
/// Float sqrt with two registers.
|
279
|
-
pub fn fsqrt_rr(&mut self, rn: Reg, rd: Reg, size: OperandSize) {
|
280
|
-
self.emit_fpu_rr(FPUOp1::Sqrt, rn, rd, size);
|
281
|
-
}
|
282
|
-
|
283
|
-
/// Float round (ceil, trunc, floor) with two registers.
|
284
|
-
pub fn fround_rr(&mut self, rn: Reg, rd: Reg, mode: RoundingMode, size: OperandSize) {
|
285
|
-
let fpu_mode = match (mode, size) {
|
286
|
-
(RoundingMode::Nearest, OperandSize::S32) => FpuRoundMode::Nearest32,
|
287
|
-
(RoundingMode::Up, OperandSize::S32) => FpuRoundMode::Plus32,
|
288
|
-
(RoundingMode::Down, OperandSize::S32) => FpuRoundMode::Minus32,
|
289
|
-
(RoundingMode::Zero, OperandSize::S32) => FpuRoundMode::Zero32,
|
290
|
-
(RoundingMode::Nearest, OperandSize::S64) => FpuRoundMode::Nearest64,
|
291
|
-
(RoundingMode::Up, OperandSize::S64) => FpuRoundMode::Plus64,
|
292
|
-
(RoundingMode::Down, OperandSize::S64) => FpuRoundMode::Minus64,
|
293
|
-
(RoundingMode::Zero, OperandSize::S64) => FpuRoundMode::Zero64,
|
294
|
-
(m, o) => panic!("Invalid rounding mode or operand size {:?}, {:?}", m, o),
|
295
|
-
};
|
296
|
-
self.emit_fpu_round(fpu_mode, rn, rd)
|
297
|
-
}
|
298
|
-
|
299
|
-
/// Return instruction.
|
300
|
-
pub fn ret(&mut self) {
|
301
|
-
self.emit(Inst::Ret {});
|
302
|
-
}
|
303
|
-
|
304
|
-
// Helpers for ALU operations.
|
305
|
-
|
306
|
-
fn emit_alu_rri(&mut self, op: ALUOp, imm: Imm12, rn: Reg, rd: Reg, size: OperandSize) {
|
307
|
-
self.emit(Inst::AluRRImm12 {
|
308
|
-
alu_op: op,
|
309
|
-
size: size.into(),
|
310
|
-
rd: Writable::from_reg(rd.into()),
|
311
|
-
rn: rn.into(),
|
312
|
-
imm12: imm,
|
313
|
-
});
|
314
|
-
}
|
315
|
-
|
316
|
-
fn emit_alu_rrr_extend(&mut self, op: ALUOp, rm: Reg, rn: Reg, rd: Reg, size: OperandSize) {
|
317
|
-
self.emit(Inst::AluRRRExtend {
|
318
|
-
alu_op: op,
|
319
|
-
size: size.into(),
|
320
|
-
rd: Writable::from_reg(rd.into()),
|
321
|
-
rn: rn.into(),
|
322
|
-
rm: rm.into(),
|
323
|
-
extendop: ExtendOp::UXTX,
|
324
|
-
});
|
325
|
-
}
|
326
|
-
|
327
|
-
fn emit_alu_rrrr(&mut self, op: ALUOp3, rm: Reg, rn: Reg, rd: Reg, ra: Reg, size: OperandSize) {
|
328
|
-
self.emit(Inst::AluRRRR {
|
329
|
-
alu_op: op,
|
330
|
-
size: size.into(),
|
331
|
-
rd: Writable::from_reg(rd.into()),
|
332
|
-
rn: rn.into(),
|
333
|
-
rm: rm.into(),
|
334
|
-
ra: ra.into(),
|
335
|
-
});
|
336
|
-
}
|
337
|
-
|
338
|
-
fn emit_fpu_rrr(&mut self, op: FPUOp2, rm: Reg, rn: Reg, rd: Reg, size: OperandSize) {
|
339
|
-
self.emit(Inst::FpuRRR {
|
340
|
-
fpu_op: op,
|
341
|
-
size: size.into(),
|
342
|
-
rd: Writable::from_reg(rd.into()),
|
343
|
-
rn: rn.into(),
|
344
|
-
rm: rm.into(),
|
345
|
-
});
|
346
|
-
}
|
347
|
-
|
348
|
-
fn emit_fpu_rr(&mut self, op: FPUOp1, rn: Reg, rd: Reg, size: OperandSize) {
|
349
|
-
self.emit(Inst::FpuRR {
|
350
|
-
fpu_op: op,
|
351
|
-
size: size.into(),
|
352
|
-
rd: Writable::from_reg(rd.into()),
|
353
|
-
rn: rn.into(),
|
354
|
-
});
|
355
|
-
}
|
356
|
-
|
357
|
-
fn emit_fpu_round(&mut self, op: FpuRoundMode, rn: Reg, rd: Reg) {
|
358
|
-
self.emit(Inst::FpuRound {
|
359
|
-
op: op,
|
360
|
-
rd: Writable::from_reg(rd.into()),
|
361
|
-
rn: rn.into(),
|
362
|
-
});
|
363
|
-
}
|
364
|
-
|
365
|
-
/// Get a label from the underlying machine code buffer.
|
366
|
-
pub fn get_label(&mut self) -> MachLabel {
|
367
|
-
self.buffer.get_label()
|
368
|
-
}
|
369
|
-
|
370
|
-
/// Get a mutable reference to underlying
|
371
|
-
/// machine buffer.
|
372
|
-
pub fn buffer_mut(&mut self) -> &mut MachBuffer<Inst> {
|
373
|
-
&mut self.buffer
|
374
|
-
}
|
375
|
-
|
376
|
-
/// Get a reference to the underlying machine buffer.
|
377
|
-
pub fn buffer(&self) -> &MachBuffer<Inst> {
|
378
|
-
&self.buffer
|
379
|
-
}
|
380
|
-
}
|