wasmtime 21.0.1 → 22.0.0
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- checksums.yaml +4 -4
- data/Cargo.lock +80 -87
- data/ext/Cargo.toml +4 -4
- data/ext/cargo-vendor/cranelift-bforest-0.109.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-bforest-0.109.0/Cargo.toml +41 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/Cargo.toml +193 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/context.rs +384 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/dominator_tree.rs +727 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/egraph.rs +835 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/inst_predicates.rs +230 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/ir/dfg.rs +1777 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/ir/extfunc.rs +402 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/ir/immediates.rs +1612 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/ir/stackslot.rs +208 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/ir/types.rs +627 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/aarch64/abi.rs +1556 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/aarch64/inst/args.rs +711 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/aarch64/inst/emit.rs +3584 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/aarch64/inst/emit_tests.rs +7901 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/aarch64/inst/imms.rs +1213 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/aarch64/inst/mod.rs +3060 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/aarch64/inst/regs.rs +269 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/aarch64/inst/unwind/systemv.rs +174 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/aarch64/inst.isle +4218 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/aarch64/pcc.rs +568 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/riscv64/abi.rs +1029 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/riscv64/inst/args.rs +2054 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/riscv64/inst/emit.rs +2682 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/riscv64/inst/emit_tests.rs +2215 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/riscv64/inst/encode.rs +675 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/riscv64/inst/imms.rs +374 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/riscv64/inst/mod.rs +1938 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/riscv64/inst/unwind/systemv.rs +170 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/riscv64/inst/vector.rs +1150 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/riscv64/inst.isle +3127 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/riscv64/inst_vector.isle +1907 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/riscv64/lower/isle.rs +649 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/riscv64/lower.isle +2923 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/riscv64/mod.rs +260 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/s390x/abi.rs +1016 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/s390x/inst/args.rs +298 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/s390x/inst/emit.rs +3401 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/s390x/inst/emit_tests.rs +13388 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/s390x/inst/imms.rs +202 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/s390x/inst/mod.rs +3401 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/s390x/inst/regs.rs +169 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/s390x/inst/unwind/systemv.rs +212 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/s390x/inst.isle +5028 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/s390x/lower.isle +3995 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/x64/abi.rs +1390 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/x64/inst/args.rs +2240 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/x64/inst/emit.rs +4287 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/x64/inst/emit_state.rs +52 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/x64/inst/emit_tests.rs +5171 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/x64/inst/mod.rs +2821 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/x64/inst/regs.rs +275 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/x64/inst/unwind/systemv.rs +198 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/x64/inst.isle +5289 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/x64/lower.isle +4810 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isa/x64/pcc.rs +1014 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/isle_prelude.rs +986 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/lib.rs +106 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/machinst/abi.rs +2419 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/machinst/blockorder.rs +465 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/machinst/buffer.rs +2508 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/machinst/isle.rs +909 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/machinst/lower.rs +1432 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/machinst/mod.rs +551 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/machinst/reg.rs +479 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/machinst/valueregs.rs +138 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/machinst/vcode.rs +1741 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/opts/cprop.isle +297 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/opts/shifts.isle +307 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/prelude.isle +664 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/prelude_lower.isle +1073 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/timing.rs +296 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/traversals.rs +216 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/verifier/mod.rs +1957 -0
- data/ext/cargo-vendor/cranelift-codegen-0.109.0/src/write.rs +638 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.109.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.109.0/Cargo.toml +36 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.109.0/src/cdsl/types.rs +496 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.109.0/src/isa/riscv64.rs +174 -0
- data/ext/cargo-vendor/cranelift-codegen-shared-0.109.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-codegen-shared-0.109.0/Cargo.toml +22 -0
- data/ext/cargo-vendor/cranelift-codegen-shared-0.109.0/src/constants.rs +28 -0
- data/ext/cargo-vendor/cranelift-control-0.109.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-control-0.109.0/Cargo.toml +30 -0
- data/ext/cargo-vendor/cranelift-entity-0.109.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-entity-0.109.0/Cargo.toml +53 -0
- data/ext/cargo-vendor/cranelift-entity-0.109.0/src/set.rs +290 -0
- data/ext/cargo-vendor/cranelift-frontend-0.109.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-frontend-0.109.0/Cargo.toml +68 -0
- data/ext/cargo-vendor/cranelift-frontend-0.109.0/src/frontend.rs +1857 -0
- data/ext/cargo-vendor/cranelift-frontend-0.109.0/src/lib.rs +187 -0
- data/ext/cargo-vendor/cranelift-frontend-0.109.0/src/ssa.rs +1328 -0
- data/ext/cargo-vendor/cranelift-isle-0.109.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-isle-0.109.0/Cargo.toml +47 -0
- data/ext/cargo-vendor/cranelift-isle-0.109.0/src/sema.rs +2492 -0
- data/ext/cargo-vendor/cranelift-native-0.109.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-native-0.109.0/Cargo.toml +43 -0
- data/ext/cargo-vendor/cranelift-native-0.109.0/src/lib.rs +188 -0
- data/ext/cargo-vendor/cranelift-native-0.109.0/src/riscv.rs +128 -0
- data/ext/cargo-vendor/cranelift-wasm-0.109.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-wasm-0.109.0/Cargo.toml +110 -0
- data/ext/cargo-vendor/cranelift-wasm-0.109.0/src/code_translator.rs +3695 -0
- data/ext/cargo-vendor/cranelift-wasm-0.109.0/src/func_translator.rs +296 -0
- data/ext/cargo-vendor/cranelift-wasm-0.109.0/src/module_translator.rs +120 -0
- data/ext/cargo-vendor/cranelift-wasm-0.109.0/src/sections_translator.rs +343 -0
- data/ext/cargo-vendor/cranelift-wasm-0.109.0/src/state.rs +522 -0
- data/ext/cargo-vendor/object-0.36.3/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/object-0.36.3/CHANGELOG.md +1028 -0
- data/ext/cargo-vendor/object-0.36.3/Cargo.toml +180 -0
- data/ext/cargo-vendor/object-0.36.3/README.md +60 -0
- data/ext/cargo-vendor/object-0.36.3/src/build/bytes.rs +146 -0
- data/ext/cargo-vendor/object-0.36.3/src/build/elf.rs +3113 -0
- data/ext/cargo-vendor/object-0.36.3/src/common.rs +590 -0
- data/ext/cargo-vendor/object-0.36.3/src/elf.rs +6303 -0
- data/ext/cargo-vendor/object-0.36.3/src/endian.rs +831 -0
- data/ext/cargo-vendor/object-0.36.3/src/macho.rs +3303 -0
- data/ext/cargo-vendor/object-0.36.3/src/pod.rs +281 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/any.rs +1334 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/archive.rs +1133 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/coff/comdat.rs +220 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/coff/file.rs +381 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/coff/relocation.rs +113 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/coff/section.rs +619 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/coff/symbol.rs +669 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/elf/attributes.rs +340 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/elf/comdat.rs +186 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/elf/file.rs +959 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/elf/hash.rs +236 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/elf/note.rs +302 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/elf/relocation.rs +661 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/elf/section.rs +1241 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/elf/segment.rs +365 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/elf/symbol.rs +654 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/elf/version.rs +513 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/gnu_compression.rs +36 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/macho/dyld_cache.rs +384 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/macho/file.rs +779 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/macho/load_command.rs +404 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/macho/section.rs +420 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/macho/segment.rs +317 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/macho/symbol.rs +532 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/mod.rs +1018 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/pe/file.rs +1033 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/pe/import.rs +381 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/pe/relocation.rs +109 -0
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- data/ext/cargo-vendor/object-0.36.3/src/read/read_cache.rs +261 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/traits.rs +589 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/wasm.rs +983 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/xcoff/file.rs +716 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/xcoff/relocation.rs +138 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/xcoff/section.rs +452 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/xcoff/symbol.rs +836 -0
- data/ext/cargo-vendor/object-0.36.3/src/write/coff/object.rs +681 -0
- data/ext/cargo-vendor/object-0.36.3/src/write/coff/writer.rs +520 -0
- data/ext/cargo-vendor/object-0.36.3/src/write/elf/object.rs +897 -0
- data/ext/cargo-vendor/object-0.36.3/src/write/elf/writer.rs +2361 -0
- data/ext/cargo-vendor/object-0.36.3/src/write/macho.rs +1124 -0
- data/ext/cargo-vendor/object-0.36.3/src/write/mod.rs +1023 -0
- data/ext/cargo-vendor/object-0.36.3/src/write/pe.rs +849 -0
- data/ext/cargo-vendor/object-0.36.3/src/write/xcoff.rs +588 -0
- data/ext/cargo-vendor/object-0.36.3/tests/build/elf.rs +254 -0
- data/ext/cargo-vendor/object-0.36.3/tests/build/mod.rs +3 -0
- data/ext/cargo-vendor/object-0.36.3/tests/integration.rs +3 -0
- data/ext/cargo-vendor/object-0.36.3/tests/read/macho.rs +49 -0
- data/ext/cargo-vendor/object-0.36.3/tests/read/mod.rs +5 -0
- data/ext/cargo-vendor/object-0.36.3/tests/round_trip/bss.rs +244 -0
- data/ext/cargo-vendor/object-0.36.3/tests/round_trip/comdat.rs +217 -0
- data/ext/cargo-vendor/object-0.36.3/tests/round_trip/common.rs +241 -0
- data/ext/cargo-vendor/object-0.36.3/tests/round_trip/elf.rs +302 -0
- data/ext/cargo-vendor/object-0.36.3/tests/round_trip/mod.rs +682 -0
- data/ext/cargo-vendor/object-0.36.3/tests/round_trip/section_flags.rs +89 -0
- data/ext/cargo-vendor/object-0.36.3/tests/round_trip/tls.rs +308 -0
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- data/ext/cargo-vendor/wasi-common-22.0.0/src/snapshots/preview_0.rs +1080 -0
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- data/ext/cargo-vendor/wasi-common-22.0.0/src/string_array.rs +75 -0
- data/ext/cargo-vendor/wasi-common-22.0.0/src/sync/sched/windows.rs +221 -0
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- /data/ext/cargo-vendor/{wit-parser-0.207.0 → wit-parser-0.209.1}/tests/ui/wasi.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.207.0 → wit-parser-0.209.1}/tests/ui/wasi.wit.json +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.207.0 → wit-parser-0.209.1}/tests/ui/world-diamond.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.207.0 → wit-parser-0.209.1}/tests/ui/world-iface-no-collide.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.207.0 → wit-parser-0.209.1}/tests/ui/world-implicit-import1.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.207.0 → wit-parser-0.209.1}/tests/ui/world-implicit-import2.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.207.0 → wit-parser-0.209.1}/tests/ui/world-implicit-import3.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.207.0 → wit-parser-0.209.1}/tests/ui/world-same-fields4.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.207.0 → wit-parser-0.209.1}/tests/ui/world-top-level-funcs.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.207.0 → wit-parser-0.209.1}/tests/ui/world-top-level-funcs.wit.json +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.207.0 → wit-parser-0.209.1}/tests/ui/world-top-level-resources.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.207.0 → wit-parser-0.209.1}/tests/ui/worlds-union-dedup.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.207.0 → wit-parser-0.209.1}/tests/ui/worlds-with-types.wit +0 -0
@@ -1,1213 +0,0 @@
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//! AArch64 ISA definitions: immediate constants.
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use crate::ir::types::*;
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use crate::isa::aarch64::inst::{OperandSize, ScalarSize};
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use crate::machinst::{AllocationConsumer, PrettyPrint};
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use std::string::String;
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/// An immediate that represents the NZCV flags.
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#[derive(Clone, Copy, Debug)]
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pub struct NZCV {
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/// The negative condition flag.
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n: bool,
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/// The zero condition flag.
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z: bool,
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/// The carry condition flag.
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c: bool,
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/// The overflow condition flag.
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v: bool,
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}
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impl NZCV {
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/// Create a new NZCV flags representation.
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pub fn new(n: bool, z: bool, c: bool, v: bool) -> NZCV {
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NZCV { n, z, c, v }
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}
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/// Bits for encoding.
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pub fn bits(&self) -> u32 {
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(u32::from(self.n) << 3)
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| (u32::from(self.z) << 2)
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| (u32::from(self.c) << 1)
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| u32::from(self.v)
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}
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}
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/// An unsigned 5-bit immediate.
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#[derive(Clone, Copy, Debug)]
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pub struct UImm5 {
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/// The value.
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value: u8,
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}
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impl UImm5 {
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/// Create an unsigned 5-bit immediate from u8.
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pub fn maybe_from_u8(value: u8) -> Option<UImm5> {
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if value < 32 {
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Some(UImm5 { value })
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} else {
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None
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}
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}
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/// Bits for encoding.
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pub fn bits(&self) -> u32 {
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u32::from(self.value)
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}
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}
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/// A signed, scaled 7-bit offset.
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#[derive(Clone, Copy, Debug)]
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pub struct SImm7Scaled {
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/// The value.
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pub value: i16,
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/// multiplied by the size of this type
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pub scale_ty: Type,
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}
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impl SImm7Scaled {
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/// Create a SImm7Scaled from a raw offset and the known scale type, if
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/// possible.
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pub fn maybe_from_i64(value: i64, scale_ty: Type) -> Option<SImm7Scaled> {
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assert!(scale_ty == I64 || scale_ty == I32 || scale_ty == F64 || scale_ty == I8X16);
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let scale = scale_ty.bytes();
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assert!(scale.is_power_of_two());
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let scale = i64::from(scale);
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let upper_limit = 63 * scale;
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let lower_limit = -(64 * scale);
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if value >= lower_limit && value <= upper_limit && (value & (scale - 1)) == 0 {
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Some(SImm7Scaled {
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value: i16::try_from(value).unwrap(),
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scale_ty,
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})
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} else {
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None
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}
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}
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/// Bits for encoding.
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pub fn bits(&self) -> u32 {
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let ty_bytes: i16 = self.scale_ty.bytes() as i16;
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let scaled: i16 = self.value / ty_bytes;
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assert!(scaled <= 63 && scaled >= -64);
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let scaled: i8 = scaled as i8;
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let encoded: u32 = scaled as u32;
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encoded & 0x7f
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}
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}
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/// Floating-point unit immediate left shift.
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#[derive(Clone, Copy, Debug)]
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pub struct FPULeftShiftImm {
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/// Shift amount.
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pub amount: u8,
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/// Lane size in bits.
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pub lane_size_in_bits: u8,
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}
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impl FPULeftShiftImm {
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/// Create a floating-point unit immediate left shift from u8.
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pub fn maybe_from_u8(amount: u8, lane_size_in_bits: u8) -> Option<Self> {
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debug_assert!(lane_size_in_bits == 32 || lane_size_in_bits == 64);
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if amount < lane_size_in_bits {
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Some(Self {
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amount,
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lane_size_in_bits,
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})
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} else {
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None
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}
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}
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/// Returns the encoding of the immediate.
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pub fn enc(&self) -> u32 {
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debug_assert!(self.lane_size_in_bits.is_power_of_two());
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debug_assert!(self.lane_size_in_bits > self.amount);
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// The encoding of the immediate follows the table below,
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// where xs encode the shift amount.
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//
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// | lane_size_in_bits | encoding |
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// +------------------------------+
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// | 8 | 0001xxx |
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// | 16 | 001xxxx |
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// | 32 | 01xxxxx |
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// | 64 | 1xxxxxx |
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//
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// The highest one bit is represented by `lane_size_in_bits`. Since
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// `lane_size_in_bits` is a power of 2 and `amount` is less
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// than `lane_size_in_bits`, they can be ORed
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// together to produced the encoded value.
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u32::from(self.lane_size_in_bits | self.amount)
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}
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}
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/// Floating-point unit immediate right shift.
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#[derive(Clone, Copy, Debug)]
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pub struct FPURightShiftImm {
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/// Shift amount.
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pub amount: u8,
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/// Lane size in bits.
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pub lane_size_in_bits: u8,
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}
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impl FPURightShiftImm {
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/// Create a floating-point unit immediate right shift from u8.
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pub fn maybe_from_u8(amount: u8, lane_size_in_bits: u8) -> Option<Self> {
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debug_assert!(lane_size_in_bits == 32 || lane_size_in_bits == 64);
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if amount > 0 && amount <= lane_size_in_bits {
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Some(Self {
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amount,
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lane_size_in_bits,
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})
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} else {
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None
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}
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}
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/// Returns encoding of the immediate.
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pub fn enc(&self) -> u32 {
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debug_assert_ne!(0, self.amount);
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// The encoding of the immediate follows the table below,
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// where xs encodes the negated shift amount.
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//
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// | lane_size_in_bits | encoding |
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// +------------------------------+
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// | 8 | 0001xxx |
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// | 16 | 001xxxx |
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// | 32 | 01xxxxx |
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// | 64 | 1xxxxxx |
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//
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// The shift amount is negated such that a shift ammount
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// of 1 (in 64-bit) is encoded as 0b111111 and a shift
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// amount of 64 is encoded as 0b000000,
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// in the bottom 6 bits.
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u32::from((self.lane_size_in_bits * 2) - self.amount)
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}
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}
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/// a 9-bit signed offset.
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#[derive(Clone, Copy, Debug)]
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pub struct SImm9 {
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/// The value.
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pub value: i16,
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}
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impl SImm9 {
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/// Create a signed 9-bit offset from a full-range value, if possible.
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pub fn maybe_from_i64(value: i64) -> Option<SImm9> {
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if value >= -256 && value <= 255 {
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Some(SImm9 {
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value: value as i16,
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})
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} else {
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None
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}
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}
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/// Bits for encoding.
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pub fn bits(&self) -> u32 {
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(self.value as u32) & 0x1ff
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}
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/// Signed value of immediate.
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pub fn value(&self) -> i32 {
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self.value as i32
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}
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}
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/// An unsigned, scaled 12-bit offset.
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#[derive(Clone, Copy, Debug)]
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pub struct UImm12Scaled {
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/// The value.
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value: u16,
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/// multiplied by the size of this type
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scale_ty: Type,
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}
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impl UImm12Scaled {
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/// Create a UImm12Scaled from a raw offset and the known scale type, if
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/// possible.
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pub fn maybe_from_i64(value: i64, scale_ty: Type) -> Option<UImm12Scaled> {
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let scale = scale_ty.bytes();
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assert!(scale.is_power_of_two());
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let scale = scale as i64;
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let limit = 4095 * scale;
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if value >= 0 && value <= limit && (value & (scale - 1)) == 0 {
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Some(UImm12Scaled {
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value: value as u16,
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scale_ty,
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})
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} else {
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None
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}
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}
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/// Create a zero immediate of this format.
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pub fn zero(scale_ty: Type) -> UImm12Scaled {
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UImm12Scaled { value: 0, scale_ty }
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}
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/// Encoded bits.
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pub fn bits(&self) -> u32 {
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(self.value as u32 / self.scale_ty.bytes()) & 0xfff
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}
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/// Value after scaling.
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pub fn value(&self) -> u32 {
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self.value as u32
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}
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}
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/// A shifted immediate value in 'imm12' format: supports 12 bits, shifted
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/// left by 0 or 12 places.
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#[derive(Copy, Clone, Debug)]
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pub struct Imm12 {
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/// The immediate bits.
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pub bits: u16,
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/// Whether the immediate bits are shifted left by 12 or not.
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pub shift12: bool,
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}
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impl Imm12 {
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/// Compute a Imm12 from raw bits, if possible.
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pub fn maybe_from_u64(val: u64) -> Option<Imm12> {
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if val & !0xfff == 0 {
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Some(Imm12 {
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bits: val as u16,
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shift12: false,
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})
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} else if val & !(0xfff << 12) == 0 {
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Some(Imm12 {
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bits: (val >> 12) as u16,
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shift12: true,
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})
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} else {
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None
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}
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}
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/// Bits for 2-bit "shift" field in e.g. AddI.
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pub fn shift_bits(&self) -> u32 {
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if self.shift12 {
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0b01
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} else {
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0b00
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}
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}
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/// Bits for 12-bit "imm" field in e.g. AddI.
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pub fn imm_bits(&self) -> u32 {
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self.bits as u32
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}
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/// Get the actual value that this immediate corresponds to.
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pub fn value(&self) -> u32 {
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let base = self.bits as u32;
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if self.shift12 {
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base << 12
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} else {
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base
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}
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}
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}
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/// An immediate for logical instructions.
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#[derive(Copy, Clone, Debug, PartialEq)]
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pub struct ImmLogic {
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/// The actual value.
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value: u64,
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/// `N` flag.
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pub n: bool,
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/// `S` field: element size and element bits.
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pub r: u8,
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/// `R` field: rotate amount.
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pub s: u8,
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/// Was this constructed for a 32-bit or 64-bit instruction?
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pub size: OperandSize,
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}
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impl ImmLogic {
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/// Compute an ImmLogic from raw bits, if possible.
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pub fn maybe_from_u64(value: u64, ty: Type) -> Option<ImmLogic> {
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// Note: This function is a port of VIXL's Assembler::IsImmLogical.
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if ty != I64 && ty != I32 {
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return None;
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}
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let operand_size = OperandSize::from_ty(ty);
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let original_value = value;
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let value = if ty == I32 {
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// To handle 32-bit logical immediates, the very easiest thing is to repeat
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// the input value twice to make a 64-bit word. The correct encoding of that
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// as a logical immediate will also be the correct encoding of the 32-bit
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// value.
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// Avoid making the assumption that the most-significant 32 bits are zero by
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// shifting the value left and duplicating it.
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let value = value << 32;
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value | value >> 32
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} else {
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value
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};
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-
// Logical immediates are encoded using parameters n, imm_s and imm_r using
|
357
|
-
// the following table:
|
358
|
-
//
|
359
|
-
// N imms immr size S R
|
360
|
-
// 1 ssssss rrrrrr 64 UInt(ssssss) UInt(rrrrrr)
|
361
|
-
// 0 0sssss xrrrrr 32 UInt(sssss) UInt(rrrrr)
|
362
|
-
// 0 10ssss xxrrrr 16 UInt(ssss) UInt(rrrr)
|
363
|
-
// 0 110sss xxxrrr 8 UInt(sss) UInt(rrr)
|
364
|
-
// 0 1110ss xxxxrr 4 UInt(ss) UInt(rr)
|
365
|
-
// 0 11110s xxxxxr 2 UInt(s) UInt(r)
|
366
|
-
// (s bits must not be all set)
|
367
|
-
//
|
368
|
-
// A pattern is constructed of size bits, where the least significant S+1 bits
|
369
|
-
// are set. The pattern is rotated right by R, and repeated across a 32 or
|
370
|
-
// 64-bit value, depending on destination register width.
|
371
|
-
//
|
372
|
-
// Put another way: the basic format of a logical immediate is a single
|
373
|
-
// contiguous stretch of 1 bits, repeated across the whole word at intervals
|
374
|
-
// given by a power of 2. To identify them quickly, we first locate the
|
375
|
-
// lowest stretch of 1 bits, then the next 1 bit above that; that combination
|
376
|
-
// is different for every logical immediate, so it gives us all the
|
377
|
-
// information we need to identify the only logical immediate that our input
|
378
|
-
// could be, and then we simply check if that's the value we actually have.
|
379
|
-
//
|
380
|
-
// (The rotation parameter does give the possibility of the stretch of 1 bits
|
381
|
-
// going 'round the end' of the word. To deal with that, we observe that in
|
382
|
-
// any situation where that happens the bitwise NOT of the value is also a
|
383
|
-
// valid logical immediate. So we simply invert the input whenever its low bit
|
384
|
-
// is set, and then we know that the rotated case can't arise.)
|
385
|
-
let (value, inverted) = if value & 1 == 1 {
|
386
|
-
(!value, true)
|
387
|
-
} else {
|
388
|
-
(value, false)
|
389
|
-
};
|
390
|
-
|
391
|
-
if value == 0 {
|
392
|
-
return None;
|
393
|
-
}
|
394
|
-
|
395
|
-
// The basic analysis idea: imagine our input word looks like this.
|
396
|
-
//
|
397
|
-
// 0011111000111110001111100011111000111110001111100011111000111110
|
398
|
-
// c b a
|
399
|
-
// |<--d-->|
|
400
|
-
//
|
401
|
-
// We find the lowest set bit (as an actual power-of-2 value, not its index)
|
402
|
-
// and call it a. Then we add a to our original number, which wipes out the
|
403
|
-
// bottommost stretch of set bits and replaces it with a 1 carried into the
|
404
|
-
// next zero bit. Then we look for the new lowest set bit, which is in
|
405
|
-
// position b, and subtract it, so now our number is just like the original
|
406
|
-
// but with the lowest stretch of set bits completely gone. Now we find the
|
407
|
-
// lowest set bit again, which is position c in the diagram above. Then we'll
|
408
|
-
// measure the distance d between bit positions a and c (using CLZ), and that
|
409
|
-
// tells us that the only valid logical immediate that could possibly be equal
|
410
|
-
// to this number is the one in which a stretch of bits running from a to just
|
411
|
-
// below b is replicated every d bits.
|
412
|
-
fn lowest_set_bit(value: u64) -> u64 {
|
413
|
-
let bit = value.trailing_zeros();
|
414
|
-
1u64.checked_shl(bit).unwrap_or(0)
|
415
|
-
}
|
416
|
-
let a = lowest_set_bit(value);
|
417
|
-
assert_ne!(0, a);
|
418
|
-
let value_plus_a = value.wrapping_add(a);
|
419
|
-
let b = lowest_set_bit(value_plus_a);
|
420
|
-
let value_plus_a_minus_b = value_plus_a - b;
|
421
|
-
let c = lowest_set_bit(value_plus_a_minus_b);
|
422
|
-
|
423
|
-
let (d, clz_a, out_n, mask) = if c != 0 {
|
424
|
-
// The general case, in which there is more than one stretch of set bits.
|
425
|
-
// Compute the repeat distance d, and set up a bitmask covering the basic
|
426
|
-
// unit of repetition (i.e. a word with the bottom d bits set). Also, in all
|
427
|
-
// of these cases the N bit of the output will be zero.
|
428
|
-
let clz_a = a.leading_zeros();
|
429
|
-
let clz_c = c.leading_zeros();
|
430
|
-
let d = clz_a - clz_c;
|
431
|
-
let mask = (1 << d) - 1;
|
432
|
-
(d, clz_a, 0, mask)
|
433
|
-
} else {
|
434
|
-
(64, a.leading_zeros(), 1, u64::max_value())
|
435
|
-
};
|
436
|
-
|
437
|
-
// If the repeat period d is not a power of two, it can't be encoded.
|
438
|
-
if !d.is_power_of_two() {
|
439
|
-
return None;
|
440
|
-
}
|
441
|
-
|
442
|
-
if ((b.wrapping_sub(a)) & !mask) != 0 {
|
443
|
-
// If the bit stretch (b - a) does not fit within the mask derived from the
|
444
|
-
// repeat period, then fail.
|
445
|
-
return None;
|
446
|
-
}
|
447
|
-
|
448
|
-
// The only possible option is b - a repeated every d bits. Now we're going to
|
449
|
-
// actually construct the valid logical immediate derived from that
|
450
|
-
// specification, and see if it equals our original input.
|
451
|
-
//
|
452
|
-
// To repeat a value every d bits, we multiply it by a number of the form
|
453
|
-
// (1 + 2^d + 2^(2d) + ...), i.e. 0x0001000100010001 or similar. These can
|
454
|
-
// be derived using a table lookup on CLZ(d).
|
455
|
-
const MULTIPLIERS: [u64; 6] = [
|
456
|
-
0x0000000000000001,
|
457
|
-
0x0000000100000001,
|
458
|
-
0x0001000100010001,
|
459
|
-
0x0101010101010101,
|
460
|
-
0x1111111111111111,
|
461
|
-
0x5555555555555555,
|
462
|
-
];
|
463
|
-
let multiplier = MULTIPLIERS[(u64::from(d).leading_zeros() - 57) as usize];
|
464
|
-
let candidate = b.wrapping_sub(a) * multiplier;
|
465
|
-
|
466
|
-
if value != candidate {
|
467
|
-
// The candidate pattern doesn't match our input value, so fail.
|
468
|
-
return None;
|
469
|
-
}
|
470
|
-
|
471
|
-
// We have a match! This is a valid logical immediate, so now we have to
|
472
|
-
// construct the bits and pieces of the instruction encoding that generates
|
473
|
-
// it.
|
474
|
-
|
475
|
-
// Count the set bits in our basic stretch. The special case of clz(0) == -1
|
476
|
-
// makes the answer come out right for stretches that reach the very top of
|
477
|
-
// the word (e.g. numbers like 0xffffc00000000000).
|
478
|
-
let clz_b = if b == 0 {
|
479
|
-
u32::max_value() // -1
|
480
|
-
} else {
|
481
|
-
b.leading_zeros()
|
482
|
-
};
|
483
|
-
let s = clz_a.wrapping_sub(clz_b);
|
484
|
-
|
485
|
-
// Decide how many bits to rotate right by, to put the low bit of that basic
|
486
|
-
// stretch in position a.
|
487
|
-
let (s, r) = if inverted {
|
488
|
-
// If we inverted the input right at the start of this function, here's
|
489
|
-
// where we compensate: the number of set bits becomes the number of clear
|
490
|
-
// bits, and the rotation count is based on position b rather than position
|
491
|
-
// a (since b is the location of the 'lowest' 1 bit after inversion).
|
492
|
-
// Need wrapping for when clz_b is max_value() (for when b == 0).
|
493
|
-
(d - s, clz_b.wrapping_add(1) & (d - 1))
|
494
|
-
} else {
|
495
|
-
(s, (clz_a + 1) & (d - 1))
|
496
|
-
};
|
497
|
-
|
498
|
-
// Now we're done, except for having to encode the S output in such a way that
|
499
|
-
// it gives both the number of set bits and the length of the repeated
|
500
|
-
// segment. The s field is encoded like this:
|
501
|
-
//
|
502
|
-
// imms size S
|
503
|
-
// ssssss 64 UInt(ssssss)
|
504
|
-
// 0sssss 32 UInt(sssss)
|
505
|
-
// 10ssss 16 UInt(ssss)
|
506
|
-
// 110sss 8 UInt(sss)
|
507
|
-
// 1110ss 4 UInt(ss)
|
508
|
-
// 11110s 2 UInt(s)
|
509
|
-
//
|
510
|
-
// So we 'or' (2 * -d) with our computed s to form imms.
|
511
|
-
let s = ((d * 2).wrapping_neg() | (s - 1)) & 0x3f;
|
512
|
-
debug_assert!(u8::try_from(r).is_ok());
|
513
|
-
debug_assert!(u8::try_from(s).is_ok());
|
514
|
-
Some(ImmLogic {
|
515
|
-
value: original_value,
|
516
|
-
n: out_n != 0,
|
517
|
-
r: r as u8,
|
518
|
-
s: s as u8,
|
519
|
-
size: operand_size,
|
520
|
-
})
|
521
|
-
}
|
522
|
-
|
523
|
-
/// Returns bits ready for encoding: (N:1, R:6, S:6)
|
524
|
-
pub fn enc_bits(&self) -> u32 {
|
525
|
-
((self.n as u32) << 12) | ((self.r as u32) << 6) | (self.s as u32)
|
526
|
-
}
|
527
|
-
|
528
|
-
/// Returns the value that this immediate represents.
|
529
|
-
pub fn value(&self) -> u64 {
|
530
|
-
self.value
|
531
|
-
}
|
532
|
-
|
533
|
-
/// Return an immediate for the bitwise-inverted value.
|
534
|
-
pub fn invert(&self) -> ImmLogic {
|
535
|
-
// For every ImmLogical immediate, the inverse can also be encoded.
|
536
|
-
Self::maybe_from_u64(!self.value, self.size.to_ty()).unwrap()
|
537
|
-
}
|
538
|
-
}
|
539
|
-
|
540
|
-
/// An immediate for shift instructions.
|
541
|
-
#[derive(Copy, Clone, Debug)]
|
542
|
-
pub struct ImmShift {
|
543
|
-
/// 6-bit shift amount.
|
544
|
-
pub imm: u8,
|
545
|
-
}
|
546
|
-
|
547
|
-
impl ImmShift {
|
548
|
-
/// Create an ImmShift from raw bits, if possible.
|
549
|
-
pub fn maybe_from_u64(val: u64) -> Option<ImmShift> {
|
550
|
-
if val < 64 {
|
551
|
-
Some(ImmShift { imm: val as u8 })
|
552
|
-
} else {
|
553
|
-
None
|
554
|
-
}
|
555
|
-
}
|
556
|
-
|
557
|
-
/// Get the immediate value.
|
558
|
-
pub fn value(&self) -> u8 {
|
559
|
-
self.imm
|
560
|
-
}
|
561
|
-
}
|
562
|
-
|
563
|
-
/// A 16-bit immediate for a MOVZ instruction, with a {0,16,32,48}-bit shift.
|
564
|
-
#[derive(Clone, Copy, Debug)]
|
565
|
-
pub struct MoveWideConst {
|
566
|
-
/// The value.
|
567
|
-
pub bits: u16,
|
568
|
-
/// Result is `bits` shifted 16*shift bits to the left.
|
569
|
-
pub shift: u8,
|
570
|
-
}
|
571
|
-
|
572
|
-
impl MoveWideConst {
|
573
|
-
/// Construct a MoveWideConst from an arbitrary 64-bit constant if possible.
|
574
|
-
pub fn maybe_from_u64(value: u64) -> Option<MoveWideConst> {
|
575
|
-
let mask0 = 0x0000_0000_0000_ffffu64;
|
576
|
-
let mask1 = 0x0000_0000_ffff_0000u64;
|
577
|
-
let mask2 = 0x0000_ffff_0000_0000u64;
|
578
|
-
let mask3 = 0xffff_0000_0000_0000u64;
|
579
|
-
|
580
|
-
if value == (value & mask0) {
|
581
|
-
return Some(MoveWideConst {
|
582
|
-
bits: (value & mask0) as u16,
|
583
|
-
shift: 0,
|
584
|
-
});
|
585
|
-
}
|
586
|
-
if value == (value & mask1) {
|
587
|
-
return Some(MoveWideConst {
|
588
|
-
bits: ((value >> 16) & mask0) as u16,
|
589
|
-
shift: 1,
|
590
|
-
});
|
591
|
-
}
|
592
|
-
if value == (value & mask2) {
|
593
|
-
return Some(MoveWideConst {
|
594
|
-
bits: ((value >> 32) & mask0) as u16,
|
595
|
-
shift: 2,
|
596
|
-
});
|
597
|
-
}
|
598
|
-
if value == (value & mask3) {
|
599
|
-
return Some(MoveWideConst {
|
600
|
-
bits: ((value >> 48) & mask0) as u16,
|
601
|
-
shift: 3,
|
602
|
-
});
|
603
|
-
}
|
604
|
-
None
|
605
|
-
}
|
606
|
-
|
607
|
-
/// Create a `MoveWideCosnt` from a given shift, if possible.
|
608
|
-
pub fn maybe_with_shift(imm: u16, shift: u8) -> Option<MoveWideConst> {
|
609
|
-
let shift_enc = shift / 16;
|
610
|
-
if shift_enc > 3 {
|
611
|
-
None
|
612
|
-
} else {
|
613
|
-
Some(MoveWideConst {
|
614
|
-
bits: imm,
|
615
|
-
shift: shift_enc,
|
616
|
-
})
|
617
|
-
}
|
618
|
-
}
|
619
|
-
|
620
|
-
/// Create a zero immediate of this format.
|
621
|
-
pub fn zero() -> MoveWideConst {
|
622
|
-
MoveWideConst { bits: 0, shift: 0 }
|
623
|
-
}
|
624
|
-
}
|
625
|
-
|
626
|
-
/// Advanced SIMD modified immediate as used by MOVI/MVNI.
|
627
|
-
#[derive(Clone, Copy, Debug, PartialEq)]
|
628
|
-
pub struct ASIMDMovModImm {
|
629
|
-
imm: u8,
|
630
|
-
shift: u8,
|
631
|
-
is_64bit: bool,
|
632
|
-
shift_ones: bool,
|
633
|
-
}
|
634
|
-
|
635
|
-
impl ASIMDMovModImm {
|
636
|
-
/// Construct an ASIMDMovModImm from an arbitrary 64-bit constant, if possible.
|
637
|
-
/// Note that the bits in `value` outside of the range specified by `size` are
|
638
|
-
/// ignored; for example, in the case of `ScalarSize::Size8` all bits above the
|
639
|
-
/// lowest 8 are ignored.
|
640
|
-
pub fn maybe_from_u64(value: u64, size: ScalarSize) -> Option<ASIMDMovModImm> {
|
641
|
-
match size {
|
642
|
-
ScalarSize::Size8 => Some(ASIMDMovModImm {
|
643
|
-
imm: value as u8,
|
644
|
-
shift: 0,
|
645
|
-
is_64bit: false,
|
646
|
-
shift_ones: false,
|
647
|
-
}),
|
648
|
-
ScalarSize::Size16 => {
|
649
|
-
let value = value as u16;
|
650
|
-
|
651
|
-
if value >> 8 == 0 {
|
652
|
-
Some(ASIMDMovModImm {
|
653
|
-
imm: value as u8,
|
654
|
-
shift: 0,
|
655
|
-
is_64bit: false,
|
656
|
-
shift_ones: false,
|
657
|
-
})
|
658
|
-
} else if value as u8 == 0 {
|
659
|
-
Some(ASIMDMovModImm {
|
660
|
-
imm: (value >> 8) as u8,
|
661
|
-
shift: 8,
|
662
|
-
is_64bit: false,
|
663
|
-
shift_ones: false,
|
664
|
-
})
|
665
|
-
} else {
|
666
|
-
None
|
667
|
-
}
|
668
|
-
}
|
669
|
-
ScalarSize::Size32 => {
|
670
|
-
let value = value as u32;
|
671
|
-
|
672
|
-
// Value is of the form 0x00MMFFFF.
|
673
|
-
if value & 0xFF00FFFF == 0x0000FFFF {
|
674
|
-
let imm = (value >> 16) as u8;
|
675
|
-
|
676
|
-
Some(ASIMDMovModImm {
|
677
|
-
imm,
|
678
|
-
shift: 16,
|
679
|
-
is_64bit: false,
|
680
|
-
shift_ones: true,
|
681
|
-
})
|
682
|
-
// Value is of the form 0x0000MMFF.
|
683
|
-
} else if value & 0xFFFF00FF == 0x000000FF {
|
684
|
-
let imm = (value >> 8) as u8;
|
685
|
-
|
686
|
-
Some(ASIMDMovModImm {
|
687
|
-
imm,
|
688
|
-
shift: 8,
|
689
|
-
is_64bit: false,
|
690
|
-
shift_ones: true,
|
691
|
-
})
|
692
|
-
} else {
|
693
|
-
// Of the 4 bytes, at most one is non-zero.
|
694
|
-
for shift in (0..32).step_by(8) {
|
695
|
-
if value & (0xFF << shift) == value {
|
696
|
-
return Some(ASIMDMovModImm {
|
697
|
-
imm: (value >> shift) as u8,
|
698
|
-
shift,
|
699
|
-
is_64bit: false,
|
700
|
-
shift_ones: false,
|
701
|
-
});
|
702
|
-
}
|
703
|
-
}
|
704
|
-
|
705
|
-
None
|
706
|
-
}
|
707
|
-
}
|
708
|
-
ScalarSize::Size64 => {
|
709
|
-
let mut imm = 0u8;
|
710
|
-
|
711
|
-
// Check if all bytes are either 0 or 0xFF.
|
712
|
-
for i in 0..8 {
|
713
|
-
let b = (value >> (i * 8)) as u8;
|
714
|
-
|
715
|
-
if b == 0 || b == 0xFF {
|
716
|
-
imm |= (b & 1) << i;
|
717
|
-
} else {
|
718
|
-
return None;
|
719
|
-
}
|
720
|
-
}
|
721
|
-
|
722
|
-
Some(ASIMDMovModImm {
|
723
|
-
imm,
|
724
|
-
shift: 0,
|
725
|
-
is_64bit: true,
|
726
|
-
shift_ones: false,
|
727
|
-
})
|
728
|
-
}
|
729
|
-
_ => None,
|
730
|
-
}
|
731
|
-
}
|
732
|
-
|
733
|
-
/// Create a zero immediate of this format.
|
734
|
-
pub fn zero(size: ScalarSize) -> Self {
|
735
|
-
ASIMDMovModImm {
|
736
|
-
imm: 0,
|
737
|
-
shift: 0,
|
738
|
-
is_64bit: size == ScalarSize::Size64,
|
739
|
-
shift_ones: false,
|
740
|
-
}
|
741
|
-
}
|
742
|
-
|
743
|
-
/// Returns the value that this immediate represents.
|
744
|
-
pub fn value(&self) -> (u8, u32, bool) {
|
745
|
-
(self.imm, self.shift as u32, self.shift_ones)
|
746
|
-
}
|
747
|
-
}
|
748
|
-
|
749
|
-
/// Advanced SIMD modified immediate as used by the vector variant of FMOV.
|
750
|
-
#[derive(Clone, Copy, Debug, PartialEq)]
|
751
|
-
pub struct ASIMDFPModImm {
|
752
|
-
imm: u8,
|
753
|
-
is_64bit: bool,
|
754
|
-
}
|
755
|
-
|
756
|
-
impl ASIMDFPModImm {
|
757
|
-
/// Construct an ASIMDFPModImm from an arbitrary 64-bit constant, if possible.
|
758
|
-
pub fn maybe_from_u64(value: u64, size: ScalarSize) -> Option<ASIMDFPModImm> {
|
759
|
-
// In all cases immediates are encoded as an 8-bit number 0b_abcdefgh;
|
760
|
-
// let `D` be the inverse of the digit `d`.
|
761
|
-
match size {
|
762
|
-
ScalarSize::Size32 => {
|
763
|
-
// In this case the representable immediates are 32-bit numbers of the form
|
764
|
-
// 0b_aBbb_bbbc_defg_h000 shifted to the left by 16.
|
765
|
-
let value = value as u32;
|
766
|
-
let b0_5 = (value >> 19) & 0b111111;
|
767
|
-
let b6 = (value >> 19) & (1 << 6);
|
768
|
-
let b7 = (value >> 24) & (1 << 7);
|
769
|
-
let imm = (b0_5 | b6 | b7) as u8;
|
770
|
-
|
771
|
-
if value == Self::value32(imm) {
|
772
|
-
Some(ASIMDFPModImm {
|
773
|
-
imm,
|
774
|
-
is_64bit: false,
|
775
|
-
})
|
776
|
-
} else {
|
777
|
-
None
|
778
|
-
}
|
779
|
-
}
|
780
|
-
ScalarSize::Size64 => {
|
781
|
-
// In this case the representable immediates are 64-bit numbers of the form
|
782
|
-
// 0b_aBbb_bbbb_bbcd_efgh shifted to the left by 48.
|
783
|
-
let b0_5 = (value >> 48) & 0b111111;
|
784
|
-
let b6 = (value >> 48) & (1 << 6);
|
785
|
-
let b7 = (value >> 56) & (1 << 7);
|
786
|
-
let imm = (b0_5 | b6 | b7) as u8;
|
787
|
-
|
788
|
-
if value == Self::value64(imm) {
|
789
|
-
Some(ASIMDFPModImm {
|
790
|
-
imm,
|
791
|
-
is_64bit: true,
|
792
|
-
})
|
793
|
-
} else {
|
794
|
-
None
|
795
|
-
}
|
796
|
-
}
|
797
|
-
_ => None,
|
798
|
-
}
|
799
|
-
}
|
800
|
-
|
801
|
-
/// Returns bits ready for encoding.
|
802
|
-
pub fn enc_bits(&self) -> u8 {
|
803
|
-
self.imm
|
804
|
-
}
|
805
|
-
|
806
|
-
/// Returns the 32-bit value that corresponds to an 8-bit encoding.
|
807
|
-
fn value32(imm: u8) -> u32 {
|
808
|
-
let imm = imm as u32;
|
809
|
-
let b0_5 = imm & 0b111111;
|
810
|
-
let b6 = (imm >> 6) & 1;
|
811
|
-
let b6_inv = b6 ^ 1;
|
812
|
-
let b7 = (imm >> 7) & 1;
|
813
|
-
|
814
|
-
b0_5 << 19 | (b6 * 0b11111) << 25 | b6_inv << 30 | b7 << 31
|
815
|
-
}
|
816
|
-
|
817
|
-
/// Returns the 64-bit value that corresponds to an 8-bit encoding.
|
818
|
-
fn value64(imm: u8) -> u64 {
|
819
|
-
let imm = imm as u64;
|
820
|
-
let b0_5 = imm & 0b111111;
|
821
|
-
let b6 = (imm >> 6) & 1;
|
822
|
-
let b6_inv = b6 ^ 1;
|
823
|
-
let b7 = (imm >> 7) & 1;
|
824
|
-
|
825
|
-
b0_5 << 48 | (b6 * 0b11111111) << 54 | b6_inv << 62 | b7 << 63
|
826
|
-
}
|
827
|
-
}
|
828
|
-
|
829
|
-
impl PrettyPrint for NZCV {
|
830
|
-
fn pretty_print(&self, _: u8, _: &mut AllocationConsumer) -> String {
|
831
|
-
let fmt = |c: char, v| if v { c.to_ascii_uppercase() } else { c };
|
832
|
-
format!(
|
833
|
-
"#{}{}{}{}",
|
834
|
-
fmt('n', self.n),
|
835
|
-
fmt('z', self.z),
|
836
|
-
fmt('c', self.c),
|
837
|
-
fmt('v', self.v)
|
838
|
-
)
|
839
|
-
}
|
840
|
-
}
|
841
|
-
|
842
|
-
impl PrettyPrint for UImm5 {
|
843
|
-
fn pretty_print(&self, _: u8, _: &mut AllocationConsumer) -> String {
|
844
|
-
format!("#{}", self.value)
|
845
|
-
}
|
846
|
-
}
|
847
|
-
|
848
|
-
impl PrettyPrint for Imm12 {
|
849
|
-
fn pretty_print(&self, _: u8, _: &mut AllocationConsumer) -> String {
|
850
|
-
let shift = if self.shift12 { 12 } else { 0 };
|
851
|
-
let value = u32::from(self.bits) << shift;
|
852
|
-
format!("#{}", value)
|
853
|
-
}
|
854
|
-
}
|
855
|
-
|
856
|
-
impl PrettyPrint for SImm7Scaled {
|
857
|
-
fn pretty_print(&self, _: u8, _: &mut AllocationConsumer) -> String {
|
858
|
-
format!("#{}", self.value)
|
859
|
-
}
|
860
|
-
}
|
861
|
-
|
862
|
-
impl PrettyPrint for FPULeftShiftImm {
|
863
|
-
fn pretty_print(&self, _: u8, _: &mut AllocationConsumer) -> String {
|
864
|
-
format!("#{}", self.amount)
|
865
|
-
}
|
866
|
-
}
|
867
|
-
|
868
|
-
impl PrettyPrint for FPURightShiftImm {
|
869
|
-
fn pretty_print(&self, _: u8, _: &mut AllocationConsumer) -> String {
|
870
|
-
format!("#{}", self.amount)
|
871
|
-
}
|
872
|
-
}
|
873
|
-
|
874
|
-
impl PrettyPrint for SImm9 {
|
875
|
-
fn pretty_print(&self, _: u8, _: &mut AllocationConsumer) -> String {
|
876
|
-
format!("#{}", self.value)
|
877
|
-
}
|
878
|
-
}
|
879
|
-
|
880
|
-
impl PrettyPrint for UImm12Scaled {
|
881
|
-
fn pretty_print(&self, _: u8, _: &mut AllocationConsumer) -> String {
|
882
|
-
format!("#{}", self.value)
|
883
|
-
}
|
884
|
-
}
|
885
|
-
|
886
|
-
impl PrettyPrint for ImmLogic {
|
887
|
-
fn pretty_print(&self, _: u8, _: &mut AllocationConsumer) -> String {
|
888
|
-
format!("#{}", self.value())
|
889
|
-
}
|
890
|
-
}
|
891
|
-
|
892
|
-
impl PrettyPrint for ImmShift {
|
893
|
-
fn pretty_print(&self, _: u8, _: &mut AllocationConsumer) -> String {
|
894
|
-
format!("#{}", self.imm)
|
895
|
-
}
|
896
|
-
}
|
897
|
-
|
898
|
-
impl PrettyPrint for MoveWideConst {
|
899
|
-
fn pretty_print(&self, _: u8, _: &mut AllocationConsumer) -> String {
|
900
|
-
if self.shift == 0 {
|
901
|
-
format!("#{}", self.bits)
|
902
|
-
} else {
|
903
|
-
format!("#{}, LSL #{}", self.bits, self.shift * 16)
|
904
|
-
}
|
905
|
-
}
|
906
|
-
}
|
907
|
-
|
908
|
-
impl PrettyPrint for ASIMDMovModImm {
|
909
|
-
fn pretty_print(&self, _: u8, _: &mut AllocationConsumer) -> String {
|
910
|
-
if self.is_64bit {
|
911
|
-
debug_assert_eq!(self.shift, 0);
|
912
|
-
|
913
|
-
let enc_imm = self.imm as i8;
|
914
|
-
let mut imm = 0u64;
|
915
|
-
|
916
|
-
for i in 0..8 {
|
917
|
-
let b = (enc_imm >> i) & 1;
|
918
|
-
|
919
|
-
imm |= (-b as u8 as u64) << (i * 8);
|
920
|
-
}
|
921
|
-
|
922
|
-
format!("#{}", imm)
|
923
|
-
} else if self.shift == 0 {
|
924
|
-
format!("#{}", self.imm)
|
925
|
-
} else {
|
926
|
-
let shift_type = if self.shift_ones { "MSL" } else { "LSL" };
|
927
|
-
format!("#{}, {} #{}", self.imm, shift_type, self.shift)
|
928
|
-
}
|
929
|
-
}
|
930
|
-
}
|
931
|
-
|
932
|
-
impl PrettyPrint for ASIMDFPModImm {
|
933
|
-
fn pretty_print(&self, _: u8, _: &mut AllocationConsumer) -> String {
|
934
|
-
if self.is_64bit {
|
935
|
-
format!("#{}", f64::from_bits(Self::value64(self.imm)))
|
936
|
-
} else {
|
937
|
-
format!("#{}", f32::from_bits(Self::value32(self.imm)))
|
938
|
-
}
|
939
|
-
}
|
940
|
-
}
|
941
|
-
|
942
|
-
#[cfg(test)]
|
943
|
-
mod test {
|
944
|
-
use super::*;
|
945
|
-
|
946
|
-
#[test]
|
947
|
-
fn imm_logical_test() {
|
948
|
-
assert_eq!(None, ImmLogic::maybe_from_u64(0, I64));
|
949
|
-
assert_eq!(None, ImmLogic::maybe_from_u64(u64::max_value(), I64));
|
950
|
-
|
951
|
-
assert_eq!(
|
952
|
-
Some(ImmLogic {
|
953
|
-
value: 1,
|
954
|
-
n: true,
|
955
|
-
r: 0,
|
956
|
-
s: 0,
|
957
|
-
size: OperandSize::Size64,
|
958
|
-
}),
|
959
|
-
ImmLogic::maybe_from_u64(1, I64)
|
960
|
-
);
|
961
|
-
|
962
|
-
assert_eq!(
|
963
|
-
Some(ImmLogic {
|
964
|
-
value: 2,
|
965
|
-
n: true,
|
966
|
-
r: 63,
|
967
|
-
s: 0,
|
968
|
-
size: OperandSize::Size64,
|
969
|
-
}),
|
970
|
-
ImmLogic::maybe_from_u64(2, I64)
|
971
|
-
);
|
972
|
-
|
973
|
-
assert_eq!(None, ImmLogic::maybe_from_u64(5, I64));
|
974
|
-
|
975
|
-
assert_eq!(None, ImmLogic::maybe_from_u64(11, I64));
|
976
|
-
|
977
|
-
assert_eq!(
|
978
|
-
Some(ImmLogic {
|
979
|
-
value: 248,
|
980
|
-
n: true,
|
981
|
-
r: 61,
|
982
|
-
s: 4,
|
983
|
-
size: OperandSize::Size64,
|
984
|
-
}),
|
985
|
-
ImmLogic::maybe_from_u64(248, I64)
|
986
|
-
);
|
987
|
-
|
988
|
-
assert_eq!(None, ImmLogic::maybe_from_u64(249, I64));
|
989
|
-
|
990
|
-
assert_eq!(
|
991
|
-
Some(ImmLogic {
|
992
|
-
value: 1920,
|
993
|
-
n: true,
|
994
|
-
r: 57,
|
995
|
-
s: 3,
|
996
|
-
size: OperandSize::Size64,
|
997
|
-
}),
|
998
|
-
ImmLogic::maybe_from_u64(1920, I64)
|
999
|
-
);
|
1000
|
-
|
1001
|
-
assert_eq!(
|
1002
|
-
Some(ImmLogic {
|
1003
|
-
value: 0x7ffe,
|
1004
|
-
n: true,
|
1005
|
-
r: 63,
|
1006
|
-
s: 13,
|
1007
|
-
size: OperandSize::Size64,
|
1008
|
-
}),
|
1009
|
-
ImmLogic::maybe_from_u64(0x7ffe, I64)
|
1010
|
-
);
|
1011
|
-
|
1012
|
-
assert_eq!(
|
1013
|
-
Some(ImmLogic {
|
1014
|
-
value: 0x30000,
|
1015
|
-
n: true,
|
1016
|
-
r: 48,
|
1017
|
-
s: 1,
|
1018
|
-
size: OperandSize::Size64,
|
1019
|
-
}),
|
1020
|
-
ImmLogic::maybe_from_u64(0x30000, I64)
|
1021
|
-
);
|
1022
|
-
|
1023
|
-
assert_eq!(
|
1024
|
-
Some(ImmLogic {
|
1025
|
-
value: 0x100000,
|
1026
|
-
n: true,
|
1027
|
-
r: 44,
|
1028
|
-
s: 0,
|
1029
|
-
size: OperandSize::Size64,
|
1030
|
-
}),
|
1031
|
-
ImmLogic::maybe_from_u64(0x100000, I64)
|
1032
|
-
);
|
1033
|
-
|
1034
|
-
assert_eq!(
|
1035
|
-
Some(ImmLogic {
|
1036
|
-
value: u64::max_value() - 1,
|
1037
|
-
n: true,
|
1038
|
-
r: 63,
|
1039
|
-
s: 62,
|
1040
|
-
size: OperandSize::Size64,
|
1041
|
-
}),
|
1042
|
-
ImmLogic::maybe_from_u64(u64::max_value() - 1, I64)
|
1043
|
-
);
|
1044
|
-
|
1045
|
-
assert_eq!(
|
1046
|
-
Some(ImmLogic {
|
1047
|
-
value: 0xaaaaaaaaaaaaaaaa,
|
1048
|
-
n: false,
|
1049
|
-
r: 1,
|
1050
|
-
s: 60,
|
1051
|
-
size: OperandSize::Size64,
|
1052
|
-
}),
|
1053
|
-
ImmLogic::maybe_from_u64(0xaaaaaaaaaaaaaaaa, I64)
|
1054
|
-
);
|
1055
|
-
|
1056
|
-
assert_eq!(
|
1057
|
-
Some(ImmLogic {
|
1058
|
-
value: 0x8181818181818181,
|
1059
|
-
n: false,
|
1060
|
-
r: 1,
|
1061
|
-
s: 49,
|
1062
|
-
size: OperandSize::Size64,
|
1063
|
-
}),
|
1064
|
-
ImmLogic::maybe_from_u64(0x8181818181818181, I64)
|
1065
|
-
);
|
1066
|
-
|
1067
|
-
assert_eq!(
|
1068
|
-
Some(ImmLogic {
|
1069
|
-
value: 0xffc3ffc3ffc3ffc3,
|
1070
|
-
n: false,
|
1071
|
-
r: 10,
|
1072
|
-
s: 43,
|
1073
|
-
size: OperandSize::Size64,
|
1074
|
-
}),
|
1075
|
-
ImmLogic::maybe_from_u64(0xffc3ffc3ffc3ffc3, I64)
|
1076
|
-
);
|
1077
|
-
|
1078
|
-
assert_eq!(
|
1079
|
-
Some(ImmLogic {
|
1080
|
-
value: 0x100000001,
|
1081
|
-
n: false,
|
1082
|
-
r: 0,
|
1083
|
-
s: 0,
|
1084
|
-
size: OperandSize::Size64,
|
1085
|
-
}),
|
1086
|
-
ImmLogic::maybe_from_u64(0x100000001, I64)
|
1087
|
-
);
|
1088
|
-
|
1089
|
-
assert_eq!(
|
1090
|
-
Some(ImmLogic {
|
1091
|
-
value: 0x1111111111111111,
|
1092
|
-
n: false,
|
1093
|
-
r: 0,
|
1094
|
-
s: 56,
|
1095
|
-
size: OperandSize::Size64,
|
1096
|
-
}),
|
1097
|
-
ImmLogic::maybe_from_u64(0x1111111111111111, I64)
|
1098
|
-
);
|
1099
|
-
|
1100
|
-
for n in 0..2 {
|
1101
|
-
let types = if n == 0 { vec![I64, I32] } else { vec![I64] };
|
1102
|
-
for s in 0..64 {
|
1103
|
-
for r in 0..64 {
|
1104
|
-
let imm = get_logical_imm(n, s, r);
|
1105
|
-
for &ty in &types {
|
1106
|
-
match ImmLogic::maybe_from_u64(imm, ty) {
|
1107
|
-
Some(ImmLogic { value, .. }) => {
|
1108
|
-
assert_eq!(imm, value);
|
1109
|
-
ImmLogic::maybe_from_u64(!value, ty).unwrap();
|
1110
|
-
}
|
1111
|
-
None => assert_eq!(0, imm),
|
1112
|
-
};
|
1113
|
-
}
|
1114
|
-
}
|
1115
|
-
}
|
1116
|
-
}
|
1117
|
-
}
|
1118
|
-
|
1119
|
-
// Repeat a value that has `width` bits, across a 64-bit value.
|
1120
|
-
fn repeat(value: u64, width: u64) -> u64 {
|
1121
|
-
let mut result = value & ((1 << width) - 1);
|
1122
|
-
let mut i = width;
|
1123
|
-
while i < 64 {
|
1124
|
-
result |= result << i;
|
1125
|
-
i *= 2;
|
1126
|
-
}
|
1127
|
-
result
|
1128
|
-
}
|
1129
|
-
|
1130
|
-
// Get the logical immediate, from the encoding N/R/S bits.
|
1131
|
-
fn get_logical_imm(n: u32, s: u32, r: u32) -> u64 {
|
1132
|
-
// An integer is constructed from the n, imm_s and imm_r bits according to
|
1133
|
-
// the following table:
|
1134
|
-
//
|
1135
|
-
// N imms immr size S R
|
1136
|
-
// 1 ssssss rrrrrr 64 UInt(ssssss) UInt(rrrrrr)
|
1137
|
-
// 0 0sssss xrrrrr 32 UInt(sssss) UInt(rrrrr)
|
1138
|
-
// 0 10ssss xxrrrr 16 UInt(ssss) UInt(rrrr)
|
1139
|
-
// 0 110sss xxxrrr 8 UInt(sss) UInt(rrr)
|
1140
|
-
// 0 1110ss xxxxrr 4 UInt(ss) UInt(rr)
|
1141
|
-
// 0 11110s xxxxxr 2 UInt(s) UInt(r)
|
1142
|
-
// (s bits must not be all set)
|
1143
|
-
//
|
1144
|
-
// A pattern is constructed of size bits, where the least significant S+1
|
1145
|
-
// bits are set. The pattern is rotated right by R, and repeated across a
|
1146
|
-
// 64-bit value.
|
1147
|
-
|
1148
|
-
if n == 1 {
|
1149
|
-
if s == 0x3f {
|
1150
|
-
return 0;
|
1151
|
-
}
|
1152
|
-
let bits = (1u64 << (s + 1)) - 1;
|
1153
|
-
bits.rotate_right(r)
|
1154
|
-
} else {
|
1155
|
-
if (s >> 1) == 0x1f {
|
1156
|
-
return 0;
|
1157
|
-
}
|
1158
|
-
let mut width = 0x20;
|
1159
|
-
while width >= 0x2 {
|
1160
|
-
if (s & width) == 0 {
|
1161
|
-
let mask = width - 1;
|
1162
|
-
if (s & mask) == mask {
|
1163
|
-
return 0;
|
1164
|
-
}
|
1165
|
-
let bits = (1u64 << ((s & mask) + 1)) - 1;
|
1166
|
-
return repeat(bits.rotate_right(r & mask), width.into());
|
1167
|
-
}
|
1168
|
-
width >>= 1;
|
1169
|
-
}
|
1170
|
-
unreachable!();
|
1171
|
-
}
|
1172
|
-
}
|
1173
|
-
|
1174
|
-
#[test]
|
1175
|
-
fn asimd_fp_mod_imm_test() {
|
1176
|
-
assert_eq!(None, ASIMDFPModImm::maybe_from_u64(0, ScalarSize::Size32));
|
1177
|
-
assert_eq!(
|
1178
|
-
None,
|
1179
|
-
ASIMDFPModImm::maybe_from_u64(0.013671875_f32.to_bits() as u64, ScalarSize::Size32)
|
1180
|
-
);
|
1181
|
-
assert_eq!(None, ASIMDFPModImm::maybe_from_u64(0, ScalarSize::Size64));
|
1182
|
-
assert_eq!(
|
1183
|
-
None,
|
1184
|
-
ASIMDFPModImm::maybe_from_u64(10000_f64.to_bits(), ScalarSize::Size64)
|
1185
|
-
);
|
1186
|
-
}
|
1187
|
-
|
1188
|
-
#[test]
|
1189
|
-
fn asimd_mov_mod_imm_test() {
|
1190
|
-
assert_eq!(
|
1191
|
-
None,
|
1192
|
-
ASIMDMovModImm::maybe_from_u64(513, ScalarSize::Size16)
|
1193
|
-
);
|
1194
|
-
assert_eq!(
|
1195
|
-
None,
|
1196
|
-
ASIMDMovModImm::maybe_from_u64(4278190335, ScalarSize::Size32)
|
1197
|
-
);
|
1198
|
-
assert_eq!(
|
1199
|
-
None,
|
1200
|
-
ASIMDMovModImm::maybe_from_u64(8388608, ScalarSize::Size64)
|
1201
|
-
);
|
1202
|
-
|
1203
|
-
assert_eq!(
|
1204
|
-
Some(ASIMDMovModImm {
|
1205
|
-
imm: 66,
|
1206
|
-
shift: 16,
|
1207
|
-
is_64bit: false,
|
1208
|
-
shift_ones: true,
|
1209
|
-
}),
|
1210
|
-
ASIMDMovModImm::maybe_from_u64(4390911, ScalarSize::Size32)
|
1211
|
-
);
|
1212
|
-
}
|
1213
|
-
}
|