wasmtime 22.0.0 → 23.0.2

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Files changed (2164) hide show
  1. checksums.yaml +4 -4
  2. data/Cargo.lock +127 -90
  3. data/ext/Cargo.toml +5 -5
  4. data/ext/cargo-vendor/cranelift-bforest-0.110.2/.cargo-checksum.json +1 -0
  5. data/ext/cargo-vendor/cranelift-bforest-0.110.2/Cargo.toml +50 -0
  6. data/ext/cargo-vendor/cranelift-bitset-0.110.2/.cargo-checksum.json +1 -0
  7. data/ext/cargo-vendor/cranelift-bitset-0.110.2/Cargo.toml +60 -0
  8. data/ext/cargo-vendor/cranelift-bitset-0.110.2/src/compound.rs +508 -0
  9. data/ext/cargo-vendor/cranelift-bitset-0.110.2/src/lib.rs +19 -0
  10. data/ext/cargo-vendor/cranelift-bitset-0.110.2/src/scalar.rs +575 -0
  11. data/ext/cargo-vendor/cranelift-bitset-0.110.2/tests/bitset.rs +78 -0
  12. data/ext/cargo-vendor/cranelift-codegen-0.110.2/.cargo-checksum.json +1 -0
  13. data/ext/cargo-vendor/cranelift-codegen-0.110.2/Cargo.toml +206 -0
  14. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/binemit/stack_map.rs +141 -0
  15. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/context.rs +390 -0
  16. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/data_value.rs +410 -0
  17. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/ir/dfg.rs +1806 -0
  18. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/ir/globalvalue.rs +147 -0
  19. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/ir/immediates.rs +2109 -0
  20. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/ir/instructions.rs +1015 -0
  21. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/ir/jumptable.rs +168 -0
  22. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/ir/mod.rs +110 -0
  23. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/ir/trapcode.rs +148 -0
  24. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/ir/types.rs +643 -0
  25. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/ir/user_stack_maps.rs +101 -0
  26. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/aarch64/inst/emit.rs +3605 -0
  27. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/aarch64/inst/emit_tests.rs +7927 -0
  28. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/aarch64/inst/mod.rs +3058 -0
  29. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/aarch64/inst.isle +4221 -0
  30. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/aarch64/lower.isle +2969 -0
  31. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/aarch64/mod.rs +259 -0
  32. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/mod.rs +462 -0
  33. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/riscv64/inst/emit.rs +2741 -0
  34. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/riscv64/inst/emit_tests.rs +2219 -0
  35. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/riscv64/inst/mod.rs +1935 -0
  36. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/riscv64/inst.isle +3153 -0
  37. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/riscv64/lower/isle.rs +654 -0
  38. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/riscv64/lower.isle +2953 -0
  39. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/riscv64/mod.rs +265 -0
  40. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/s390x/inst/emit.rs +3421 -0
  41. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/s390x/inst/mod.rs +3395 -0
  42. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/s390x/lower.isle +3983 -0
  43. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/s390x/mod.rs +220 -0
  44. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/x64/inst/emit.rs +4297 -0
  45. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/x64/inst/emit_state.rs +65 -0
  46. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/x64/inst/mod.rs +2818 -0
  47. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/x64/inst.isle +5299 -0
  48. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/x64/lower.isle +4819 -0
  49. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/x64/mod.rs +239 -0
  50. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isle_prelude.rs +965 -0
  51. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/legalizer/mod.rs +343 -0
  52. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/lib.rs +106 -0
  53. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/machinst/abi.rs +2427 -0
  54. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/machinst/buffer.rs +2544 -0
  55. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/machinst/helpers.rs +23 -0
  56. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/machinst/isle.rs +908 -0
  57. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/machinst/lower.rs +1462 -0
  58. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/machinst/mod.rs +564 -0
  59. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/machinst/vcode.rs +1840 -0
  60. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/prelude.isle +654 -0
  61. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/prelude_lower.isle +1070 -0
  62. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/write.rs +660 -0
  63. data/ext/cargo-vendor/cranelift-codegen-meta-0.110.2/.cargo-checksum.json +1 -0
  64. data/ext/cargo-vendor/cranelift-codegen-meta-0.110.2/Cargo.toml +45 -0
  65. data/ext/cargo-vendor/cranelift-codegen-meta-0.110.2/src/cdsl/types.rs +512 -0
  66. data/ext/cargo-vendor/cranelift-codegen-meta-0.110.2/src/cdsl/typevar.rs +980 -0
  67. data/ext/cargo-vendor/cranelift-codegen-meta-0.110.2/src/gen_inst.rs +1278 -0
  68. data/ext/cargo-vendor/cranelift-codegen-meta-0.110.2/src/shared/instructions.rs +3760 -0
  69. data/ext/cargo-vendor/cranelift-codegen-meta-0.110.2/src/shared/types.rs +143 -0
  70. data/ext/cargo-vendor/cranelift-codegen-shared-0.110.2/.cargo-checksum.json +1 -0
  71. data/ext/cargo-vendor/cranelift-codegen-shared-0.110.2/Cargo.toml +31 -0
  72. data/ext/cargo-vendor/cranelift-control-0.110.2/.cargo-checksum.json +1 -0
  73. data/ext/cargo-vendor/cranelift-control-0.110.2/Cargo.toml +39 -0
  74. data/ext/cargo-vendor/cranelift-entity-0.110.2/.cargo-checksum.json +1 -0
  75. data/ext/cargo-vendor/cranelift-entity-0.110.2/Cargo.toml +66 -0
  76. data/ext/cargo-vendor/cranelift-entity-0.110.2/src/set.rs +193 -0
  77. data/ext/cargo-vendor/cranelift-frontend-0.110.2/.cargo-checksum.json +1 -0
  78. data/ext/cargo-vendor/cranelift-frontend-0.110.2/Cargo.toml +87 -0
  79. data/ext/cargo-vendor/cranelift-frontend-0.110.2/src/frontend.rs +2867 -0
  80. data/ext/cargo-vendor/cranelift-isle-0.110.2/.cargo-checksum.json +1 -0
  81. data/ext/cargo-vendor/cranelift-isle-0.110.2/Cargo.toml +60 -0
  82. data/ext/cargo-vendor/cranelift-isle-0.110.2/src/codegen.rs +920 -0
  83. data/ext/cargo-vendor/cranelift-isle-0.110.2/src/parser.rs +562 -0
  84. data/ext/cargo-vendor/cranelift-isle-0.110.2/src/sema.rs +2503 -0
  85. data/ext/cargo-vendor/cranelift-isle-0.110.2/src/trie_again.rs +695 -0
  86. data/ext/cargo-vendor/cranelift-native-0.110.2/.cargo-checksum.json +1 -0
  87. data/ext/cargo-vendor/cranelift-native-0.110.2/Cargo.toml +52 -0
  88. data/ext/cargo-vendor/cranelift-native-0.110.2/src/lib.rs +188 -0
  89. data/ext/cargo-vendor/cranelift-wasm-0.110.2/.cargo-checksum.json +1 -0
  90. data/ext/cargo-vendor/cranelift-wasm-0.110.2/Cargo.toml +119 -0
  91. data/ext/cargo-vendor/cranelift-wasm-0.110.2/src/code_translator/bounds_checks.rs +731 -0
  92. data/ext/cargo-vendor/cranelift-wasm-0.110.2/src/code_translator.rs +3694 -0
  93. data/ext/cargo-vendor/cranelift-wasm-0.110.2/src/heap.rs +119 -0
  94. data/ext/cargo-vendor/cranelift-wasm-0.110.2/src/sections_translator.rs +333 -0
  95. data/ext/cargo-vendor/deterministic-wasi-ctx-0.1.23/.cargo-checksum.json +1 -0
  96. data/ext/cargo-vendor/deterministic-wasi-ctx-0.1.23/Cargo.toml +69 -0
  97. data/ext/cargo-vendor/termcolor-1.4.1/.cargo-checksum.json +1 -0
  98. data/ext/cargo-vendor/termcolor-1.4.1/COPYING +3 -0
  99. data/ext/cargo-vendor/termcolor-1.4.1/Cargo.toml +40 -0
  100. data/ext/cargo-vendor/termcolor-1.4.1/LICENSE-MIT +21 -0
  101. data/ext/cargo-vendor/termcolor-1.4.1/README.md +110 -0
  102. data/ext/cargo-vendor/termcolor-1.4.1/UNLICENSE +24 -0
  103. data/ext/cargo-vendor/termcolor-1.4.1/rustfmt.toml +2 -0
  104. data/ext/cargo-vendor/termcolor-1.4.1/src/lib.rs +2572 -0
  105. data/ext/cargo-vendor/wasi-common-23.0.2/.cargo-checksum.json +1 -0
  106. data/ext/cargo-vendor/wasi-common-23.0.2/Cargo.toml +234 -0
  107. data/ext/cargo-vendor/wasi-common-23.0.2/src/tokio/mod.rs +135 -0
  108. data/ext/cargo-vendor/wasi-common-23.0.2/tests/all/async_.rs +295 -0
  109. data/ext/cargo-vendor/wasi-common-23.0.2/tests/all/sync.rs +284 -0
  110. data/ext/cargo-vendor/wasm-encoder-0.212.0/.cargo-checksum.json +1 -0
  111. data/ext/cargo-vendor/wasm-encoder-0.212.0/Cargo.toml +49 -0
  112. data/ext/cargo-vendor/wasm-encoder-0.212.0/src/component/types.rs +771 -0
  113. data/ext/cargo-vendor/wasm-encoder-0.212.0/src/core/code.rs +3571 -0
  114. data/ext/cargo-vendor/wasm-encoder-0.212.0/src/core/exports.rs +85 -0
  115. data/ext/cargo-vendor/wasm-encoder-0.212.0/src/core/globals.rs +100 -0
  116. data/ext/cargo-vendor/wasm-encoder-0.212.0/src/core/imports.rs +143 -0
  117. data/ext/cargo-vendor/wasm-encoder-0.212.0/src/core/memories.rs +115 -0
  118. data/ext/cargo-vendor/wasm-encoder-0.212.0/src/core/tables.rs +121 -0
  119. data/ext/cargo-vendor/wasm-encoder-0.212.0/src/core/tags.rs +85 -0
  120. data/ext/cargo-vendor/wasm-encoder-0.212.0/src/core/types.rs +663 -0
  121. data/ext/cargo-vendor/wasm-encoder-0.212.0/src/lib.rs +218 -0
  122. data/ext/cargo-vendor/wasm-encoder-0.212.0/src/reencode.rs +1804 -0
  123. data/ext/cargo-vendor/wasm-encoder-0.215.0/.cargo-checksum.json +1 -0
  124. data/ext/cargo-vendor/wasm-encoder-0.215.0/Cargo.toml +65 -0
  125. data/ext/cargo-vendor/wasm-encoder-0.215.0/README.md +80 -0
  126. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/component/aliases.rs +160 -0
  127. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/component/builder.rs +455 -0
  128. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/component/canonicals.rs +159 -0
  129. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/component/components.rs +29 -0
  130. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/component/exports.rs +124 -0
  131. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/component/imports.rs +175 -0
  132. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/component/instances.rs +200 -0
  133. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/component/modules.rs +29 -0
  134. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/component/names.rs +149 -0
  135. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/component/start.rs +52 -0
  136. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/component/types.rs +802 -0
  137. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/component.rs +168 -0
  138. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/core/code.rs +3947 -0
  139. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/core/custom.rs +73 -0
  140. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/core/data.rs +186 -0
  141. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/core/dump.rs +627 -0
  142. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/core/elements.rs +222 -0
  143. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/core/exports.rs +85 -0
  144. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/core/functions.rs +63 -0
  145. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/core/globals.rs +100 -0
  146. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/core/imports.rs +143 -0
  147. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/core/linking.rs +263 -0
  148. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/core/memories.rs +115 -0
  149. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/core/names.rs +298 -0
  150. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/core/producers.rs +181 -0
  151. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/core/start.rs +39 -0
  152. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/core/tables.rs +129 -0
  153. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/core/tags.rs +85 -0
  154. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/core/types.rs +678 -0
  155. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/core.rs +168 -0
  156. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/lib.rs +218 -0
  157. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/raw.rs +30 -0
  158. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/reencode.rs +2002 -0
  159. data/ext/cargo-vendor/wasmparser-0.212.0/.cargo-checksum.json +1 -0
  160. data/ext/cargo-vendor/wasmparser-0.212.0/Cargo.lock +669 -0
  161. data/ext/cargo-vendor/wasmparser-0.212.0/Cargo.toml +112 -0
  162. data/ext/cargo-vendor/wasmparser-0.212.0/src/binary_reader.rs +1968 -0
  163. data/ext/cargo-vendor/wasmparser-0.212.0/src/features.rs +166 -0
  164. data/ext/cargo-vendor/wasmparser-0.212.0/src/lib.rs +814 -0
  165. data/ext/cargo-vendor/wasmparser-0.212.0/src/parser.rs +1682 -0
  166. data/ext/cargo-vendor/wasmparser-0.212.0/src/readers/core/operators.rs +453 -0
  167. data/ext/cargo-vendor/wasmparser-0.212.0/src/readers/core/tables.rs +93 -0
  168. data/ext/cargo-vendor/wasmparser-0.212.0/src/readers/core/types.rs +1941 -0
  169. data/ext/cargo-vendor/wasmparser-0.212.0/src/resources.rs +234 -0
  170. data/ext/cargo-vendor/wasmparser-0.212.0/src/validator/component.rs +3252 -0
  171. data/ext/cargo-vendor/wasmparser-0.212.0/src/validator/core.rs +1454 -0
  172. data/ext/cargo-vendor/wasmparser-0.212.0/src/validator/operators.rs +4230 -0
  173. data/ext/cargo-vendor/wasmparser-0.212.0/src/validator/types.rs +4598 -0
  174. data/ext/cargo-vendor/wasmparser-0.212.0/src/validator.rs +1632 -0
  175. data/ext/cargo-vendor/wasmprinter-0.212.0/.cargo-checksum.json +1 -0
  176. data/ext/cargo-vendor/wasmprinter-0.212.0/Cargo.toml +54 -0
  177. data/ext/cargo-vendor/wasmprinter-0.212.0/src/lib.rs +3221 -0
  178. data/ext/cargo-vendor/wasmprinter-0.212.0/src/operator.rs +1189 -0
  179. data/ext/cargo-vendor/wasmprinter-0.212.0/src/print.rs +190 -0
  180. data/ext/cargo-vendor/wasmprinter-0.212.0/tests/all.rs +48 -0
  181. data/ext/cargo-vendor/wasmtime-23.0.2/.cargo-checksum.json +1 -0
  182. data/ext/cargo-vendor/wasmtime-23.0.2/Cargo.toml +399 -0
  183. data/ext/cargo-vendor/wasmtime-23.0.2/build.rs +38 -0
  184. data/ext/cargo-vendor/wasmtime-23.0.2/src/compile/code_builder.rs +274 -0
  185. data/ext/cargo-vendor/wasmtime-23.0.2/src/compile/runtime.rs +167 -0
  186. data/ext/cargo-vendor/wasmtime-23.0.2/src/compile.rs +881 -0
  187. data/ext/cargo-vendor/wasmtime-23.0.2/src/config.rs +2902 -0
  188. data/ext/cargo-vendor/wasmtime-23.0.2/src/engine/serialization.rs +893 -0
  189. data/ext/cargo-vendor/wasmtime-23.0.2/src/engine.rs +719 -0
  190. data/ext/cargo-vendor/wasmtime-23.0.2/src/lib.rs +406 -0
  191. data/ext/cargo-vendor/wasmtime-23.0.2/src/profiling_agent/jitdump.rs +65 -0
  192. data/ext/cargo-vendor/wasmtime-23.0.2/src/profiling_agent/perfmap.rs +47 -0
  193. data/ext/cargo-vendor/wasmtime-23.0.2/src/profiling_agent/vtune.rs +80 -0
  194. data/ext/cargo-vendor/wasmtime-23.0.2/src/profiling_agent.rs +104 -0
  195. data/ext/cargo-vendor/wasmtime-23.0.2/src/runtime/code_memory.rs +337 -0
  196. data/ext/cargo-vendor/wasmtime-23.0.2/src/runtime/component/bindgen_examples/mod.rs +488 -0
  197. data/ext/cargo-vendor/wasmtime-23.0.2/src/runtime/component/component.rs +811 -0
  198. data/ext/cargo-vendor/wasmtime-23.0.2/src/runtime/component/func/host.rs +439 -0
  199. data/ext/cargo-vendor/wasmtime-23.0.2/src/runtime/component/func/options.rs +552 -0
  200. data/ext/cargo-vendor/wasmtime-23.0.2/src/runtime/component/func/typed.rs +2497 -0
  201. data/ext/cargo-vendor/wasmtime-23.0.2/src/runtime/component/func.rs +688 -0
  202. data/ext/cargo-vendor/wasmtime-23.0.2/src/runtime/component/instance.rs +846 -0
  203. data/ext/cargo-vendor/wasmtime-23.0.2/src/runtime/component/linker.rs +673 -0
  204. data/ext/cargo-vendor/wasmtime-23.0.2/src/runtime/component/matching.rs +216 -0
  205. data/ext/cargo-vendor/wasmtime-23.0.2/src/runtime/component/mod.rs +663 -0
  206. data/ext/cargo-vendor/wasmtime-23.0.2/src/runtime/component/resources.rs +1132 -0
  207. data/ext/cargo-vendor/wasmtime-23.0.2/src/runtime/component/values.rs +979 -0
  208. data/ext/cargo-vendor/wasmtime-23.0.2/src/runtime/coredump.rs +339 -0
  209. data/ext/cargo-vendor/wasmtime-23.0.2/src/runtime/debug.rs +165 -0
  210. data/ext/cargo-vendor/wasmtime-23.0.2/src/runtime/externals/global.rs +310 -0
  211. data/ext/cargo-vendor/wasmtime-23.0.2/src/runtime/externals/table.rs +480 -0
  212. data/ext/cargo-vendor/wasmtime-23.0.2/src/runtime/func/typed.rs +788 -0
  213. data/ext/cargo-vendor/wasmtime-23.0.2/src/runtime/func.rs +2593 -0
  214. data/ext/cargo-vendor/wasmtime-23.0.2/src/runtime/gc/disabled/rooting.rs +224 -0
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  1008. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/riscv64/inst/encode.rs +0 -0
  1009. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/riscv64/inst/imms.rs +0 -0
  1010. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/riscv64/inst/regs.rs +0 -0
  1011. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/riscv64/inst/unwind/systemv.rs +0 -0
  1012. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/riscv64/inst/unwind.rs +0 -0
  1013. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/riscv64/inst/vector.rs +0 -0
  1014. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/riscv64/inst_vector.isle +0 -0
  1015. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/riscv64/lower/isle/generated_code.rs +0 -0
  1016. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/riscv64/lower.rs +0 -0
  1017. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/riscv64/settings.rs +0 -0
  1018. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/s390x/abi.rs +0 -0
  1019. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/s390x/inst/args.rs +0 -0
  1020. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/s390x/inst/emit_tests.rs +0 -0
  1021. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/s390x/inst/imms.rs +0 -0
  1022. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/s390x/inst/regs.rs +0 -0
  1023. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/s390x/inst/unwind/systemv.rs +0 -0
  1024. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/s390x/inst/unwind.rs +0 -0
  1025. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/s390x/inst.isle +0 -0
  1026. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/s390x/lower/isle/generated_code.rs +0 -0
  1027. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/s390x/lower/isle.rs +0 -0
  1028. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/s390x/lower.rs +0 -0
  1029. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/s390x/settings.rs +0 -0
  1030. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/unwind/systemv.rs +0 -0
  1031. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/unwind/winx64.rs +0 -0
  1032. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/unwind.rs +0 -0
  1033. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/x64/abi.rs +0 -0
  1034. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/x64/encoding/evex.rs +0 -0
  1035. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/x64/encoding/mod.rs +0 -0
  1036. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/x64/encoding/rex.rs +0 -0
  1037. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/x64/encoding/vex.rs +0 -0
  1038. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/x64/inst/args.rs +0 -0
  1039. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/x64/inst/emit_tests.rs +0 -0
  1040. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/x64/inst/regs.rs +0 -0
  1041. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/x64/inst/unwind/systemv.rs +0 -0
  1042. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/x64/inst/unwind/winx64.rs +0 -0
  1043. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/x64/inst/unwind.rs +0 -0
  1044. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/x64/lower/isle/generated_code.rs +0 -0
  1045. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/x64/lower/isle.rs +0 -0
  1046. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/x64/lower.rs +0 -0
  1047. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/x64/pcc.rs +0 -0
  1048. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/x64/settings.rs +0 -0
  1049. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/iterators.rs +0 -0
  1050. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/legalizer/globalvalue.rs +0 -0
  1051. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/loop_analysis.rs +0 -0
  1052. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/machinst/blockorder.rs +0 -0
  1053. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/machinst/compile.rs +0 -0
  1054. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/machinst/inst_common.rs +0 -0
  1055. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/machinst/pcc.rs +0 -0
  1056. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/machinst/reg.rs +0 -0
  1057. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/machinst/valueregs.rs +0 -0
  1058. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/nan_canonicalization.rs +0 -0
  1059. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/opts/README.md +0 -0
  1060. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/opts/arithmetic.isle +0 -0
  1061. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/opts/bitops.isle +0 -0
  1062. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/opts/cprop.isle +0 -0
  1063. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/opts/extends.isle +0 -0
  1064. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/opts/generated_code.rs +0 -0
  1065. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/opts/icmp.isle +0 -0
  1066. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/opts/remat.isle +0 -0
  1067. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/opts/selects.isle +0 -0
  1068. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/opts/shifts.isle +0 -0
  1069. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/opts/spaceship.isle +0 -0
  1070. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/opts/spectre.isle +0 -0
  1071. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/opts/vector.isle +0 -0
  1072. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/opts.rs +0 -0
  1073. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/prelude_opt.isle +0 -0
  1074. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/print_errors.rs +0 -0
  1075. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/ranges.rs +0 -0
  1076. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/remove_constant_phis.rs +0 -0
  1077. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/result.rs +0 -0
  1078. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/scoped_hash_map.rs +0 -0
  1079. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/settings.rs +0 -0
  1080. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/souper_harvest.rs +0 -0
  1081. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/timing.rs +0 -0
  1082. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/traversals.rs +0 -0
  1083. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/unionfind.rs +0 -0
  1084. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/unreachable_code.rs +0 -0
  1085. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/value_label.rs +0 -0
  1086. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/verifier/mod.rs +0 -0
  1087. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/LICENSE +0 -0
  1088. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/README.md +0 -0
  1089. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/src/cdsl/formats.rs +0 -0
  1090. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/src/cdsl/instructions.rs +0 -0
  1091. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/src/cdsl/isa.rs +0 -0
  1092. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/src/cdsl/mod.rs +0 -0
  1093. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/src/cdsl/operands.rs +0 -0
  1094. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/src/cdsl/settings.rs +0 -0
  1095. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/src/constant_hash.rs +0 -0
  1096. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/src/error.rs +0 -0
  1097. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/src/gen_isle.rs +0 -0
  1098. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/src/gen_settings.rs +0 -0
  1099. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/src/gen_types.rs +0 -0
  1100. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/src/isa/arm64.rs +0 -0
  1101. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/src/isa/mod.rs +0 -0
  1102. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/src/isa/riscv64.rs +0 -0
  1103. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/src/isa/s390x.rs +0 -0
  1104. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/src/isa/x86.rs +0 -0
  1105. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/src/isle.rs +0 -0
  1106. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/src/lib.rs +0 -0
  1107. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/src/shared/entities.rs +0 -0
  1108. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/src/shared/formats.rs +0 -0
  1109. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/src/shared/immediates.rs +0 -0
  1110. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/src/shared/mod.rs +0 -0
  1111. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/src/shared/settings.rs +0 -0
  1112. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/src/srcgen.rs +0 -0
  1113. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/src/unique_table.rs +0 -0
  1114. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.109.0 → cranelift-codegen-shared-0.110.2}/LICENSE +0 -0
  1115. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.109.0 → cranelift-codegen-shared-0.110.2}/README.md +0 -0
  1116. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.109.0 → cranelift-codegen-shared-0.110.2}/src/constant_hash.rs +0 -0
  1117. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.109.0 → cranelift-codegen-shared-0.110.2}/src/constants.rs +0 -0
  1118. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.109.0 → cranelift-codegen-shared-0.110.2}/src/lib.rs +0 -0
  1119. /data/ext/cargo-vendor/{cranelift-control-0.109.0 → cranelift-control-0.110.2}/LICENSE +0 -0
  1120. /data/ext/cargo-vendor/{cranelift-control-0.109.0 → cranelift-control-0.110.2}/README.md +0 -0
  1121. /data/ext/cargo-vendor/{cranelift-control-0.109.0 → cranelift-control-0.110.2}/src/chaos.rs +0 -0
  1122. /data/ext/cargo-vendor/{cranelift-control-0.109.0 → cranelift-control-0.110.2}/src/lib.rs +0 -0
  1123. /data/ext/cargo-vendor/{cranelift-control-0.109.0 → cranelift-control-0.110.2}/src/zero_sized.rs +0 -0
  1124. /data/ext/cargo-vendor/{cranelift-entity-0.109.0 → cranelift-entity-0.110.2}/LICENSE +0 -0
  1125. /data/ext/cargo-vendor/{cranelift-entity-0.109.0 → cranelift-entity-0.110.2}/README.md +0 -0
  1126. /data/ext/cargo-vendor/{cranelift-entity-0.109.0 → cranelift-entity-0.110.2}/src/boxed_slice.rs +0 -0
  1127. /data/ext/cargo-vendor/{cranelift-entity-0.109.0 → cranelift-entity-0.110.2}/src/iter.rs +0 -0
  1128. /data/ext/cargo-vendor/{cranelift-entity-0.109.0 → cranelift-entity-0.110.2}/src/keys.rs +0 -0
  1129. /data/ext/cargo-vendor/{cranelift-entity-0.109.0 → cranelift-entity-0.110.2}/src/lib.rs +0 -0
  1130. /data/ext/cargo-vendor/{cranelift-entity-0.109.0 → cranelift-entity-0.110.2}/src/list.rs +0 -0
  1131. /data/ext/cargo-vendor/{cranelift-entity-0.109.0 → cranelift-entity-0.110.2}/src/map.rs +0 -0
  1132. /data/ext/cargo-vendor/{cranelift-entity-0.109.0 → cranelift-entity-0.110.2}/src/packed_option.rs +0 -0
  1133. /data/ext/cargo-vendor/{cranelift-entity-0.109.0 → cranelift-entity-0.110.2}/src/primary.rs +0 -0
  1134. /data/ext/cargo-vendor/{cranelift-entity-0.109.0 → cranelift-entity-0.110.2}/src/sparse.rs +0 -0
  1135. /data/ext/cargo-vendor/{cranelift-entity-0.109.0 → cranelift-entity-0.110.2}/src/unsigned.rs +0 -0
  1136. /data/ext/cargo-vendor/{cranelift-frontend-0.109.0 → cranelift-frontend-0.110.2}/LICENSE +0 -0
  1137. /data/ext/cargo-vendor/{cranelift-frontend-0.109.0 → cranelift-frontend-0.110.2}/README.md +0 -0
  1138. /data/ext/cargo-vendor/{cranelift-frontend-0.109.0 → cranelift-frontend-0.110.2}/src/lib.rs +0 -0
  1139. /data/ext/cargo-vendor/{cranelift-frontend-0.109.0 → cranelift-frontend-0.110.2}/src/ssa.rs +0 -0
  1140. /data/ext/cargo-vendor/{cranelift-frontend-0.109.0 → cranelift-frontend-0.110.2}/src/switch.rs +0 -0
  1141. /data/ext/cargo-vendor/{cranelift-frontend-0.109.0 → cranelift-frontend-0.110.2}/src/variable.rs +0 -0
  1142. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/README.md +0 -0
  1143. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/build.rs +0 -0
  1144. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/fail/bad_converters.isle +0 -0
  1145. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/fail/bound_var_type_mismatch.isle +0 -0
  1146. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/fail/converter_extractor_constructor.isle +0 -0
  1147. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/fail/error1.isle +0 -0
  1148. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/fail/extra_parens.isle +0 -0
  1149. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/fail/impure_expression.isle +0 -0
  1150. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/fail/impure_rhs.isle +0 -0
  1151. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/fail/multi_internal_etor.isle +0 -0
  1152. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/fail/multi_prio.isle +0 -0
  1153. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/link/borrows.isle +0 -0
  1154. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/link/borrows_main.rs +0 -0
  1155. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/link/iflets.isle +0 -0
  1156. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/link/iflets_main.rs +0 -0
  1157. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/link/multi_constructor.isle +0 -0
  1158. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/link/multi_constructor_main.rs +0 -0
  1159. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/link/multi_extractor.isle +0 -0
  1160. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/link/multi_extractor_main.rs +0 -0
  1161. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/link/test.isle +0 -0
  1162. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/link/test_main.rs +0 -0
  1163. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/pass/bound_var.isle +0 -0
  1164. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/pass/construct_and_extract.isle +0 -0
  1165. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/pass/conversions.isle +0 -0
  1166. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/pass/conversions_extern.isle +0 -0
  1167. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/pass/let.isle +0 -0
  1168. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/pass/nodebug.isle +0 -0
  1169. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/pass/prio_trie_bug.isle +0 -0
  1170. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/pass/test2.isle +0 -0
  1171. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/pass/test3.isle +0 -0
  1172. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/pass/test4.isle +0 -0
  1173. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/pass/tutorial.isle +0 -0
  1174. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/run/iconst.isle +0 -0
  1175. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/run/iconst_main.rs +0 -0
  1176. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/run/let_shadowing.isle +0 -0
  1177. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/run/let_shadowing_main.rs +0 -0
  1178. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/src/ast.rs +0 -0
  1179. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/src/compile.rs +0 -0
  1180. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/src/disjointsets.rs +0 -0
  1181. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/src/error.rs +0 -0
  1182. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/src/lexer.rs +0 -0
  1183. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/src/lib.rs +0 -0
  1184. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/src/log.rs +0 -0
  1185. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/src/overlap.rs +0 -0
  1186. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/src/serialize.rs +0 -0
  1187. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/src/stablemapset.rs +0 -0
  1188. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/tests/run_tests.rs +0 -0
  1189. /data/ext/cargo-vendor/{cranelift-native-0.109.0 → cranelift-native-0.110.2}/LICENSE +0 -0
  1190. /data/ext/cargo-vendor/{cranelift-native-0.109.0 → cranelift-native-0.110.2}/README.md +0 -0
  1191. /data/ext/cargo-vendor/{cranelift-native-0.109.0 → cranelift-native-0.110.2}/src/riscv.rs +0 -0
  1192. /data/ext/cargo-vendor/{cranelift-wasm-0.109.0 → cranelift-wasm-0.110.2}/LICENSE +0 -0
  1193. /data/ext/cargo-vendor/{cranelift-wasm-0.109.0 → cranelift-wasm-0.110.2}/README.md +0 -0
  1194. /data/ext/cargo-vendor/{cranelift-wasm-0.109.0 → cranelift-wasm-0.110.2}/src/environ/dummy.rs +0 -0
  1195. /data/ext/cargo-vendor/{cranelift-wasm-0.109.0 → cranelift-wasm-0.110.2}/src/environ/mod.rs +0 -0
  1196. /data/ext/cargo-vendor/{cranelift-wasm-0.109.0 → cranelift-wasm-0.110.2}/src/environ/spec.rs +0 -0
  1197. /data/ext/cargo-vendor/{cranelift-wasm-0.109.0 → cranelift-wasm-0.110.2}/src/func_translator.rs +0 -0
  1198. /data/ext/cargo-vendor/{cranelift-wasm-0.109.0 → cranelift-wasm-0.110.2}/src/lib.rs +0 -0
  1199. /data/ext/cargo-vendor/{cranelift-wasm-0.109.0 → cranelift-wasm-0.110.2}/src/module_translator.rs +0 -0
  1200. /data/ext/cargo-vendor/{cranelift-wasm-0.109.0 → cranelift-wasm-0.110.2}/src/state.rs +0 -0
  1201. /data/ext/cargo-vendor/{cranelift-wasm-0.109.0 → cranelift-wasm-0.110.2}/src/table.rs +0 -0
  1202. /data/ext/cargo-vendor/{cranelift-wasm-0.109.0 → cranelift-wasm-0.110.2}/src/translation_utils.rs +0 -0
  1203. /data/ext/cargo-vendor/{deterministic-wasi-ctx-0.1.22 → deterministic-wasi-ctx-0.1.23}/README.md +0 -0
  1204. /data/ext/cargo-vendor/{deterministic-wasi-ctx-0.1.22 → deterministic-wasi-ctx-0.1.23}/src/clocks.rs +0 -0
  1205. /data/ext/cargo-vendor/{deterministic-wasi-ctx-0.1.22 → deterministic-wasi-ctx-0.1.23}/src/lib.rs +0 -0
  1206. /data/ext/cargo-vendor/{deterministic-wasi-ctx-0.1.22 → deterministic-wasi-ctx-0.1.23}/src/noop_scheduler.rs +0 -0
  1207. /data/ext/cargo-vendor/{deterministic-wasi-ctx-0.1.22 → deterministic-wasi-ctx-0.1.23}/tests/clocks.rs +0 -0
  1208. /data/ext/cargo-vendor/{deterministic-wasi-ctx-0.1.22 → deterministic-wasi-ctx-0.1.23}/tests/common/mod.rs +0 -0
  1209. /data/ext/cargo-vendor/{deterministic-wasi-ctx-0.1.22 → deterministic-wasi-ctx-0.1.23}/tests/random.rs +0 -0
  1210. /data/ext/cargo-vendor/{deterministic-wasi-ctx-0.1.22 → deterministic-wasi-ctx-0.1.23}/tests/scheduler.rs +0 -0
  1211. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/LICENSE +0 -0
  1212. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/README.md +0 -0
  1213. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/clocks.rs +0 -0
  1214. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/ctx.rs +0 -0
  1215. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/dir.rs +0 -0
  1216. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/error.rs +0 -0
  1217. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/file.rs +0 -0
  1218. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/lib.rs +0 -0
  1219. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/pipe.rs +0 -0
  1220. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/random.rs +0 -0
  1221. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/sched/subscription.rs +0 -0
  1222. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/sched.rs +0 -0
  1223. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/snapshots/mod.rs +0 -0
  1224. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/snapshots/preview_0.rs +0 -0
  1225. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/snapshots/preview_1/error.rs +0 -0
  1226. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/snapshots/preview_1.rs +0 -0
  1227. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/string_array.rs +0 -0
  1228. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/sync/clocks.rs +0 -0
  1229. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/sync/dir.rs +0 -0
  1230. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/sync/file.rs +0 -0
  1231. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/sync/mod.rs +0 -0
  1232. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/sync/net.rs +0 -0
  1233. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/sync/sched/unix.rs +0 -0
  1234. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/sync/sched/windows.rs +0 -0
  1235. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/sync/sched.rs +0 -0
  1236. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/sync/stdio.rs +0 -0
  1237. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/table.rs +0 -0
  1238. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/tokio/dir.rs +0 -0
  1239. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/tokio/file.rs +0 -0
  1240. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/tokio/net.rs +0 -0
  1241. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/tokio/sched/unix.rs +0 -0
  1242. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/tokio/sched/windows.rs +0 -0
  1243. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/tokio/sched.rs +0 -0
  1244. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/tokio/stdio.rs +0 -0
  1245. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/tests/all/main.rs +0 -0
  1246. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/witx/preview0/typenames.witx +0 -0
  1247. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/witx/preview0/wasi_unstable.witx +0 -0
  1248. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/witx/preview1/typenames.witx +0 -0
  1249. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/witx/preview1/wasi_snapshot_preview1.witx +0 -0
  1250. /data/ext/cargo-vendor/{wasm-encoder-0.209.1 → wasm-encoder-0.212.0}/LICENSE +0 -0
  1251. /data/ext/cargo-vendor/{wasm-encoder-0.209.1 → wasm-encoder-0.212.0}/README.md +0 -0
  1252. /data/ext/cargo-vendor/{wasm-encoder-0.209.1 → wasm-encoder-0.212.0}/src/component/aliases.rs +0 -0
  1253. /data/ext/cargo-vendor/{wasm-encoder-0.209.1 → wasm-encoder-0.212.0}/src/component/builder.rs +0 -0
  1254. /data/ext/cargo-vendor/{wasm-encoder-0.209.1 → wasm-encoder-0.212.0}/src/component/canonicals.rs +0 -0
  1255. /data/ext/cargo-vendor/{wasm-encoder-0.209.1 → wasm-encoder-0.212.0}/src/component/components.rs +0 -0
  1256. /data/ext/cargo-vendor/{wasm-encoder-0.209.1 → wasm-encoder-0.212.0}/src/component/exports.rs +0 -0
  1257. /data/ext/cargo-vendor/{wasm-encoder-0.209.1 → wasm-encoder-0.212.0}/src/component/imports.rs +0 -0
  1258. /data/ext/cargo-vendor/{wasm-encoder-0.209.1 → wasm-encoder-0.212.0}/src/component/instances.rs +0 -0
  1259. /data/ext/cargo-vendor/{wasm-encoder-0.209.1 → wasm-encoder-0.212.0}/src/component/modules.rs +0 -0
  1260. /data/ext/cargo-vendor/{wasm-encoder-0.209.1 → wasm-encoder-0.212.0}/src/component/names.rs +0 -0
  1261. /data/ext/cargo-vendor/{wasm-encoder-0.209.1 → wasm-encoder-0.212.0}/src/component/start.rs +0 -0
  1262. /data/ext/cargo-vendor/{wasm-encoder-0.209.1 → wasm-encoder-0.212.0}/src/component.rs +0 -0
  1263. /data/ext/cargo-vendor/{wasm-encoder-0.209.1 → wasm-encoder-0.212.0}/src/core/custom.rs +0 -0
  1264. /data/ext/cargo-vendor/{wasm-encoder-0.209.1 → wasm-encoder-0.212.0}/src/core/data.rs +0 -0
  1265. /data/ext/cargo-vendor/{wasm-encoder-0.209.1 → wasm-encoder-0.212.0}/src/core/dump.rs +0 -0
  1266. /data/ext/cargo-vendor/{wasm-encoder-0.209.1 → wasm-encoder-0.212.0}/src/core/elements.rs +0 -0
  1267. /data/ext/cargo-vendor/{wasm-encoder-0.209.1 → wasm-encoder-0.212.0}/src/core/functions.rs +0 -0
  1268. /data/ext/cargo-vendor/{wasm-encoder-0.209.1 → wasm-encoder-0.212.0}/src/core/linking.rs +0 -0
  1269. /data/ext/cargo-vendor/{wasm-encoder-0.209.1 → wasm-encoder-0.212.0}/src/core/names.rs +0 -0
  1270. /data/ext/cargo-vendor/{wasm-encoder-0.209.1 → wasm-encoder-0.212.0}/src/core/producers.rs +0 -0
  1271. /data/ext/cargo-vendor/{wasm-encoder-0.209.1 → wasm-encoder-0.212.0}/src/core/start.rs +0 -0
  1272. /data/ext/cargo-vendor/{wasm-encoder-0.209.1 → wasm-encoder-0.212.0}/src/core.rs +0 -0
  1273. /data/ext/cargo-vendor/{wasm-encoder-0.209.1 → wasm-encoder-0.212.0}/src/raw.rs +0 -0
  1274. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/README.md +0 -0
  1275. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/benches/benchmark.rs +0 -0
  1276. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/examples/simple.rs +0 -0
  1277. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/collections/hash.rs +0 -0
  1278. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/collections/index_map/detail.rs +0 -0
  1279. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/collections/index_map/tests.rs +0 -0
  1280. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/collections/index_map.rs +0 -0
  1281. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/collections/index_set.rs +0 -0
  1282. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/collections/map.rs +0 -0
  1283. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/collections/mod.rs +0 -0
  1284. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/collections/set.rs +0 -0
  1285. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/limits.rs +0 -0
  1286. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/component/aliases.rs +0 -0
  1287. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/component/canonicals.rs +0 -0
  1288. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/component/exports.rs +0 -0
  1289. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/component/imports.rs +0 -0
  1290. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/component/instances.rs +0 -0
  1291. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/component/names.rs +0 -0
  1292. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/component/start.rs +0 -0
  1293. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/component/types.rs +0 -0
  1294. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/component.rs +0 -0
  1295. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/core/branch_hinting.rs +0 -0
  1296. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/core/code.rs +0 -0
  1297. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/core/coredumps.rs +0 -0
  1298. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/core/custom.rs +0 -0
  1299. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/core/data.rs +0 -0
  1300. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/core/dylink0.rs +0 -0
  1301. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/core/elements.rs +0 -0
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  1303. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/core/functions.rs +0 -0
  1304. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/core/globals.rs +0 -0
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  1306. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/core/init.rs +0 -0
  1307. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/core/linking.rs +0 -0
  1308. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/core/memories.rs +0 -0
  1309. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/core/names.rs +0 -0
  1310. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/core/producers.rs +0 -0
  1311. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/core/reloc.rs +0 -0
  1312. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/core/tags.rs +0 -0
  1313. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/core/types/matches.rs +0 -0
  1314. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/core.rs +0 -0
  1315. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers.rs +0 -0
  1316. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/validator/core/canonical.rs +0 -0
  1317. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/validator/func.rs +0 -0
  1318. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/validator/names.rs +0 -0
  1319. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/tests/big-module.rs +0 -0
  1320. /data/ext/cargo-vendor/{wasmprinter-0.209.1 → wasmprinter-0.212.0}/LICENSE +0 -0
  1321. /data/ext/cargo-vendor/{wasmprinter-0.209.1 → wasmprinter-0.212.0}/README.md +0 -0
  1322. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/LICENSE +0 -0
  1323. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/README.md +0 -0
  1324. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/proptest-regressions/runtime/vm/instance/allocator/pooling/memory_pool.txt +0 -0
  1325. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/code.rs +0 -0
  1326. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/component/bindgen_examples/_0_hello_world.rs +0 -0
  1327. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/component/bindgen_examples/_1_world_imports.rs +0 -0
  1328. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/component/bindgen_examples/_2_world_exports.rs +0 -0
  1329. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/component/bindgen_examples/_3_interface_imports.rs +0 -0
  1330. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/component/bindgen_examples/_4_imported_resources.rs +0 -0
  1331. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/component/bindgen_examples/_5_all_world_export_kinds.rs +0 -0
  1332. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/component/bindgen_examples/_6_exported_resources.rs +0 -0
  1333. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/component/resource_table.rs +0 -0
  1334. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/component/storage.rs +0 -0
  1335. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/component/store.rs +0 -0
  1336. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/component/types.rs +0 -0
  1337. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/externals.rs +0 -0
  1338. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/gc/disabled/anyref.rs +0 -0
  1339. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/gc/disabled/externref.rs +0 -0
  1340. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/gc/disabled/i31.rs +0 -0
  1341. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/gc/disabled.rs +0 -0
  1342. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/gc/enabled/anyref.rs +0 -0
  1343. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/gc/enabled/i31.rs +0 -0
  1344. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/gc/enabled.rs +0 -0
  1345. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/gc/noextern.rs +0 -0
  1346. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/gc.rs +0 -0
  1347. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/resources.rs +0 -0
  1348. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/signatures.rs +0 -0
  1349. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/store/context.rs +0 -0
  1350. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/store/func_refs.rs +0 -0
  1351. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/trampoline/global.rs +0 -0
  1352. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/type_registry.rs +0 -0
  1353. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/uninhabited.rs +0 -0
  1354. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/unix.rs +0 -0
  1355. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/v128.rs +0 -0
  1356. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/arch/aarch64.rs +0 -0
  1357. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/arch/mod.rs +0 -0
  1358. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/arch/s390x.S +0 -0
  1359. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/arch/s390x.rs +0 -0
  1360. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/arch/x86_64.rs +0 -0
  1361. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/async_yield.rs +0 -0
  1362. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/debug_builtins.rs +0 -0
  1363. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/export.rs +0 -0
  1364. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/gc/enabled/externref.rs +0 -0
  1365. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/gc/enabled.rs +0 -0
  1366. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/gc/host_data.rs +0 -0
  1367. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/gc/i31.rs +0 -0
  1368. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/helpers.c +0 -0
  1369. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/imports.rs +0 -0
  1370. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/mpk/pkru.rs +0 -0
  1371. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/send_sync_ptr.rs +0 -0
  1372. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/store_box.rs +0 -0
  1373. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/sys/custom/capi.rs +0 -0
  1374. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/sys/custom/traphandlers.rs +0 -0
  1375. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/sys/miri/mod.rs +0 -0
  1376. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/sys/miri/traphandlers.rs +0 -0
  1377. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/sys/miri/vm.rs +0 -0
  1378. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/sys/mod.rs +0 -0
  1379. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/sys/unix/machports.rs +0 -0
  1380. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/sys/unix/macos_traphandlers.rs +0 -0
  1381. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/sys/unix/mod.rs +0 -0
  1382. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/sys/unix/vm.rs +0 -0
  1383. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/sys/windows/mod.rs +0 -0
  1384. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/sys/windows/traphandlers.rs +0 -0
  1385. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/sys/windows/vm.rs +0 -0
  1386. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/threads/mod.rs +0 -0
  1387. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/threads/parking_spot.rs +0 -0
  1388. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/traphandlers/backtrace.rs +0 -0
  1389. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/traphandlers/coredump_disabled.rs +0 -0
  1390. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/traphandlers/coredump_enabled.rs +0 -0
  1391. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/windows.rs +0 -0
  1392. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/sync_nostd.rs +0 -0
  1393. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/sync_std.rs +0 -0
  1394. /data/ext/cargo-vendor/{wasmtime-asm-macros-22.0.0 → wasmtime-asm-macros-23.0.2}/src/lib.rs +0 -0
  1395. /data/ext/cargo-vendor/{wasmtime-cache-22.0.0 → wasmtime-cache-23.0.2}/LICENSE +0 -0
  1396. /data/ext/cargo-vendor/{wasmtime-cache-22.0.0 → wasmtime-cache-23.0.2}/build.rs +0 -0
  1397. /data/ext/cargo-vendor/{wasmtime-cache-22.0.0 → wasmtime-cache-23.0.2}/src/config/tests.rs +0 -0
  1398. /data/ext/cargo-vendor/{wasmtime-cache-22.0.0 → wasmtime-cache-23.0.2}/src/config.rs +0 -0
  1399. /data/ext/cargo-vendor/{wasmtime-cache-22.0.0 → wasmtime-cache-23.0.2}/src/lib.rs +0 -0
  1400. /data/ext/cargo-vendor/{wasmtime-cache-22.0.0 → wasmtime-cache-23.0.2}/src/tests.rs +0 -0
  1401. /data/ext/cargo-vendor/{wasmtime-cache-22.0.0 → wasmtime-cache-23.0.2}/src/worker/tests/system_time_stub.rs +0 -0
  1402. /data/ext/cargo-vendor/{wasmtime-cache-22.0.0 → wasmtime-cache-23.0.2}/src/worker/tests.rs +0 -0
  1403. /data/ext/cargo-vendor/{wasmtime-cache-22.0.0 → wasmtime-cache-23.0.2}/src/worker.rs +0 -0
  1404. /data/ext/cargo-vendor/{wasmtime-cache-22.0.0 → wasmtime-cache-23.0.2}/tests/cache_write_default_config.rs +0 -0
  1405. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/build.rs +0 -0
  1406. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/src/component.rs +0 -0
  1407. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/src/lib.rs +0 -0
  1408. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/char.wit +0 -0
  1409. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/conventions.wit +0 -0
  1410. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/dead-code.wit +0 -0
  1411. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/direct-import.wit +0 -0
  1412. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/empty.wit +0 -0
  1413. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/flags.wit +0 -0
  1414. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/floats.wit +0 -0
  1415. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/function-new.wit +0 -0
  1416. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/integers.wit +0 -0
  1417. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/lists.wit +0 -0
  1418. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/many-arguments.wit +0 -0
  1419. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/multi-return.wit +0 -0
  1420. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/multiversion/deps/v1/root.wit +0 -0
  1421. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/multiversion/deps/v2/root.wit +0 -0
  1422. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/multiversion/root.wit +0 -0
  1423. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/records.wit +0 -0
  1424. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/rename.wit +0 -0
  1425. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/resources-export.wit +0 -0
  1426. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/resources-import.wit +0 -0
  1427. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/share-types.wit +0 -0
  1428. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/simple-functions.wit +0 -0
  1429. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/simple-lists.wit +0 -0
  1430. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/simple-wasi.wit +0 -0
  1431. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/small-anonymous.wit +0 -0
  1432. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/smoke-default.wit +0 -0
  1433. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/smoke-export.wit +0 -0
  1434. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/smoke.wit +0 -0
  1435. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/strings.wit +0 -0
  1436. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/unversioned-foo.wit +0 -0
  1437. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/use-paths.wit +0 -0
  1438. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/variants.wit +0 -0
  1439. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/wat.wit +0 -0
  1440. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/worlds-with-types.wit +0 -0
  1441. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen_no_std.rs +0 -0
  1442. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/expanded.rs +0 -0
  1443. /data/ext/cargo-vendor/{wasmtime-component-util-22.0.0 → wasmtime-component-util-23.0.2}/src/lib.rs +0 -0
  1444. /data/ext/cargo-vendor/{wasmtime-cranelift-22.0.0 → wasmtime-cranelift-23.0.2}/LICENSE +0 -0
  1445. /data/ext/cargo-vendor/{wasmtime-cranelift-22.0.0 → wasmtime-cranelift-23.0.2}/SECURITY.md +0 -0
  1446. /data/ext/cargo-vendor/{wasmtime-cranelift-22.0.0 → wasmtime-cranelift-23.0.2}/src/builder.rs +0 -0
  1447. /data/ext/cargo-vendor/{wasmtime-cranelift-22.0.0 → wasmtime-cranelift-23.0.2}/src/compiled_function.rs +0 -0
  1448. /data/ext/cargo-vendor/{wasmtime-cranelift-22.0.0 → wasmtime-cranelift-23.0.2}/src/compiler/component.rs +0 -0
  1449. /data/ext/cargo-vendor/{wasmtime-cranelift-22.0.0 → wasmtime-cranelift-23.0.2}/src/debug/transform/refs.rs +0 -0
  1450. /data/ext/cargo-vendor/{wasmtime-cranelift-22.0.0 → wasmtime-cranelift-23.0.2}/src/gc/disabled.rs +0 -0
  1451. /data/ext/cargo-vendor/{wasmtime-cranelift-22.0.0 → wasmtime-cranelift-23.0.2}/src/gc.rs +0 -0
  1452. /data/ext/cargo-vendor/{wasmtime-cranelift-22.0.0 → wasmtime-cranelift-23.0.2}/src/isa_builder.rs +0 -0
  1453. /data/ext/cargo-vendor/{wasmtime-cranelift-22.0.0 → wasmtime-cranelift-23.0.2}/src/obj.rs +0 -0
  1454. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/LICENSE +0 -0
  1455. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/examples/factc.rs +0 -0
  1456. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/src/address_map.rs +0 -0
  1457. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/src/builtin.rs +0 -0
  1458. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/src/compile/address_map.rs +0 -0
  1459. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/src/compile/module_artifacts.rs +0 -0
  1460. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/src/compile/module_types.rs +0 -0
  1461. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/src/compile/trap_encoding.rs +0 -0
  1462. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/src/component/artifacts.rs +0 -0
  1463. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/src/component/compiler.rs +0 -0
  1464. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/src/component/translate/adapt.rs +0 -0
  1465. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/src/component/types_builder/resources.rs +0 -0
  1466. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/src/component/vmcomponent_offsets.rs +0 -0
  1467. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/src/demangling.rs +0 -0
  1468. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/src/fact/core_types.rs +0 -0
  1469. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/src/fact/signature.rs +0 -0
  1470. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/src/fact/trampoline.rs +0 -0
  1471. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/src/fact/transcode.rs +0 -0
  1472. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/src/fact/traps.rs +0 -0
  1473. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/src/fact.rs +0 -0
  1474. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/src/gc.rs +0 -0
  1475. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/src/module_artifacts.rs +0 -0
  1476. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/src/module_types.rs +0 -0
  1477. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/src/obj.rs +0 -0
  1478. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/src/ref_bits.rs +0 -0
  1479. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/src/scopevec.rs +0 -0
  1480. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/src/trap_encoding.rs +0 -0
  1481. /data/ext/cargo-vendor/{wasmtime-fiber-22.0.0 → wasmtime-fiber-23.0.2}/LICENSE +0 -0
  1482. /data/ext/cargo-vendor/{wasmtime-fiber-22.0.0 → wasmtime-fiber-23.0.2}/build.rs +0 -0
  1483. /data/ext/cargo-vendor/{wasmtime-fiber-22.0.0 → wasmtime-fiber-23.0.2}/src/lib.rs +0 -0
  1484. /data/ext/cargo-vendor/{wasmtime-fiber-22.0.0 → wasmtime-fiber-23.0.2}/src/unix/aarch64.rs +0 -0
  1485. /data/ext/cargo-vendor/{wasmtime-fiber-22.0.0 → wasmtime-fiber-23.0.2}/src/unix/arm.rs +0 -0
  1486. /data/ext/cargo-vendor/{wasmtime-fiber-22.0.0 → wasmtime-fiber-23.0.2}/src/unix/riscv64.rs +0 -0
  1487. /data/ext/cargo-vendor/{wasmtime-fiber-22.0.0 → wasmtime-fiber-23.0.2}/src/unix/s390x.S +0 -0
  1488. /data/ext/cargo-vendor/{wasmtime-fiber-22.0.0 → wasmtime-fiber-23.0.2}/src/unix/x86.rs +0 -0
  1489. /data/ext/cargo-vendor/{wasmtime-fiber-22.0.0 → wasmtime-fiber-23.0.2}/src/unix/x86_64.rs +0 -0
  1490. /data/ext/cargo-vendor/{wasmtime-fiber-22.0.0 → wasmtime-fiber-23.0.2}/src/unix.rs +0 -0
  1491. /data/ext/cargo-vendor/{wasmtime-fiber-22.0.0 → wasmtime-fiber-23.0.2}/src/windows.c +0 -0
  1492. /data/ext/cargo-vendor/{wasmtime-fiber-22.0.0 → wasmtime-fiber-23.0.2}/src/windows.rs +0 -0
  1493. /data/ext/cargo-vendor/{wasmtime-jit-debug-22.0.0 → wasmtime-jit-debug-23.0.2}/README.md +0 -0
  1494. /data/ext/cargo-vendor/{wasmtime-jit-debug-22.0.0 → wasmtime-jit-debug-23.0.2}/src/gdb_jit_int.rs +0 -0
  1495. /data/ext/cargo-vendor/{wasmtime-jit-debug-22.0.0 → wasmtime-jit-debug-23.0.2}/src/lib.rs +0 -0
  1496. /data/ext/cargo-vendor/{wasmtime-jit-debug-22.0.0 → wasmtime-jit-debug-23.0.2}/src/perf_jitdump.rs +0 -0
  1497. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-22.0.0 → wasmtime-jit-icache-coherence-23.0.2}/src/lib.rs +0 -0
  1498. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-22.0.0 → wasmtime-jit-icache-coherence-23.0.2}/src/libc.rs +0 -0
  1499. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-22.0.0 → wasmtime-jit-icache-coherence-23.0.2}/src/miri.rs +0 -0
  1500. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-22.0.0 → wasmtime-jit-icache-coherence-23.0.2}/src/win.rs +0 -0
  1501. /data/ext/cargo-vendor/{wasmtime-slab-22.0.0 → wasmtime-slab-23.0.2}/src/lib.rs +0 -0
  1502. /data/ext/cargo-vendor/{wasmtime-types-22.0.0 → wasmtime-types-23.0.2}/LICENSE +0 -0
  1503. /data/ext/cargo-vendor/{wasmtime-types-22.0.0 → wasmtime-types-23.0.2}/src/error.rs +0 -0
  1504. /data/ext/cargo-vendor/{wasmtime-versioned-export-macros-22.0.0 → wasmtime-versioned-export-macros-23.0.2}/src/lib.rs +0 -0
  1505. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/LICENSE +0 -0
  1506. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/README.md +0 -0
  1507. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/clocks/host.rs +0 -0
  1508. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/clocks.rs +0 -0
  1509. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/ctx.rs +0 -0
  1510. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/error.rs +0 -0
  1511. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/host/clocks.rs +0 -0
  1512. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/host/env.rs +0 -0
  1513. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/host/exit.rs +0 -0
  1514. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/host/filesystem/sync.rs +0 -0
  1515. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/host/instance_network.rs +0 -0
  1516. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/host/mod.rs +0 -0
  1517. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/host/network.rs +0 -0
  1518. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/host/random.rs +0 -0
  1519. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/host/tcp.rs +0 -0
  1520. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/host/tcp_create_socket.rs +0 -0
  1521. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/host/udp.rs +0 -0
  1522. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/host/udp_create_socket.rs +0 -0
  1523. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/ip_name_lookup.rs +0 -0
  1524. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/network.rs +0 -0
  1525. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/pipe.rs +0 -0
  1526. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/poll.rs +0 -0
  1527. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/preview0.rs +0 -0
  1528. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/random.rs +0 -0
  1529. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/runtime.rs +0 -0
  1530. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/stdio/worker_thread_stdin.rs +0 -0
  1531. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/stream.rs +0 -0
  1532. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/tcp.rs +0 -0
  1533. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/udp.rs +0 -0
  1534. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/write_stream.rs +0 -0
  1535. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/tests/all/main.rs +0 -0
  1536. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/tests/all/preview1.rs +0 -0
  1537. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/tests/process_stdin.rs +0 -0
  1538. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/command-extended.wit +0 -0
  1539. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/cli/command.wit +0 -0
  1540. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/cli/environment.wit +0 -0
  1541. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/cli/exit.wit +0 -0
  1542. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/cli/imports.wit +0 -0
  1543. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/cli/run.wit +0 -0
  1544. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/cli/stdio.wit +0 -0
  1545. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/cli/terminal.wit +0 -0
  1546. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/clocks/monotonic-clock.wit +0 -0
  1547. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/clocks/wall-clock.wit +0 -0
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  1549. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/filesystem/preopens.wit +0 -0
  1550. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/filesystem/types.wit +0 -0
  1551. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/filesystem/world.wit +0 -0
  1552. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/http/handler.wit +0 -0
  1553. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/http/proxy.wit +0 -0
  1554. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/http/types.wit +0 -0
  1555. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/io/error.wit +0 -0
  1556. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/io/poll.wit +0 -0
  1557. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/io/streams.wit +0 -0
  1558. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/io/world.wit +0 -0
  1559. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/random/insecure-seed.wit +0 -0
  1560. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/random/insecure.wit +0 -0
  1561. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/random/random.wit +0 -0
  1562. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/random/world.wit +0 -0
  1563. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/sockets/instance-network.wit +0 -0
  1564. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/sockets/ip-name-lookup.wit +0 -0
  1565. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/sockets/network.wit +0 -0
  1566. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/sockets/tcp-create-socket.wit +0 -0
  1567. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/sockets/tcp.wit +0 -0
  1568. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/sockets/udp-create-socket.wit +0 -0
  1569. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/sockets/udp.wit +0 -0
  1570. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/sockets/world.wit +0 -0
  1571. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/test.wit +0 -0
  1572. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/witx/preview0/typenames.witx +0 -0
  1573. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/witx/preview0/wasi_unstable.witx +0 -0
  1574. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/witx/preview1/typenames.witx +0 -0
  1575. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/witx/preview1/wasi_snapshot_preview1.witx +0 -0
  1576. /data/ext/cargo-vendor/{wasmtime-winch-22.0.0 → wasmtime-winch-23.0.2}/LICENSE +0 -0
  1577. /data/ext/cargo-vendor/{wasmtime-winch-22.0.0 → wasmtime-winch-23.0.2}/src/builder.rs +0 -0
  1578. /data/ext/cargo-vendor/{wasmtime-winch-22.0.0 → wasmtime-winch-23.0.2}/src/lib.rs +0 -0
  1579. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-22.0.0 → wasmtime-wit-bindgen-23.0.2}/src/rust.rs +0 -0
  1580. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-22.0.0 → wasmtime-wit-bindgen-23.0.2}/src/source.rs +0 -0
  1581. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-22.0.0 → wasmtime-wit-bindgen-23.0.2}/src/types.rs +0 -0
  1582. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/README.md +0 -0
  1583. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/src/component/alias.rs +0 -0
  1584. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/src/component/custom.rs +0 -0
  1585. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/src/component/export.rs +0 -0
  1586. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/src/component/func.rs +0 -0
  1587. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/src/component/import.rs +0 -0
  1588. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/src/component/instance.rs +0 -0
  1589. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/src/component/item_ref.rs +0 -0
  1590. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/src/component/module.rs +0 -0
  1591. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/src/component/types.rs +0 -0
  1592. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/src/component/wast.rs +0 -0
  1593. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/src/core/custom.rs +0 -0
  1594. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/src/core/export.rs +0 -0
  1595. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/src/core/func.rs +0 -0
  1596. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/src/core/global.rs +0 -0
  1597. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/src/core/import.rs +0 -0
  1598. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/src/core/resolve/mod.rs +0 -0
  1599. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/src/core/tag.rs +0 -0
  1600. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/src/core/wast.rs +0 -0
  1601. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/src/encode.rs +0 -0
  1602. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/src/error.rs +0 -0
  1603. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/src/gensym.rs +0 -0
  1604. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/src/lexer.rs +0 -0
  1605. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/src/names.rs +0 -0
  1606. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/src/token.rs +0 -0
  1607. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/src/wast.rs +0 -0
  1608. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/tests/annotations.rs +0 -0
  1609. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/tests/comments.rs +0 -0
  1610. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/tests/parse-fail/bad-core-func-alias.wat +0 -0
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  1722. /data/ext/cargo-vendor/{wat-1.209.1 → wat-1.215.0}/README.md +0 -0
  1723. /data/ext/cargo-vendor/{wast-209.0.1 → wiggle-23.0.2}/LICENSE +0 -0
  1724. /data/ext/cargo-vendor/{wiggle-22.0.0 → wiggle-23.0.2}/README.md +0 -0
  1725. /data/ext/cargo-vendor/{wiggle-22.0.0 → wiggle-23.0.2}/src/error.rs +0 -0
  1726. /data/ext/cargo-vendor/{wiggle-22.0.0 → wiggle-23.0.2}/src/guest_type.rs +0 -0
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  1728. /data/ext/cargo-vendor/{wiggle-22.0.0 → wiggle-23.0.2}/src/region.rs +0 -0
  1729. /data/ext/cargo-vendor/{wat-1.209.1 → wiggle-generate-23.0.2}/LICENSE +0 -0
  1730. /data/ext/cargo-vendor/{wiggle-generate-22.0.0 → wiggle-generate-23.0.2}/README.md +0 -0
  1731. /data/ext/cargo-vendor/{wiggle-generate-22.0.0 → wiggle-generate-23.0.2}/src/codegen_settings.rs +0 -0
  1732. /data/ext/cargo-vendor/{wiggle-generate-22.0.0 → wiggle-generate-23.0.2}/src/config.rs +0 -0
  1733. /data/ext/cargo-vendor/{wiggle-generate-22.0.0 → wiggle-generate-23.0.2}/src/funcs.rs +0 -0
  1734. /data/ext/cargo-vendor/{wiggle-generate-22.0.0 → wiggle-generate-23.0.2}/src/lib.rs +0 -0
  1735. /data/ext/cargo-vendor/{wiggle-generate-22.0.0 → wiggle-generate-23.0.2}/src/lifetimes.rs +0 -0
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  1737. /data/ext/cargo-vendor/{wiggle-generate-22.0.0 → wiggle-generate-23.0.2}/src/names.rs +0 -0
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  1739. /data/ext/cargo-vendor/{wiggle-generate-22.0.0 → wiggle-generate-23.0.2}/src/types/flags.rs +0 -0
  1740. /data/ext/cargo-vendor/{wiggle-generate-22.0.0 → wiggle-generate-23.0.2}/src/types/handle.rs +0 -0
  1741. /data/ext/cargo-vendor/{wiggle-generate-22.0.0 → wiggle-generate-23.0.2}/src/types/mod.rs +0 -0
  1742. /data/ext/cargo-vendor/{wiggle-generate-22.0.0 → wiggle-generate-23.0.2}/src/types/record.rs +0 -0
  1743. /data/ext/cargo-vendor/{wiggle-generate-22.0.0 → wiggle-generate-23.0.2}/src/types/variant.rs +0 -0
  1744. /data/ext/cargo-vendor/{wiggle-generate-22.0.0 → wiggle-generate-23.0.2}/src/wasmtime.rs +0 -0
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  1747. /data/ext/cargo-vendor/{wiggle-macro-22.0.0 → wiggle-macro-23.0.2}/src/lib.rs +0 -0
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  1752. /data/ext/cargo-vendor/{winch-codegen-0.20.0 → winch-codegen-0.21.2}/src/codegen/bounds.rs +0 -0
  1753. /data/ext/cargo-vendor/{winch-codegen-0.20.0 → winch-codegen-0.21.2}/src/codegen/builtin.rs +0 -0
  1754. /data/ext/cargo-vendor/{winch-codegen-0.20.0 → winch-codegen-0.21.2}/src/codegen/call.rs +0 -0
  1755. /data/ext/cargo-vendor/{winch-codegen-0.20.0 → winch-codegen-0.21.2}/src/codegen/context.rs +0 -0
  1756. /data/ext/cargo-vendor/{winch-codegen-0.20.0 → winch-codegen-0.21.2}/src/codegen/control.rs +0 -0
  1757. /data/ext/cargo-vendor/{winch-codegen-0.20.0 → winch-codegen-0.21.2}/src/frame/mod.rs +0 -0
  1758. /data/ext/cargo-vendor/{winch-codegen-0.20.0 → winch-codegen-0.21.2}/src/isa/aarch64/abi.rs +0 -0
  1759. /data/ext/cargo-vendor/{winch-codegen-0.20.0 → winch-codegen-0.21.2}/src/isa/aarch64/address.rs +0 -0
  1760. /data/ext/cargo-vendor/{winch-codegen-0.20.0 → winch-codegen-0.21.2}/src/isa/aarch64/asm.rs +0 -0
  1761. /data/ext/cargo-vendor/{winch-codegen-0.20.0 → winch-codegen-0.21.2}/src/isa/aarch64/masm.rs +0 -0
  1762. /data/ext/cargo-vendor/{winch-codegen-0.20.0 → winch-codegen-0.21.2}/src/isa/aarch64/mod.rs +0 -0
  1763. /data/ext/cargo-vendor/{winch-codegen-0.20.0 → winch-codegen-0.21.2}/src/isa/aarch64/regs.rs +0 -0
  1764. /data/ext/cargo-vendor/{winch-codegen-0.20.0 → winch-codegen-0.21.2}/src/isa/mod.rs +0 -0
  1765. /data/ext/cargo-vendor/{winch-codegen-0.20.0 → winch-codegen-0.21.2}/src/isa/reg.rs +0 -0
  1766. /data/ext/cargo-vendor/{winch-codegen-0.20.0 → winch-codegen-0.21.2}/src/isa/x64/abi.rs +0 -0
  1767. /data/ext/cargo-vendor/{winch-codegen-0.20.0 → winch-codegen-0.21.2}/src/isa/x64/address.rs +0 -0
  1768. /data/ext/cargo-vendor/{winch-codegen-0.20.0 → winch-codegen-0.21.2}/src/isa/x64/asm.rs +0 -0
  1769. /data/ext/cargo-vendor/{winch-codegen-0.20.0 → winch-codegen-0.21.2}/src/isa/x64/masm.rs +0 -0
  1770. /data/ext/cargo-vendor/{winch-codegen-0.20.0 → winch-codegen-0.21.2}/src/isa/x64/mod.rs +0 -0
  1771. /data/ext/cargo-vendor/{winch-codegen-0.20.0 → winch-codegen-0.21.2}/src/isa/x64/regs.rs +0 -0
  1772. /data/ext/cargo-vendor/{winch-codegen-0.20.0 → winch-codegen-0.21.2}/src/lib.rs +0 -0
  1773. /data/ext/cargo-vendor/{winch-codegen-0.20.0 → winch-codegen-0.21.2}/src/masm.rs +0 -0
  1774. /data/ext/cargo-vendor/{winch-codegen-0.20.0 → winch-codegen-0.21.2}/src/regalloc.rs +0 -0
  1775. /data/ext/cargo-vendor/{winch-codegen-0.20.0 → winch-codegen-0.21.2}/src/regset.rs +0 -0
  1776. /data/ext/cargo-vendor/{winch-codegen-0.20.0 → winch-codegen-0.21.2}/src/stack.rs +0 -0
  1777. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/README.md +0 -0
  1778. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/src/abi.rs +0 -0
  1779. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/src/ast/toposort.rs +0 -0
  1780. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/src/live.rs +0 -0
  1781. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/src/metadata.rs +0 -0
  1782. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/src/serde_.rs +0 -0
  1783. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/src/sizealign.rs +0 -0
  1784. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/all.rs +0 -0
  1785. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/comments.wit +0 -0
  1786. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/comments.wit.json +0 -0
  1787. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/complex-include/deps/bar/root.wit +0 -0
  1788. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/complex-include/deps/baz/root.wit +0 -0
  1789. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/complex-include/root.wit +0 -0
  1790. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/complex-include.wit.json +0 -0
  1791. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/cross-package-resource/deps/foo/foo.wit +0 -0
  1792. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/cross-package-resource/foo.wit +0 -0
  1793. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/cross-package-resource.wit.json +0 -0
  1794. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/diamond1/deps/dep1/types.wit +0 -0
  1795. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/diamond1/deps/dep2/types.wit +0 -0
  1796. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/diamond1/join.wit +0 -0
  1797. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/diamond1.wit.json +0 -0
  1798. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/disambiguate-diamond/shared1.wit +0 -0
  1799. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/disambiguate-diamond/shared2.wit +0 -0
  1800. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/disambiguate-diamond/world.wit +0 -0
  1801. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/disambiguate-diamond.wit.json +0 -0
  1802. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/empty.wit +0 -0
  1803. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/empty.wit.json +0 -0
  1804. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/feature-gates.wit +0 -0
  1805. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/foreign-deps/deps/another-pkg/other-doc.wit +0 -0
  1806. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/foreign-deps/deps/corp/saas.wit +0 -0
  1807. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/foreign-deps/deps/different-pkg/the-doc.wit +0 -0
  1808. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/foreign-deps/deps/foreign-pkg/the-doc.wit +0 -0
  1809. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/foreign-deps/deps/some-pkg/some-doc.wit +0 -0
  1810. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/foreign-deps/deps/wasi/clocks.wit +0 -0
  1811. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/foreign-deps/deps/wasi/filesystem.wit +0 -0
  1812. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/foreign-deps/root.wit +0 -0
  1813. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/foreign-deps-union/deps/another-pkg/other-doc.wit +0 -0
  1814. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/foreign-deps-union/deps/corp/saas.wit +0 -0
  1815. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/foreign-deps-union/deps/different-pkg/the-doc.wit +0 -0
  1816. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/foreign-deps-union/deps/foreign-pkg/the-doc.wit +0 -0
  1817. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/foreign-deps-union/deps/some-pkg/some-doc.wit +0 -0
  1818. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/foreign-deps-union/deps/wasi/clocks.wit +0 -0
  1819. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/foreign-deps-union/deps/wasi/filesystem.wit +0 -0
  1820. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/foreign-deps-union/deps/wasi/wasi.wit +0 -0
  1821. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/foreign-deps-union/root.wit +0 -0
  1822. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/foreign-deps-union.wit.json +0 -0
  1823. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/foreign-deps.wit.json +0 -0
  1824. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/functions.wit +0 -0
  1825. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/functions.wit.json +0 -0
  1826. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/ignore-files-deps/deps/bar/types.wit +0 -0
  1827. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/ignore-files-deps/deps/ignore-me.txt +0 -0
  1828. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/ignore-files-deps/world.wit +0 -0
  1829. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/ignore-files-deps.wit.json +0 -0
  1830. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/import-export-overlap1.wit +0 -0
  1831. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/import-export-overlap1.wit.json +0 -0
  1832. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/import-export-overlap2.wit +0 -0
  1833. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/import-export-overlap2.wit.json +0 -0
  1834. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/include-reps.wit +0 -0
  1835. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/include-reps.wit.json +0 -0
  1836. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/kebab-name-include-with.wit +0 -0
  1837. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/kebab-name-include-with.wit.json +0 -0
  1838. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/kinds-of-deps/a.wit +0 -0
  1839. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/kinds-of-deps/deps/b/root.wit +0 -0
  1840. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/kinds-of-deps/deps/c.wit +0 -0
  1841. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/kinds-of-deps/deps/d.wat +0 -0
  1842. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/kinds-of-deps/deps/e.wasm +0 -0
  1843. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/kinds-of-deps.wit.json +0 -0
  1844. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/many-names/a.wit +0 -0
  1845. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/many-names/b.wit +0 -0
  1846. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/many-names.wit.json +0 -0
  1847. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/multi-file/bar.wit +0 -0
  1848. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/multi-file/cycle-a.wit +0 -0
  1849. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/multi-file/cycle-b.wit +0 -0
  1850. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/multi-file/foo.wit +0 -0
  1851. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/multi-file.wit.json +0 -0
  1852. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/name-both-resource-and-type/deps/dep/foo.wit +0 -0
  1853. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/name-both-resource-and-type/foo.wit +0 -0
  1854. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/name-both-resource-and-type.wit.json +0 -0
  1855. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/package-syntax1.wit +0 -0
  1856. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/package-syntax1.wit.json +0 -0
  1857. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/package-syntax3.wit +0 -0
  1858. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/package-syntax3.wit.json +0 -0
  1859. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/package-syntax4.wit +0 -0
  1860. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/package-syntax4.wit.json +0 -0
  1861. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/alias-no-type.wit +0 -0
  1862. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/alias-no-type.wit.result +0 -0
  1863. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/async.wit.result +0 -0
  1864. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/async1.wit.result +0 -0
  1865. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-function.wit +0 -0
  1866. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-function.wit.result +0 -0
  1867. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-function2.wit +0 -0
  1868. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-function2.wit.result +0 -0
  1869. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-gate1.wit +0 -0
  1870. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-gate1.wit.result +0 -0
  1871. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-gate2.wit +0 -0
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  1873. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-gate3.wit +0 -0
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  1875. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-gate4.wit +0 -0
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  1877. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-gate5.wit +0 -0
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  1879. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-include1.wit +0 -0
  1880. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-include1.wit.result +0 -0
  1881. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-include2.wit +0 -0
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  1885. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-list.wit +0 -0
  1886. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-list.wit.result +0 -0
  1887. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-pkg1/root.wit +0 -0
  1888. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-pkg1.wit.result +0 -0
  1889. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-pkg2/deps/bar/empty.wit +0 -0
  1890. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-pkg2/root.wit +0 -0
  1891. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-pkg2.wit.result +0 -0
  1892. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-pkg3/deps/bar/baz.wit +0 -0
  1893. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-pkg3/root.wit +0 -0
  1894. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-pkg3.wit.result +0 -0
  1895. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-pkg4/deps/bar/baz.wit +0 -0
  1896. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-pkg4/root.wit +0 -0
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  1898. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-pkg5/deps/bar/baz.wit +0 -0
  1899. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-pkg5/root.wit +0 -0
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  1901. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-pkg6/deps/bar/baz.wit +0 -0
  1902. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-pkg6/root.wit +0 -0
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  1904. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-resource1.wit +0 -0
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  1908. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-resource11.wit +0 -0
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  1911. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-resource12.wit.result +0 -0
  1912. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-resource13.wit +0 -0
  1913. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-resource13.wit.result +0 -0
  1914. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-resource14.wit +0 -0
  1915. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-resource14.wit.result +0 -0
  1916. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-resource15/deps/foo/foo.wit +0 -0
  1917. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-resource15/foo.wit +0 -0
  1918. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-resource15.wit.result +0 -0
  1919. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-resource2.wit +0 -0
  1920. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-resource2.wit.result +0 -0
  1921. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-resource3.wit +0 -0
  1922. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-resource3.wit.result +0 -0
  1923. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-resource4.wit +0 -0
  1924. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-resource4.wit.result +0 -0
  1925. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-resource5.wit +0 -0
  1926. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-resource5.wit.result +0 -0
  1927. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-resource6.wit +0 -0
  1928. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-resource6.wit.result +0 -0
  1929. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-resource7.wit +0 -0
  1930. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-resource7.wit.result +0 -0
  1931. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-resource8.wit +0 -0
  1932. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-resource8.wit.result +0 -0
  1933. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-resource9.wit +0 -0
  1934. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-resource9.wit.result +0 -0
  1935. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-since1.wit +0 -0
  1936. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-since1.wit.result +0 -0
  1937. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-since3.wit +0 -0
  1938. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-since3.wit.result +0 -0
  1939. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-world-type1.wit +0 -0
  1940. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-world-type1.wit.result +0 -0
  1941. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/conflicting-package/a.wit +0 -0
  1942. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/conflicting-package/b.wit +0 -0
  1943. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/conflicting-package.wit.result +0 -0
  1944. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/cycle.wit +0 -0
  1945. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/cycle.wit.result +0 -0
  1946. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/cycle2.wit +0 -0
  1947. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/cycle2.wit.result +0 -0
  1948. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/cycle3.wit +0 -0
  1949. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/cycle3.wit.result +0 -0
  1950. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/cycle4.wit +0 -0
  1951. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/cycle4.wit.result +0 -0
  1952. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/cycle5.wit +0 -0
  1953. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/cycle5.wit.result +0 -0
  1954. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/dangling-type.wit +0 -0
  1955. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/dangling-type.wit.result +0 -0
  1956. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/duplicate-function-params.wit +0 -0
  1957. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/duplicate-function-params.wit.result +0 -0
  1958. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/duplicate-functions.wit +0 -0
  1959. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/duplicate-functions.wit.result +0 -0
  1960. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/duplicate-interface.wit +0 -0
  1961. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/duplicate-interface.wit.result +0 -0
  1962. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/duplicate-interface2/foo.wit +0 -0
  1963. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/duplicate-interface2/foo2.wit +0 -0
  1964. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/duplicate-interface2.wit.result +0 -0
  1965. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/duplicate-type.wit +0 -0
  1966. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/duplicate-type.wit.result +0 -0
  1967. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/empty-enum.wit +0 -0
  1968. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/empty-enum.wit.result +0 -0
  1969. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/empty-variant1.wit +0 -0
  1970. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/empty-variant1.wit.result +0 -0
  1971. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/export-twice.wit +0 -0
  1972. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/export-twice.wit.result +0 -0
  1973. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/import-and-export1.wit +0 -0
  1974. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/import-and-export1.wit.result +0 -0
  1975. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/import-and-export2.wit +0 -0
  1976. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/import-and-export2.wit.result +0 -0
  1977. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/import-and-export3.wit +0 -0
  1978. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/import-and-export3.wit.result +0 -0
  1979. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/import-and-export4.wit +0 -0
  1980. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/import-and-export4.wit.result +0 -0
  1981. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/import-and-export5.wit +0 -0
  1982. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/import-and-export5.wit.result +0 -0
  1983. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/import-twice.wit +0 -0
  1984. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/import-twice.wit.result +0 -0
  1985. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/include-cycle.wit +0 -0
  1986. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/include-cycle.wit.result +0 -0
  1987. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/include-foreign/deps/bar/empty.wit +0 -0
  1988. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/include-foreign/root.wit +0 -0
  1989. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/include-foreign.wit.result +0 -0
  1990. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/include-with-id.wit +0 -0
  1991. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/include-with-id.wit.result +0 -0
  1992. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/include-with-on-id.wit +0 -0
  1993. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/include-with-on-id.wit.result +0 -0
  1994. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/invalid-toplevel.wit +0 -0
  1995. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/invalid-toplevel.wit.result +0 -0
  1996. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/invalid-type-reference.wit +0 -0
  1997. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/invalid-type-reference.wit.result +0 -0
  1998. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/invalid-type-reference2.wit +0 -0
  1999. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/invalid-type-reference2.wit.result +0 -0
  2000. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/kebab-name-include-not-found.wit +0 -0
  2001. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/kebab-name-include-not-found.wit.result +0 -0
  2002. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/kebab-name-include.wit +0 -0
  2003. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/kebab-name-include.wit.result +0 -0
  2004. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/keyword.wit +0 -0
  2005. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/keyword.wit.result +0 -0
  2006. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/missing-package.wit +0 -0
  2007. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/missing-package.wit.result +0 -0
  2008. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/multiple-package-docs/a.wit +0 -0
  2009. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/multiple-package-docs/b.wit +0 -0
  2010. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/multiple-package-docs.wit.result +0 -0
  2011. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/no-access-to-sibling-use/bar.wit +0 -0
  2012. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/no-access-to-sibling-use/foo.wit +0 -0
  2013. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/no-access-to-sibling-use.wit.result +0 -0
  2014. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/non-existance-world-include/deps/bar/baz.wit +0 -0
  2015. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/non-existance-world-include/root.wit +0 -0
  2016. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/non-existance-world-include.wit.result +0 -0
  2017. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/pkg-cycle/deps/a1/root.wit +0 -0
  2018. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/pkg-cycle/root.wit +0 -0
  2019. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/pkg-cycle.wit.result +0 -0
  2020. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/pkg-cycle2/deps/a1/root.wit +0 -0
  2021. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/pkg-cycle2/deps/a2/root.wit +0 -0
  2022. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/pkg-cycle2/root.wit +0 -0
  2023. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/pkg-cycle2.wit.result +0 -0
  2024. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/resources-multiple-returns-borrow.wit +0 -0
  2025. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/resources-multiple-returns-borrow.wit.result +0 -0
  2026. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/resources-return-borrow.wit +0 -0
  2027. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/resources-return-borrow.wit.result +0 -0
  2028. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/return-borrow1.wit +0 -0
  2029. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/return-borrow1.wit.result +0 -0
  2030. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/return-borrow2.wit +0 -0
  2031. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/return-borrow2.wit.result +0 -0
  2032. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/return-borrow3.wit +0 -0
  2033. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/return-borrow3.wit.result +0 -0
  2034. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/return-borrow4.wit +0 -0
  2035. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/return-borrow4.wit.result +0 -0
  2036. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/return-borrow5.wit +0 -0
  2037. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/return-borrow5.wit.result +0 -0
  2038. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/return-borrow6.wit +0 -0
  2039. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/return-borrow6.wit.result +0 -0
  2040. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/return-borrow7.wit +0 -0
  2041. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/return-borrow7.wit.result +0 -0
  2042. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/return-borrow8/deps/baz.wit +0 -0
  2043. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/return-borrow8/foo.wit +0 -0
  2044. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/return-borrow8.wit.result +0 -0
  2045. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/type-and-resource-same-name/deps/dep/foo.wit +0 -0
  2046. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/type-and-resource-same-name/foo.wit +0 -0
  2047. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/type-and-resource-same-name.wit.result +0 -0
  2048. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/undefined-typed.wit +0 -0
  2049. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/undefined-typed.wit.result +0 -0
  2050. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/unknown-interface.wit +0 -0
  2051. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/unknown-interface.wit.result +0 -0
  2052. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/unresolved-interface1.wit +0 -0
  2053. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/unresolved-interface1.wit.result +0 -0
  2054. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/unresolved-interface2.wit +0 -0
  2055. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/unresolved-interface2.wit.result +0 -0
  2056. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/unresolved-interface3.wit +0 -0
  2057. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/unresolved-interface3.wit.result +0 -0
  2058. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/unresolved-interface4.wit +0 -0
  2059. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/unresolved-interface4.wit.result +0 -0
  2060. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/unresolved-use1.wit +0 -0
  2061. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/unresolved-use1.wit.result +0 -0
  2062. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/unresolved-use10/bar.wit +0 -0
  2063. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/unresolved-use10/foo.wit +0 -0
  2064. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/unresolved-use10.wit.result +0 -0
  2065. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/unresolved-use2.wit +0 -0
  2066. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/unresolved-use2.wit.result +0 -0
  2067. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/unresolved-use3.wit +0 -0
  2068. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/unresolved-use3.wit.result +0 -0
  2069. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/unresolved-use7.wit +0 -0
  2070. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/unresolved-use7.wit.result +0 -0
  2071. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/unresolved-use8.wit +0 -0
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  2073. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/unresolved-use9.wit +0 -0
  2074. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/unresolved-use9.wit.result +0 -0
  2075. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/unterminated-string.wit.result +0 -0
  2076. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/use-and-include-world/deps/bar/baz.wit +0 -0
  2077. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/use-and-include-world/root.wit +0 -0
  2078. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/use-and-include-world.wit.result +0 -0
  2079. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/use-conflict.wit +0 -0
  2080. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/use-conflict.wit.result +0 -0
  2081. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/use-conflict2.wit +0 -0
  2082. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/use-conflict2.wit.result +0 -0
  2083. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/use-conflict3.wit +0 -0
  2084. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/use-conflict3.wit.result +0 -0
  2085. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/use-cycle1.wit +0 -0
  2086. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/use-cycle1.wit.result +0 -0
  2087. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/use-cycle4.wit +0 -0
  2088. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/use-cycle4.wit.result +0 -0
  2089. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/use-shadow1.wit +0 -0
  2090. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/use-shadow1.wit.result +0 -0
  2091. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/use-world/deps/bar/baz.wit +0 -0
  2092. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/use-world/root.wit +0 -0
  2093. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/use-world.wit.result +0 -0
  2094. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/world-interface-clash.wit +0 -0
  2095. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/world-interface-clash.wit.result +0 -0
  2096. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/world-same-fields2.wit +0 -0
  2097. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/world-same-fields2.wit.result +0 -0
  2098. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/world-same-fields3.wit +0 -0
  2099. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/world-same-fields3.wit.result +0 -0
  2100. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/world-top-level-func.wit +0 -0
  2101. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/world-top-level-func.wit.result +0 -0
  2102. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/world-top-level-func2.wit +0 -0
  2103. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/world-top-level-func2.wit.result +0 -0
  2104. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/random.wit +0 -0
  2105. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/random.wit.json +0 -0
  2106. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/resources-empty.wit +0 -0
  2107. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/resources-empty.wit.json +0 -0
  2108. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/resources-multiple-returns-own.wit +0 -0
  2109. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/resources-multiple-returns-own.wit.json +0 -0
  2110. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/resources-multiple.wit +0 -0
  2111. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/resources-multiple.wit.json +0 -0
  2112. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/resources-return-own.wit +0 -0
  2113. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/resources-return-own.wit.json +0 -0
  2114. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/resources.wit +0 -0
  2115. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/resources.wit.json +0 -0
  2116. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/resources1.wit +0 -0
  2117. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/resources1.wit.json +0 -0
  2118. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/same-name-import-export.wit +0 -0
  2119. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/same-name-import-export.wit.json +0 -0
  2120. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/shared-types.wit +0 -0
  2121. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/shared-types.wit.json +0 -0
  2122. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/simple-wasm-text.wat +0 -0
  2123. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/simple-wasm-text.wit.json +0 -0
  2124. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/since-and-unstable.wit +0 -0
  2125. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/stress-export-elaborate.wit +0 -0
  2126. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/stress-export-elaborate.wit.json +0 -0
  2127. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/type-then-eof.wit +0 -0
  2128. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/type-then-eof.wit.json +0 -0
  2129. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/types.wit +0 -0
  2130. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/types.wit.json +0 -0
  2131. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/union-fuzz-1.wit +0 -0
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  2135. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/use-chain.wit +0 -0
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  2137. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/use.wit +0 -0
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  2139. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/versions/deps/a1/foo.wit +0 -0
  2140. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/versions/deps/a2/foo.wit +0 -0
  2141. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/versions/foo.wit +0 -0
  2142. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/versions.wit.json +0 -0
  2143. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/wasi.wit +0 -0
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  2145. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/world-diamond.wit +0 -0
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  2147. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/world-iface-no-collide.wit +0 -0
  2148. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/world-iface-no-collide.wit.json +0 -0
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  2161. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/worlds-union-dedup.wit +0 -0
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  2163. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/worlds-with-types.wit +0 -0
  2164. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/worlds-with-types.wit.json +0 -0
@@ -1,4218 +0,0 @@
1
- ;; Instruction formats.
2
- (type MInst
3
- (enum
4
- ;; A no-op of zero size.
5
- (Nop0)
6
-
7
- ;; A no-op that is one instruction large.
8
- (Nop4)
9
-
10
- ;; An ALU operation with two register sources and a register destination.
11
- (AluRRR
12
- (alu_op ALUOp)
13
- (size OperandSize)
14
- (rd WritableReg)
15
- (rn Reg)
16
- (rm Reg))
17
-
18
- ;; An ALU operation with three register sources and a register destination.
19
- (AluRRRR
20
- (alu_op ALUOp3)
21
- (size OperandSize)
22
- (rd WritableReg)
23
- (rn Reg)
24
- (rm Reg)
25
- (ra Reg))
26
-
27
- ;; An ALU operation with a register source and an immediate-12 source, and a register
28
- ;; destination.
29
- (AluRRImm12
30
- (alu_op ALUOp)
31
- (size OperandSize)
32
- (rd WritableReg)
33
- (rn Reg)
34
- (imm12 Imm12))
35
-
36
- ;; An ALU operation with a register source and an immediate-logic source, and a register destination.
37
- (AluRRImmLogic
38
- (alu_op ALUOp)
39
- (size OperandSize)
40
- (rd WritableReg)
41
- (rn Reg)
42
- (imml ImmLogic))
43
-
44
- ;; An ALU operation with a register source and an immediate-shiftamt source, and a register destination.
45
- (AluRRImmShift
46
- (alu_op ALUOp)
47
- (size OperandSize)
48
- (rd WritableReg)
49
- (rn Reg)
50
- (immshift ImmShift))
51
-
52
- ;; An ALU operation with two register sources, one of which can be shifted, and a register
53
- ;; destination.
54
- (AluRRRShift
55
- (alu_op ALUOp)
56
- (size OperandSize)
57
- (rd WritableReg)
58
- (rn Reg)
59
- (rm Reg)
60
- (shiftop ShiftOpAndAmt))
61
-
62
- ;; An ALU operation with two register sources, one of which can be {zero,sign}-extended and
63
- ;; shifted, and a register destination.
64
- (AluRRRExtend
65
- (alu_op ALUOp)
66
- (size OperandSize)
67
- (rd WritableReg)
68
- (rn Reg)
69
- (rm Reg)
70
- (extendop ExtendOp))
71
-
72
- ;; A bit op instruction with a single register source.
73
- (BitRR
74
- (op BitOp)
75
- (size OperandSize)
76
- (rd WritableReg)
77
- (rn Reg))
78
-
79
- ;; An unsigned (zero-extending) 8-bit load.
80
- (ULoad8
81
- (rd WritableReg)
82
- (mem AMode)
83
- (flags MemFlags))
84
-
85
- ;; A signed (sign-extending) 8-bit load.
86
- (SLoad8
87
- (rd WritableReg)
88
- (mem AMode)
89
- (flags MemFlags))
90
-
91
- ;; An unsigned (zero-extending) 16-bit load.
92
- (ULoad16
93
- (rd WritableReg)
94
- (mem AMode)
95
- (flags MemFlags))
96
-
97
- ;; A signed (sign-extending) 16-bit load.
98
- (SLoad16
99
- (rd WritableReg)
100
- (mem AMode)
101
- (flags MemFlags))
102
-
103
- ;; An unsigned (zero-extending) 32-bit load.
104
- (ULoad32
105
- (rd WritableReg)
106
- (mem AMode)
107
- (flags MemFlags))
108
-
109
- ;; A signed (sign-extending) 32-bit load.
110
- (SLoad32
111
- (rd WritableReg)
112
- (mem AMode)
113
- (flags MemFlags))
114
-
115
- ;; A 64-bit load.
116
- (ULoad64
117
- (rd WritableReg)
118
- (mem AMode)
119
- (flags MemFlags))
120
-
121
- ;; An 8-bit store.
122
- (Store8
123
- (rd Reg)
124
- (mem AMode)
125
- (flags MemFlags))
126
-
127
- ;; A 16-bit store.
128
- (Store16
129
- (rd Reg)
130
- (mem AMode)
131
- (flags MemFlags))
132
-
133
- ;; A 32-bit store.
134
- (Store32
135
- (rd Reg)
136
- (mem AMode)
137
- (flags MemFlags))
138
-
139
- ;; A 64-bit store.
140
- (Store64
141
- (rd Reg)
142
- (mem AMode)
143
- (flags MemFlags))
144
-
145
- ;; A store of a pair of registers.
146
- (StoreP64
147
- (rt Reg)
148
- (rt2 Reg)
149
- (mem PairAMode)
150
- (flags MemFlags))
151
-
152
- ;; A load of a pair of registers.
153
- (LoadP64
154
- (rt WritableReg)
155
- (rt2 WritableReg)
156
- (mem PairAMode)
157
- (flags MemFlags))
158
-
159
- ;; A MOV instruction. These are encoded as ORR's (AluRRR form).
160
- ;; The 32-bit version zeroes the top 32 bits of the
161
- ;; destination, which is effectively an alias for an unsigned
162
- ;; 32-to-64-bit extension.
163
- (Mov
164
- (size OperandSize)
165
- (rd WritableReg)
166
- (rm Reg))
167
-
168
- ;; Like `Move` but with a particular `PReg` source (for implementing CLIF
169
- ;; instructions like `get_stack_pointer`).
170
- (MovFromPReg
171
- (rd WritableReg)
172
- (rm PReg))
173
-
174
- ;; Like `Move` but with a particular `PReg` destination (for
175
- ;; implementing CLIF instructions like `set_pinned_reg`).
176
- (MovToPReg
177
- (rd PReg)
178
- (rm Reg))
179
-
180
- ;; A MOV[Z,N] with a 16-bit immediate.
181
- (MovWide
182
- (op MoveWideOp)
183
- (rd WritableReg)
184
- (imm MoveWideConst)
185
- (size OperandSize))
186
-
187
- ;; A MOVK with a 16-bit immediate. Modifies its register; we
188
- ;; model this with a separate input `rn` and output `rd` virtual
189
- ;; register, with a regalloc constraint to tie them together.
190
- (MovK
191
- (rd WritableReg)
192
- (rn Reg)
193
- (imm MoveWideConst)
194
- (size OperandSize))
195
-
196
-
197
- ;; A sign- or zero-extend operation.
198
- (Extend
199
- (rd WritableReg)
200
- (rn Reg)
201
- (signed bool)
202
- (from_bits u8)
203
- (to_bits u8))
204
-
205
- ;; A conditional-select operation.
206
- (CSel
207
- (rd WritableReg)
208
- (cond Cond)
209
- (rn Reg)
210
- (rm Reg))
211
-
212
- ;; A conditional-select negation operation.
213
- (CSNeg
214
- (rd WritableReg)
215
- (cond Cond)
216
- (rn Reg)
217
- (rm Reg))
218
-
219
- ;; A conditional-set operation.
220
- (CSet
221
- (rd WritableReg)
222
- (cond Cond))
223
-
224
- ;; A conditional-set-mask operation.
225
- (CSetm
226
- (rd WritableReg)
227
- (cond Cond))
228
-
229
- ;; A conditional comparison with a second register.
230
- (CCmp
231
- (size OperandSize)
232
- (rn Reg)
233
- (rm Reg)
234
- (nzcv NZCV)
235
- (cond Cond))
236
-
237
- ;; A conditional comparison with an immediate.
238
- (CCmpImm
239
- (size OperandSize)
240
- (rn Reg)
241
- (imm UImm5)
242
- (nzcv NZCV)
243
- (cond Cond))
244
-
245
- ;; A synthetic insn, which is a load-linked store-conditional loop, that has the overall
246
- ;; effect of atomically modifying a memory location in a particular way. Because we have
247
- ;; no way to explain to the regalloc about earlyclobber registers, this instruction has
248
- ;; completely fixed operand registers, and we rely on the RA's coalescing to remove copies
249
- ;; in the surrounding code to the extent it can. Load- and store-exclusive instructions,
250
- ;; with acquire-release semantics, are used to access memory. The operand conventions are:
251
- ;;
252
- ;; x25 (rd) address
253
- ;; x26 (rd) second operand for `op`
254
- ;; x27 (wr) old value
255
- ;; x24 (wr) scratch reg; value afterwards has no meaning
256
- ;; x28 (wr) scratch reg; value afterwards has no meaning
257
- (AtomicRMWLoop
258
- (ty Type) ;; I8, I16, I32 or I64
259
- (op AtomicRMWLoopOp)
260
- (flags MemFlags)
261
- (addr Reg)
262
- (operand Reg)
263
- (oldval WritableReg)
264
- (scratch1 WritableReg)
265
- (scratch2 WritableReg))
266
-
267
- ;; Similar to AtomicRMWLoop, a compare-and-swap operation implemented using a load-linked
268
- ;; store-conditional loop, with acquire-release semantics.
269
- ;; Note that the operand conventions, although very similar to AtomicRMWLoop, are different:
270
- ;;
271
- ;; x25 (rd) address
272
- ;; x26 (rd) expected value
273
- ;; x28 (rd) replacement value
274
- ;; x27 (wr) old value
275
- ;; x24 (wr) scratch reg; value afterwards has no meaning
276
- (AtomicCASLoop
277
- (ty Type) ;; I8, I16, I32 or I64
278
- (flags MemFlags)
279
- (addr Reg)
280
- (expected Reg)
281
- (replacement Reg)
282
- (oldval WritableReg)
283
- (scratch WritableReg))
284
-
285
- ;; An atomic read-modify-write operation. These instructions require the
286
- ;; Large System Extension (LSE) ISA support (FEAT_LSE). The instructions have
287
- ;; acquire-release semantics.
288
- (AtomicRMW
289
- (op AtomicRMWOp)
290
- (rs Reg)
291
- (rt WritableReg)
292
- (rn Reg)
293
- (ty Type)
294
- (flags MemFlags))
295
-
296
- ;; An atomic compare-and-swap operation. These instructions require the
297
- ;; Large System Extension (LSE) ISA support (FEAT_LSE). The instructions have
298
- ;; acquire-release semantics.
299
- (AtomicCAS
300
- ;; `rd` is really `rs` in the encoded instruction (so `rd` == `rs`); we separate
301
- ;; them here to have separate use and def vregs for regalloc.
302
- (rd WritableReg)
303
- (rs Reg)
304
- (rt Reg)
305
- (rn Reg)
306
- (ty Type)
307
- (flags MemFlags))
308
-
309
- ;; Read `access_ty` bits from address `rt`, either 8, 16, 32 or 64-bits, and put
310
- ;; it in `rn`, optionally zero-extending to fill a word or double word result.
311
- ;; This instruction is sequentially consistent.
312
- (LoadAcquire
313
- (access_ty Type) ;; I8, I16, I32 or I64
314
- (rt WritableReg)
315
- (rn Reg)
316
- (flags MemFlags))
317
-
318
- ;; Write the lowest `ty` bits of `rt` to address `rn`.
319
- ;; This instruction is sequentially consistent.
320
- (StoreRelease
321
- (access_ty Type) ;; I8, I16, I32 or I64
322
- (rt Reg)
323
- (rn Reg)
324
- (flags MemFlags))
325
-
326
- ;; A memory fence. This must provide ordering to ensure that, at a minimum, neither loads
327
- ;; nor stores may move forwards or backwards across the fence. Currently emitted as "dmb
328
- ;; ish". This instruction is sequentially consistent.
329
- (Fence)
330
-
331
- ;; Consumption of speculative data barrier.
332
- (Csdb)
333
-
334
- ;; FPU 32-bit move.
335
- (FpuMove32
336
- (rd WritableReg)
337
- (rn Reg))
338
-
339
- ;; FPU move. Note that this is distinct from a vector-register
340
- ;; move; moving just 64 bits seems to be significantly faster.
341
- (FpuMove64
342
- (rd WritableReg)
343
- (rn Reg))
344
-
345
- ;; Vector register move.
346
- (FpuMove128
347
- (rd WritableReg)
348
- (rn Reg))
349
-
350
- ;; Move to scalar from a vector element.
351
- (FpuMoveFromVec
352
- (rd WritableReg)
353
- (rn Reg)
354
- (idx u8)
355
- (size VectorSize))
356
-
357
- ;; Zero-extend a SIMD & FP scalar to the full width of a vector register.
358
- ;; 16-bit scalars require half-precision floating-point support (FEAT_FP16).
359
- (FpuExtend
360
- (rd WritableReg)
361
- (rn Reg)
362
- (size ScalarSize))
363
-
364
- ;; 1-op FPU instruction.
365
- (FpuRR
366
- (fpu_op FPUOp1)
367
- (size ScalarSize)
368
- (rd WritableReg)
369
- (rn Reg))
370
-
371
- ;; 2-op FPU instruction.
372
- (FpuRRR
373
- (fpu_op FPUOp2)
374
- (size ScalarSize)
375
- (rd WritableReg)
376
- (rn Reg)
377
- (rm Reg))
378
-
379
- (FpuRRI
380
- (fpu_op FPUOpRI)
381
- (rd WritableReg)
382
- (rn Reg))
383
-
384
- ;; Variant of FpuRRI that modifies its `rd`, and so we name the
385
- ;; input state `ri` (for "input") and constrain the two
386
- ;; together.
387
- (FpuRRIMod
388
- (fpu_op FPUOpRIMod)
389
- (rd WritableReg)
390
- (ri Reg)
391
- (rn Reg))
392
-
393
-
394
- ;; 3-op FPU instruction.
395
- ;; 16-bit scalars require half-precision floating-point support (FEAT_FP16).
396
- (FpuRRRR
397
- (fpu_op FPUOp3)
398
- (size ScalarSize)
399
- (rd WritableReg)
400
- (rn Reg)
401
- (rm Reg)
402
- (ra Reg))
403
-
404
- ;; FPU comparison.
405
- (FpuCmp
406
- (size ScalarSize)
407
- (rn Reg)
408
- (rm Reg))
409
-
410
- ;; Floating-point load, single-precision (32 bit).
411
- (FpuLoad32
412
- (rd WritableReg)
413
- (mem AMode)
414
- (flags MemFlags))
415
-
416
- ;; Floating-point store, single-precision (32 bit).
417
- (FpuStore32
418
- (rd Reg)
419
- (mem AMode)
420
- (flags MemFlags))
421
-
422
- ;; Floating-point load, double-precision (64 bit).
423
- (FpuLoad64
424
- (rd WritableReg)
425
- (mem AMode)
426
- (flags MemFlags))
427
-
428
- ;; Floating-point store, double-precision (64 bit).
429
- (FpuStore64
430
- (rd Reg)
431
- (mem AMode)
432
- (flags MemFlags))
433
-
434
- ;; Floating-point/vector load, 128 bit.
435
- (FpuLoad128
436
- (rd WritableReg)
437
- (mem AMode)
438
- (flags MemFlags))
439
-
440
- ;; Floating-point/vector store, 128 bit.
441
- (FpuStore128
442
- (rd Reg)
443
- (mem AMode)
444
- (flags MemFlags))
445
-
446
- ;; A load of a pair of floating-point registers, double precision (64-bit).
447
- (FpuLoadP64
448
- (rt WritableReg)
449
- (rt2 WritableReg)
450
- (mem PairAMode)
451
- (flags MemFlags))
452
-
453
- ;; A store of a pair of floating-point registers, double precision (64-bit).
454
- (FpuStoreP64
455
- (rt Reg)
456
- (rt2 Reg)
457
- (mem PairAMode)
458
- (flags MemFlags))
459
-
460
- ;; A load of a pair of floating-point registers, 128-bit.
461
- (FpuLoadP128
462
- (rt WritableReg)
463
- (rt2 WritableReg)
464
- (mem PairAMode)
465
- (flags MemFlags))
466
-
467
- ;; A store of a pair of floating-point registers, 128-bit.
468
- (FpuStoreP128
469
- (rt Reg)
470
- (rt2 Reg)
471
- (mem PairAMode)
472
- (flags MemFlags))
473
-
474
- ;; Conversion: FP -> integer.
475
- (FpuToInt
476
- (op FpuToIntOp)
477
- (rd WritableReg)
478
- (rn Reg))
479
-
480
- ;; Conversion: integer -> FP.
481
- (IntToFpu
482
- (op IntToFpuOp)
483
- (rd WritableReg)
484
- (rn Reg))
485
-
486
- ;; FP conditional select, 32 bit.
487
- (FpuCSel32
488
- (rd WritableReg)
489
- (rn Reg)
490
- (rm Reg)
491
- (cond Cond))
492
-
493
- ;; FP conditional select, 64 bit.
494
- (FpuCSel64
495
- (rd WritableReg)
496
- (rn Reg)
497
- (rm Reg)
498
- (cond Cond))
499
-
500
- ;; Round to integer.
501
- (FpuRound
502
- (op FpuRoundMode)
503
- (rd WritableReg)
504
- (rn Reg))
505
-
506
- ;; Move from a GPR to a vector register. The scalar value is parked in the lowest lane
507
- ;; of the destination, and all other lanes are zeroed out. Currently only 32- and 64-bit
508
- ;; transactions are supported.
509
- (MovToFpu
510
- (rd WritableReg)
511
- (rn Reg)
512
- (size ScalarSize))
513
-
514
- ;; Loads a floating-point immediate.
515
- (FpuMoveFPImm
516
- (rd WritableReg)
517
- (imm ASIMDFPModImm)
518
- (size ScalarSize))
519
-
520
- ;; Move to a vector element from a GPR.
521
- (MovToVec
522
- (rd WritableReg)
523
- (ri Reg)
524
- (rn Reg)
525
- (idx u8)
526
- (size VectorSize))
527
-
528
- ;; Unsigned move from a vector element to a GPR.
529
- (MovFromVec
530
- (rd WritableReg)
531
- (rn Reg)
532
- (idx u8)
533
- (size ScalarSize))
534
-
535
- ;; Signed move from a vector element to a GPR.
536
- (MovFromVecSigned
537
- (rd WritableReg)
538
- (rn Reg)
539
- (idx u8)
540
- (size VectorSize)
541
- (scalar_size OperandSize))
542
-
543
- ;; Duplicate general-purpose register to vector.
544
- (VecDup
545
- (rd WritableReg)
546
- (rn Reg)
547
- (size VectorSize))
548
-
549
- ;; Duplicate scalar to vector.
550
- (VecDupFromFpu
551
- (rd WritableReg)
552
- (rn Reg)
553
- (size VectorSize)
554
- (lane u8))
555
-
556
- ;; Duplicate FP immediate to vector.
557
- (VecDupFPImm
558
- (rd WritableReg)
559
- (imm ASIMDFPModImm)
560
- (size VectorSize))
561
-
562
- ;; Duplicate immediate to vector.
563
- (VecDupImm
564
- (rd WritableReg)
565
- (imm ASIMDMovModImm)
566
- (invert bool)
567
- (size VectorSize))
568
-
569
- ;; Vector extend.
570
- (VecExtend
571
- (t VecExtendOp)
572
- (rd WritableReg)
573
- (rn Reg)
574
- (high_half bool)
575
- (lane_size ScalarSize))
576
-
577
- ;; Move vector element to another vector element.
578
- (VecMovElement
579
- (rd WritableReg)
580
- (ri Reg)
581
- (rn Reg)
582
- (dest_idx u8)
583
- (src_idx u8)
584
- (size VectorSize))
585
-
586
- ;; Vector widening operation.
587
- (VecRRLong
588
- (op VecRRLongOp)
589
- (rd WritableReg)
590
- (rn Reg)
591
- (high_half bool))
592
-
593
- ;; Vector narrowing operation -- low half.
594
- (VecRRNarrowLow
595
- (op VecRRNarrowOp)
596
- (rd WritableReg)
597
- (rn Reg)
598
- (lane_size ScalarSize))
599
-
600
- ;; Vector narrowing operation -- high half.
601
- (VecRRNarrowHigh
602
- (op VecRRNarrowOp)
603
- (rd WritableReg)
604
- (ri Reg)
605
- (rn Reg)
606
- (lane_size ScalarSize))
607
-
608
- ;; 1-operand vector instruction that operates on a pair of elements.
609
- (VecRRPair
610
- (op VecPairOp)
611
- (rd WritableReg)
612
- (rn Reg))
613
-
614
- ;; 2-operand vector instruction that produces a result with twice the
615
- ;; lane width and half the number of lanes.
616
- (VecRRRLong
617
- (alu_op VecRRRLongOp)
618
- (rd WritableReg)
619
- (rn Reg)
620
- (rm Reg)
621
- (high_half bool))
622
-
623
- ;; 2-operand vector instruction that produces a result with
624
- ;; twice the lane width and half the number of lanes. Variant
625
- ;; that modifies `rd` (so takes its initial state as `ri`).
626
- (VecRRRLongMod
627
- (alu_op VecRRRLongModOp)
628
- (rd WritableReg)
629
- (ri Reg)
630
- (rn Reg)
631
- (rm Reg)
632
- (high_half bool))
633
-
634
- ;; 1-operand vector instruction that extends elements of the input
635
- ;; register and operates on a pair of elements. The output lane width
636
- ;; is double that of the input.
637
- (VecRRPairLong
638
- (op VecRRPairLongOp)
639
- (rd WritableReg)
640
- (rn Reg))
641
-
642
- ;; A vector ALU op.
643
- (VecRRR
644
- (alu_op VecALUOp)
645
- (rd WritableReg)
646
- (rn Reg)
647
- (rm Reg)
648
- (size VectorSize))
649
-
650
- ;; A vector ALU op modifying a source register.
651
- (VecRRRMod
652
- (alu_op VecALUModOp)
653
- (rd WritableReg)
654
- (ri Reg)
655
- (rn Reg)
656
- (rm Reg)
657
- (size VectorSize))
658
-
659
- ;; A vector ALU op modifying a source register.
660
- (VecFmlaElem
661
- (alu_op VecALUModOp)
662
- (rd WritableReg)
663
- (ri Reg)
664
- (rn Reg)
665
- (rm Reg)
666
- (size VectorSize)
667
- (idx u8))
668
-
669
- ;; Vector two register miscellaneous instruction.
670
- (VecMisc
671
- (op VecMisc2)
672
- (rd WritableReg)
673
- (rn Reg)
674
- (size VectorSize))
675
-
676
- ;; Vector instruction across lanes.
677
- (VecLanes
678
- (op VecLanesOp)
679
- (rd WritableReg)
680
- (rn Reg)
681
- (size VectorSize))
682
-
683
- ;; Vector shift by immediate Shift Left (immediate), Unsigned Shift Right (immediate)
684
- ;; Signed Shift Right (immediate). These are somewhat unusual in that, for right shifts,
685
- ;; the allowed range of `imm` values is 1 to lane-size-in-bits, inclusive. A zero
686
- ;; right-shift cannot be encoded. Left shifts are "normal", though, having valid `imm`
687
- ;; values from 0 to lane-size-in-bits - 1 inclusive.
688
- (VecShiftImm
689
- (op VecShiftImmOp)
690
- (rd WritableReg)
691
- (rn Reg)
692
- (size VectorSize)
693
- (imm u8))
694
-
695
- ;; Destructive vector shift by immediate.
696
- (VecShiftImmMod
697
- (op VecShiftImmModOp)
698
- (rd WritableReg)
699
- (ri Reg)
700
- (rn Reg)
701
- (size VectorSize)
702
- (imm u8))
703
-
704
- ;; Vector extract - create a new vector, being the concatenation of the lowest `imm4` bytes
705
- ;; of `rm` followed by the uppermost `16 - imm4` bytes of `rn`.
706
- (VecExtract
707
- (rd WritableReg)
708
- (rn Reg)
709
- (rm Reg)
710
- (imm4 u8))
711
-
712
- ;; Table vector lookup - single register table. The table
713
- ;; consists of 8-bit elements and is stored in `rn`, while `rm`
714
- ;; contains 8-bit element indices. This variant emits `TBL`,
715
- ;; which sets elements that correspond to out-of-range indices
716
- ;; (greater than 15) to 0.
717
- (VecTbl
718
- (rd WritableReg)
719
- (rn Reg)
720
- (rm Reg))
721
-
722
- ;; Table vector lookup - single register table. The table
723
- ;; consists of 8-bit elements and is stored in `rn`, while `rm`
724
- ;; contains 8-bit element indices. This variant emits `TBX`,
725
- ;; which leaves elements that correspond to out-of-range indices
726
- ;; (greater than 15) unmodified. Hence, it takes an input vreg in
727
- ;; `ri` that is constrained to the same allocation as `rd`.
728
- (VecTblExt
729
- (rd WritableReg)
730
- (ri Reg)
731
- (rn Reg)
732
- (rm Reg))
733
-
734
- ;; Table vector lookup - two register table. The table consists
735
- ;; of 8-bit elements and is stored in `rn` and `rn2`, while
736
- ;; `rm` contains 8-bit element indices. The table registers
737
- ;; `rn` and `rn2` must have consecutive numbers modulo 32, that
738
- ;; is v31 and v0 (in that order) are consecutive registers.
739
- ;; This variant emits `TBL`, which sets out-of-range results to
740
- ;; 0.
741
- (VecTbl2
742
- (rd WritableReg)
743
- (rn Reg)
744
- (rn2 Reg)
745
- (rm Reg))
746
-
747
- ;; Table vector lookup - two register table. The table consists
748
- ;; of 8-bit elements and is stored in `rn` and `rn2`, while
749
- ;; `rm` contains 8-bit element indices. The table registers
750
- ;; `rn` and `rn2` must have consecutive numbers modulo 32, that
751
- ;; is v31 and v0 (in that order) are consecutive registers.
752
- ;; This variant emits `TBX`, which leaves out-of-range results
753
- ;; unmodified, hence takes the initial state of the result
754
- ;; register in vreg `ri`.
755
- (VecTbl2Ext
756
- (rd WritableReg)
757
- (ri Reg)
758
- (rn Reg)
759
- (rn2 Reg)
760
- (rm Reg))
761
-
762
- ;; Load an element and replicate to all lanes of a vector.
763
- (VecLoadReplicate
764
- (rd WritableReg)
765
- (rn Reg)
766
- (size VectorSize)
767
- (flags MemFlags))
768
-
769
- ;; Vector conditional select, 128 bit. A synthetic instruction, which generates a 4-insn
770
- ;; control-flow diamond.
771
- (VecCSel
772
- (rd WritableReg)
773
- (rn Reg)
774
- (rm Reg)
775
- (cond Cond))
776
-
777
- ;; Move to the NZCV flags (actually a `MSR NZCV, Xn` insn).
778
- (MovToNZCV
779
- (rn Reg))
780
-
781
- ;; Move from the NZCV flags (actually a `MRS Xn, NZCV` insn).
782
- (MovFromNZCV
783
- (rd WritableReg))
784
-
785
- ;; A machine call instruction. N.B.: this allows only a +/- 128MB offset (it uses a relocation
786
- ;; of type `Reloc::Arm64Call`); if the destination distance is not `RelocDistance::Near`, the
787
- ;; code should use a `LoadExtName` / `CallInd` sequence instead, allowing an arbitrary 64-bit
788
- ;; target.
789
- (Call
790
- (info BoxCallInfo))
791
-
792
- ;; A machine indirect-call instruction.
793
- (CallInd
794
- (info BoxCallIndInfo))
795
-
796
- ;; A return-call macro instruction.
797
- (ReturnCall
798
- (callee BoxExternalName)
799
- (info BoxReturnCallInfo))
800
-
801
- ;; An indirect return-call macro instruction.
802
- (ReturnCallInd
803
- (callee Reg)
804
- (info BoxReturnCallInfo))
805
-
806
- ;; A pseudo-instruction that captures register arguments in vregs.
807
- (Args
808
- (args VecArgPair))
809
-
810
- ;; A pseudo-instruction that moves vregs to return registers.
811
- (Rets
812
- (rets VecRetPair))
813
-
814
- ;; ---- branches (exactly one must appear at end of BB) ----
815
-
816
- ;; A machine return instruction.
817
- (Ret)
818
-
819
- ;; A machine return instruction with pointer authentication using SP as the
820
- ;; modifier. This instruction requires pointer authentication support
821
- ;; (FEAT_PAuth) unless `is_hint` is true, in which case it is equivalent to
822
- ;; the combination of a no-op and a return instruction on platforms without
823
- ;; the relevant support.
824
- (AuthenticatedRet
825
- (key APIKey)
826
- (is_hint bool))
827
-
828
- ;; An unconditional branch.
829
- (Jump
830
- (dest BranchTarget))
831
-
832
- ;; A conditional branch. Contains two targets; at emission time, both are emitted, but
833
- ;; the MachBuffer knows to truncate the trailing branch if fallthrough. We optimize the
834
- ;; choice of taken/not_taken (inverting the branch polarity as needed) based on the
835
- ;; fallthrough at the time of lowering.
836
- (CondBr
837
- (taken BranchTarget)
838
- (not_taken BranchTarget)
839
- (kind CondBrKind))
840
-
841
- ;; A conditional branch which tests the `bit` of `rn` and branches
842
- ;; depending on `kind`.
843
- (TestBitAndBranch
844
- (kind TestBitAndBranchKind)
845
- (taken BranchTarget)
846
- (not_taken BranchTarget)
847
- (rn Reg)
848
- (bit u8))
849
-
850
- ;; A conditional trap: execute a `udf` if the condition is true. This is
851
- ;; one VCode instruction because it uses embedded control flow; it is
852
- ;; logically a single-in, single-out region, but needs to appear as one
853
- ;; unit to the register allocator.
854
- ;;
855
- ;; The `CondBrKind` gives the conditional-branch condition that will
856
- ;; *execute* the embedded `Inst`. (In the emitted code, we use the inverse
857
- ;; of this condition in a branch that skips the trap instruction.)
858
- (TrapIf
859
- (kind CondBrKind)
860
- (trap_code TrapCode))
861
-
862
- ;; An indirect branch through a register, augmented with set of all
863
- ;; possible successors.
864
- (IndirectBr
865
- (rn Reg)
866
- (targets VecMachLabel))
867
-
868
- ;; A "break" instruction, used for e.g. traps and debug breakpoints.
869
- (Brk)
870
-
871
- ;; An instruction guaranteed to always be undefined and to trigger an illegal instruction at
872
- ;; runtime.
873
- (Udf
874
- (trap_code TrapCode))
875
-
876
- ;; Compute the address (using a PC-relative offset) of a memory location, using the `ADR`
877
- ;; instruction. Note that we take a simple offset, not a `MemLabel`, here, because `Adr` is
878
- ;; only used for now in fixed lowering sequences with hardcoded offsets. In the future we may
879
- ;; need full `MemLabel` support.
880
- (Adr
881
- (rd WritableReg)
882
- ;; Offset in range -2^20 .. 2^20.
883
- (off i32))
884
-
885
- ;; Compute the address (using a PC-relative offset) of a 4KB page.
886
- (Adrp
887
- (rd WritableReg)
888
- (off i32))
889
-
890
- ;; Raw 32-bit word, used for inline constants and jump-table entries.
891
- (Word4
892
- (data u32))
893
-
894
- ;; Raw 64-bit word, used for inline constants.
895
- (Word8
896
- (data u64))
897
-
898
- ;; Jump-table sequence, as one compound instruction (see note in lower_inst.rs for rationale).
899
- (JTSequence
900
- (default MachLabel)
901
- (targets BoxVecMachLabel)
902
- (ridx Reg)
903
- (rtmp1 WritableReg)
904
- (rtmp2 WritableReg))
905
-
906
- ;; Load an inline symbol reference.
907
- (LoadExtName
908
- (rd WritableReg)
909
- (name BoxExternalName)
910
- (offset i64))
911
-
912
- ;; Load address referenced by `mem` into `rd`.
913
- (LoadAddr
914
- (rd WritableReg)
915
- (mem AMode))
916
-
917
- ;; Pointer authentication code for instruction address with modifier in SP;
918
- ;; equivalent to a no-op if Pointer authentication (FEAT_PAuth) is not
919
- ;; supported.
920
- (Paci
921
- (key APIKey))
922
-
923
- ;; Strip pointer authentication code from instruction address in LR;
924
- ;; equivalent to a no-op if Pointer authentication (FEAT_PAuth) is not
925
- ;; supported.
926
- (Xpaclri)
927
-
928
- ;; Branch target identification; equivalent to a no-op if Branch Target
929
- ;; Identification (FEAT_BTI) is not supported.
930
- (Bti
931
- (targets BranchTargetType))
932
-
933
- ;; Meta-insn, no-op in generated code: emit constant/branch veneer island
934
- ;; at this point (with a guard jump around it) if less than the needed
935
- ;; space is available before the next branch deadline. See the `MachBuffer`
936
- ;; implementation in `machinst/buffer.rs` for the overall algorithm. In
937
- ;; brief, we retain a set of "pending/unresolved label references" from
938
- ;; branches as we scan forward through instructions to emit machine code;
939
- ;; if we notice we're about to go out of range on an unresolved reference,
940
- ;; we stop, emit a bunch of "veneers" (branches in a form that has a longer
941
- ;; range, e.g. a 26-bit-offset unconditional jump), and point the original
942
- ;; label references to those. This is an "island" because it comes in the
943
- ;; middle of the code.
944
- ;;
945
- ;; This meta-instruction is a necessary part of the logic that determines
946
- ;; where to place islands. Ordinarily, we want to place them between basic
947
- ;; blocks, so we compute the worst-case size of each block, and emit the
948
- ;; island before starting a block if we would exceed a deadline before the
949
- ;; end of the block. However, some sequences (such as an inline jumptable)
950
- ;; are variable-length and not accounted for by this logic; so these
951
- ;; lowered sequences include an `EmitIsland` to trigger island generation
952
- ;; where necessary.
953
- (EmitIsland
954
- ;; The needed space before the next deadline.
955
- (needed_space CodeOffset))
956
-
957
- ;; A call to the `ElfTlsGetAddr` libcall. Returns address of TLS symbol in x0.
958
- (ElfTlsGetAddr
959
- (symbol BoxExternalName)
960
- (rd WritableReg)
961
- (tmp WritableReg))
962
-
963
- (MachOTlsGetAddr
964
- (symbol ExternalName)
965
- (rd WritableReg))
966
-
967
- ;; An unwind pseudo-instruction.
968
- (Unwind
969
- (inst UnwindInst))
970
-
971
- ;; A dummy use, useful to keep a value alive.
972
- (DummyUse
973
- (reg Reg))
974
-
975
- ;; Emits an inline stack probe loop.
976
- ;;
977
- ;; Note that this is emitted post-regalloc so `start` and `end` can be
978
- ;; temporary registers such as the spilltmp and tmp2 registers. This also
979
- ;; means that the internal codegen can't use these registers.
980
- (StackProbeLoop (start WritableReg)
981
- (end Reg)
982
- (step Imm12))))
983
-
984
- ;; An ALU operation. This can be paired with several instruction formats
985
- ;; below (see `Inst`) in any combination.
986
- (type ALUOp
987
- (enum
988
- (Add)
989
- (Sub)
990
- (Orr)
991
- (OrrNot)
992
- (And)
993
- (AndS)
994
- (AndNot)
995
- ;; XOR (AArch64 calls this "EOR")
996
- (Eor)
997
- ;; XNOR (AArch64 calls this "EOR-NOT")
998
- (EorNot)
999
- ;; Add, setting flags
1000
- (AddS)
1001
- ;; Sub, setting flags
1002
- (SubS)
1003
- ;; Signed multiply, high-word result
1004
- (SMulH)
1005
- ;; Unsigned multiply, high-word result
1006
- (UMulH)
1007
- (SDiv)
1008
- (UDiv)
1009
- (RotR)
1010
- (Lsr)
1011
- (Asr)
1012
- (Lsl)
1013
- ;; Add with carry
1014
- (Adc)
1015
- ;; Add with carry, settings flags
1016
- (AdcS)
1017
- ;; Subtract with carry
1018
- (Sbc)
1019
- ;; Subtract with carry, settings flags
1020
- (SbcS)
1021
- ))
1022
-
1023
- ;; An ALU operation with three arguments.
1024
- (type ALUOp3
1025
- (enum
1026
- ;; Multiply-add
1027
- (MAdd)
1028
- ;; Multiply-sub
1029
- (MSub)
1030
- ;; Unsigned-Multiply-add
1031
- (UMAddL)
1032
- ;; Signed-Multiply-add
1033
- (SMAddL)
1034
- ))
1035
-
1036
- (type MoveWideOp
1037
- (enum
1038
- (MovZ)
1039
- (MovN)
1040
- ))
1041
-
1042
- (type UImm5 (primitive UImm5))
1043
- (type Imm12 (primitive Imm12))
1044
- (type ImmLogic (primitive ImmLogic))
1045
- (type ImmShift (primitive ImmShift))
1046
- (type ShiftOpAndAmt (primitive ShiftOpAndAmt))
1047
- (type MoveWideConst (primitive MoveWideConst))
1048
- (type NZCV (primitive NZCV))
1049
- (type ASIMDFPModImm (primitive ASIMDFPModImm))
1050
- (type ASIMDMovModImm (primitive ASIMDMovModImm))
1051
- (type SImm7Scaled (primitive SImm7Scaled))
1052
-
1053
- (type BoxCallInfo (primitive BoxCallInfo))
1054
- (type BoxCallIndInfo (primitive BoxCallIndInfo))
1055
- (type BoxReturnCallInfo (primitive BoxReturnCallInfo))
1056
- (type CondBrKind (primitive CondBrKind))
1057
- (type BranchTarget (primitive BranchTarget))
1058
- (type BoxJTSequenceInfo (primitive BoxJTSequenceInfo))
1059
- (type CodeOffset (primitive CodeOffset))
1060
- (type VecMachLabel extern (enum))
1061
-
1062
- (type ExtendOp extern
1063
- (enum
1064
- (UXTB)
1065
- (UXTH)
1066
- (UXTW)
1067
- (UXTX)
1068
- (SXTB)
1069
- (SXTH)
1070
- (SXTW)
1071
- (SXTX)
1072
- ))
1073
-
1074
- ;; An operation on the bits of a register. This can be paired with several instruction formats
1075
- ;; below (see `Inst`) in any combination.
1076
- (type BitOp
1077
- (enum
1078
- ;; Bit reverse
1079
- (RBit)
1080
- (Clz)
1081
- (Cls)
1082
- ;; Byte reverse
1083
- (Rev16)
1084
- (Rev32)
1085
- (Rev64)
1086
- ))
1087
-
1088
- (type MemLabel extern (enum))
1089
- (type SImm9 extern (enum))
1090
- (type UImm12Scaled extern (enum))
1091
-
1092
- ;; An addressing mode specified for a load/store operation.
1093
- (type AMode
1094
- (enum
1095
- ;;
1096
- ;; Real ARM64 addressing modes:
1097
- ;;
1098
- ;; "post-indexed" mode as per AArch64 docs: postincrement reg after
1099
- ;; address computation.
1100
- ;; Specialized here to SP so we don't have to emit regalloc metadata.
1101
- (SPPostIndexed
1102
- (simm9 SImm9))
1103
-
1104
- ;; "pre-indexed" mode as per AArch64 docs: preincrement reg before
1105
- ;; address computation.
1106
- ;; Specialized here to SP so we don't have to emit regalloc metadata.
1107
- (SPPreIndexed
1108
- (simm9 SImm9))
1109
-
1110
- ;; N.B.: RegReg, RegScaled, and RegScaledExtended all correspond to
1111
- ;; what the ISA calls the "register offset" addressing mode. We split
1112
- ;; out several options here for more ergonomic codegen.
1113
- ;;
1114
- ;; Register plus register offset.
1115
- (RegReg
1116
- (rn Reg)
1117
- (rm Reg))
1118
-
1119
- ;; Register plus register offset, scaled by type's size.
1120
- (RegScaled
1121
- (rn Reg)
1122
- (rm Reg))
1123
-
1124
- ;; Register plus register offset, scaled by type's size, with index
1125
- ;; sign- or zero-extended first.
1126
- (RegScaledExtended
1127
- (rn Reg)
1128
- (rm Reg)
1129
- (extendop ExtendOp))
1130
-
1131
- ;; Register plus register offset, with index sign- or zero-extended
1132
- ;; first.
1133
- (RegExtended
1134
- (rn Reg)
1135
- (rm Reg)
1136
- (extendop ExtendOp))
1137
-
1138
- ;; Unscaled signed 9-bit immediate offset from reg.
1139
- (Unscaled
1140
- (rn Reg)
1141
- (simm9 SImm9))
1142
-
1143
- ;; Scaled (by size of a type) unsigned 12-bit immediate offset from reg.
1144
- (UnsignedOffset
1145
- (rn Reg)
1146
- (uimm12 UImm12Scaled))
1147
-
1148
- ;; virtual addressing modes that are lowered at emission time:
1149
- ;;
1150
- ;; Reference to a "label": e.g., a symbol.
1151
- (Label
1152
- (label MemLabel))
1153
-
1154
- ;; Arbitrary offset from a register. Converted to generation of large
1155
- ;; offsets with multiple instructions as necessary during code emission.
1156
- (RegOffset
1157
- (rn Reg)
1158
- (off i64))
1159
-
1160
- ;; Offset from the stack pointer.
1161
- (SPOffset
1162
- (off i64))
1163
-
1164
- ;; Offset from the frame pointer.
1165
- (FPOffset
1166
- (off i64))
1167
-
1168
- ;; A reference to a constant which is placed outside of the function's
1169
- ;; body, typically at the end.
1170
- (Const
1171
- (addr VCodeConstant))
1172
-
1173
- ;; Offset from the beginning of the argument area to the argument
1174
- ;; referenced. This can only be determined when the function has been
1175
- ;; processed fully, as the size of the argument area after the prologue
1176
- ;; is only known once all return_call instructions in the function body
1177
- ;; have been processed.
1178
- (IncomingArg
1179
- (off i64))
1180
-
1181
- ;; Offset into the slot area of the stack, which lies just above the
1182
- ;; outgoing argument area that's setup by the function prologue.
1183
- ;; At emission time, this is converted to `SPOffset` with a fixup added to
1184
- ;; the offset constant. The fixup is a running value that is tracked as
1185
- ;; emission iterates through instructions in linear order, and can be
1186
- ;; adjusted up and down with [Inst::VirtualSPOffsetAdj].
1187
- ;;
1188
- ;; The standard ABI is in charge of handling this (by emitting the
1189
- ;; adjustment meta-instructions). See the diagram in the documentation
1190
- ;; for [crate::isa::aarch64::abi](the ABI module) for more details.
1191
- (SlotOffset
1192
- (off i64))))
1193
-
1194
- ;; A memory argument to a load/store-pair.
1195
- (type PairAMode (enum
1196
- ;; Signed, scaled 7-bit offset from a register.
1197
- (SignedOffset
1198
- (reg Reg)
1199
- (simm7 SImm7Scaled))
1200
-
1201
- ;; Pre-increment register before address computation.
1202
- (SPPreIndexed (simm7 SImm7Scaled))
1203
-
1204
- ;; Post-increment register after address computation.
1205
- (SPPostIndexed (simm7 SImm7Scaled))
1206
- ))
1207
-
1208
- (type FPUOpRI extern (enum))
1209
- (type FPUOpRIMod extern (enum))
1210
-
1211
- (type OperandSize extern
1212
- (enum Size32
1213
- Size64))
1214
-
1215
- (type TestBitAndBranchKind (enum (Z) (NZ)))
1216
-
1217
- ;; Helper for calculating the `OperandSize` corresponding to a type
1218
- (decl operand_size (Type) OperandSize)
1219
- (rule 1 (operand_size (fits_in_32 _ty)) (OperandSize.Size32))
1220
- (rule (operand_size (fits_in_64 _ty)) (OperandSize.Size64))
1221
-
1222
- (type ScalarSize extern
1223
- (enum Size8
1224
- Size16
1225
- Size32
1226
- Size64
1227
- Size128))
1228
-
1229
- ;; Helper for calculating the `ScalarSize` corresponding to a type
1230
- (decl scalar_size (Type) ScalarSize)
1231
-
1232
- (rule (scalar_size $I8) (ScalarSize.Size8))
1233
- (rule (scalar_size $I16) (ScalarSize.Size16))
1234
- (rule (scalar_size $I32) (ScalarSize.Size32))
1235
- (rule (scalar_size $I64) (ScalarSize.Size64))
1236
- (rule (scalar_size $I128) (ScalarSize.Size128))
1237
-
1238
- (rule (scalar_size $F32) (ScalarSize.Size32))
1239
- (rule (scalar_size $F64) (ScalarSize.Size64))
1240
-
1241
- ;; Helper for calculating the `ScalarSize` lane type from vector type
1242
- (decl lane_size (Type) ScalarSize)
1243
- (rule 1 (lane_size (multi_lane 8 _)) (ScalarSize.Size8))
1244
- (rule 1 (lane_size (multi_lane 16 _)) (ScalarSize.Size16))
1245
- (rule 1 (lane_size (multi_lane 32 _)) (ScalarSize.Size32))
1246
- (rule 1 (lane_size (multi_lane 64 _)) (ScalarSize.Size64))
1247
- (rule (lane_size (dynamic_lane 8 _)) (ScalarSize.Size8))
1248
- (rule (lane_size (dynamic_lane 16 _)) (ScalarSize.Size16))
1249
- (rule (lane_size (dynamic_lane 32 _)) (ScalarSize.Size32))
1250
- (rule (lane_size (dynamic_lane 64 _)) (ScalarSize.Size64))
1251
-
1252
- ;; Helper for extracting the size of a lane from the input `VectorSize`
1253
- (decl pure vector_lane_size (VectorSize) ScalarSize)
1254
- (rule (vector_lane_size (VectorSize.Size8x16)) (ScalarSize.Size8))
1255
- (rule (vector_lane_size (VectorSize.Size8x8)) (ScalarSize.Size8))
1256
- (rule (vector_lane_size (VectorSize.Size16x8)) (ScalarSize.Size16))
1257
- (rule (vector_lane_size (VectorSize.Size16x4)) (ScalarSize.Size16))
1258
- (rule (vector_lane_size (VectorSize.Size32x4)) (ScalarSize.Size32))
1259
- (rule (vector_lane_size (VectorSize.Size32x2)) (ScalarSize.Size32))
1260
- (rule (vector_lane_size (VectorSize.Size64x2)) (ScalarSize.Size64))
1261
-
1262
- (type Cond extern
1263
- (enum
1264
- (Eq)
1265
- (Ne)
1266
- (Hs)
1267
- (Lo)
1268
- (Mi)
1269
- (Pl)
1270
- (Vs)
1271
- (Vc)
1272
- (Hi)
1273
- (Ls)
1274
- (Ge)
1275
- (Lt)
1276
- (Gt)
1277
- (Le)
1278
- (Al)
1279
- (Nv)
1280
- ))
1281
-
1282
- (type VectorSize extern
1283
- (enum
1284
- (Size8x8)
1285
- (Size8x16)
1286
- (Size16x4)
1287
- (Size16x8)
1288
- (Size32x2)
1289
- (Size32x4)
1290
- (Size64x2)
1291
- ))
1292
-
1293
- ;; Helper for calculating the `VectorSize` corresponding to a type
1294
- (decl vector_size (Type) VectorSize)
1295
- (rule 1 (vector_size (multi_lane 8 8)) (VectorSize.Size8x8))
1296
- (rule 1 (vector_size (multi_lane 8 16)) (VectorSize.Size8x16))
1297
- (rule 1 (vector_size (multi_lane 16 4)) (VectorSize.Size16x4))
1298
- (rule 1 (vector_size (multi_lane 16 8)) (VectorSize.Size16x8))
1299
- (rule 1 (vector_size (multi_lane 32 2)) (VectorSize.Size32x2))
1300
- (rule 1 (vector_size (multi_lane 32 4)) (VectorSize.Size32x4))
1301
- (rule 1 (vector_size (multi_lane 64 2)) (VectorSize.Size64x2))
1302
- (rule (vector_size (dynamic_lane 8 8)) (VectorSize.Size8x8))
1303
- (rule (vector_size (dynamic_lane 8 16)) (VectorSize.Size8x16))
1304
- (rule (vector_size (dynamic_lane 16 4)) (VectorSize.Size16x4))
1305
- (rule (vector_size (dynamic_lane 16 8)) (VectorSize.Size16x8))
1306
- (rule (vector_size (dynamic_lane 32 2)) (VectorSize.Size32x2))
1307
- (rule (vector_size (dynamic_lane 32 4)) (VectorSize.Size32x4))
1308
- (rule (vector_size (dynamic_lane 64 2)) (VectorSize.Size64x2))
1309
-
1310
- ;; A floating-point unit (FPU) operation with one arg.
1311
- (type FPUOp1
1312
- (enum
1313
- (Abs)
1314
- (Neg)
1315
- (Sqrt)
1316
- (Cvt32To64)
1317
- (Cvt64To32)
1318
- ))
1319
-
1320
- ;; A floating-point unit (FPU) operation with two args.
1321
- (type FPUOp2
1322
- (enum
1323
- (Add)
1324
- (Sub)
1325
- (Mul)
1326
- (Div)
1327
- (Max)
1328
- (Min)
1329
- ))
1330
-
1331
- ;; A floating-point unit (FPU) operation with three args.
1332
- (type FPUOp3
1333
- (enum
1334
- (MAdd)
1335
- ))
1336
-
1337
- ;; A conversion from an FP to an integer value.
1338
- (type FpuToIntOp
1339
- (enum
1340
- (F32ToU32)
1341
- (F32ToI32)
1342
- (F32ToU64)
1343
- (F32ToI64)
1344
- (F64ToU32)
1345
- (F64ToI32)
1346
- (F64ToU64)
1347
- (F64ToI64)
1348
- ))
1349
-
1350
- ;; A conversion from an integer to an FP value.
1351
- (type IntToFpuOp
1352
- (enum
1353
- (U32ToF32)
1354
- (I32ToF32)
1355
- (U32ToF64)
1356
- (I32ToF64)
1357
- (U64ToF32)
1358
- (I64ToF32)
1359
- (U64ToF64)
1360
- (I64ToF64)
1361
- ))
1362
-
1363
- ;; Modes for FP rounding ops: round down (floor) or up (ceil), or toward zero (trunc), or to
1364
- ;; nearest, and for 32- or 64-bit FP values.
1365
- (type FpuRoundMode
1366
- (enum
1367
- (Minus32)
1368
- (Minus64)
1369
- (Plus32)
1370
- (Plus64)
1371
- (Zero32)
1372
- (Zero64)
1373
- (Nearest32)
1374
- (Nearest64)
1375
- ))
1376
-
1377
- ;; Type of vector element extensions.
1378
- (type VecExtendOp
1379
- (enum
1380
- ;; Signed extension
1381
- (Sxtl)
1382
- ;; Unsigned extension
1383
- (Uxtl)
1384
- ))
1385
-
1386
- ;; A vector ALU operation.
1387
- (type VecALUOp
1388
- (enum
1389
- ;; Signed saturating add
1390
- (Sqadd)
1391
- ;; Unsigned saturating add
1392
- (Uqadd)
1393
- ;; Signed saturating subtract
1394
- (Sqsub)
1395
- ;; Unsigned saturating subtract
1396
- (Uqsub)
1397
- ;; Compare bitwise equal
1398
- (Cmeq)
1399
- ;; Compare signed greater than or equal
1400
- (Cmge)
1401
- ;; Compare signed greater than
1402
- (Cmgt)
1403
- ;; Compare unsigned higher
1404
- (Cmhs)
1405
- ;; Compare unsigned higher or same
1406
- (Cmhi)
1407
- ;; Floating-point compare equal
1408
- (Fcmeq)
1409
- ;; Floating-point compare greater than
1410
- (Fcmgt)
1411
- ;; Floating-point compare greater than or equal
1412
- (Fcmge)
1413
- ;; Bitwise and
1414
- (And)
1415
- ;; Bitwise bit clear
1416
- (Bic)
1417
- ;; Bitwise inclusive or
1418
- (Orr)
1419
- ;; Bitwise exclusive or
1420
- (Eor)
1421
- ;; Unsigned maximum pairwise
1422
- (Umaxp)
1423
- ;; Add
1424
- (Add)
1425
- ;; Subtract
1426
- (Sub)
1427
- ;; Multiply
1428
- (Mul)
1429
- ;; Signed shift left
1430
- (Sshl)
1431
- ;; Unsigned shift left
1432
- (Ushl)
1433
- ;; Unsigned minimum
1434
- (Umin)
1435
- ;; Signed minimum
1436
- (Smin)
1437
- ;; Unsigned maximum
1438
- (Umax)
1439
- ;; Signed maximum
1440
- (Smax)
1441
- ;; Unsigned rounding halving add
1442
- (Urhadd)
1443
- ;; Floating-point add
1444
- (Fadd)
1445
- ;; Floating-point subtract
1446
- (Fsub)
1447
- ;; Floating-point divide
1448
- (Fdiv)
1449
- ;; Floating-point maximum
1450
- (Fmax)
1451
- ;; Floating-point minimum
1452
- (Fmin)
1453
- ;; Floating-point multiply
1454
- (Fmul)
1455
- ;; Add pairwise
1456
- (Addp)
1457
- ;; Zip vectors (primary) [meaning, high halves]
1458
- (Zip1)
1459
- ;; Zip vectors (secondary)
1460
- (Zip2)
1461
- ;; Signed saturating rounding doubling multiply returning high half
1462
- (Sqrdmulh)
1463
- ;; Unzip vectors (primary)
1464
- (Uzp1)
1465
- ;; Unzip vectors (secondary)
1466
- (Uzp2)
1467
- ;; Transpose vectors (primary)
1468
- (Trn1)
1469
- ;; Transpose vectors (secondary)
1470
- (Trn2)
1471
- ))
1472
-
1473
- ;; A Vector ALU operation which modifies a source register.
1474
- (type VecALUModOp
1475
- (enum
1476
- ;; Bitwise select
1477
- (Bsl)
1478
- ;; Floating-point fused multiply-add vectors
1479
- (Fmla)
1480
- ;; Floating-point fused multiply-subtract vectors
1481
- (Fmls)
1482
- ))
1483
-
1484
- ;; A Vector miscellaneous operation with two registers.
1485
- (type VecMisc2
1486
- (enum
1487
- ;; Bitwise NOT
1488
- (Not)
1489
- ;; Negate
1490
- (Neg)
1491
- ;; Absolute value
1492
- (Abs)
1493
- ;; Floating-point absolute value
1494
- (Fabs)
1495
- ;; Floating-point negate
1496
- (Fneg)
1497
- ;; Floating-point square root
1498
- (Fsqrt)
1499
- ;; Reverse elements in 16-bit lanes
1500
- (Rev16)
1501
- ;; Reverse elements in 32-bit lanes
1502
- (Rev32)
1503
- ;; Reverse elements in 64-bit doublewords
1504
- (Rev64)
1505
- ;; Floating-point convert to signed integer, rounding toward zero
1506
- (Fcvtzs)
1507
- ;; Floating-point convert to unsigned integer, rounding toward zero
1508
- (Fcvtzu)
1509
- ;; Signed integer convert to floating-point
1510
- (Scvtf)
1511
- ;; Unsigned integer convert to floating-point
1512
- (Ucvtf)
1513
- ;; Floating point round to integral, rounding towards nearest
1514
- (Frintn)
1515
- ;; Floating point round to integral, rounding towards zero
1516
- (Frintz)
1517
- ;; Floating point round to integral, rounding towards minus infinity
1518
- (Frintm)
1519
- ;; Floating point round to integral, rounding towards plus infinity
1520
- (Frintp)
1521
- ;; Population count per byte
1522
- (Cnt)
1523
- ;; Compare bitwise equal to 0
1524
- (Cmeq0)
1525
- ;; Compare signed greater than or equal to 0
1526
- (Cmge0)
1527
- ;; Compare signed greater than 0
1528
- (Cmgt0)
1529
- ;; Compare signed less than or equal to 0
1530
- (Cmle0)
1531
- ;; Compare signed less than 0
1532
- (Cmlt0)
1533
- ;; Floating point compare equal to 0
1534
- (Fcmeq0)
1535
- ;; Floating point compare greater than or equal to 0
1536
- (Fcmge0)
1537
- ;; Floating point compare greater than 0
1538
- (Fcmgt0)
1539
- ;; Floating point compare less than or equal to 0
1540
- (Fcmle0)
1541
- ;; Floating point compare less than 0
1542
- (Fcmlt0)
1543
- ))
1544
-
1545
- ;; A vector widening operation with one argument.
1546
- (type VecRRLongOp
1547
- (enum
1548
- ;; Floating-point convert to higher precision long, 16-bit elements
1549
- (Fcvtl16)
1550
- ;; Floating-point convert to higher precision long, 32-bit elements
1551
- (Fcvtl32)
1552
- ;; Shift left long (by element size), 8-bit elements
1553
- (Shll8)
1554
- ;; Shift left long (by element size), 16-bit elements
1555
- (Shll16)
1556
- ;; Shift left long (by element size), 32-bit elements
1557
- (Shll32)
1558
- ))
1559
-
1560
- ;; A vector narrowing operation with one argument.
1561
- (type VecRRNarrowOp
1562
- (enum
1563
- ;; Extract narrow.
1564
- (Xtn)
1565
- ;; Signed saturating extract narrow.
1566
- (Sqxtn)
1567
- ;; Signed saturating extract unsigned narrow.
1568
- (Sqxtun)
1569
- ;; Unsigned saturating extract narrow.
1570
- (Uqxtn)
1571
- ;; Floating-point convert to lower precision narrow.
1572
- (Fcvtn)
1573
- ))
1574
-
1575
- (type VecRRRLongOp
1576
- (enum
1577
- ;; Signed multiply long.
1578
- (Smull8)
1579
- (Smull16)
1580
- (Smull32)
1581
- ;; Unsigned multiply long.
1582
- (Umull8)
1583
- (Umull16)
1584
- (Umull32)
1585
- ))
1586
-
1587
- (type VecRRRLongModOp
1588
- (enum
1589
- ;; Unsigned multiply add long
1590
- (Umlal8)
1591
- (Umlal16)
1592
- (Umlal32)
1593
- ))
1594
-
1595
- ;; A vector operation on a pair of elements with one register.
1596
- (type VecPairOp
1597
- (enum
1598
- ;; Add pair of elements
1599
- (Addp)
1600
- ))
1601
-
1602
- ;; 1-operand vector instruction that extends elements of the input register
1603
- ;; and operates on a pair of elements.
1604
- (type VecRRPairLongOp
1605
- (enum
1606
- ;; Sign extend and add pair of elements
1607
- (Saddlp8)
1608
- (Saddlp16)
1609
- ;; Unsigned extend and add pair of elements
1610
- (Uaddlp8)
1611
- (Uaddlp16)
1612
- ))
1613
-
1614
- ;; An operation across the lanes of vectors.
1615
- (type VecLanesOp
1616
- (enum
1617
- ;; Integer addition across a vector
1618
- (Addv)
1619
- ;; Unsigned minimum across a vector
1620
- (Uminv)
1621
- ))
1622
-
1623
- ;; A shift-by-immediate operation on each lane of a vector.
1624
- (type VecShiftImmOp
1625
- (enum
1626
- ;; Unsigned shift left
1627
- (Shl)
1628
- ;; Unsigned shift right
1629
- (Ushr)
1630
- ;; Signed shift right
1631
- (Sshr)
1632
- ))
1633
-
1634
- ;; Destructive shift-by-immediate operation on each lane of a vector.
1635
- (type VecShiftImmModOp
1636
- (enum
1637
- ;; Shift left and insert
1638
- (Sli)
1639
- ))
1640
-
1641
- ;; Atomic read-modify-write operations with acquire-release semantics
1642
- (type AtomicRMWOp
1643
- (enum
1644
- (Add)
1645
- (Clr)
1646
- (Eor)
1647
- (Set)
1648
- (Smax)
1649
- (Smin)
1650
- (Umax)
1651
- (Umin)
1652
- (Swp)
1653
- ))
1654
-
1655
- ;; Atomic read-modify-write operations, with acquire-release semantics,
1656
- ;; implemented with a loop.
1657
- (type AtomicRMWLoopOp
1658
- (enum
1659
- (Add)
1660
- (Sub)
1661
- (And)
1662
- (Nand)
1663
- (Eor)
1664
- (Orr)
1665
- (Smax)
1666
- (Smin)
1667
- (Umax)
1668
- (Umin)
1669
- (Xchg)
1670
- ))
1671
-
1672
- ;; Keys for instruction address PACs
1673
- (type APIKey
1674
- (enum
1675
- ;; API key A with the modifier of SP
1676
- (ASP)
1677
- ;; API key B with the modifier of SP
1678
- (BSP)
1679
- ;; API key A with the modifier of zero
1680
- (AZ)
1681
- ;; API key B with the modifier of zero
1682
- (BZ)
1683
- ))
1684
-
1685
- ;; Branch target types
1686
- (type BranchTargetType
1687
- (enum
1688
- (None)
1689
- (C)
1690
- (J)
1691
- (JC)
1692
- ))
1693
-
1694
- ;; Extractors for target features ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1695
- (decl pure partial sign_return_address_disabled () Unit)
1696
- (extern constructor sign_return_address_disabled sign_return_address_disabled)
1697
-
1698
- (decl use_lse () Inst)
1699
- (extern extractor use_lse use_lse)
1700
-
1701
- ;; Extractor helpers for various immediate constants ;;;;;;;;;;;;;;;;;;;;;;;;;;
1702
-
1703
- (decl pure partial move_wide_const_from_u64 (Type u64) MoveWideConst)
1704
- (extern constructor move_wide_const_from_u64 move_wide_const_from_u64)
1705
-
1706
- (decl pure partial move_wide_const_from_inverted_u64 (Type u64) MoveWideConst)
1707
- (extern constructor move_wide_const_from_inverted_u64 move_wide_const_from_inverted_u64)
1708
-
1709
- (decl pure partial imm_logic_from_u64 (Type u64) ImmLogic)
1710
- (extern constructor imm_logic_from_u64 imm_logic_from_u64)
1711
-
1712
- (decl pure partial imm_size_from_type (Type) u16)
1713
- (extern constructor imm_size_from_type imm_size_from_type)
1714
-
1715
- (decl pure partial imm_logic_from_imm64 (Type Imm64) ImmLogic)
1716
- (extern constructor imm_logic_from_imm64 imm_logic_from_imm64)
1717
-
1718
- (decl pure partial imm_shift_from_imm64 (Type Imm64) ImmShift)
1719
- (extern constructor imm_shift_from_imm64 imm_shift_from_imm64)
1720
-
1721
- (decl imm_shift_from_u8 (u8) ImmShift)
1722
- (extern constructor imm_shift_from_u8 imm_shift_from_u8)
1723
-
1724
- (decl imm12_from_u64 (Imm12) u64)
1725
- (extern extractor imm12_from_u64 imm12_from_u64)
1726
-
1727
- (decl u8_into_uimm5 (u8) UImm5)
1728
- (extern constructor u8_into_uimm5 u8_into_uimm5)
1729
-
1730
- (decl u8_into_imm12 (u8) Imm12)
1731
- (extern constructor u8_into_imm12 u8_into_imm12)
1732
-
1733
- (decl u64_into_imm_logic (Type u64) ImmLogic)
1734
- (extern constructor u64_into_imm_logic u64_into_imm_logic)
1735
-
1736
- (decl branch_target (MachLabel) BranchTarget)
1737
- (extern constructor branch_target branch_target)
1738
- (convert MachLabel BranchTarget branch_target)
1739
-
1740
- (decl targets_jt_space (BoxVecMachLabel) CodeOffset)
1741
- (extern constructor targets_jt_space targets_jt_space)
1742
-
1743
- ;; Calculate the minimum floating-point bound for a conversion to floating
1744
- ;; point from an integer type.
1745
- ;; Accepts whether the output is signed, the size of the input
1746
- ;; floating point type in bits, and the size of the output integer type
1747
- ;; in bits.
1748
- (decl min_fp_value (bool u8 u8) Reg)
1749
- (extern constructor min_fp_value min_fp_value)
1750
-
1751
- ;; Calculate the maximum floating-point bound for a conversion to floating
1752
- ;; point from an integer type.
1753
- ;; Accepts whether the output is signed, the size of the input
1754
- ;; floating point type in bits, and the size of the output integer type
1755
- ;; in bits.
1756
- (decl max_fp_value (bool u8 u8) Reg)
1757
- (extern constructor max_fp_value max_fp_value)
1758
-
1759
- ;; Constructs an FPUOpRI.Ushr* given the size in bits of the value (or lane)
1760
- ;; and the amount to shift by.
1761
- (decl fpu_op_ri_ushr (u8 u8) FPUOpRI)
1762
- (extern constructor fpu_op_ri_ushr fpu_op_ri_ushr)
1763
-
1764
- ;; Constructs an FPUOpRIMod.Sli* given the size in bits of the value (or lane)
1765
- ;; and the amount to shift by.
1766
- (decl fpu_op_ri_sli (u8 u8) FPUOpRIMod)
1767
- (extern constructor fpu_op_ri_sli fpu_op_ri_sli)
1768
-
1769
- (decl pure partial lshr_from_u64 (Type u64) ShiftOpAndAmt)
1770
- (extern constructor lshr_from_u64 lshr_from_u64)
1771
-
1772
- (decl pure partial lshl_from_imm64 (Type Imm64) ShiftOpAndAmt)
1773
- (extern constructor lshl_from_imm64 lshl_from_imm64)
1774
-
1775
- (decl pure partial lshl_from_u64 (Type u64) ShiftOpAndAmt)
1776
- (extern constructor lshl_from_u64 lshl_from_u64)
1777
-
1778
- (decl pure partial ashr_from_u64 (Type u64) ShiftOpAndAmt)
1779
- (extern constructor ashr_from_u64 ashr_from_u64)
1780
-
1781
- (decl integral_ty (Type) Type)
1782
- (extern extractor integral_ty integral_ty)
1783
-
1784
- (decl valid_atomic_transaction (Type) Type)
1785
- (extern extractor valid_atomic_transaction valid_atomic_transaction)
1786
-
1787
- (decl pure partial is_zero_simm9 (SImm9) Unit)
1788
- (extern constructor is_zero_simm9 is_zero_simm9)
1789
-
1790
- (decl pure partial is_zero_uimm12 (UImm12Scaled) Unit)
1791
- (extern constructor is_zero_uimm12 is_zero_uimm12)
1792
-
1793
- ;; Helper to go directly from a `Value`, when it's an `iconst`, to an `Imm12`.
1794
- (decl imm12_from_value (Imm12) Value)
1795
- (extractor
1796
- (imm12_from_value n)
1797
- (iconst (u64_from_imm64 (imm12_from_u64 n))))
1798
-
1799
- ;; Conceptually the same as `imm12_from_value`, but tries negating the constant
1800
- ;; value (first sign-extending to handle narrow widths).
1801
- (decl pure partial imm12_from_negated_value (Value) Imm12)
1802
- (rule
1803
- (imm12_from_negated_value (has_type ty (iconst n)))
1804
- (if-let (imm12_from_u64 imm) (i64_as_u64 (i64_neg (i64_sextend_imm64 ty n))))
1805
- imm)
1806
-
1807
- ;; Helper type to represent a value and an extend operation fused together.
1808
- (type ExtendedValue extern (enum))
1809
- (decl extended_value_from_value (ExtendedValue) Value)
1810
- (extern extractor extended_value_from_value extended_value_from_value)
1811
-
1812
- ;; Constructors used to poke at the fields of an `ExtendedValue`.
1813
- (decl put_extended_in_reg (ExtendedValue) Reg)
1814
- (extern constructor put_extended_in_reg put_extended_in_reg)
1815
- (decl get_extended_op (ExtendedValue) ExtendOp)
1816
- (extern constructor get_extended_op get_extended_op)
1817
-
1818
- (decl nzcv (bool bool bool bool) NZCV)
1819
- (extern constructor nzcv nzcv)
1820
-
1821
- (decl cond_br_zero (Reg) CondBrKind)
1822
- (extern constructor cond_br_zero cond_br_zero)
1823
-
1824
- (decl cond_br_not_zero (Reg) CondBrKind)
1825
- (extern constructor cond_br_not_zero cond_br_not_zero)
1826
-
1827
- (decl cond_br_cond (Cond) CondBrKind)
1828
- (extern constructor cond_br_cond cond_br_cond)
1829
-
1830
- ;; Instruction creation helpers ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1831
-
1832
- ;; Helper for creating the zero register.
1833
- (decl zero_reg () Reg)
1834
- (extern constructor zero_reg zero_reg)
1835
-
1836
- (decl fp_reg () Reg)
1837
- (extern constructor fp_reg fp_reg)
1838
-
1839
- (decl stack_reg () Reg)
1840
- (extern constructor stack_reg stack_reg)
1841
-
1842
- (decl writable_link_reg () WritableReg)
1843
- (extern constructor writable_link_reg writable_link_reg)
1844
-
1845
- (decl writable_zero_reg () WritableReg)
1846
- (extern constructor writable_zero_reg writable_zero_reg)
1847
-
1848
- (decl value_regs_zero () ValueRegs)
1849
- (rule (value_regs_zero)
1850
- (value_regs
1851
- (imm $I64 (ImmExtend.Zero) 0)
1852
- (imm $I64 (ImmExtend.Zero) 0)))
1853
-
1854
-
1855
- ;; Helper for emitting `MInst.Mov` instructions.
1856
- (decl mov (Reg Type) Reg)
1857
- (rule (mov src ty)
1858
- (let ((dst WritableReg (temp_writable_reg $I64))
1859
- (_ Unit (emit (MInst.Mov (operand_size ty) dst src))))
1860
- dst))
1861
-
1862
- ;; Helper for emitting `MInst.MovZ` instructions.
1863
- (decl movz (MoveWideConst OperandSize) Reg)
1864
- (rule (movz imm size)
1865
- (let ((dst WritableReg (temp_writable_reg $I64))
1866
- (_ Unit (emit (MInst.MovWide (MoveWideOp.MovZ) dst imm size))))
1867
- dst))
1868
-
1869
- ;; Helper for emitting `MInst.MovN` instructions.
1870
- (decl movn (MoveWideConst OperandSize) Reg)
1871
- (rule (movn imm size)
1872
- (let ((dst WritableReg (temp_writable_reg $I64))
1873
- (_ Unit (emit (MInst.MovWide (MoveWideOp.MovN) dst imm size))))
1874
- dst))
1875
-
1876
- ;; Helper for emitting `MInst.AluRRImmLogic` instructions.
1877
- (decl alu_rr_imm_logic (ALUOp Type Reg ImmLogic) Reg)
1878
- (rule (alu_rr_imm_logic op ty src imm)
1879
- (let ((dst WritableReg (temp_writable_reg $I64))
1880
- (_ Unit (emit (MInst.AluRRImmLogic op (operand_size ty) dst src imm))))
1881
- dst))
1882
-
1883
- ;; Helper for emitting `MInst.AluRRImmShift` instructions.
1884
- (decl alu_rr_imm_shift (ALUOp Type Reg ImmShift) Reg)
1885
- (rule (alu_rr_imm_shift op ty src imm)
1886
- (let ((dst WritableReg (temp_writable_reg $I64))
1887
- (_ Unit (emit (MInst.AluRRImmShift op (operand_size ty) dst src imm))))
1888
- dst))
1889
-
1890
- ;; Helper for emitting `MInst.AluRRR` instructions.
1891
- (decl alu_rrr (ALUOp Type Reg Reg) Reg)
1892
- (rule (alu_rrr op ty src1 src2)
1893
- (let ((dst WritableReg (temp_writable_reg $I64))
1894
- (_ Unit (emit (MInst.AluRRR op (operand_size ty) dst src1 src2))))
1895
- dst))
1896
-
1897
- ;; Helper for emitting `MInst.VecRRR` instructions.
1898
- (decl vec_rrr (VecALUOp Reg Reg VectorSize) Reg)
1899
- (rule (vec_rrr op src1 src2 size)
1900
- (let ((dst WritableReg (temp_writable_reg $I8X16))
1901
- (_ Unit (emit (MInst.VecRRR op dst src1 src2 size))))
1902
- dst))
1903
-
1904
- ;; Helper for emitting `MInst.FpuRR` instructions.
1905
- (decl fpu_rr (FPUOp1 Reg ScalarSize) Reg)
1906
- (rule (fpu_rr op src size)
1907
- (let ((dst WritableReg (temp_writable_reg $F64))
1908
- (_ Unit (emit (MInst.FpuRR op size dst src))))
1909
- dst))
1910
-
1911
- ;; Helper for emitting `MInst.VecRRRMod` instructions which use three registers,
1912
- ;; one of which is both source and output.
1913
- (decl vec_rrr_mod (VecALUModOp Reg Reg Reg VectorSize) Reg)
1914
- (rule (vec_rrr_mod op src1 src2 src3 size)
1915
- (let ((dst WritableReg (temp_writable_reg $I8X16))
1916
- (_1 Unit (emit (MInst.VecRRRMod op dst src1 src2 src3 size))))
1917
- dst))
1918
-
1919
- ;; Helper for emitting `MInst.VecFmlaElem` instructions which use three registers,
1920
- ;; one of which is both source and output.
1921
- (decl vec_fmla_elem (VecALUModOp Reg Reg Reg VectorSize u8) Reg)
1922
- (rule (vec_fmla_elem op src1 src2 src3 size idx)
1923
- (let ((dst WritableReg (temp_writable_reg $I8X16))
1924
- (_1 Unit (emit (MInst.VecFmlaElem op dst src1 src2 src3 size idx))))
1925
- dst))
1926
-
1927
- (decl fpu_rri (FPUOpRI Reg) Reg)
1928
- (rule (fpu_rri op src)
1929
- (let ((dst WritableReg (temp_writable_reg $F64))
1930
- (_ Unit (emit (MInst.FpuRRI op dst src))))
1931
- dst))
1932
-
1933
- (decl fpu_rri_mod (FPUOpRIMod Reg Reg) Reg)
1934
- (rule (fpu_rri_mod op dst_src src)
1935
- (let ((dst WritableReg (temp_writable_reg $F64))
1936
- (_ Unit (emit (MInst.FpuRRIMod op dst dst_src src))))
1937
- dst))
1938
-
1939
- ;; Helper for emitting `MInst.FpuRRR` instructions.
1940
- (decl fpu_rrr (FPUOp2 Reg Reg ScalarSize) Reg)
1941
- (rule (fpu_rrr op src1 src2 size)
1942
- (let ((dst WritableReg (temp_writable_reg $F64))
1943
- (_ Unit (emit (MInst.FpuRRR op size dst src1 src2))))
1944
- dst))
1945
-
1946
- ;; Helper for emitting `MInst.FpuRRRR` instructions.
1947
- (decl fpu_rrrr (FPUOp3 ScalarSize Reg Reg Reg) Reg)
1948
- (rule (fpu_rrrr size op src1 src2 src3)
1949
- (let ((dst WritableReg (temp_writable_reg $F64))
1950
- (_ Unit (emit (MInst.FpuRRRR size op dst src1 src2 src3))))
1951
- dst))
1952
-
1953
- ;; Helper for emitting `MInst.FpuCmp` instructions.
1954
- (decl fpu_cmp (ScalarSize Reg Reg) ProducesFlags)
1955
- (rule (fpu_cmp size rn rm)
1956
- (ProducesFlags.ProducesFlagsSideEffect
1957
- (MInst.FpuCmp size rn rm)))
1958
-
1959
- ;; Helper for emitting `MInst.VecLanes` instructions.
1960
- (decl vec_lanes (VecLanesOp Reg VectorSize) Reg)
1961
- (rule (vec_lanes op src size)
1962
- (let ((dst WritableReg (temp_writable_reg $I8X16))
1963
- (_ Unit (emit (MInst.VecLanes op dst src size))))
1964
- dst))
1965
-
1966
- ;; Helper for emitting `MInst.VecShiftImm` instructions.
1967
- (decl vec_shift_imm (VecShiftImmOp u8 Reg VectorSize) Reg)
1968
- (rule (vec_shift_imm op imm src size)
1969
- (let ((dst WritableReg (temp_writable_reg $I8X16))
1970
- (_ Unit (emit (MInst.VecShiftImm op dst src size imm))))
1971
- dst))
1972
-
1973
- ;; Helper for emitting `MInst.VecDup` instructions.
1974
- (decl vec_dup (Reg VectorSize) Reg)
1975
- (rule (vec_dup src size)
1976
- (let ((dst WritableReg (temp_writable_reg $I8X16))
1977
- (_ Unit (emit (MInst.VecDup dst src size))))
1978
- dst))
1979
-
1980
- ;; Helper for emitting `MInst.VecDupFromFpu` instructions.
1981
- (decl vec_dup_from_fpu (Reg VectorSize u8) Reg)
1982
- (rule (vec_dup_from_fpu src size lane)
1983
- (let ((dst WritableReg (temp_writable_reg $I8X16))
1984
- (_ Unit (emit (MInst.VecDupFromFpu dst src size lane))))
1985
- dst))
1986
-
1987
- ;; Helper for emitting `MInst.VecDupImm` instructions.
1988
- (decl vec_dup_imm (ASIMDMovModImm bool VectorSize) Reg)
1989
- (rule (vec_dup_imm imm invert size)
1990
- (let ((dst WritableReg (temp_writable_reg $I8X16))
1991
- (_ Unit (emit (MInst.VecDupImm dst imm invert size))))
1992
- dst))
1993
-
1994
- ;; Helper for emitting `MInst.AluRRImm12` instructions.
1995
- (decl alu_rr_imm12 (ALUOp Type Reg Imm12) Reg)
1996
- (rule (alu_rr_imm12 op ty src imm)
1997
- (let ((dst WritableReg (temp_writable_reg $I64))
1998
- (_ Unit (emit (MInst.AluRRImm12 op (operand_size ty) dst src imm))))
1999
- dst))
2000
-
2001
- ;; Helper for emitting `MInst.AluRRRShift` instructions.
2002
- (decl alu_rrr_shift (ALUOp Type Reg Reg ShiftOpAndAmt) Reg)
2003
- (rule (alu_rrr_shift op ty src1 src2 shift)
2004
- (let ((dst WritableReg (temp_writable_reg $I64))
2005
- (_ Unit (emit (MInst.AluRRRShift op (operand_size ty) dst src1 src2 shift))))
2006
- dst))
2007
-
2008
- ;; Helper for emitting `cmp` instructions, setting flags, with a right-shifted
2009
- ;; second operand register.
2010
- (decl cmp_rr_shift (OperandSize Reg Reg u64) ProducesFlags)
2011
- (rule (cmp_rr_shift size src1 src2 shift_amount)
2012
- (if-let shift (lshr_from_u64 $I64 shift_amount))
2013
- (ProducesFlags.ProducesFlagsSideEffect
2014
- (MInst.AluRRRShift (ALUOp.SubS) size (writable_zero_reg)
2015
- src1 src2 shift)))
2016
-
2017
- ;; Helper for emitting `cmp` instructions, setting flags, with an arithmetic right-shifted
2018
- ;; second operand register.
2019
- (decl cmp_rr_shift_asr (OperandSize Reg Reg u64) ProducesFlags)
2020
- (rule (cmp_rr_shift_asr size src1 src2 shift_amount)
2021
- (if-let shift (ashr_from_u64 $I64 shift_amount))
2022
- (ProducesFlags.ProducesFlagsSideEffect
2023
- (MInst.AluRRRShift (ALUOp.SubS) size (writable_zero_reg)
2024
- src1 src2 shift)))
2025
-
2026
- ;; Helper for emitting `MInst.AluRRRExtend` instructions.
2027
- (decl alu_rrr_extend (ALUOp Type Reg Reg ExtendOp) Reg)
2028
- (rule (alu_rrr_extend op ty src1 src2 extend)
2029
- (let ((dst WritableReg (temp_writable_reg $I64))
2030
- (_ Unit (emit (MInst.AluRRRExtend op (operand_size ty) dst src1 src2 extend))))
2031
- dst))
2032
-
2033
- ;; Same as `alu_rrr_extend`, but takes an `ExtendedValue` packed "pair" instead
2034
- ;; of a `Reg` and an `ExtendOp`.
2035
- (decl alu_rr_extend_reg (ALUOp Type Reg ExtendedValue) Reg)
2036
- (rule (alu_rr_extend_reg op ty src1 extended_reg)
2037
- (let ((src2 Reg (put_extended_in_reg extended_reg))
2038
- (extend ExtendOp (get_extended_op extended_reg)))
2039
- (alu_rrr_extend op ty src1 src2 extend)))
2040
-
2041
- ;; Helper for emitting `MInst.AluRRRR` instructions.
2042
- (decl alu_rrrr (ALUOp3 Type Reg Reg Reg) Reg)
2043
- (rule (alu_rrrr op ty src1 src2 src3)
2044
- (let ((dst WritableReg (temp_writable_reg $I64))
2045
- (_ Unit (emit (MInst.AluRRRR op (operand_size ty) dst src1 src2 src3))))
2046
- dst))
2047
-
2048
- ;; Helper for emitting paired `MInst.AluRRR` instructions
2049
- (decl alu_rrr_with_flags_paired (Type Reg Reg ALUOp) ProducesFlags)
2050
- (rule (alu_rrr_with_flags_paired ty src1 src2 alu_op)
2051
- (let ((dst WritableReg (temp_writable_reg $I64)))
2052
- (ProducesFlags.ProducesFlagsReturnsResultWithConsumer
2053
- (MInst.AluRRR alu_op (operand_size ty) dst src1 src2)
2054
- dst)))
2055
-
2056
- ;; Should only be used for AdcS and SbcS
2057
- (decl alu_rrr_with_flags_chained (Type Reg Reg ALUOp) ConsumesAndProducesFlags)
2058
- (rule (alu_rrr_with_flags_chained ty src1 src2 alu_op)
2059
- (let ((dst WritableReg (temp_writable_reg $I64)))
2060
- (ConsumesAndProducesFlags.ReturnsReg
2061
- (MInst.AluRRR alu_op (operand_size ty) dst src1 src2)
2062
- dst)))
2063
-
2064
- ;; Helper for emitting `MInst.BitRR` instructions.
2065
- (decl bit_rr (BitOp Type Reg) Reg)
2066
- (rule (bit_rr op ty src)
2067
- (let ((dst WritableReg (temp_writable_reg $I64))
2068
- (_ Unit (emit (MInst.BitRR op (operand_size ty) dst src))))
2069
- dst))
2070
-
2071
- ;; Helper for emitting `adds` instructions.
2072
- (decl add_with_flags_paired (Type Reg Reg) ProducesFlags)
2073
- (rule (add_with_flags_paired ty src1 src2)
2074
- (let ((dst WritableReg (temp_writable_reg $I64)))
2075
- (ProducesFlags.ProducesFlagsReturnsResultWithConsumer
2076
- (MInst.AluRRR (ALUOp.AddS) (operand_size ty) dst src1 src2)
2077
- dst)))
2078
-
2079
- ;; Helper for emitting `adc` instructions.
2080
- (decl adc_paired (Type Reg Reg) ConsumesFlags)
2081
- (rule (adc_paired ty src1 src2)
2082
- (let ((dst WritableReg (temp_writable_reg $I64)))
2083
- (ConsumesFlags.ConsumesFlagsReturnsResultWithProducer
2084
- (MInst.AluRRR (ALUOp.Adc) (operand_size ty) dst src1 src2)
2085
- dst)))
2086
-
2087
- ;; Helper for emitting `subs` instructions.
2088
- (decl sub_with_flags_paired (Type Reg Reg) ProducesFlags)
2089
- (rule (sub_with_flags_paired ty src1 src2)
2090
- (let ((dst WritableReg (temp_writable_reg $I64)))
2091
- (ProducesFlags.ProducesFlagsReturnsResultWithConsumer
2092
- (MInst.AluRRR (ALUOp.SubS) (operand_size ty) dst src1 src2)
2093
- dst)))
2094
-
2095
- ;; Helper for materializing a boolean value into a register from
2096
- ;; flags.
2097
- (decl materialize_bool_result (Cond) ConsumesFlags)
2098
- (rule (materialize_bool_result cond)
2099
- (let ((dst WritableReg (temp_writable_reg $I64)))
2100
- (ConsumesFlags.ConsumesFlagsReturnsReg
2101
- (MInst.CSet dst cond)
2102
- dst)))
2103
-
2104
- (decl cmn_imm (OperandSize Reg Imm12) ProducesFlags)
2105
- (rule (cmn_imm size src1 src2)
2106
- (ProducesFlags.ProducesFlagsSideEffect
2107
- (MInst.AluRRImm12 (ALUOp.AddS) size (writable_zero_reg)
2108
- src1 src2)))
2109
-
2110
- (decl cmp (OperandSize Reg Reg) ProducesFlags)
2111
- (rule (cmp size src1 src2)
2112
- (ProducesFlags.ProducesFlagsSideEffect
2113
- (MInst.AluRRR (ALUOp.SubS) size (writable_zero_reg)
2114
- src1 src2)))
2115
-
2116
- (decl cmp_imm (OperandSize Reg Imm12) ProducesFlags)
2117
- (rule (cmp_imm size src1 src2)
2118
- (ProducesFlags.ProducesFlagsSideEffect
2119
- (MInst.AluRRImm12 (ALUOp.SubS) size (writable_zero_reg)
2120
- src1 src2)))
2121
-
2122
- (decl cmp64_imm (Reg Imm12) ProducesFlags)
2123
- (rule (cmp64_imm src1 src2)
2124
- (cmp_imm (OperandSize.Size64) src1 src2))
2125
-
2126
- (decl cmp_extend (OperandSize Reg Reg ExtendOp) ProducesFlags)
2127
- (rule (cmp_extend size src1 src2 extend)
2128
- (ProducesFlags.ProducesFlagsSideEffect
2129
- (MInst.AluRRRExtend (ALUOp.SubS) size (writable_zero_reg)
2130
- src1 src2 extend)))
2131
-
2132
- ;; Helper for emitting `sbc` instructions.
2133
- (decl sbc_paired (Type Reg Reg) ConsumesFlags)
2134
- (rule (sbc_paired ty src1 src2)
2135
- (let ((dst WritableReg (temp_writable_reg $I64)))
2136
- (ConsumesFlags.ConsumesFlagsReturnsResultWithProducer
2137
- (MInst.AluRRR (ALUOp.Sbc) (operand_size ty) dst src1 src2)
2138
- dst)))
2139
-
2140
- ;; Helper for emitting `MInst.VecMisc` instructions.
2141
- (decl vec_misc (VecMisc2 Reg VectorSize) Reg)
2142
- (rule (vec_misc op src size)
2143
- (let ((dst WritableReg (temp_writable_reg $I8X16))
2144
- (_ Unit (emit (MInst.VecMisc op dst src size))))
2145
- dst))
2146
-
2147
- ;; Helper for emitting `MInst.VecTbl` instructions.
2148
- (decl vec_tbl (Reg Reg) Reg)
2149
- (rule (vec_tbl rn rm)
2150
- (let ((dst WritableReg (temp_writable_reg $I8X16))
2151
- (_ Unit (emit (MInst.VecTbl dst rn rm))))
2152
- dst))
2153
-
2154
- (decl vec_tbl_ext (Reg Reg Reg) Reg)
2155
- (rule (vec_tbl_ext ri rn rm)
2156
- (let ((dst WritableReg (temp_writable_reg $I8X16))
2157
- (_ Unit (emit (MInst.VecTblExt dst ri rn rm))))
2158
- dst))
2159
-
2160
- ;; Helper for emitting `MInst.VecTbl2` instructions.
2161
- (decl vec_tbl2 (Reg Reg Reg Type) Reg)
2162
- (rule (vec_tbl2 rn rn2 rm ty)
2163
- (let (
2164
- (dst WritableReg (temp_writable_reg $I8X16))
2165
- (_ Unit (emit (MInst.VecTbl2 dst rn rn2 rm)))
2166
- )
2167
- dst))
2168
-
2169
- ;; Helper for emitting `MInst.VecTbl2Ext` instructions.
2170
- (decl vec_tbl2_ext (Reg Reg Reg Reg Type) Reg)
2171
- (rule (vec_tbl2_ext ri rn rn2 rm ty)
2172
- (let (
2173
- (dst WritableReg (temp_writable_reg $I8X16))
2174
- (_ Unit (emit (MInst.VecTbl2Ext dst ri rn rn2 rm)))
2175
- )
2176
- dst))
2177
-
2178
- ;; Helper for emitting `MInst.VecRRRLong` instructions.
2179
- (decl vec_rrr_long (VecRRRLongOp Reg Reg bool) Reg)
2180
- (rule (vec_rrr_long op src1 src2 high_half)
2181
- (let ((dst WritableReg (temp_writable_reg $I8X16))
2182
- (_ Unit (emit (MInst.VecRRRLong op dst src1 src2 high_half))))
2183
- dst))
2184
-
2185
- ;; Helper for emitting `MInst.VecRRPairLong` instructions.
2186
- (decl vec_rr_pair_long (VecRRPairLongOp Reg) Reg)
2187
- (rule (vec_rr_pair_long op src)
2188
- (let ((dst WritableReg (temp_writable_reg $I8X16))
2189
- (_ Unit (emit (MInst.VecRRPairLong op dst src))))
2190
- dst))
2191
-
2192
- ;; Helper for emitting `MInst.VecRRRLongMod` instructions.
2193
- (decl vec_rrrr_long (VecRRRLongModOp Reg Reg Reg bool) Reg)
2194
- (rule (vec_rrrr_long op src1 src2 src3 high_half)
2195
- (let ((dst WritableReg (temp_writable_reg $I8X16))
2196
- (_ Unit (emit (MInst.VecRRRLongMod op dst src1 src2 src3 high_half))))
2197
- dst))
2198
-
2199
- ;; Helper for emitting `MInst.VecRRNarrow` instructions.
2200
- (decl vec_rr_narrow_low (VecRRNarrowOp Reg ScalarSize) Reg)
2201
- (rule (vec_rr_narrow_low op src size)
2202
- (let ((dst WritableReg (temp_writable_reg $I8X16))
2203
- (_ Unit (emit (MInst.VecRRNarrowLow op dst src size))))
2204
- dst))
2205
-
2206
- ;; Helper for emitting `MInst.VecRRNarrow` instructions which update the
2207
- ;; high half of the destination register.
2208
- (decl vec_rr_narrow_high (VecRRNarrowOp Reg Reg ScalarSize) Reg)
2209
- (rule (vec_rr_narrow_high op mod src size)
2210
- (let ((dst WritableReg (temp_writable_reg $I8X16))
2211
- (_ Unit (emit (MInst.VecRRNarrowHigh op dst mod src size))))
2212
- dst))
2213
-
2214
- ;; Helper for emitting `MInst.VecRRLong` instructions.
2215
- (decl vec_rr_long (VecRRLongOp Reg bool) Reg)
2216
- (rule (vec_rr_long op src high_half)
2217
- (let ((dst WritableReg (temp_writable_reg $I8X16))
2218
- (_ Unit (emit (MInst.VecRRLong op dst src high_half))))
2219
- dst))
2220
-
2221
- ;; Helper for emitting `MInst.FpuCSel32` / `MInst.FpuCSel64`
2222
- ;; instructions.
2223
- (decl fpu_csel (Type Cond Reg Reg) ConsumesFlags)
2224
- (rule (fpu_csel $F32 cond if_true if_false)
2225
- (let ((dst WritableReg (temp_writable_reg $F32)))
2226
- (ConsumesFlags.ConsumesFlagsReturnsReg
2227
- (MInst.FpuCSel32 dst if_true if_false cond)
2228
- dst)))
2229
-
2230
- (rule (fpu_csel $F64 cond if_true if_false)
2231
- (let ((dst WritableReg (temp_writable_reg $F64)))
2232
- (ConsumesFlags.ConsumesFlagsReturnsReg
2233
- (MInst.FpuCSel64 dst if_true if_false cond)
2234
- dst)))
2235
-
2236
- ;; Helper for emitting `MInst.VecCSel` instructions.
2237
- (decl vec_csel (Cond Reg Reg) ConsumesFlags)
2238
- (rule (vec_csel cond if_true if_false)
2239
- (let ((dst WritableReg (temp_writable_reg $I8X16)))
2240
- (ConsumesFlags.ConsumesFlagsReturnsReg
2241
- (MInst.VecCSel dst if_true if_false cond)
2242
- dst)))
2243
-
2244
- ;; Helper for emitting `MInst.FpuRound` instructions.
2245
- (decl fpu_round (FpuRoundMode Reg) Reg)
2246
- (rule (fpu_round op rn)
2247
- (let ((dst WritableReg (temp_writable_reg $F64))
2248
- (_ Unit (emit (MInst.FpuRound op dst rn))))
2249
- dst))
2250
-
2251
- ;; Helper for emitting `MInst.FpuMove64` and `MInst.FpuMove128` instructions.
2252
- (decl fpu_move (Type Reg) Reg)
2253
- (rule (fpu_move _ src)
2254
- (let ((dst WritableReg (temp_writable_reg $I8X16))
2255
- (_ Unit (emit (MInst.FpuMove128 dst src))))
2256
- dst))
2257
- (rule 1 (fpu_move (fits_in_64 _) src)
2258
- (let ((dst WritableReg (temp_writable_reg $F64))
2259
- (_ Unit (emit (MInst.FpuMove64 dst src))))
2260
- dst))
2261
-
2262
- ;; Helper for emitting `MInst.MovToFpu` instructions.
2263
- (decl mov_to_fpu (Reg ScalarSize) Reg)
2264
- (rule (mov_to_fpu x size)
2265
- (let ((dst WritableReg (temp_writable_reg $I8X16))
2266
- (_ Unit (emit (MInst.MovToFpu dst x size))))
2267
- dst))
2268
-
2269
- ;; Helper for emitting `MInst.FpuMoveFPImm` instructions.
2270
- (decl fpu_move_fp_imm (ASIMDFPModImm ScalarSize) Reg)
2271
- (rule (fpu_move_fp_imm imm size)
2272
- (let ((dst WritableReg (temp_writable_reg $I8X16))
2273
- (_ Unit (emit (MInst.FpuMoveFPImm dst imm size))))
2274
- dst))
2275
-
2276
- ;; Helper for emitting `MInst.MovToVec` instructions.
2277
- (decl mov_to_vec (Reg Reg u8 VectorSize) Reg)
2278
- (rule (mov_to_vec src1 src2 lane size)
2279
- (let ((dst WritableReg (temp_writable_reg $I8X16))
2280
- (_ Unit (emit (MInst.MovToVec dst src1 src2 lane size))))
2281
- dst))
2282
-
2283
- ;; Helper for emitting `MInst.VecMovElement` instructions.
2284
- (decl mov_vec_elem (Reg Reg u8 u8 VectorSize) Reg)
2285
- (rule (mov_vec_elem src1 src2 dst_idx src_idx size)
2286
- (let ((dst WritableReg (temp_writable_reg $I8X16))
2287
- (_ Unit (emit (MInst.VecMovElement dst src1 src2 dst_idx src_idx size))))
2288
- dst))
2289
-
2290
- ;; Helper for emitting `MInst.MovFromVec` instructions.
2291
- (decl mov_from_vec (Reg u8 ScalarSize) Reg)
2292
- (rule (mov_from_vec rn idx size)
2293
- (let ((dst WritableReg (temp_writable_reg $I64))
2294
- (_ Unit (emit (MInst.MovFromVec dst rn idx size))))
2295
- dst))
2296
-
2297
- ;; Helper for emitting `MInst.MovFromVecSigned` instructions.
2298
- (decl mov_from_vec_signed (Reg u8 VectorSize OperandSize) Reg)
2299
- (rule (mov_from_vec_signed rn idx size scalar_size)
2300
- (let ((dst WritableReg (temp_writable_reg $I64))
2301
- (_ Unit (emit (MInst.MovFromVecSigned dst rn idx size scalar_size))))
2302
- dst))
2303
-
2304
- (decl fpu_move_from_vec (Reg u8 VectorSize) Reg)
2305
- (rule (fpu_move_from_vec rn idx size)
2306
- (let ((dst WritableReg (temp_writable_reg $I8X16))
2307
- (_ Unit (emit (MInst.FpuMoveFromVec dst rn idx size))))
2308
- dst))
2309
-
2310
- ;; Helper for emitting `MInst.Extend` instructions.
2311
- (decl extend (Reg bool u8 u8) Reg)
2312
- (rule (extend rn signed from_bits to_bits)
2313
- (let ((dst WritableReg (temp_writable_reg $I64))
2314
- (_ Unit (emit (MInst.Extend dst rn signed from_bits to_bits))))
2315
- dst))
2316
-
2317
- ;; Helper for emitting `MInst.FpuExtend` instructions.
2318
- (decl fpu_extend (Reg ScalarSize) Reg)
2319
- (rule (fpu_extend src size)
2320
- (let ((dst WritableReg (temp_writable_reg $F32X4))
2321
- (_ Unit (emit (MInst.FpuExtend dst src size))))
2322
- dst))
2323
-
2324
- ;; Helper for emitting `MInst.VecExtend` instructions.
2325
- (decl vec_extend (VecExtendOp Reg bool ScalarSize) Reg)
2326
- (rule (vec_extend op src high_half size)
2327
- (let ((dst WritableReg (temp_writable_reg $I8X16))
2328
- (_ Unit (emit (MInst.VecExtend op dst src high_half size))))
2329
- dst))
2330
-
2331
- ;; Helper for emitting `MInst.VecExtract` instructions.
2332
- (decl vec_extract (Reg Reg u8) Reg)
2333
- (rule (vec_extract src1 src2 idx)
2334
- (let ((dst WritableReg (temp_writable_reg $I8X16))
2335
- (_ Unit (emit (MInst.VecExtract dst src1 src2 idx))))
2336
- dst))
2337
-
2338
- ;; Helper for emitting `MInst.LoadAcquire` instructions.
2339
- (decl load_acquire (Type MemFlags Reg) Reg)
2340
- (rule (load_acquire ty flags addr)
2341
- (let ((dst WritableReg (temp_writable_reg $I64))
2342
- (_ Unit (emit (MInst.LoadAcquire ty dst addr flags))))
2343
- dst))
2344
-
2345
- ;; Helper for emitting `MInst.StoreRelease` instructions.
2346
- (decl store_release (Type MemFlags Reg Reg) SideEffectNoResult)
2347
- (rule (store_release ty flags src addr)
2348
- (SideEffectNoResult.Inst (MInst.StoreRelease ty src addr flags)))
2349
-
2350
- ;; Helper for generating a `tst` instruction.
2351
- ;;
2352
- ;; Produces a `ProducesFlags` rather than a register or emitted instruction
2353
- ;; which must be paired with `with_flags*` helpers.
2354
- (decl tst_imm (Type Reg ImmLogic) ProducesFlags)
2355
- (rule (tst_imm ty reg imm)
2356
- (ProducesFlags.ProducesFlagsSideEffect
2357
- (MInst.AluRRImmLogic (ALUOp.AndS)
2358
- (operand_size ty)
2359
- (writable_zero_reg)
2360
- reg
2361
- imm)))
2362
-
2363
- ;; Helper for generating a `CSel` instruction.
2364
- ;;
2365
- ;; Note that this doesn't actually emit anything, instead it produces a
2366
- ;; `ConsumesFlags` instruction which must be consumed with `with_flags*`
2367
- ;; helpers.
2368
- (decl csel (Cond Reg Reg) ConsumesFlags)
2369
- (rule (csel cond if_true if_false)
2370
- (let ((dst WritableReg (temp_writable_reg $I64)))
2371
- (ConsumesFlags.ConsumesFlagsReturnsReg
2372
- (MInst.CSel dst cond if_true if_false)
2373
- dst)))
2374
-
2375
- ;; Helper for constructing `cset` instructions.
2376
- (decl cset (Cond) ConsumesFlags)
2377
- (rule (cset cond)
2378
- (let ((dst WritableReg (temp_writable_reg $I64)))
2379
- (ConsumesFlags.ConsumesFlagsReturnsReg (MInst.CSet dst cond) dst)))
2380
-
2381
- ;; Helper for constructing `cset` instructions, when the flags producer will
2382
- ;; also return a value.
2383
- (decl cset_paired (Cond) ConsumesFlags)
2384
- (rule (cset_paired cond)
2385
- (let ((dst WritableReg (temp_writable_reg $I64)))
2386
- (ConsumesFlags.ConsumesFlagsReturnsResultWithProducer (MInst.CSet dst cond) dst)))
2387
-
2388
- ;; Helper for constructing `csetm` instructions.
2389
- (decl csetm (Cond) ConsumesFlags)
2390
- (rule (csetm cond)
2391
- (let ((dst WritableReg (temp_writable_reg $I64)))
2392
- (ConsumesFlags.ConsumesFlagsReturnsReg (MInst.CSetm dst cond) dst)))
2393
-
2394
- ;; Helper for generating a `CSNeg` instruction.
2395
- ;;
2396
- ;; Note that this doesn't actually emit anything, instead it produces a
2397
- ;; `ConsumesFlags` instruction which must be consumed with `with_flags*`
2398
- ;; helpers.
2399
- (decl csneg (Cond Reg Reg) ConsumesFlags)
2400
- (rule (csneg cond if_true if_false)
2401
- (let ((dst WritableReg (temp_writable_reg $I64)))
2402
- (ConsumesFlags.ConsumesFlagsReturnsReg
2403
- (MInst.CSNeg dst cond if_true if_false)
2404
- dst)))
2405
-
2406
- ;; Helper for generating `MInst.CCmp` instructions.
2407
- ;; Creates a new `ProducesFlags` from the supplied `ProducesFlags` followed
2408
- ;; immediately by the `MInst.CCmp` instruction.
2409
- (decl ccmp (OperandSize Reg Reg NZCV Cond ProducesFlags) ProducesFlags)
2410
- (rule (ccmp size rn rm nzcv cond inst_input)
2411
- (produces_flags_concat inst_input (ProducesFlags.ProducesFlagsSideEffect (MInst.CCmp size rn rm nzcv cond))))
2412
-
2413
- ;; Helper for generating `MInst.CCmpImm` instructions.
2414
- (decl ccmp_imm (OperandSize Reg UImm5 NZCV Cond) ConsumesFlags)
2415
- (rule 1 (ccmp_imm size rn imm nzcv cond)
2416
- (let ((dst WritableReg (temp_writable_reg $I64)))
2417
- (ConsumesFlags.ConsumesFlagsTwiceReturnsValueRegs
2418
- (MInst.CCmpImm size rn imm nzcv cond)
2419
- (MInst.CSet dst cond)
2420
- (value_reg dst))))
2421
-
2422
- ;; Helpers for generating `add` instructions.
2423
-
2424
- (decl add (Type Reg Reg) Reg)
2425
- (rule (add ty x y) (alu_rrr (ALUOp.Add) ty x y))
2426
-
2427
- (decl add_imm (Type Reg Imm12) Reg)
2428
- (rule (add_imm ty x y) (alu_rr_imm12 (ALUOp.Add) ty x y))
2429
-
2430
- (decl add_extend (Type Reg ExtendedValue) Reg)
2431
- (rule (add_extend ty x y) (alu_rr_extend_reg (ALUOp.Add) ty x y))
2432
-
2433
- (decl add_extend_op (Type Reg Reg ExtendOp) Reg)
2434
- (rule (add_extend_op ty x y extend) (alu_rrr_extend (ALUOp.Add) ty x y extend))
2435
-
2436
- (decl add_shift (Type Reg Reg ShiftOpAndAmt) Reg)
2437
- (rule (add_shift ty x y z) (alu_rrr_shift (ALUOp.Add) ty x y z))
2438
-
2439
- (decl add_vec (Reg Reg VectorSize) Reg)
2440
- (rule (add_vec x y size) (vec_rrr (VecALUOp.Add) x y size))
2441
-
2442
- ;; Helpers for generating `sub` instructions.
2443
-
2444
- (decl sub (Type Reg Reg) Reg)
2445
- (rule (sub ty x y) (alu_rrr (ALUOp.Sub) ty x y))
2446
-
2447
- (decl sub_imm (Type Reg Imm12) Reg)
2448
- (rule (sub_imm ty x y) (alu_rr_imm12 (ALUOp.Sub) ty x y))
2449
-
2450
- (decl sub_extend (Type Reg ExtendedValue) Reg)
2451
- (rule (sub_extend ty x y) (alu_rr_extend_reg (ALUOp.Sub) ty x y))
2452
-
2453
- (decl sub_shift (Type Reg Reg ShiftOpAndAmt) Reg)
2454
- (rule (sub_shift ty x y z) (alu_rrr_shift (ALUOp.Sub) ty x y z))
2455
-
2456
- (decl sub_vec (Reg Reg VectorSize) Reg)
2457
- (rule (sub_vec x y size) (vec_rrr (VecALUOp.Sub) x y size))
2458
-
2459
- (decl sub_i128 (ValueRegs ValueRegs) ValueRegs)
2460
- (rule (sub_i128 x y)
2461
- (let
2462
- ;; Get the high/low registers for `x`.
2463
- ((x_regs ValueRegs x)
2464
- (x_lo Reg (value_regs_get x_regs 0))
2465
- (x_hi Reg (value_regs_get x_regs 1))
2466
-
2467
- ;; Get the high/low registers for `y`.
2468
- (y_regs ValueRegs y)
2469
- (y_lo Reg (value_regs_get y_regs 0))
2470
- (y_hi Reg (value_regs_get y_regs 1)))
2471
- ;; the actual subtraction is `subs` followed by `sbc` which comprises
2472
- ;; the low/high bits of the result
2473
- (with_flags
2474
- (sub_with_flags_paired $I64 x_lo y_lo)
2475
- (sbc_paired $I64 x_hi y_hi))))
2476
-
2477
- ;; Helpers for generating `madd` instructions.
2478
-
2479
- (decl madd (Type Reg Reg Reg) Reg)
2480
- (rule (madd ty x y z) (alu_rrrr (ALUOp3.MAdd) ty x y z))
2481
-
2482
- ;; Helpers for generating `msub` instructions.
2483
-
2484
- (decl msub (Type Reg Reg Reg) Reg)
2485
- (rule (msub ty x y z) (alu_rrrr (ALUOp3.MSub) ty x y z))
2486
-
2487
- ;; Helpers for generating `umaddl` instructions
2488
- (decl umaddl (Reg Reg Reg) Reg)
2489
- (rule (umaddl x y z) (alu_rrrr (ALUOp3.UMAddL) $I32 x y z))
2490
-
2491
- ;; Helpers for generating `smaddl` instructions
2492
- (decl smaddl (Reg Reg Reg) Reg)
2493
- (rule (smaddl x y z) (alu_rrrr (ALUOp3.SMAddL) $I32 x y z))
2494
-
2495
- ;; Helper for generating `uqadd` instructions.
2496
- (decl uqadd (Reg Reg VectorSize) Reg)
2497
- (rule (uqadd x y size) (vec_rrr (VecALUOp.Uqadd) x y size))
2498
-
2499
- ;; Helper for generating `sqadd` instructions.
2500
- (decl sqadd (Reg Reg VectorSize) Reg)
2501
- (rule (sqadd x y size) (vec_rrr (VecALUOp.Sqadd) x y size))
2502
-
2503
- ;; Helper for generating `uqsub` instructions.
2504
- (decl uqsub (Reg Reg VectorSize) Reg)
2505
- (rule (uqsub x y size) (vec_rrr (VecALUOp.Uqsub) x y size))
2506
-
2507
- ;; Helper for generating `sqsub` instructions.
2508
- (decl sqsub (Reg Reg VectorSize) Reg)
2509
- (rule (sqsub x y size) (vec_rrr (VecALUOp.Sqsub) x y size))
2510
-
2511
- ;; Helper for generating `umulh` instructions.
2512
- (decl umulh (Type Reg Reg) Reg)
2513
- (rule (umulh ty x y) (alu_rrr (ALUOp.UMulH) ty x y))
2514
-
2515
- ;; Helper for generating `smulh` instructions.
2516
- (decl smulh (Type Reg Reg) Reg)
2517
- (rule (smulh ty x y) (alu_rrr (ALUOp.SMulH) ty x y))
2518
-
2519
- ;; Helper for generating `mul` instructions.
2520
- (decl mul (Reg Reg VectorSize) Reg)
2521
- (rule (mul x y size) (vec_rrr (VecALUOp.Mul) x y size))
2522
-
2523
- ;; Helper for generating `neg` instructions.
2524
- (decl neg (Reg VectorSize) Reg)
2525
- (rule (neg x size) (vec_misc (VecMisc2.Neg) x size))
2526
-
2527
- ;; Helper for generating `rev16` instructions.
2528
- (decl rev16 (Reg VectorSize) Reg)
2529
- (rule (rev16 x size) (vec_misc (VecMisc2.Rev16) x size))
2530
-
2531
- ;; Helper for generating `rev32` instructions.
2532
- (decl rev32 (Reg VectorSize) Reg)
2533
- (rule (rev32 x size) (vec_misc (VecMisc2.Rev32) x size))
2534
-
2535
- ;; Helper for generating `rev64` instructions.
2536
- (decl rev64 (Reg VectorSize) Reg)
2537
- (rule (rev64 x size) (vec_misc (VecMisc2.Rev64) x size))
2538
-
2539
- ;; Helper for generating `xtn` instructions.
2540
- (decl xtn (Reg ScalarSize) Reg)
2541
- (rule (xtn x size) (vec_rr_narrow_low (VecRRNarrowOp.Xtn) x size))
2542
-
2543
- ;; Helper for generating `fcvtn` instructions.
2544
- (decl fcvtn (Reg ScalarSize) Reg)
2545
- (rule (fcvtn x size) (vec_rr_narrow_low (VecRRNarrowOp.Fcvtn) x size))
2546
-
2547
- ;; Helper for generating `sqxtn` instructions.
2548
- (decl sqxtn (Reg ScalarSize) Reg)
2549
- (rule (sqxtn x size) (vec_rr_narrow_low (VecRRNarrowOp.Sqxtn) x size))
2550
-
2551
- ;; Helper for generating `sqxtn2` instructions.
2552
- (decl sqxtn2 (Reg Reg ScalarSize) Reg)
2553
- (rule (sqxtn2 x y size) (vec_rr_narrow_high (VecRRNarrowOp.Sqxtn) x y size))
2554
-
2555
- ;; Helper for generating `sqxtun` instructions.
2556
- (decl sqxtun (Reg ScalarSize) Reg)
2557
- (rule (sqxtun x size) (vec_rr_narrow_low (VecRRNarrowOp.Sqxtun) x size))
2558
-
2559
- ;; Helper for generating `sqxtun2` instructions.
2560
- (decl sqxtun2 (Reg Reg ScalarSize) Reg)
2561
- (rule (sqxtun2 x y size) (vec_rr_narrow_high (VecRRNarrowOp.Sqxtun) x y size))
2562
-
2563
- ;; Helper for generating `uqxtn` instructions.
2564
- (decl uqxtn (Reg ScalarSize) Reg)
2565
- (rule (uqxtn x size) (vec_rr_narrow_low (VecRRNarrowOp.Uqxtn) x size))
2566
-
2567
- ;; Helper for generating `uqxtn2` instructions.
2568
- (decl uqxtn2 (Reg Reg ScalarSize) Reg)
2569
- (rule (uqxtn2 x y size) (vec_rr_narrow_high (VecRRNarrowOp.Uqxtn) x y size))
2570
-
2571
- ;; Helper for generating `fence` instructions.
2572
- (decl aarch64_fence () SideEffectNoResult)
2573
- (rule (aarch64_fence)
2574
- (SideEffectNoResult.Inst (MInst.Fence)))
2575
-
2576
- ;; Helper for generating `csdb` instructions.
2577
- (decl csdb () SideEffectNoResult)
2578
- (rule (csdb)
2579
- (SideEffectNoResult.Inst (MInst.Csdb)))
2580
-
2581
- ;; Helper for generating `brk` instructions.
2582
- (decl brk () SideEffectNoResult)
2583
- (rule (brk)
2584
- (SideEffectNoResult.Inst (MInst.Brk)))
2585
-
2586
- ;; Helper for generating `addp` instructions.
2587
- (decl addp (Reg Reg VectorSize) Reg)
2588
- (rule (addp x y size) (vec_rrr (VecALUOp.Addp) x y size))
2589
-
2590
- ;; Helper for generating `zip1` instructions.
2591
- (decl zip1 (Reg Reg VectorSize) Reg)
2592
- (rule (zip1 x y size) (vec_rrr (VecALUOp.Zip1) x y size))
2593
-
2594
- ;; Helper for generating vector `abs` instructions.
2595
- (decl vec_abs (Reg VectorSize) Reg)
2596
- (rule (vec_abs x size) (vec_misc (VecMisc2.Abs) x size))
2597
-
2598
- ;; Helper for generating instruction sequences to calculate a scalar absolute
2599
- ;; value.
2600
- (decl abs (OperandSize Reg) Reg)
2601
- (rule (abs size x)
2602
- (value_regs_get (with_flags (cmp_imm size x (u8_into_imm12 0))
2603
- (csneg (Cond.Gt) x x)) 0))
2604
-
2605
- ;; Helper for generating `addv` instructions.
2606
- (decl addv (Reg VectorSize) Reg)
2607
- (rule (addv x size) (vec_lanes (VecLanesOp.Addv) x size))
2608
-
2609
- ;; Helper for generating `shll32` instructions.
2610
- (decl shll32 (Reg bool) Reg)
2611
- (rule (shll32 x high_half) (vec_rr_long (VecRRLongOp.Shll32) x high_half))
2612
-
2613
- ;; Helpers for generating `addlp` instructions.
2614
-
2615
- (decl saddlp8 (Reg) Reg)
2616
- (rule (saddlp8 x) (vec_rr_pair_long (VecRRPairLongOp.Saddlp8) x))
2617
-
2618
- (decl saddlp16 (Reg) Reg)
2619
- (rule (saddlp16 x) (vec_rr_pair_long (VecRRPairLongOp.Saddlp16) x))
2620
-
2621
- (decl uaddlp8 (Reg) Reg)
2622
- (rule (uaddlp8 x) (vec_rr_pair_long (VecRRPairLongOp.Uaddlp8) x))
2623
-
2624
- (decl uaddlp16 (Reg) Reg)
2625
- (rule (uaddlp16 x) (vec_rr_pair_long (VecRRPairLongOp.Uaddlp16) x))
2626
-
2627
- ;; Helper for generating `umlal32` instructions.
2628
- (decl umlal32 (Reg Reg Reg bool) Reg)
2629
- (rule (umlal32 x y z high_half) (vec_rrrr_long (VecRRRLongModOp.Umlal32) x y z high_half))
2630
-
2631
- ;; Helper for generating `smull8` instructions.
2632
- (decl smull8 (Reg Reg bool) Reg)
2633
- (rule (smull8 x y high_half) (vec_rrr_long (VecRRRLongOp.Smull8) x y high_half))
2634
-
2635
- ;; Helper for generating `umull8` instructions.
2636
- (decl umull8 (Reg Reg bool) Reg)
2637
- (rule (umull8 x y high_half) (vec_rrr_long (VecRRRLongOp.Umull8) x y high_half))
2638
-
2639
- ;; Helper for generating `smull16` instructions.
2640
- (decl smull16 (Reg Reg bool) Reg)
2641
- (rule (smull16 x y high_half) (vec_rrr_long (VecRRRLongOp.Smull16) x y high_half))
2642
-
2643
- ;; Helper for generating `umull16` instructions.
2644
- (decl umull16 (Reg Reg bool) Reg)
2645
- (rule (umull16 x y high_half) (vec_rrr_long (VecRRRLongOp.Umull16) x y high_half))
2646
-
2647
- ;; Helper for generating `smull32` instructions.
2648
- (decl smull32 (Reg Reg bool) Reg)
2649
- (rule (smull32 x y high_half) (vec_rrr_long (VecRRRLongOp.Smull32) x y high_half))
2650
-
2651
- ;; Helper for generating `umull32` instructions.
2652
- (decl umull32 (Reg Reg bool) Reg)
2653
- (rule (umull32 x y high_half) (vec_rrr_long (VecRRRLongOp.Umull32) x y high_half))
2654
-
2655
- ;; Helper for generating `asr` instructions.
2656
- (decl asr (Type Reg Reg) Reg)
2657
- (rule (asr ty x y) (alu_rrr (ALUOp.Asr) ty x y))
2658
-
2659
- (decl asr_imm (Type Reg ImmShift) Reg)
2660
- (rule (asr_imm ty x imm) (alu_rr_imm_shift (ALUOp.Asr) ty x imm))
2661
-
2662
- ;; Helper for generating `lsr` instructions.
2663
- (decl lsr (Type Reg Reg) Reg)
2664
- (rule (lsr ty x y) (alu_rrr (ALUOp.Lsr) ty x y))
2665
-
2666
- (decl lsr_imm (Type Reg ImmShift) Reg)
2667
- (rule (lsr_imm ty x imm) (alu_rr_imm_shift (ALUOp.Lsr) ty x imm))
2668
-
2669
- ;; Helper for generating `lsl` instructions.
2670
- (decl lsl (Type Reg Reg) Reg)
2671
- (rule (lsl ty x y) (alu_rrr (ALUOp.Lsl) ty x y))
2672
-
2673
- (decl lsl_imm (Type Reg ImmShift) Reg)
2674
- (rule (lsl_imm ty x imm) (alu_rr_imm_shift (ALUOp.Lsl) ty x imm))
2675
-
2676
- ;; Helper for generating `udiv` instructions.
2677
- (decl a64_udiv (Type Reg Reg) Reg)
2678
- (rule (a64_udiv ty x y) (alu_rrr (ALUOp.UDiv) ty x y))
2679
-
2680
- ;; Helper for generating `sdiv` instructions.
2681
- (decl a64_sdiv (Type Reg Reg) Reg)
2682
- (rule (a64_sdiv ty x y) (alu_rrr (ALUOp.SDiv) ty x y))
2683
-
2684
- ;; Helper for generating `not` instructions.
2685
- (decl not (Reg VectorSize) Reg)
2686
- (rule (not x size) (vec_misc (VecMisc2.Not) x size))
2687
-
2688
- ;; Helpers for generating `orr_not` instructions.
2689
-
2690
- (decl orr_not (Type Reg Reg) Reg)
2691
- (rule (orr_not ty x y) (alu_rrr (ALUOp.OrrNot) ty x y))
2692
-
2693
- (decl orr_not_shift (Type Reg Reg ShiftOpAndAmt) Reg)
2694
- (rule (orr_not_shift ty x y shift) (alu_rrr_shift (ALUOp.OrrNot) ty x y shift))
2695
-
2696
- ;; Helpers for generating `orr` instructions.
2697
-
2698
- (decl orr (Type Reg Reg) Reg)
2699
- (rule (orr ty x y) (alu_rrr (ALUOp.Orr) ty x y))
2700
-
2701
- (decl orr_imm (Type Reg ImmLogic) Reg)
2702
- (rule (orr_imm ty x y) (alu_rr_imm_logic (ALUOp.Orr) ty x y))
2703
-
2704
- (decl orr_shift (Type Reg Reg ShiftOpAndAmt) Reg)
2705
- (rule (orr_shift ty x y shift) (alu_rrr_shift (ALUOp.Orr) ty x y shift))
2706
-
2707
- (decl orr_vec (Reg Reg VectorSize) Reg)
2708
- (rule (orr_vec x y size) (vec_rrr (VecALUOp.Orr) x y size))
2709
-
2710
- ;; Helpers for generating `and` instructions.
2711
-
2712
- (decl and_reg (Type Reg Reg) Reg)
2713
- (rule (and_reg ty x y) (alu_rrr (ALUOp.And) ty x y))
2714
-
2715
- (decl and_imm (Type Reg ImmLogic) Reg)
2716
- (rule (and_imm ty x y) (alu_rr_imm_logic (ALUOp.And) ty x y))
2717
-
2718
- (decl and_vec (Reg Reg VectorSize) Reg)
2719
- (rule (and_vec x y size) (vec_rrr (VecALUOp.And) x y size))
2720
-
2721
- ;; Helpers for generating `eor` instructions.
2722
- (decl eor (Type Reg Reg) Reg)
2723
- (rule (eor ty x y) (alu_rrr (ALUOp.Eor) ty x y))
2724
-
2725
- (decl eor_vec (Reg Reg VectorSize) Reg)
2726
- (rule (eor_vec x y size) (vec_rrr (VecALUOp.Eor) x y size))
2727
-
2728
- ;; Helpers for generating `bic` instructions.
2729
-
2730
- (decl bic (Type Reg Reg) Reg)
2731
- (rule (bic ty x y) (alu_rrr (ALUOp.AndNot) ty x y))
2732
-
2733
- (decl bic_vec (Reg Reg VectorSize) Reg)
2734
- (rule (bic_vec x y size) (vec_rrr (VecALUOp.Bic) x y size))
2735
-
2736
- ;; Helpers for generating `sshl` instructions.
2737
- (decl sshl (Reg Reg VectorSize) Reg)
2738
- (rule (sshl x y size) (vec_rrr (VecALUOp.Sshl) x y size))
2739
-
2740
- ;; Helpers for generating `ushl` instructions.
2741
- (decl ushl (Reg Reg VectorSize) Reg)
2742
- (rule (ushl x y size) (vec_rrr (VecALUOp.Ushl) x y size))
2743
-
2744
- ;; Helpers for generating `ushl` instructions.
2745
- (decl ushl_vec_imm (Reg u8 VectorSize) Reg)
2746
- (rule (ushl_vec_imm x amt size) (vec_shift_imm (VecShiftImmOp.Shl) amt x size))
2747
-
2748
- ;; Helpers for generating `ushr` instructions.
2749
- (decl ushr_vec_imm (Reg u8 VectorSize) Reg)
2750
- (rule (ushr_vec_imm x amt size) (vec_shift_imm (VecShiftImmOp.Ushr) amt x size))
2751
-
2752
- ;; Helpers for generating `sshr` instructions.
2753
- (decl sshr_vec_imm (Reg u8 VectorSize) Reg)
2754
- (rule (sshr_vec_imm x amt size) (vec_shift_imm (VecShiftImmOp.Sshr) amt x size))
2755
-
2756
- ;; Helpers for generating `rotr` instructions.
2757
-
2758
- (decl a64_rotr (Type Reg Reg) Reg)
2759
- (rule (a64_rotr ty x y) (alu_rrr (ALUOp.RotR) ty x y))
2760
-
2761
- (decl a64_rotr_imm (Type Reg ImmShift) Reg)
2762
- (rule (a64_rotr_imm ty x y) (alu_rr_imm_shift (ALUOp.RotR) ty x y))
2763
-
2764
- ;; Helpers for generating `rbit` instructions.
2765
-
2766
- (decl rbit (Type Reg) Reg)
2767
- (rule (rbit ty x) (bit_rr (BitOp.RBit) ty x))
2768
-
2769
- ;; Helpers for generating `clz` instructions.
2770
-
2771
- (decl a64_clz (Type Reg) Reg)
2772
- (rule (a64_clz ty x) (bit_rr (BitOp.Clz) ty x))
2773
-
2774
- ;; Helpers for generating `cls` instructions.
2775
-
2776
- (decl a64_cls (Type Reg) Reg)
2777
- (rule (a64_cls ty x) (bit_rr (BitOp.Cls) ty x))
2778
-
2779
- ;; Helpers for generating `rev` instructions
2780
-
2781
- (decl a64_rev16 (Type Reg) Reg)
2782
- (rule (a64_rev16 ty x) (bit_rr (BitOp.Rev16) ty x))
2783
-
2784
- (decl a64_rev32 (Type Reg) Reg)
2785
- (rule (a64_rev32 ty x) (bit_rr (BitOp.Rev32) ty x))
2786
-
2787
- (decl a64_rev64 (Type Reg) Reg)
2788
- (rule (a64_rev64 ty x) (bit_rr (BitOp.Rev64) ty x))
2789
-
2790
- ;; Helpers for generating `eon` instructions.
2791
-
2792
- (decl eon (Type Reg Reg) Reg)
2793
- (rule (eon ty x y) (alu_rrr (ALUOp.EorNot) ty x y))
2794
-
2795
- ;; Helpers for generating `cnt` instructions.
2796
-
2797
- (decl vec_cnt (Reg VectorSize) Reg)
2798
- (rule (vec_cnt x size) (vec_misc (VecMisc2.Cnt) x size))
2799
-
2800
- ;; Helpers for generating a `bsl` instruction.
2801
-
2802
- (decl bsl (Type Reg Reg Reg) Reg)
2803
- (rule (bsl ty c x y)
2804
- (vec_rrr_mod (VecALUModOp.Bsl) c x y (vector_size ty)))
2805
-
2806
- ;; Helper for generating a `udf` instruction.
2807
-
2808
- (decl udf (TrapCode) SideEffectNoResult)
2809
- (rule (udf trap_code)
2810
- (SideEffectNoResult.Inst (MInst.Udf trap_code)))
2811
-
2812
- ;; Helpers for generating various load instructions, with varying
2813
- ;; widths and sign/zero-extending properties.
2814
- (decl aarch64_uload8 (AMode MemFlags) Reg)
2815
- (rule (aarch64_uload8 amode flags)
2816
- (let ((dst WritableReg (temp_writable_reg $I64))
2817
- (_ Unit (emit (MInst.ULoad8 dst amode flags))))
2818
- dst))
2819
- (decl aarch64_sload8 (AMode MemFlags) Reg)
2820
- (rule (aarch64_sload8 amode flags)
2821
- (let ((dst WritableReg (temp_writable_reg $I64))
2822
- (_ Unit (emit (MInst.SLoad8 dst amode flags))))
2823
- dst))
2824
- (decl aarch64_uload16 (AMode MemFlags) Reg)
2825
- (rule (aarch64_uload16 amode flags)
2826
- (let ((dst WritableReg (temp_writable_reg $I64))
2827
- (_ Unit (emit (MInst.ULoad16 dst amode flags))))
2828
- dst))
2829
- (decl aarch64_sload16 (AMode MemFlags) Reg)
2830
- (rule (aarch64_sload16 amode flags)
2831
- (let ((dst WritableReg (temp_writable_reg $I64))
2832
- (_ Unit (emit (MInst.SLoad16 dst amode flags))))
2833
- dst))
2834
- (decl aarch64_uload32 (AMode MemFlags) Reg)
2835
- (rule (aarch64_uload32 amode flags)
2836
- (let ((dst WritableReg (temp_writable_reg $I64))
2837
- (_ Unit (emit (MInst.ULoad32 dst amode flags))))
2838
- dst))
2839
- (decl aarch64_sload32 (AMode MemFlags) Reg)
2840
- (rule (aarch64_sload32 amode flags)
2841
- (let ((dst WritableReg (temp_writable_reg $I64))
2842
- (_ Unit (emit (MInst.SLoad32 dst amode flags))))
2843
- dst))
2844
- (decl aarch64_uload64 (AMode MemFlags) Reg)
2845
- (rule (aarch64_uload64 amode flags)
2846
- (let ((dst WritableReg (temp_writable_reg $I64))
2847
- (_ Unit (emit (MInst.ULoad64 dst amode flags))))
2848
- dst))
2849
- (decl aarch64_fpuload32 (AMode MemFlags) Reg)
2850
- (rule (aarch64_fpuload32 amode flags)
2851
- (let ((dst WritableReg (temp_writable_reg $F64))
2852
- (_ Unit (emit (MInst.FpuLoad32 dst amode flags))))
2853
- dst))
2854
- (decl aarch64_fpuload64 (AMode MemFlags) Reg)
2855
- (rule (aarch64_fpuload64 amode flags)
2856
- (let ((dst WritableReg (temp_writable_reg $F64))
2857
- (_ Unit (emit (MInst.FpuLoad64 dst amode flags))))
2858
- dst))
2859
- (decl aarch64_fpuload128 (AMode MemFlags) Reg)
2860
- (rule (aarch64_fpuload128 amode flags)
2861
- (let ((dst WritableReg (temp_writable_reg $F64X2))
2862
- (_ Unit (emit (MInst.FpuLoad128 dst amode flags))))
2863
- dst))
2864
- (decl aarch64_loadp64 (PairAMode MemFlags) ValueRegs)
2865
- (rule (aarch64_loadp64 amode flags)
2866
- (let ((dst1 WritableReg (temp_writable_reg $I64))
2867
- (dst2 WritableReg (temp_writable_reg $I64))
2868
- (_ Unit (emit (MInst.LoadP64 dst1 dst2 amode flags))))
2869
- (value_regs dst1 dst2)))
2870
-
2871
- ;; Helpers for generating various store instructions with varying
2872
- ;; widths.
2873
- (decl aarch64_store8 (AMode MemFlags Reg) SideEffectNoResult)
2874
- (rule (aarch64_store8 amode flags val)
2875
- (SideEffectNoResult.Inst (MInst.Store8 val amode flags)))
2876
- (decl aarch64_store16 (AMode MemFlags Reg) SideEffectNoResult)
2877
- (rule (aarch64_store16 amode flags val)
2878
- (SideEffectNoResult.Inst (MInst.Store16 val amode flags)))
2879
- (decl aarch64_store32 (AMode MemFlags Reg) SideEffectNoResult)
2880
- (rule (aarch64_store32 amode flags val)
2881
- (SideEffectNoResult.Inst (MInst.Store32 val amode flags)))
2882
- (decl aarch64_store64 (AMode MemFlags Reg) SideEffectNoResult)
2883
- (rule (aarch64_store64 amode flags val)
2884
- (SideEffectNoResult.Inst (MInst.Store64 val amode flags)))
2885
- (decl aarch64_fpustore32 (AMode MemFlags Reg) SideEffectNoResult)
2886
- (rule (aarch64_fpustore32 amode flags val)
2887
- (SideEffectNoResult.Inst (MInst.FpuStore32 val amode flags)))
2888
- (decl aarch64_fpustore64 (AMode MemFlags Reg) SideEffectNoResult)
2889
- (rule (aarch64_fpustore64 amode flags val)
2890
- (SideEffectNoResult.Inst (MInst.FpuStore64 val amode flags)))
2891
- (decl aarch64_fpustore128 (AMode MemFlags Reg) SideEffectNoResult)
2892
- (rule (aarch64_fpustore128 amode flags val)
2893
- (SideEffectNoResult.Inst (MInst.FpuStore128 val amode flags)))
2894
- (decl aarch64_storep64 (PairAMode MemFlags Reg Reg) SideEffectNoResult)
2895
- (rule (aarch64_storep64 amode flags val1 val2)
2896
- (SideEffectNoResult.Inst (MInst.StoreP64 val1 val2 amode flags)))
2897
-
2898
- ;; Helper for generating a `trapif` instruction.
2899
-
2900
- (decl trap_if (ProducesFlags TrapCode Cond) InstOutput)
2901
- (rule (trap_if flags trap_code cond)
2902
- (side_effect
2903
- (with_flags_side_effect flags
2904
- (ConsumesFlags.ConsumesFlagsSideEffect
2905
- (MInst.TrapIf (cond_br_cond cond) trap_code)))))
2906
-
2907
- ;; Immediate value helpers ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2908
-
2909
- ;; Type of extension performed by an immediate helper
2910
- (type ImmExtend
2911
- (enum
2912
- (Sign)
2913
- (Zero)))
2914
-
2915
- ;; Arguments:
2916
- ;; * Immediate type
2917
- ;; * Way to extend the immediate value to the full width of the destination
2918
- ;; register
2919
- ;; * Immediate value - only the bits that fit within the type are used and
2920
- ;; extended, while the rest are ignored
2921
- ;;
2922
- ;; Note that, unlike the convention in the AArch64 backend, this helper leaves
2923
- ;; all bits in the destination register in a defined state, i.e. smaller types
2924
- ;; such as `I8` are either sign- or zero-extended.
2925
- (decl imm (Type ImmExtend u64) Reg)
2926
-
2927
- ;; Move wide immediate instructions; to simplify, we only match when we
2928
- ;; are zero-extending the value.
2929
- (rule 3 (imm (integral_ty ty) (ImmExtend.Zero) k)
2930
- (if-let n (move_wide_const_from_u64 ty k))
2931
- (add_range_fact
2932
- (movz n (operand_size ty))
2933
- 64 k k))
2934
- (rule 2 (imm (integral_ty (ty_32_or_64 ty)) (ImmExtend.Zero) k)
2935
- (if-let n (move_wide_const_from_inverted_u64 ty k))
2936
- (add_range_fact
2937
- (movn n (operand_size ty))
2938
- 64 k k))
2939
-
2940
- ;; Weird logical-instruction immediate in ORI using zero register; to simplify,
2941
- ;; we only match when we are zero-extending the value.
2942
- (rule 1 (imm (integral_ty ty) (ImmExtend.Zero) k)
2943
- (if-let n (imm_logic_from_u64 ty k))
2944
- (if-let m (imm_size_from_type ty))
2945
- (add_range_fact
2946
- (orr_imm ty (zero_reg) n)
2947
- m k k))
2948
-
2949
- (decl load_constant64_full (Type ImmExtend u64) Reg)
2950
- (extern constructor load_constant64_full load_constant64_full)
2951
-
2952
- ;; Fallback for integral 64-bit constants
2953
- (rule (imm (integral_ty ty) extend n)
2954
- (load_constant64_full ty extend n))
2955
-
2956
- ;; Sign extension helpers ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2957
-
2958
- ;; Place a `Value` into a register, sign extending it to 32-bits
2959
- (decl put_in_reg_sext32 (Value) Reg)
2960
- (rule -1 (put_in_reg_sext32 val @ (value_type (fits_in_32 ty)))
2961
- (extend val $true (ty_bits ty) 32))
2962
-
2963
- ;; 32/64-bit passthrough.
2964
- (rule (put_in_reg_sext32 val @ (value_type $I32)) val)
2965
- (rule (put_in_reg_sext32 val @ (value_type $I64)) val)
2966
-
2967
- ;; Place a `Value` into a register, zero extending it to 32-bits
2968
- (decl put_in_reg_zext32 (Value) Reg)
2969
- (rule -1 (put_in_reg_zext32 val @ (value_type (fits_in_32 ty)))
2970
- (extend val $false (ty_bits ty) 32))
2971
-
2972
- ;; 32/64-bit passthrough.
2973
- (rule (put_in_reg_zext32 val @ (value_type $I32)) val)
2974
- (rule (put_in_reg_zext32 val @ (value_type $I64)) val)
2975
-
2976
- ;; Place a `Value` into a register, sign extending it to 64-bits
2977
- (decl put_in_reg_sext64 (Value) Reg)
2978
- (rule 1 (put_in_reg_sext64 val @ (value_type (fits_in_32 ty)))
2979
- (extend val $true (ty_bits ty) 64))
2980
-
2981
- ;; 64-bit passthrough.
2982
- (rule (put_in_reg_sext64 val @ (value_type $I64)) val)
2983
-
2984
- ;; Place a `Value` into a register, zero extending it to 64-bits
2985
- (decl put_in_reg_zext64 (Value) Reg)
2986
- (rule 1 (put_in_reg_zext64 val @ (value_type (fits_in_32 ty)))
2987
- (extend val $false (ty_bits ty) 64))
2988
-
2989
- ;; 64-bit passthrough.
2990
- (rule (put_in_reg_zext64 val @ (value_type $I64)) val)
2991
-
2992
- ;; Misc instruction helpers ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2993
-
2994
- (decl trap_if_zero_divisor (Reg) Reg)
2995
- (rule (trap_if_zero_divisor reg)
2996
- (let ((_ Unit (emit (MInst.TrapIf (cond_br_zero reg) (trap_code_division_by_zero)))))
2997
- reg))
2998
-
2999
- (decl size_from_ty (Type) OperandSize)
3000
- (rule 1 (size_from_ty (fits_in_32 _ty)) (OperandSize.Size32))
3001
- (rule (size_from_ty $I64) (OperandSize.Size64))
3002
-
3003
- ;; Check for signed overflow. The only case is min_value / -1.
3004
- ;; The following checks must be done in 32-bit or 64-bit, depending
3005
- ;; on the input type.
3006
- (decl trap_if_div_overflow (Type Reg Reg) Reg)
3007
- (rule (trap_if_div_overflow ty x y)
3008
- (let (
3009
- ;; Check RHS is -1.
3010
- (_ Unit (emit (MInst.AluRRImm12 (ALUOp.AddS) (operand_size ty) (writable_zero_reg) y (u8_into_imm12 1))))
3011
-
3012
- ;; Check LHS is min_value, by subtracting 1 and branching if
3013
- ;; there is overflow.
3014
- (_ Unit (emit (MInst.CCmpImm (size_from_ty ty)
3015
- x
3016
- (u8_into_uimm5 1)
3017
- (nzcv $false $false $false $false)
3018
- (Cond.Eq))))
3019
- (_ Unit (emit (MInst.TrapIf (cond_br_cond (Cond.Vs))
3020
- (trap_code_integer_overflow))))
3021
- )
3022
- x))
3023
-
3024
- ;; Check for unsigned overflow.
3025
- (decl trap_if_overflow (ProducesFlags TrapCode) Reg)
3026
- (rule (trap_if_overflow producer tc)
3027
- (with_flags_reg
3028
- producer
3029
- (ConsumesFlags.ConsumesFlagsSideEffect
3030
- (MInst.TrapIf (cond_br_cond (Cond.Hs)) tc))))
3031
-
3032
- (decl sink_atomic_load (Inst) Reg)
3033
- (rule (sink_atomic_load x @ (atomic_load _ addr))
3034
- (let ((_ Unit (sink_inst x)))
3035
- (put_in_reg addr)))
3036
-
3037
- ;; Helper for generating either an `AluRRR`, `AluRRRShift`, or `AluRRImmLogic`
3038
- ;; instruction depending on the input. Note that this requires that the `ALUOp`
3039
- ;; specified is commutative.
3040
- (decl alu_rs_imm_logic_commutative (ALUOp Type Value Value) Reg)
3041
-
3042
- ;; Base case of operating on registers.
3043
- (rule -1 (alu_rs_imm_logic_commutative op ty x y)
3044
- (alu_rrr op ty x y))
3045
-
3046
- ;; Special cases for when one operand is a constant.
3047
- (rule (alu_rs_imm_logic_commutative op ty x (iconst k))
3048
- (if-let imm (imm_logic_from_imm64 ty k))
3049
- (alu_rr_imm_logic op ty x imm))
3050
- (rule 1 (alu_rs_imm_logic_commutative op ty (iconst k) x)
3051
- (if-let imm (imm_logic_from_imm64 ty k))
3052
- (alu_rr_imm_logic op ty x imm))
3053
-
3054
- ;; Special cases for when one operand is shifted left by a constant.
3055
- (rule (alu_rs_imm_logic_commutative op ty x (ishl y (iconst k)))
3056
- (if-let amt (lshl_from_imm64 ty k))
3057
- (alu_rrr_shift op ty x y amt))
3058
- (rule 1 (alu_rs_imm_logic_commutative op ty (ishl x (iconst k)) y)
3059
- (if-let amt (lshl_from_imm64 ty k))
3060
- (alu_rrr_shift op ty y x amt))
3061
-
3062
- ;; Same as `alu_rs_imm_logic_commutative` above, except that it doesn't require
3063
- ;; that the operation is commutative.
3064
- (decl alu_rs_imm_logic (ALUOp Type Value Value) Reg)
3065
- (rule -1 (alu_rs_imm_logic op ty x y)
3066
- (alu_rrr op ty x y))
3067
- (rule (alu_rs_imm_logic op ty x (iconst k))
3068
- (if-let imm (imm_logic_from_imm64 ty k))
3069
- (alu_rr_imm_logic op ty x imm))
3070
- (rule (alu_rs_imm_logic op ty x (ishl y (iconst k)))
3071
- (if-let amt (lshl_from_imm64 ty k))
3072
- (alu_rrr_shift op ty x y amt))
3073
-
3074
- ;; Helper for generating i128 bitops which simply do the same operation to the
3075
- ;; hi/lo registers.
3076
- ;;
3077
- ;; TODO: Support immlogic here
3078
- (decl i128_alu_bitop (ALUOp Type Value Value) ValueRegs)
3079
- (rule (i128_alu_bitop op ty x y)
3080
- (let (
3081
- (x_regs ValueRegs (put_in_regs x))
3082
- (x_lo Reg (value_regs_get x_regs 0))
3083
- (x_hi Reg (value_regs_get x_regs 1))
3084
- (y_regs ValueRegs (put_in_regs y))
3085
- (y_lo Reg (value_regs_get y_regs 0))
3086
- (y_hi Reg (value_regs_get y_regs 1))
3087
- )
3088
- (value_regs
3089
- (alu_rrr op ty x_lo y_lo)
3090
- (alu_rrr op ty x_hi y_hi))))
3091
-
3092
- ;; Helper for emitting `MInst.VecLoadReplicate` instructions.
3093
- (decl ld1r (Reg VectorSize MemFlags) Reg)
3094
- (rule (ld1r src size flags)
3095
- (let ((dst WritableReg (temp_writable_reg $I8X16))
3096
- (_ Unit (emit (MInst.VecLoadReplicate dst src size flags))))
3097
- dst))
3098
-
3099
- ;; Helper for emitting `MInst.LoadExtName` instructions.
3100
- (decl load_ext_name (BoxExternalName i64) Reg)
3101
- (rule (load_ext_name extname offset)
3102
- (let ((dst WritableReg (temp_writable_reg $I64))
3103
- (_ Unit (emit (MInst.LoadExtName dst extname offset))))
3104
- dst))
3105
-
3106
- ;; Lower the address of a load or a store.
3107
- ;;
3108
- ;; This will create an `AMode` representing the address of the `Value` provided
3109
- ;; at runtime plus the immediate offset `i32` provided. The `Type` here is used
3110
- ;; to represent the size of the value being loaded or stored for offset scaling
3111
- ;; if necessary.
3112
- ;;
3113
- ;; Note that this is broken up into two phases. In the first phase this attempts
3114
- ;; to find constants within the `val` provided and fold them in to the `offset`
3115
- ;; provided. Afterwards though the `amode_no_more_iconst` helper is used at
3116
- ;; which pointer constants are no longer pattern-matched and instead only
3117
- ;; various modes are generated. This in theory would not be necessary with
3118
- ;; mid-end optimizations that fold constants into load/store immediate offsets
3119
- ;; instead, but for now each backend needs to do this.
3120
- (decl amode (Type Value i32) AMode)
3121
- (rule 0 (amode ty val offset)
3122
- (amode_no_more_iconst ty val offset))
3123
- (rule 1 (amode ty (iadd x (iconst (simm32 y))) offset)
3124
- (if-let new_offset (s32_add_fallible y offset))
3125
- (amode_no_more_iconst ty x new_offset))
3126
- (rule 2 (amode ty (iadd (iconst (simm32 x)) y) offset)
3127
- (if-let new_offset (s32_add_fallible x offset))
3128
- (amode_no_more_iconst ty y new_offset))
3129
-
3130
- (decl amode_no_more_iconst (Type Value i32) AMode)
3131
- ;; Base case: move the `offset` into a register and add it to `val` via the
3132
- ;; amode
3133
- (rule 0 (amode_no_more_iconst ty val offset)
3134
- (AMode.RegReg val (imm $I64 (ImmExtend.Zero) (i64_as_u64 offset))))
3135
-
3136
- ;; Optimize cases where the `offset` provided fits into a immediates of
3137
- ;; various kinds of addressing modes.
3138
- (rule 1 (amode_no_more_iconst ty val offset)
3139
- (if-let simm9 (simm9_from_i64 offset))
3140
- (AMode.Unscaled val simm9))
3141
- (rule 2 (amode_no_more_iconst ty val offset)
3142
- (if-let uimm12 (uimm12_scaled_from_i64 offset ty))
3143
- (AMode.UnsignedOffset val uimm12))
3144
-
3145
- ;; Optimizations where addition can fold some operations into the `amode`.
3146
- ;;
3147
- ;; Note that here these take higher priority than constants because an
3148
- ;; add-of-extend can be folded into an amode, representing 2 otherwise emitted
3149
- ;; instructions. Constants on the other hand added to the amode represent only
3150
- ;; a single instruction folded in, so fewer instructions should be generated
3151
- ;; with these higher priority than the rules above.
3152
- (rule 3 (amode_no_more_iconst ty (iadd x y) offset)
3153
- (AMode.RegReg (amode_add x offset) y))
3154
- (rule 4 (amode_no_more_iconst ty (iadd x (uextend y @ (value_type $I32))) offset)
3155
- (AMode.RegExtended (amode_add x offset) y (ExtendOp.UXTW)))
3156
- (rule 4 (amode_no_more_iconst ty (iadd x (sextend y @ (value_type $I32))) offset)
3157
- (AMode.RegExtended (amode_add x offset) y (ExtendOp.SXTW)))
3158
- (rule 5 (amode_no_more_iconst ty (iadd (uextend x @ (value_type $I32)) y) offset)
3159
- (AMode.RegExtended (amode_add y offset) x (ExtendOp.UXTW)))
3160
- (rule 5 (amode_no_more_iconst ty (iadd (sextend x @ (value_type $I32)) y) offset)
3161
- (AMode.RegExtended (amode_add y offset) x (ExtendOp.SXTW)))
3162
-
3163
- ;; `RegScaled*` rules where this matches an addition of an "index register" to a
3164
- ;; base register. The index register is shifted by the size of the type loaded
3165
- ;; in bytes to enable this mode matching.
3166
- ;;
3167
- ;; Note that this can additionally bundle an extending operation but the
3168
- ;; extension must happen before the shift. This will pattern-match the shift
3169
- ;; first and then if that succeeds afterwards try to find an extend.
3170
- (rule 6 (amode_no_more_iconst ty (iadd x (ishl y (iconst (u64_from_imm64 n)))) offset)
3171
- (if-let $true (u64_eq (ty_bytes ty) (u64_shl 1 n)))
3172
- (amode_reg_scaled (amode_add x offset) y))
3173
- (rule 7 (amode_no_more_iconst ty (iadd (ishl y (iconst (u64_from_imm64 n))) x) offset)
3174
- (if-let $true (u64_eq (ty_bytes ty) (u64_shl 1 n)))
3175
- (amode_reg_scaled (amode_add x offset) y))
3176
-
3177
- (decl amode_reg_scaled (Reg Value) AMode)
3178
- (rule 0 (amode_reg_scaled base index)
3179
- (AMode.RegScaled base index))
3180
- (rule 1 (amode_reg_scaled base (uextend index @ (value_type $I32)))
3181
- (AMode.RegScaledExtended base index (ExtendOp.UXTW)))
3182
- (rule 1 (amode_reg_scaled base (sextend index @ (value_type $I32)))
3183
- (AMode.RegScaledExtended base index (ExtendOp.SXTW)))
3184
-
3185
- ;; Helper to add a 32-bit signed immediate to the register provided. This will
3186
- ;; select an appropriate `add` instruction to use.
3187
- (decl amode_add (Reg i32) Reg)
3188
- (rule 0 (amode_add x y)
3189
- (add $I64 x (imm $I64 (ImmExtend.Zero) (i64_as_u64 y))))
3190
- (rule 1 (amode_add x y)
3191
- (if-let (imm12_from_u64 imm12) (i64_as_u64 y))
3192
- (add_imm $I64 x imm12))
3193
- (rule 2 (amode_add x 0) x)
3194
-
3195
- ;; Creates a `PairAMode` for the `Value` provided plus the `i32` constant
3196
- ;; offset provided.
3197
- (decl pair_amode (Value i32) PairAMode)
3198
-
3199
- ;; Base case where `val` and `offset` are combined with an `add`
3200
- (rule 0 (pair_amode val offset)
3201
- (if-let simm7 (simm7_scaled_from_i64 0 $I64))
3202
- (PairAMode.SignedOffset (amode_add val offset) simm7))
3203
-
3204
- ;; Optimization when `offset` can fit into a `SImm7Scaled`.
3205
- (rule 1 (pair_amode val offset)
3206
- (if-let simm7 (simm7_scaled_from_i64 offset $I64))
3207
- (PairAMode.SignedOffset val simm7))
3208
-
3209
- (decl pure partial simm7_scaled_from_i64 (i64 Type) SImm7Scaled)
3210
- (extern constructor simm7_scaled_from_i64 simm7_scaled_from_i64)
3211
-
3212
- (decl pure partial uimm12_scaled_from_i64 (i64 Type) UImm12Scaled)
3213
- (extern constructor uimm12_scaled_from_i64 uimm12_scaled_from_i64)
3214
-
3215
- (decl pure partial simm9_from_i64 (i64) SImm9)
3216
- (extern constructor simm9_from_i64 simm9_from_i64)
3217
-
3218
-
3219
- (decl sink_load_into_addr (Type Inst) Reg)
3220
- (rule (sink_load_into_addr ty x @ (load _ addr (offset32 offset)))
3221
- (let ((_ Unit (sink_inst x)))
3222
- (add_imm_to_addr addr (i64_as_u64 offset))))
3223
-
3224
- (decl add_imm_to_addr (Reg u64) Reg)
3225
- (rule 2 (add_imm_to_addr val 0) val)
3226
- (rule 1 (add_imm_to_addr val (imm12_from_u64 imm)) (add_imm $I64 val imm))
3227
- (rule 0 (add_imm_to_addr val offset) (add $I64 val (imm $I64 (ImmExtend.Zero) offset)))
3228
-
3229
- ;; Lower a constant f32.
3230
- ;;
3231
- ;; Note that we must make sure that all bits outside the lowest 32 are set to 0
3232
- ;; because this function is also used to load wider constants (that have zeros
3233
- ;; in their most significant bits).
3234
- (decl constant_f32 (u32) Reg)
3235
- (rule 2 (constant_f32 0)
3236
- (vec_dup_imm (asimd_mov_mod_imm_zero (ScalarSize.Size32))
3237
- $false
3238
- (VectorSize.Size32x2)))
3239
- (rule 1 (constant_f32 n)
3240
- (if-let imm (asimd_fp_mod_imm_from_u64 n (ScalarSize.Size32)))
3241
- (fpu_move_fp_imm imm (ScalarSize.Size32)))
3242
- (rule (constant_f32 n)
3243
- (mov_to_fpu (imm $I32 (ImmExtend.Zero) n) (ScalarSize.Size32)))
3244
-
3245
- ;; Lower a constant f64.
3246
- ;;
3247
- ;; Note that we must make sure that all bits outside the lowest 64 are set to 0
3248
- ;; because this function is also used to load wider constants (that have zeros
3249
- ;; in their most significant bits).
3250
- ;; TODO: Treat as half of a 128 bit vector and consider replicated patterns.
3251
- ;; Scalar MOVI might also be an option.
3252
- (decl constant_f64 (u64) Reg)
3253
- (rule 4 (constant_f64 0)
3254
- (vec_dup_imm (asimd_mov_mod_imm_zero (ScalarSize.Size32))
3255
- $false
3256
- (VectorSize.Size32x2)))
3257
- (rule 3 (constant_f64 n)
3258
- (if-let imm (asimd_fp_mod_imm_from_u64 n (ScalarSize.Size64)))
3259
- (fpu_move_fp_imm imm (ScalarSize.Size64)))
3260
- (rule 2 (constant_f64 (u64_as_u32 n))
3261
- (constant_f32 n))
3262
- (rule 1 (constant_f64 (u64_low32_bits_unset n))
3263
- (mov_to_fpu (imm $I64 (ImmExtend.Zero) n) (ScalarSize.Size64)))
3264
- (rule (constant_f64 n)
3265
- (fpu_load64 (AMode.Const (emit_u64_le_const n)) (mem_flags_trusted)))
3266
-
3267
- ;; Tests whether the low 32 bits in the input are all zero.
3268
- (decl u64_low32_bits_unset (u64) u64)
3269
- (extern extractor u64_low32_bits_unset u64_low32_bits_unset)
3270
-
3271
- ;; Lower a constant f128.
3272
- (decl constant_f128 (u128) Reg)
3273
- (rule 3 (constant_f128 0)
3274
- (vec_dup_imm (asimd_mov_mod_imm_zero (ScalarSize.Size8))
3275
- $false
3276
- (VectorSize.Size8x16)))
3277
-
3278
- ;; If the upper 64-bits are all zero then defer to `constant_f64`.
3279
- (rule 2 (constant_f128 (u128_as_u64 n)) (constant_f64 n))
3280
-
3281
- ;; If the low half of the u128 equals the high half then delegate to the splat
3282
- ;; logic as a splat of a 64-bit value.
3283
- (rule 1 (constant_f128 (u128_replicated_u64 n))
3284
- (splat_const n (VectorSize.Size64x2)))
3285
-
3286
- ;; Base case is to load the constant from memory.
3287
- (rule (constant_f128 n)
3288
- (fpu_load128 (AMode.Const (emit_u128_le_const n)) (mem_flags_trusted)))
3289
-
3290
- ;; Lower a vector splat with a constant parameter.
3291
- ;;
3292
- ;; The 64-bit input here only uses the low bits for the lane size in
3293
- ;; `VectorSize` and all other bits are ignored.
3294
- (decl splat_const (u64 VectorSize) Reg)
3295
-
3296
- ;; If the splat'd constant can itself be reduced in size then attempt to do so
3297
- ;; as it will make it easier to create the immediates in the instructions below.
3298
- (rule 5 (splat_const (u64_replicated_u32 n) (VectorSize.Size64x2))
3299
- (splat_const n (VectorSize.Size32x4)))
3300
- (rule 5 (splat_const (u32_replicated_u16 n) (VectorSize.Size32x4))
3301
- (splat_const n (VectorSize.Size16x8)))
3302
- (rule 5 (splat_const (u32_replicated_u16 n) (VectorSize.Size32x2))
3303
- (splat_const n (VectorSize.Size16x4)))
3304
- (rule 5 (splat_const (u16_replicated_u8 n) (VectorSize.Size16x8))
3305
- (splat_const n (VectorSize.Size8x16)))
3306
- (rule 5 (splat_const (u16_replicated_u8 n) (VectorSize.Size16x4))
3307
- (splat_const n (VectorSize.Size8x8)))
3308
-
3309
- ;; Special cases for `vec_dup_imm` instructions where the input is either
3310
- ;; negated or not.
3311
- (rule 4 (splat_const n size)
3312
- (if-let imm (asimd_mov_mod_imm_from_u64 n (vector_lane_size size)))
3313
- (vec_dup_imm imm $false size))
3314
- (rule 3 (splat_const n size)
3315
- (if-let imm (asimd_mov_mod_imm_from_u64 (u64_not n) (vector_lane_size size)))
3316
- (vec_dup_imm imm $true size))
3317
-
3318
- ;; Special case a 32-bit splat where an immediate can be created by
3319
- ;; concatenating the 32-bit constant into a 64-bit value
3320
- (rule 2 (splat_const n (VectorSize.Size32x4))
3321
- (if-let imm (asimd_mov_mod_imm_from_u64 (u64_or n (u64_shl n 32)) (ScalarSize.Size64)))
3322
- (vec_dup_imm imm $false (VectorSize.Size64x2)))
3323
- (rule 2 (splat_const n (VectorSize.Size32x2))
3324
- (if-let imm (asimd_mov_mod_imm_from_u64 (u64_or n (u64_shl n 32)) (ScalarSize.Size64)))
3325
- (fpu_extend (vec_dup_imm imm $false (VectorSize.Size64x2)) (ScalarSize.Size64)))
3326
-
3327
- (rule 1 (splat_const n size)
3328
- (if-let imm (asimd_fp_mod_imm_from_u64 n (vector_lane_size size)))
3329
- (vec_dup_fp_imm imm size))
3330
-
3331
- ;; The base case for splat is to use `vec_dup` with the immediate loaded into a
3332
- ;; register.
3333
- (rule (splat_const n size)
3334
- (vec_dup (imm $I64 (ImmExtend.Zero) n) size))
3335
-
3336
- ;; Lower a FloatCC to a Cond.
3337
- (decl fp_cond_code (FloatCC) Cond)
3338
- ;; TODO: Port lower_fp_condcode() to ISLE.
3339
- (extern constructor fp_cond_code fp_cond_code)
3340
-
3341
- ;; Lower an integer cond code.
3342
- (decl cond_code (IntCC) Cond)
3343
- ;; TODO: Port lower_condcode() to ISLE.
3344
- (extern constructor cond_code cond_code)
3345
-
3346
- ;; Invert a condition code.
3347
- (decl invert_cond (Cond) Cond)
3348
- ;; TODO: Port cond.invert() to ISLE.
3349
- (extern constructor invert_cond invert_cond)
3350
-
3351
- ;; Generate comparison to zero operator from input condition code
3352
- (decl float_cc_cmp_zero_to_vec_misc_op (FloatCC) VecMisc2)
3353
- (extern constructor float_cc_cmp_zero_to_vec_misc_op float_cc_cmp_zero_to_vec_misc_op)
3354
-
3355
- (decl float_cc_cmp_zero_to_vec_misc_op_swap (FloatCC) VecMisc2)
3356
- (extern constructor float_cc_cmp_zero_to_vec_misc_op_swap float_cc_cmp_zero_to_vec_misc_op_swap)
3357
-
3358
- ;; Match valid generic compare to zero cases
3359
- (decl fcmp_zero_cond (FloatCC) FloatCC)
3360
- (extern extractor fcmp_zero_cond fcmp_zero_cond)
3361
-
3362
- ;; Match not equal compare to zero separately as it requires two output instructions
3363
- (decl fcmp_zero_cond_not_eq (FloatCC) FloatCC)
3364
- (extern extractor fcmp_zero_cond_not_eq fcmp_zero_cond_not_eq)
3365
-
3366
- ;; Helper for generating float compare to zero instructions where 2nd argument is zero
3367
- (decl float_cmp_zero (FloatCC Reg VectorSize) Reg)
3368
- (rule (float_cmp_zero cond rn size)
3369
- (vec_misc (float_cc_cmp_zero_to_vec_misc_op cond) rn size))
3370
-
3371
- ;; Helper for generating float compare to zero instructions in case where 1st argument is zero
3372
- (decl float_cmp_zero_swap (FloatCC Reg VectorSize) Reg)
3373
- (rule (float_cmp_zero_swap cond rn size)
3374
- (vec_misc (float_cc_cmp_zero_to_vec_misc_op_swap cond) rn size))
3375
-
3376
- ;; Helper for generating float compare equal to zero instruction
3377
- (decl fcmeq0 (Reg VectorSize) Reg)
3378
- (rule (fcmeq0 rn size)
3379
- (vec_misc (VecMisc2.Fcmeq0) rn size))
3380
-
3381
- ;; Generate comparison to zero operator from input condition code
3382
- (decl int_cc_cmp_zero_to_vec_misc_op (IntCC) VecMisc2)
3383
- (extern constructor int_cc_cmp_zero_to_vec_misc_op int_cc_cmp_zero_to_vec_misc_op)
3384
-
3385
- (decl int_cc_cmp_zero_to_vec_misc_op_swap (IntCC) VecMisc2)
3386
- (extern constructor int_cc_cmp_zero_to_vec_misc_op_swap int_cc_cmp_zero_to_vec_misc_op_swap)
3387
-
3388
- ;; Match valid generic compare to zero cases
3389
- (decl icmp_zero_cond (IntCC) IntCC)
3390
- (extern extractor icmp_zero_cond icmp_zero_cond)
3391
-
3392
- ;; Match not equal compare to zero separately as it requires two output instructions
3393
- (decl icmp_zero_cond_not_eq (IntCC) IntCC)
3394
- (extern extractor icmp_zero_cond_not_eq icmp_zero_cond_not_eq)
3395
-
3396
- ;; Helper for generating int compare to zero instructions where 2nd argument is zero
3397
- (decl int_cmp_zero (IntCC Reg VectorSize) Reg)
3398
- (rule (int_cmp_zero cond rn size)
3399
- (vec_misc (int_cc_cmp_zero_to_vec_misc_op cond) rn size))
3400
-
3401
- ;; Helper for generating int compare to zero instructions in case where 1st argument is zero
3402
- (decl int_cmp_zero_swap (IntCC Reg VectorSize) Reg)
3403
- (rule (int_cmp_zero_swap cond rn size)
3404
- (vec_misc (int_cc_cmp_zero_to_vec_misc_op_swap cond) rn size))
3405
-
3406
- ;; Helper for generating int compare equal to zero instruction
3407
- (decl cmeq0 (Reg VectorSize) Reg)
3408
- (rule (cmeq0 rn size)
3409
- (vec_misc (VecMisc2.Cmeq0) rn size))
3410
-
3411
- ;; Helper for emitting `MInst.AtomicRMW` instructions.
3412
- (decl lse_atomic_rmw (AtomicRMWOp Value Reg Type MemFlags) Reg)
3413
- (rule (lse_atomic_rmw op p r_arg2 ty flags)
3414
- (let (
3415
- (r_addr Reg p)
3416
- (dst WritableReg (temp_writable_reg ty))
3417
- (_ Unit (emit (MInst.AtomicRMW op r_arg2 dst r_addr ty flags)))
3418
- )
3419
- dst))
3420
-
3421
- ;; Helper for emitting `MInst.AtomicCAS` instructions.
3422
- (decl lse_atomic_cas (Reg Reg Reg Type MemFlags) Reg)
3423
- (rule (lse_atomic_cas addr expect replace ty flags)
3424
- (let (
3425
- (dst WritableReg (temp_writable_reg ty))
3426
- (_ Unit (emit (MInst.AtomicCAS dst expect replace addr ty flags)))
3427
- )
3428
- dst))
3429
-
3430
- ;; Helper for emitting `MInst.AtomicRMWLoop` instructions.
3431
- ;; - Make sure that both args are in virtual regs, since in effect
3432
- ;; we have to do a parallel copy to get them safely to the AtomicRMW input
3433
- ;; regs, and that's not guaranteed safe if either is in a real reg.
3434
- ;; - Move the args to the preordained AtomicRMW input regs
3435
- ;; - And finally, copy the preordained AtomicRMW output reg to its destination.
3436
- (decl atomic_rmw_loop (AtomicRMWLoopOp Reg Reg Type MemFlags) Reg)
3437
- (rule (atomic_rmw_loop op addr operand ty flags)
3438
- (let ((dst WritableReg (temp_writable_reg $I64))
3439
- (scratch1 WritableReg (temp_writable_reg $I64))
3440
- (scratch2 WritableReg (temp_writable_reg $I64))
3441
- (_ Unit (emit (MInst.AtomicRMWLoop ty op flags addr operand dst scratch1 scratch2))))
3442
- dst))
3443
-
3444
- ;; Helper for emitting `MInst.AtomicCASLoop` instructions.
3445
- ;; This is very similar to, but not identical to, the AtomicRmw case. Note
3446
- ;; that the AtomicCASLoop sequence does its own masking, so we don't need to worry
3447
- ;; about zero-extending narrow (I8/I16/I32) values here.
3448
- ;; Make sure that all three args are in virtual regs. See corresponding comment
3449
- ;; for `atomic_rmw_loop` above.
3450
- (decl atomic_cas_loop (Reg Reg Reg Type MemFlags) Reg)
3451
- (rule (atomic_cas_loop addr expect replace ty flags)
3452
- (let ((dst WritableReg (temp_writable_reg $I64))
3453
- (scratch WritableReg (temp_writable_reg $I64))
3454
- (_ Unit (emit (MInst.AtomicCASLoop ty flags addr expect replace dst scratch))))
3455
- dst))
3456
-
3457
- ;; Copy a register of the given type to a new register.
3458
- ;;
3459
- ;; Generally, regalloc should take care of this kind of thing for us. This is
3460
- ;; only useful for implementing things like `bitcast` from an `r64` to an `i64`
3461
- ;; to avoid conflicting constraints on a single aliased value by splitting the
3462
- ;; value into two parts.
3463
- (decl copy_reg (Type Reg) Reg)
3464
- (rule (copy_reg $I32 src)
3465
- (let ((dst WritableReg (temp_writable_reg $I32))
3466
- (_ Unit (emit (MInst.Mov (OperandSize.Size32)
3467
- dst
3468
- src))))
3469
- dst))
3470
- (rule (copy_reg $I64 src)
3471
- (let ((dst WritableReg (temp_writable_reg $I64))
3472
- (_ Unit (emit (MInst.Mov (OperandSize.Size64)
3473
- dst
3474
- src))))
3475
- dst))
3476
-
3477
-
3478
- ;; Helper for emitting `MInst.MovPReg` instructions.
3479
- (decl mov_from_preg (PReg) Reg)
3480
- (rule (mov_from_preg src)
3481
- (let ((dst WritableReg (temp_writable_reg $I64))
3482
- (_ Unit (emit (MInst.MovFromPReg dst src))))
3483
- dst))
3484
-
3485
- (decl mov_to_preg (PReg Reg) SideEffectNoResult)
3486
- (rule (mov_to_preg dst src)
3487
- (SideEffectNoResult.Inst (MInst.MovToPReg dst src)))
3488
-
3489
- (decl preg_sp () PReg)
3490
- (extern constructor preg_sp preg_sp)
3491
-
3492
- (decl preg_fp () PReg)
3493
- (extern constructor preg_fp preg_fp)
3494
-
3495
- (decl preg_link () PReg)
3496
- (extern constructor preg_link preg_link)
3497
-
3498
- (decl preg_pinned () PReg)
3499
- (extern constructor preg_pinned preg_pinned)
3500
-
3501
- (decl aarch64_sp () Reg)
3502
- (rule (aarch64_sp)
3503
- (mov_from_preg (preg_sp)))
3504
-
3505
- (decl aarch64_fp () Reg)
3506
- (rule (aarch64_fp)
3507
- (mov_from_preg (preg_fp)))
3508
-
3509
- (decl aarch64_link () Reg)
3510
- (rule 1 (aarch64_link)
3511
- (if (preserve_frame_pointers))
3512
- (if (sign_return_address_disabled))
3513
- (let ((dst WritableReg (temp_writable_reg $I64))
3514
- ;; Even though LR is not an allocatable register, whether it
3515
- ;; contains the return address for the current function is
3516
- ;; unknown at this point. For example, this operation may come
3517
- ;; immediately after a call, in which case LR would not have a
3518
- ;; valid value. That's why we must obtain the return address from
3519
- ;; the frame record that corresponds to the current subroutine on
3520
- ;; the stack; the presence of the record is guaranteed by the
3521
- ;; `preserve_frame_pointers` setting.
3522
- (addr AMode (AMode.FPOffset 8))
3523
- (_ Unit (emit (MInst.ULoad64 dst addr (mem_flags_trusted)))))
3524
- dst))
3525
-
3526
- (rule (aarch64_link)
3527
- (if (preserve_frame_pointers))
3528
- ;; Similarly to the rule above, we must load the return address from the
3529
- ;; the frame record. Furthermore, we can use LR as a scratch register
3530
- ;; because the function will set it to the return address immediately
3531
- ;; before returning.
3532
- (let ((addr AMode (AMode.FPOffset 8))
3533
- (lr WritableReg (writable_link_reg))
3534
- (_ Unit (emit (MInst.ULoad64 lr addr (mem_flags_trusted))))
3535
- (_ Unit (emit (MInst.Xpaclri))))
3536
- (mov_from_preg (preg_link))))
3537
-
3538
- ;; Helper for getting the maximum shift amount for a type.
3539
-
3540
- (decl max_shift (Type) u8)
3541
- (rule (max_shift $F64) 63)
3542
- (rule (max_shift $F32) 31)
3543
-
3544
- ;; Helper for generating `fcopysign` instruction sequences.
3545
-
3546
- (decl fcopy_sign (Reg Reg Type) Reg)
3547
- (rule 1 (fcopy_sign x y (ty_scalar_float ty))
3548
- (let ((dst WritableReg (temp_writable_reg $F64))
3549
- (tmp Reg (fpu_rri (fpu_op_ri_ushr (ty_bits ty) (max_shift ty)) y))
3550
- (_ Unit (emit (MInst.FpuRRIMod (fpu_op_ri_sli (ty_bits ty) (max_shift ty)) dst x tmp))))
3551
- dst))
3552
- (rule (fcopy_sign x y ty @ (multi_lane _ _))
3553
- (let ((dst WritableReg (temp_writable_reg $I8X16))
3554
- (tmp Reg (ushr_vec_imm y (max_shift (lane_type ty)) (vector_size ty)))
3555
- (_ Unit (emit (MInst.VecShiftImmMod (VecShiftImmModOp.Sli) dst x tmp (vector_size ty) (max_shift (lane_type ty))))))
3556
- dst))
3557
-
3558
- ;; Helpers for generating `MInst.FpuToInt` instructions.
3559
-
3560
- (decl fpu_to_int_nan_check (ScalarSize Reg) Reg)
3561
- (rule (fpu_to_int_nan_check size src)
3562
- (let ((r ValueRegs
3563
- (with_flags (fpu_cmp size src src)
3564
- (ConsumesFlags.ConsumesFlagsReturnsReg
3565
- (MInst.TrapIf (cond_br_cond (Cond.Vs))
3566
- (trap_code_bad_conversion_to_integer))
3567
- src))))
3568
- (value_regs_get r 0)))
3569
-
3570
- ;; Checks that the value is not less than the minimum bound,
3571
- ;; accepting a boolean (whether the type is signed), input type,
3572
- ;; output type, and registers containing the source and minimum bound.
3573
- (decl fpu_to_int_underflow_check (bool Type Type Reg Reg) Reg)
3574
- (rule (fpu_to_int_underflow_check $true $F32 (fits_in_16 out_ty) src min)
3575
- (let ((r ValueRegs
3576
- (with_flags (fpu_cmp (ScalarSize.Size32) src min)
3577
- (ConsumesFlags.ConsumesFlagsReturnsReg
3578
- (MInst.TrapIf (cond_br_cond (Cond.Le))
3579
- (trap_code_integer_overflow))
3580
- src))))
3581
- (value_regs_get r 0)))
3582
- (rule (fpu_to_int_underflow_check $true $F64 (fits_in_32 out_ty) src min)
3583
- (let ((r ValueRegs
3584
- (with_flags (fpu_cmp (ScalarSize.Size64) src min)
3585
- (ConsumesFlags.ConsumesFlagsReturnsReg
3586
- (MInst.TrapIf (cond_br_cond (Cond.Le))
3587
- (trap_code_integer_overflow))
3588
- src))))
3589
- (value_regs_get r 0)))
3590
- (rule -1 (fpu_to_int_underflow_check $true in_ty _out_ty src min)
3591
- (let ((r ValueRegs
3592
- (with_flags (fpu_cmp (scalar_size in_ty) src min)
3593
- (ConsumesFlags.ConsumesFlagsReturnsReg
3594
- (MInst.TrapIf (cond_br_cond (Cond.Lt))
3595
- (trap_code_integer_overflow))
3596
- src))))
3597
- (value_regs_get r 0)))
3598
- (rule (fpu_to_int_underflow_check $false in_ty _out_ty src min)
3599
- (let ((r ValueRegs
3600
- (with_flags (fpu_cmp (scalar_size in_ty) src min)
3601
- (ConsumesFlags.ConsumesFlagsReturnsReg
3602
- (MInst.TrapIf (cond_br_cond (Cond.Le))
3603
- (trap_code_integer_overflow))
3604
- src))))
3605
- (value_regs_get r 0)))
3606
-
3607
- (decl fpu_to_int_overflow_check (ScalarSize Reg Reg) Reg)
3608
- (rule (fpu_to_int_overflow_check size src max)
3609
- (let ((r ValueRegs
3610
- (with_flags (fpu_cmp size src max)
3611
- (ConsumesFlags.ConsumesFlagsReturnsReg
3612
- (MInst.TrapIf (cond_br_cond (Cond.Ge))
3613
- (trap_code_integer_overflow))
3614
- src))))
3615
- (value_regs_get r 0)))
3616
-
3617
- ;; Emits the appropriate instruction sequence to convert a
3618
- ;; floating-point value to an integer, trapping if the value
3619
- ;; is a NaN or does not fit in the target type.
3620
- ;; Accepts the specific conversion op, the source register,
3621
- ;; whether the input is signed, and finally the input and output
3622
- ;; types.
3623
- (decl fpu_to_int_cvt (FpuToIntOp Reg bool Type Type) Reg)
3624
- (rule (fpu_to_int_cvt op src signed in_ty out_ty)
3625
- (let ((size ScalarSize (scalar_size in_ty))
3626
- (in_bits u8 (ty_bits in_ty))
3627
- (out_bits u8 (ty_bits out_ty))
3628
- (src Reg (fpu_to_int_nan_check size src))
3629
- (min Reg (min_fp_value signed in_bits out_bits))
3630
- (src Reg (fpu_to_int_underflow_check signed in_ty out_ty src min))
3631
- (max Reg (max_fp_value signed in_bits out_bits))
3632
- (src Reg (fpu_to_int_overflow_check size src max)))
3633
- (fpu_to_int op src)))
3634
-
3635
- ;; Emits the appropriate instruction sequence to convert a
3636
- ;; floating-point value to an integer, saturating if the value
3637
- ;; does not fit in the target type.
3638
- ;; Accepts the specific conversion op, the source register,
3639
- ;; whether the input is signed, and finally the output type.
3640
- (decl fpu_to_int_cvt_sat (FpuToIntOp Reg bool Type) Reg)
3641
- (rule 1 (fpu_to_int_cvt_sat op src _ $I64)
3642
- (fpu_to_int op src))
3643
- (rule 1 (fpu_to_int_cvt_sat op src _ $I32)
3644
- (fpu_to_int op src))
3645
- (rule (fpu_to_int_cvt_sat op src $false (fits_in_16 out_ty))
3646
- (let ((result Reg (fpu_to_int op src))
3647
- (max Reg (imm out_ty (ImmExtend.Zero) (ty_mask out_ty))))
3648
- (with_flags_reg
3649
- (cmp (OperandSize.Size32) result max)
3650
- (csel (Cond.Hi) max result))))
3651
- (rule (fpu_to_int_cvt_sat op src $true (fits_in_16 out_ty))
3652
- (let ((result Reg (fpu_to_int op src))
3653
- (max Reg (signed_max out_ty))
3654
- (min Reg (signed_min out_ty))
3655
- (result Reg (with_flags_reg
3656
- (cmp (operand_size out_ty) result max)
3657
- (csel (Cond.Gt) max result)))
3658
- (result Reg (with_flags_reg
3659
- (cmp (operand_size out_ty) result min)
3660
- (csel (Cond.Lt) min result))))
3661
- result))
3662
-
3663
- (decl signed_min (Type) Reg)
3664
- (rule (signed_min $I8) (imm $I8 (ImmExtend.Sign) 0x80))
3665
- (rule (signed_min $I16) (imm $I16 (ImmExtend.Sign) 0x8000))
3666
-
3667
- (decl signed_max (Type) Reg)
3668
- (rule (signed_max $I8) (imm $I8 (ImmExtend.Sign) 0x7F))
3669
- (rule (signed_max $I16) (imm $I16 (ImmExtend.Sign) 0x7FFF))
3670
-
3671
- (decl fpu_to_int (FpuToIntOp Reg) Reg)
3672
- (rule (fpu_to_int op src)
3673
- (let ((dst WritableReg (temp_writable_reg $I64))
3674
- (_ Unit (emit (MInst.FpuToInt op dst src))))
3675
- dst))
3676
-
3677
- ;; Helper for generating `MInst.IntToFpu` instructions.
3678
-
3679
- (decl int_to_fpu (IntToFpuOp Reg) Reg)
3680
- (rule (int_to_fpu op src)
3681
- (let ((dst WritableReg (temp_writable_reg $I8X16))
3682
- (_ Unit (emit (MInst.IntToFpu op dst src))))
3683
- dst))
3684
-
3685
- ;;;; Helpers for Emitting Calls ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3686
-
3687
- (decl gen_call (SigRef ExternalName RelocDistance ValueSlice) InstOutput)
3688
- (extern constructor gen_call gen_call)
3689
-
3690
- (decl gen_call_indirect (SigRef Value ValueSlice) InstOutput)
3691
- (extern constructor gen_call_indirect gen_call_indirect)
3692
-
3693
- ;; Helpers for pinned register manipulation.
3694
-
3695
- (decl write_pinned_reg (Reg) SideEffectNoResult)
3696
- (rule (write_pinned_reg val)
3697
- (mov_to_preg (preg_pinned) val))
3698
-
3699
- ;; Helpers for stackslot effective address generation.
3700
-
3701
- (decl compute_stack_addr (StackSlot Offset32) Reg)
3702
- (rule (compute_stack_addr stack_slot offset)
3703
- (let ((dst WritableReg (temp_writable_reg $I64))
3704
- (_ Unit (emit (abi_stackslot_addr dst stack_slot offset))))
3705
- dst))
3706
-
3707
- ;; Helper for emitting instruction sequences to perform a vector comparison.
3708
-
3709
- (decl vec_cmp_vc (Reg Reg VectorSize) Reg)
3710
- (rule (vec_cmp_vc rn rm size)
3711
- (let ((dst Reg (vec_rrr (VecALUOp.Fcmeq) rn rn size))
3712
- (tmp Reg (vec_rrr (VecALUOp.Fcmeq) rm rm size))
3713
- (dst Reg (vec_rrr (VecALUOp.And) dst tmp size)))
3714
- dst))
3715
-
3716
- (decl vec_cmp (Reg Reg Type Cond) Reg)
3717
-
3718
- ;; Floating point Vs / Vc
3719
- (rule (vec_cmp rn rm ty (Cond.Vc))
3720
- (if (ty_vector_float ty))
3721
- (vec_cmp_vc rn rm (vector_size ty)))
3722
- (rule (vec_cmp rn rm ty (Cond.Vs))
3723
- (if (ty_vector_float ty))
3724
- (let ((tmp Reg (vec_cmp_vc rn rm (vector_size ty))))
3725
- (vec_misc (VecMisc2.Not) tmp (vector_size ty))))
3726
-
3727
- ;; 'Less than' operations are implemented by swapping the order of
3728
- ;; operands and using the 'greater than' instructions.
3729
- ;; 'Not equal' is implemented with 'equal' and inverting the result.
3730
-
3731
- ;; Floating-point
3732
- (rule (vec_cmp rn rm ty (Cond.Eq))
3733
- (if (ty_vector_float ty))
3734
- (vec_rrr (VecALUOp.Fcmeq) rn rm (vector_size ty)))
3735
- (rule (vec_cmp rn rm ty (Cond.Ne))
3736
- (if (ty_vector_float ty))
3737
- (let ((tmp Reg (vec_rrr (VecALUOp.Fcmeq) rn rm (vector_size ty))))
3738
- (vec_misc (VecMisc2.Not) tmp (vector_size ty))))
3739
- (rule (vec_cmp rn rm ty (Cond.Ge))
3740
- (if (ty_vector_float ty))
3741
- (vec_rrr (VecALUOp.Fcmge) rn rm (vector_size ty)))
3742
- (rule (vec_cmp rn rm ty (Cond.Gt))
3743
- (if (ty_vector_float ty))
3744
- (vec_rrr (VecALUOp.Fcmgt) rn rm (vector_size ty)))
3745
- ;; Floating-point swapped-operands
3746
- (rule (vec_cmp rn rm ty (Cond.Mi))
3747
- (if (ty_vector_float ty))
3748
- (vec_rrr (VecALUOp.Fcmgt) rm rn (vector_size ty)))
3749
- (rule (vec_cmp rn rm ty (Cond.Ls))
3750
- (if (ty_vector_float ty))
3751
- (vec_rrr (VecALUOp.Fcmge) rm rn (vector_size ty)))
3752
-
3753
- ;; Integer
3754
- (rule 1 (vec_cmp rn rm ty (Cond.Eq))
3755
- (if (ty_vector_not_float ty))
3756
- (vec_rrr (VecALUOp.Cmeq) rn rm (vector_size ty)))
3757
- (rule 1 (vec_cmp rn rm ty (Cond.Ne))
3758
- (if (ty_vector_not_float ty))
3759
- (let ((tmp Reg (vec_rrr (VecALUOp.Cmeq) rn rm (vector_size ty))))
3760
- (vec_misc (VecMisc2.Not) tmp (vector_size ty))))
3761
- (rule 1 (vec_cmp rn rm ty (Cond.Ge))
3762
- (if (ty_vector_not_float ty))
3763
- (vec_rrr (VecALUOp.Cmge) rn rm (vector_size ty)))
3764
- (rule 1 (vec_cmp rn rm ty (Cond.Gt))
3765
- (if (ty_vector_not_float ty))
3766
- (vec_rrr (VecALUOp.Cmgt) rn rm (vector_size ty)))
3767
- (rule (vec_cmp rn rm ty (Cond.Hs))
3768
- (if (ty_vector_not_float ty))
3769
- (vec_rrr (VecALUOp.Cmhs) rn rm (vector_size ty)))
3770
- (rule (vec_cmp rn rm ty (Cond.Hi))
3771
- (if (ty_vector_not_float ty))
3772
- (vec_rrr (VecALUOp.Cmhi) rn rm (vector_size ty)))
3773
- ;; Integer swapped-operands
3774
- (rule (vec_cmp rn rm ty (Cond.Le))
3775
- (if (ty_vector_not_float ty))
3776
- (vec_rrr (VecALUOp.Cmge) rm rn (vector_size ty)))
3777
- (rule (vec_cmp rn rm ty (Cond.Lt))
3778
- (if (ty_vector_not_float ty))
3779
- (vec_rrr (VecALUOp.Cmgt) rm rn (vector_size ty)))
3780
- (rule 1 (vec_cmp rn rm ty (Cond.Ls))
3781
- (if (ty_vector_not_float ty))
3782
- (vec_rrr (VecALUOp.Cmhs) rm rn (vector_size ty)))
3783
- (rule (vec_cmp rn rm ty (Cond.Lo))
3784
- (if (ty_vector_not_float ty))
3785
- (vec_rrr (VecALUOp.Cmhi) rm rn (vector_size ty)))
3786
-
3787
- ;; Helper for determining if any value in a vector is true.
3788
- ;; This operation is implemented by using umaxp to create a scalar value, which
3789
- ;; is then compared against zero.
3790
- ;;
3791
- ;; umaxp vn.4s, vm.4s, vm.4s
3792
- ;; mov xm, vn.d[0]
3793
- ;; cmp xm, #0
3794
- (decl vanytrue (Reg Type) ProducesFlags)
3795
- (rule 1 (vanytrue src (ty_vec128 ty))
3796
- (let ((src Reg (vec_rrr (VecALUOp.Umaxp) src src (VectorSize.Size32x4)))
3797
- (src Reg (mov_from_vec src 0 (ScalarSize.Size64))))
3798
- (cmp_imm (OperandSize.Size64) src (u8_into_imm12 0))))
3799
- (rule (vanytrue src ty)
3800
- (if (ty_vec64 ty))
3801
- (let ((src Reg (mov_from_vec src 0 (ScalarSize.Size64))))
3802
- (cmp_imm (OperandSize.Size64) src (u8_into_imm12 0))))
3803
-
3804
- ;;;; TLS Values ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3805
-
3806
- ;; Helper for emitting ElfTlsGetAddr.
3807
- (decl elf_tls_get_addr (ExternalName) Reg)
3808
- (rule (elf_tls_get_addr name)
3809
- (let ((dst WritableReg (temp_writable_reg $I64))
3810
- (tmp WritableReg (temp_writable_reg $I64))
3811
- (_ Unit (emit (MInst.ElfTlsGetAddr (box_external_name name) dst tmp))))
3812
- dst))
3813
-
3814
- (decl macho_tls_get_addr (ExternalName) Reg)
3815
- (rule (macho_tls_get_addr name)
3816
- (let ((dst WritableReg (temp_writable_reg $I64))
3817
- (_ Unit (emit (MInst.MachOTlsGetAddr name dst))))
3818
- dst))
3819
-
3820
- ;; A tuple of `ProducesFlags` and `IntCC`.
3821
- (type FlagsAndCC (enum (FlagsAndCC (flags ProducesFlags)
3822
- (cc IntCC))))
3823
-
3824
- ;; Helper constructor for `FlagsAndCC`.
3825
- (decl flags_and_cc (ProducesFlags IntCC) FlagsAndCC)
3826
- (rule (flags_and_cc flags cc) (FlagsAndCC.FlagsAndCC flags cc))
3827
-
3828
- ;; Materialize a `FlagsAndCC` into a boolean `ValueRegs`.
3829
- (decl flags_and_cc_to_bool (FlagsAndCC) ValueRegs)
3830
- (rule (flags_and_cc_to_bool (FlagsAndCC.FlagsAndCC flags cc))
3831
- (with_flags flags (materialize_bool_result (cond_code cc))))
3832
-
3833
- ;; Get the `ProducesFlags` out of a `FlagsAndCC`.
3834
- (decl flags_and_cc_flags (FlagsAndCC) ProducesFlags)
3835
- (rule (flags_and_cc_flags (FlagsAndCC.FlagsAndCC flags _cc)) flags)
3836
-
3837
- ;; Get the `IntCC` out of a `FlagsAndCC`.
3838
- (decl flags_and_cc_cc (FlagsAndCC) IntCC)
3839
- (rule (flags_and_cc_cc (FlagsAndCC.FlagsAndCC _flags cc)) cc)
3840
-
3841
- ;; Helpers for lowering `icmp` sequences.
3842
- ;; `lower_icmp` contains shared functionality for lowering `icmp`
3843
- ;; sequences, which `lower_icmp_into_{reg,flags}` extend from.
3844
- (decl lower_icmp (IntCC Value Value Type) FlagsAndCC)
3845
- (decl lower_icmp_into_reg (IntCC Value Value Type Type) ValueRegs)
3846
- (decl lower_icmp_into_flags (IntCC Value Value Type) FlagsAndCC)
3847
- (decl lower_icmp_const (IntCC Value u64 Type) FlagsAndCC)
3848
- ;; For most cases, `lower_icmp_into_flags` is the same as `lower_icmp`,
3849
- ;; except for some I128 cases (see below).
3850
- (rule -1 (lower_icmp_into_flags cond x y ty) (lower_icmp cond x y ty))
3851
-
3852
- ;; Vectors.
3853
- ;; `icmp` into flags for vectors is invalid.
3854
- (rule 1 (lower_icmp_into_reg cond x y in_ty @ (multi_lane _ _) _out_ty)
3855
- (let ((cond Cond (cond_code cond))
3856
- (rn Reg (put_in_reg x))
3857
- (rm Reg (put_in_reg y)))
3858
- (vec_cmp rn rm in_ty cond)))
3859
-
3860
- ;; Determines the appropriate extend op given the value type and the given ArgumentExtension.
3861
- (decl lower_extend_op (Type ArgumentExtension) ExtendOp)
3862
- (rule (lower_extend_op $I8 (ArgumentExtension.Sext)) (ExtendOp.SXTB))
3863
- (rule (lower_extend_op $I16 (ArgumentExtension.Sext)) (ExtendOp.SXTH))
3864
- (rule (lower_extend_op $I8 (ArgumentExtension.Uext)) (ExtendOp.UXTB))
3865
- (rule (lower_extend_op $I16 (ArgumentExtension.Uext)) (ExtendOp.UXTH))
3866
-
3867
- ;; Integers <= 64-bits.
3868
- (rule -2 (lower_icmp_into_reg cond rn rm in_ty out_ty)
3869
- (if (ty_int_ref_scalar_64 in_ty))
3870
- (let ((cc Cond (cond_code cond)))
3871
- (flags_and_cc_to_bool (lower_icmp cond rn rm in_ty))))
3872
-
3873
- (rule 1 (lower_icmp cond rn rm (fits_in_16 ty))
3874
- (if (signed_cond_code cond))
3875
- (let ((rn Reg (put_in_reg_sext32 rn)))
3876
- (flags_and_cc (cmp_extend (operand_size ty) rn rm (lower_extend_op ty (ArgumentExtension.Sext))) cond)))
3877
- (rule -1 (lower_icmp cond rn (imm12_from_value rm) (fits_in_16 ty))
3878
- (let ((rn Reg (put_in_reg_zext32 rn)))
3879
- (flags_and_cc (cmp_imm (operand_size ty) rn rm) cond)))
3880
- (rule -2 (lower_icmp cond rn rm (fits_in_16 ty))
3881
- (let ((rn Reg (put_in_reg_zext32 rn)))
3882
- (flags_and_cc (cmp_extend (operand_size ty) rn rm (lower_extend_op ty (ArgumentExtension.Uext))) cond)))
3883
- (rule -3 (lower_icmp cond rn (u64_from_iconst c) ty)
3884
- (if (ty_int_ref_scalar_64 ty))
3885
- (lower_icmp_const cond rn c ty))
3886
- (rule -4 (lower_icmp cond rn rm ty)
3887
- (if (ty_int_ref_scalar_64 ty))
3888
- (flags_and_cc (cmp (operand_size ty) rn rm) cond))
3889
-
3890
- ;; We get better encodings when testing against an immediate that's even instead
3891
- ;; of odd, so rewrite comparisons to use even immediates:
3892
- ;;
3893
- ;; A >= B + 1
3894
- ;; ==> A - 1 >= B
3895
- ;; ==> A > B
3896
- (rule (lower_icmp_const (IntCC.UnsignedGreaterThanOrEqual) a b ty)
3897
- (if (ty_int_ref_scalar_64 ty))
3898
- (if-let $true (u64_is_odd b))
3899
- (if-let (imm12_from_u64 imm) (u64_sub b 1))
3900
- (flags_and_cc (cmp_imm (operand_size ty) a imm) (IntCC.UnsignedGreaterThan)))
3901
- (rule (lower_icmp_const (IntCC.SignedGreaterThanOrEqual) a b ty)
3902
- (if (ty_int_ref_scalar_64 ty))
3903
- (if-let $true (u64_is_odd b))
3904
- (if-let (imm12_from_u64 imm) (u64_sub b 1))
3905
- (flags_and_cc (cmp_imm (operand_size ty) a imm) (IntCC.SignedGreaterThan)))
3906
-
3907
- (rule -1 (lower_icmp_const cond rn (imm12_from_u64 c) ty)
3908
- (if (ty_int_ref_scalar_64 ty))
3909
- (flags_and_cc (cmp_imm (operand_size ty) rn c) cond))
3910
- (rule -2 (lower_icmp_const cond rn c ty)
3911
- (if (ty_int_ref_scalar_64 ty))
3912
- (flags_and_cc (cmp (operand_size ty) rn (imm ty (ImmExtend.Zero) c)) cond))
3913
-
3914
-
3915
- ;; 128-bit integers.
3916
- (rule (lower_icmp_into_reg cond @ (IntCC.Equal) rn rm $I128 $I8)
3917
- (let ((cc Cond (cond_code cond)))
3918
- (flags_and_cc_to_bool
3919
- (lower_icmp cond rn rm $I128))))
3920
- (rule (lower_icmp_into_reg cond @ (IntCC.NotEqual) rn rm $I128 $I8)
3921
- (let ((cc Cond (cond_code cond)))
3922
- (flags_and_cc_to_bool
3923
- (lower_icmp cond rn rm $I128))))
3924
-
3925
- ;; cmp lhs_lo, rhs_lo
3926
- ;; ccmp lhs_hi, rhs_hi, #0, eq
3927
- (decl lower_icmp_i128_eq_ne (Value Value) ProducesFlags)
3928
- (rule (lower_icmp_i128_eq_ne lhs rhs)
3929
- (let ((lhs ValueRegs (put_in_regs lhs))
3930
- (rhs ValueRegs (put_in_regs rhs))
3931
- (lhs_lo Reg (value_regs_get lhs 0))
3932
- (lhs_hi Reg (value_regs_get lhs 1))
3933
- (rhs_lo Reg (value_regs_get rhs 0))
3934
- (rhs_hi Reg (value_regs_get rhs 1))
3935
- (cmp_inst ProducesFlags (cmp (OperandSize.Size64) lhs_lo rhs_lo)))
3936
- (ccmp (OperandSize.Size64) lhs_hi rhs_hi
3937
- (nzcv $false $false $false $false) (Cond.Eq) cmp_inst)))
3938
-
3939
- (rule (lower_icmp (IntCC.Equal) lhs rhs $I128)
3940
- (flags_and_cc (lower_icmp_i128_eq_ne lhs rhs) (IntCC.Equal)))
3941
- (rule (lower_icmp (IntCC.NotEqual) lhs rhs $I128)
3942
- (flags_and_cc (lower_icmp_i128_eq_ne lhs rhs) (IntCC.NotEqual)))
3943
-
3944
- ;; cmp lhs_lo, rhs_lo
3945
- ;; cset tmp1, unsigned_cond
3946
- ;; cmp lhs_hi, rhs_hi
3947
- ;; cset tmp2, cond
3948
- ;; csel dst, tmp1, tmp2, eq
3949
- (rule -1 (lower_icmp_into_reg cond lhs rhs $I128 $I8)
3950
- (let ((unsigned_cond Cond (cond_code (intcc_unsigned cond)))
3951
- (cond Cond (cond_code cond))
3952
- (lhs ValueRegs (put_in_regs lhs))
3953
- (rhs ValueRegs (put_in_regs rhs))
3954
- (lhs_lo Reg (value_regs_get lhs 0))
3955
- (lhs_hi Reg (value_regs_get lhs 1))
3956
- (rhs_lo Reg (value_regs_get rhs 0))
3957
- (rhs_hi Reg (value_regs_get rhs 1))
3958
- (tmp1 Reg (with_flags_reg (cmp (OperandSize.Size64) lhs_lo rhs_lo)
3959
- (materialize_bool_result unsigned_cond))))
3960
- (with_flags (cmp (OperandSize.Size64) lhs_hi rhs_hi)
3961
- (lower_icmp_i128_consumer cond tmp1))))
3962
-
3963
- (decl lower_icmp_i128_consumer (Cond Reg) ConsumesFlags)
3964
- (rule (lower_icmp_i128_consumer cond tmp1)
3965
- (let ((tmp2 WritableReg (temp_writable_reg $I64))
3966
- (dst WritableReg (temp_writable_reg $I64)))
3967
- (ConsumesFlags.ConsumesFlagsTwiceReturnsValueRegs
3968
- (MInst.CSet tmp2 cond)
3969
- (MInst.CSel dst (Cond.Eq) tmp1 tmp2)
3970
- (value_reg dst))))
3971
-
3972
- (decl lower_bmask (Type Type ValueRegs) ValueRegs)
3973
-
3974
-
3975
- ;; For conversions that exactly fit a register, we can use csetm.
3976
- ;;
3977
- ;; cmp val, #0
3978
- ;; csetm res, ne
3979
- (rule 0
3980
- (lower_bmask (fits_in_64 _) (ty_32_or_64 in_ty) val)
3981
- (with_flags_reg
3982
- (cmp_imm (operand_size in_ty) (value_regs_get val 0) (u8_into_imm12 0))
3983
- (csetm (Cond.Ne))))
3984
-
3985
- ;; For conversions from a 128-bit value into a 64-bit or smaller one, we or the
3986
- ;; two registers of the 128-bit value together, and then recurse with the
3987
- ;; combined value as a 64-bit test.
3988
- ;;
3989
- ;; orr val, lo, hi
3990
- ;; cmp val, #0
3991
- ;; csetm res, ne
3992
- (rule 1
3993
- (lower_bmask (fits_in_64 ty) $I128 val)
3994
- (let ((lo Reg (value_regs_get val 0))
3995
- (hi Reg (value_regs_get val 1))
3996
- (combined Reg (orr $I64 lo hi)))
3997
- (lower_bmask ty $I64 (value_reg combined))))
3998
-
3999
- ;; For converting from any type into i128, duplicate the result of
4000
- ;; converting to i64.
4001
- (rule 2
4002
- (lower_bmask $I128 in_ty val)
4003
- (let ((res ValueRegs (lower_bmask $I64 in_ty val))
4004
- (res Reg (value_regs_get res 0)))
4005
- (value_regs res res)))
4006
-
4007
- ;; For conversions smaller than a register, we need to mask off the high bits, and then
4008
- ;; we can recurse into the general case.
4009
- ;;
4010
- ;; and tmp, val, #ty_mask
4011
- ;; cmp tmp, #0
4012
- ;; csetm res, ne
4013
- (rule 3
4014
- (lower_bmask out_ty (fits_in_16 in_ty) val)
4015
- ; This if-let can't fail due to ty_mask always producing 8/16 consecutive 1s.
4016
- (if-let mask_bits (imm_logic_from_u64 $I32 (ty_mask in_ty)))
4017
- (let ((masked Reg (and_imm $I32 (value_regs_get val 0) mask_bits)))
4018
- (lower_bmask out_ty $I32 masked)))
4019
-
4020
- ;; Exceptional `lower_icmp_into_flags` rules.
4021
- ;; We need to guarantee that the flags for `cond` are correct, so we
4022
- ;; compare `dst` with 1.
4023
- (rule (lower_icmp_into_flags cond @ (IntCC.SignedGreaterThanOrEqual) lhs rhs $I128)
4024
- (let ((dst ValueRegs (lower_icmp_into_reg cond lhs rhs $I128 $I8))
4025
- (dst Reg (value_regs_get dst 0))
4026
- (tmp Reg (imm $I64 (ImmExtend.Sign) 1))) ;; mov tmp, #1
4027
- (flags_and_cc (cmp (OperandSize.Size64) dst tmp) cond)))
4028
- (rule (lower_icmp_into_flags cond @ (IntCC.UnsignedGreaterThanOrEqual) lhs rhs $I128)
4029
- (let ((dst ValueRegs (lower_icmp_into_reg cond lhs rhs $I128 $I8))
4030
- (dst Reg (value_regs_get dst 0))
4031
- (tmp Reg (imm $I64 (ImmExtend.Zero) 1)))
4032
- (flags_and_cc (cmp (OperandSize.Size64) dst tmp) cond)))
4033
- (rule (lower_icmp_into_flags cond @ (IntCC.SignedLessThanOrEqual) lhs rhs $I128)
4034
- (let ((dst ValueRegs (lower_icmp_into_reg cond lhs rhs $I128 $I8))
4035
- (dst Reg (value_regs_get dst 0))
4036
- (tmp Reg (imm $I64 (ImmExtend.Sign) 1)))
4037
- (flags_and_cc (cmp (OperandSize.Size64) tmp dst) cond)))
4038
- (rule (lower_icmp_into_flags cond @ (IntCC.UnsignedLessThanOrEqual) lhs rhs $I128)
4039
- (let ((dst ValueRegs (lower_icmp_into_reg cond lhs rhs $I128 $I8))
4040
- (dst Reg (value_regs_get dst 0))
4041
- (tmp Reg (imm $I64 (ImmExtend.Zero) 1)))
4042
- (flags_and_cc (cmp (OperandSize.Size64) tmp dst) cond)))
4043
- ;; For strict comparisons, we compare with 0.
4044
- (rule (lower_icmp_into_flags cond @ (IntCC.SignedGreaterThan) lhs rhs $I128)
4045
- (let ((dst ValueRegs (lower_icmp_into_reg cond lhs rhs $I128 $I8))
4046
- (dst Reg (value_regs_get dst 0)))
4047
- (flags_and_cc (cmp (OperandSize.Size64) dst (zero_reg)) cond)))
4048
- (rule (lower_icmp_into_flags cond @ (IntCC.UnsignedGreaterThan) lhs rhs $I128)
4049
- (let ((dst ValueRegs (lower_icmp_into_reg cond lhs rhs $I128 $I8))
4050
- (dst Reg (value_regs_get dst 0)))
4051
- (flags_and_cc (cmp (OperandSize.Size64) dst (zero_reg)) cond)))
4052
- (rule (lower_icmp_into_flags cond @ (IntCC.SignedLessThan) lhs rhs $I128)
4053
- (let ((dst ValueRegs (lower_icmp_into_reg cond lhs rhs $I128 $I8))
4054
- (dst Reg (value_regs_get dst 0)))
4055
- (flags_and_cc (cmp (OperandSize.Size64) (zero_reg) dst) cond)))
4056
- (rule (lower_icmp_into_flags cond @ (IntCC.UnsignedLessThan) lhs rhs $I128)
4057
- (let ((dst ValueRegs (lower_icmp_into_reg cond lhs rhs $I128 $I8))
4058
- (dst Reg (value_regs_get dst 0)))
4059
- (flags_and_cc (cmp (OperandSize.Size64) (zero_reg) dst) cond)))
4060
-
4061
- ;; Helpers for generating select instruction sequences.
4062
- (decl lower_select (ProducesFlags Cond Type Value Value) ValueRegs)
4063
- (rule 2 (lower_select flags cond (ty_scalar_float ty) rn rm)
4064
- (with_flags flags (fpu_csel ty cond rn rm)))
4065
- (rule 3 (lower_select flags cond (ty_vec128 ty) rn rm)
4066
- (with_flags flags (vec_csel cond rn rm)))
4067
- (rule (lower_select flags cond ty rn rm)
4068
- (if (ty_vec64 ty))
4069
- (with_flags flags (fpu_csel $F64 cond rn rm)))
4070
- (rule 4 (lower_select flags cond $I128 rn rm)
4071
- (let ((dst_lo WritableReg (temp_writable_reg $I64))
4072
- (dst_hi WritableReg (temp_writable_reg $I64))
4073
- (rn ValueRegs (put_in_regs rn))
4074
- (rm ValueRegs (put_in_regs rm))
4075
- (rn_lo Reg (value_regs_get rn 0))
4076
- (rn_hi Reg (value_regs_get rn 1))
4077
- (rm_lo Reg (value_regs_get rm 0))
4078
- (rm_hi Reg (value_regs_get rm 1)))
4079
- (with_flags flags
4080
- (ConsumesFlags.ConsumesFlagsTwiceReturnsValueRegs
4081
- (MInst.CSel dst_lo cond rn_lo rm_lo)
4082
- (MInst.CSel dst_hi cond rn_hi rm_hi)
4083
- (value_regs dst_lo dst_hi)))))
4084
- (rule 1 (lower_select flags cond ty rn rm)
4085
- (if (ty_int_ref_scalar_64 ty))
4086
- (with_flags flags (csel cond rn rm)))
4087
-
4088
- ;; Helper for emitting `MInst.Jump` instructions.
4089
- (decl aarch64_jump (BranchTarget) SideEffectNoResult)
4090
- (rule (aarch64_jump target)
4091
- (SideEffectNoResult.Inst (MInst.Jump target)))
4092
-
4093
- ;; Helper for emitting `MInst.JTSequence` instructions.
4094
- ;; Emit the compound instruction that does:
4095
- ;;
4096
- ;; b.hs default
4097
- ;; csel rB, xzr, rIndex, hs
4098
- ;; csdb
4099
- ;; adr rA, jt
4100
- ;; ldrsw rB, [rA, rB, uxtw #2]
4101
- ;; add rA, rA, rB
4102
- ;; br rA
4103
- ;; [jt entries]
4104
- ;;
4105
- ;; This must be *one* instruction in the vcode because
4106
- ;; we cannot allow regalloc to insert any spills/fills
4107
- ;; in the middle of the sequence; otherwise, the ADR's
4108
- ;; PC-rel offset to the jumptable would be incorrect.
4109
- ;; (The alternative is to introduce a relocation pass
4110
- ;; for inlined jumptables, which is much worse, IMHO.)
4111
- (decl jt_sequence (Reg MachLabel BoxVecMachLabel) ConsumesFlags)
4112
- (rule (jt_sequence ridx default targets)
4113
- (let ((rtmp1 WritableReg (temp_writable_reg $I64))
4114
- (rtmp2 WritableReg (temp_writable_reg $I64)))
4115
- (ConsumesFlags.ConsumesFlagsSideEffect
4116
- (MInst.JTSequence default targets ridx rtmp1 rtmp2))))
4117
-
4118
- ;; Helper for emitting `MInst.CondBr` instructions.
4119
- (decl cond_br (BranchTarget BranchTarget CondBrKind) ConsumesFlags)
4120
- (rule (cond_br taken not_taken kind)
4121
- (ConsumesFlags.ConsumesFlagsSideEffect
4122
- (MInst.CondBr taken not_taken kind)))
4123
-
4124
- ;; Helper for emitting `MInst.TestBitAndBranch` instructions.
4125
- (decl test_branch (TestBitAndBranchKind BranchTarget BranchTarget Reg u8) SideEffectNoResult)
4126
- (rule (test_branch kind taken not_taken rn bit)
4127
- (SideEffectNoResult.Inst (MInst.TestBitAndBranch kind taken not_taken rn bit)))
4128
-
4129
- ;; Helper for emitting `tbnz` instructions.
4130
- (decl tbnz (BranchTarget BranchTarget Reg u8) SideEffectNoResult)
4131
- (rule (tbnz taken not_taken rn bit)
4132
- (test_branch (TestBitAndBranchKind.NZ) taken not_taken rn bit))
4133
-
4134
- ;; Helper for emitting `tbz` instructions.
4135
- (decl tbz (BranchTarget BranchTarget Reg u8) SideEffectNoResult)
4136
- (rule (tbz taken not_taken rn bit)
4137
- (test_branch (TestBitAndBranchKind.Z) taken not_taken rn bit))
4138
-
4139
- ;; Helper for emitting `MInst.MovToNZCV` instructions.
4140
- (decl mov_to_nzcv (Reg) ProducesFlags)
4141
- (rule (mov_to_nzcv rn)
4142
- (ProducesFlags.ProducesFlagsSideEffect
4143
- (MInst.MovToNZCV rn)))
4144
-
4145
- ;; Helper for emitting `MInst.EmitIsland` instructions.
4146
- (decl emit_island (CodeOffset) SideEffectNoResult)
4147
- (rule (emit_island needed_space)
4148
- (SideEffectNoResult.Inst
4149
- (MInst.EmitIsland needed_space)))
4150
-
4151
- ;; Helper for emitting `br_table` sequences.
4152
- (decl br_table_impl (u64 Reg MachLabel BoxVecMachLabel) Unit)
4153
- (rule (br_table_impl (imm12_from_u64 jt_size) ridx default targets)
4154
- (emit_side_effect (with_flags_side_effect
4155
- (cmp_imm (OperandSize.Size32) ridx jt_size)
4156
- (jt_sequence ridx default targets))))
4157
- (rule -1 (br_table_impl jt_size ridx default targets)
4158
- (let ((jt_size Reg (imm $I64 (ImmExtend.Zero) jt_size)))
4159
- (emit_side_effect (with_flags_side_effect
4160
- (cmp (OperandSize.Size32) ridx jt_size)
4161
- (jt_sequence ridx default targets)))))
4162
-
4163
- ;; Helper for emitting the `uzp1` instruction
4164
- (decl vec_uzp1 (Reg Reg VectorSize) Reg)
4165
- (rule (vec_uzp1 rn rm size) (vec_rrr (VecALUOp.Uzp1) rn rm size))
4166
-
4167
- ;; Helper for emitting the `uzp2` instruction
4168
- (decl vec_uzp2 (Reg Reg VectorSize) Reg)
4169
- (rule (vec_uzp2 rn rm size) (vec_rrr (VecALUOp.Uzp2) rn rm size))
4170
-
4171
- ;; Helper for emitting the `zip1` instruction
4172
- (decl vec_zip1 (Reg Reg VectorSize) Reg)
4173
- (rule (vec_zip1 rn rm size) (vec_rrr (VecALUOp.Zip1) rn rm size))
4174
-
4175
- ;; Helper for emitting the `zip2` instruction
4176
- (decl vec_zip2 (Reg Reg VectorSize) Reg)
4177
- (rule (vec_zip2 rn rm size) (vec_rrr (VecALUOp.Zip2) rn rm size))
4178
-
4179
- ;; Helper for emitting the `trn1` instruction
4180
- (decl vec_trn1 (Reg Reg VectorSize) Reg)
4181
- (rule (vec_trn1 rn rm size) (vec_rrr (VecALUOp.Trn1) rn rm size))
4182
-
4183
- ;; Helper for emitting the `trn2` instruction
4184
- (decl vec_trn2 (Reg Reg VectorSize) Reg)
4185
- (rule (vec_trn2 rn rm size) (vec_rrr (VecALUOp.Trn2) rn rm size))
4186
-
4187
- ;; Helper for creating a zero value `ASIMDMovModImm` immediate.
4188
- (decl asimd_mov_mod_imm_zero (ScalarSize) ASIMDMovModImm)
4189
- (extern constructor asimd_mov_mod_imm_zero asimd_mov_mod_imm_zero)
4190
-
4191
- ;; Helper for fallibly creating an `ASIMDMovModImm` immediate from its parts.
4192
- (decl pure partial asimd_mov_mod_imm_from_u64 (u64 ScalarSize) ASIMDMovModImm)
4193
- (extern constructor asimd_mov_mod_imm_from_u64 asimd_mov_mod_imm_from_u64)
4194
-
4195
- ;; Helper for fallibly creating an `ASIMDFPModImm` immediate from its parts.
4196
- (decl pure partial asimd_fp_mod_imm_from_u64 (u64 ScalarSize) ASIMDFPModImm)
4197
- (extern constructor asimd_fp_mod_imm_from_u64 asimd_fp_mod_imm_from_u64)
4198
-
4199
- ;; Helper for creating a `VecDupFPImm` instruction
4200
- (decl vec_dup_fp_imm (ASIMDFPModImm VectorSize) Reg)
4201
- (rule (vec_dup_fp_imm imm size)
4202
- (let ((dst WritableReg (temp_writable_reg $I8X16))
4203
- (_ Unit (emit (MInst.VecDupFPImm dst imm size))))
4204
- dst))
4205
-
4206
- ;; Helper for creating a `FpuLoad64` instruction
4207
- (decl fpu_load64 (AMode MemFlags) Reg)
4208
- (rule (fpu_load64 amode flags)
4209
- (let ((dst WritableReg (temp_writable_reg $I8X16))
4210
- (_ Unit (emit (MInst.FpuLoad64 dst amode flags))))
4211
- dst))
4212
-
4213
- ;; Helper for creating a `FpuLoad128` instruction
4214
- (decl fpu_load128 (AMode MemFlags) Reg)
4215
- (rule (fpu_load128 amode flags)
4216
- (let ((dst WritableReg (temp_writable_reg $I8X16))
4217
- (_ Unit (emit (MInst.FpuLoad128 dst amode flags))))
4218
- dst))