wasmtime 22.0.0 → 23.0.2

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Files changed (2164) hide show
  1. checksums.yaml +4 -4
  2. data/Cargo.lock +127 -90
  3. data/ext/Cargo.toml +5 -5
  4. data/ext/cargo-vendor/cranelift-bforest-0.110.2/.cargo-checksum.json +1 -0
  5. data/ext/cargo-vendor/cranelift-bforest-0.110.2/Cargo.toml +50 -0
  6. data/ext/cargo-vendor/cranelift-bitset-0.110.2/.cargo-checksum.json +1 -0
  7. data/ext/cargo-vendor/cranelift-bitset-0.110.2/Cargo.toml +60 -0
  8. data/ext/cargo-vendor/cranelift-bitset-0.110.2/src/compound.rs +508 -0
  9. data/ext/cargo-vendor/cranelift-bitset-0.110.2/src/lib.rs +19 -0
  10. data/ext/cargo-vendor/cranelift-bitset-0.110.2/src/scalar.rs +575 -0
  11. data/ext/cargo-vendor/cranelift-bitset-0.110.2/tests/bitset.rs +78 -0
  12. data/ext/cargo-vendor/cranelift-codegen-0.110.2/.cargo-checksum.json +1 -0
  13. data/ext/cargo-vendor/cranelift-codegen-0.110.2/Cargo.toml +206 -0
  14. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/binemit/stack_map.rs +141 -0
  15. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/context.rs +390 -0
  16. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/data_value.rs +410 -0
  17. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/ir/dfg.rs +1806 -0
  18. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/ir/globalvalue.rs +147 -0
  19. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/ir/immediates.rs +2109 -0
  20. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/ir/instructions.rs +1015 -0
  21. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/ir/jumptable.rs +168 -0
  22. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/ir/mod.rs +110 -0
  23. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/ir/trapcode.rs +148 -0
  24. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/ir/types.rs +643 -0
  25. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/ir/user_stack_maps.rs +101 -0
  26. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/aarch64/inst/emit.rs +3605 -0
  27. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/aarch64/inst/emit_tests.rs +7927 -0
  28. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/aarch64/inst/mod.rs +3058 -0
  29. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/aarch64/inst.isle +4221 -0
  30. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/aarch64/lower.isle +2969 -0
  31. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/aarch64/mod.rs +259 -0
  32. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/mod.rs +462 -0
  33. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/riscv64/inst/emit.rs +2741 -0
  34. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/riscv64/inst/emit_tests.rs +2219 -0
  35. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/riscv64/inst/mod.rs +1935 -0
  36. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/riscv64/inst.isle +3153 -0
  37. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/riscv64/lower/isle.rs +654 -0
  38. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/riscv64/lower.isle +2953 -0
  39. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/riscv64/mod.rs +265 -0
  40. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/s390x/inst/emit.rs +3421 -0
  41. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/s390x/inst/mod.rs +3395 -0
  42. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/s390x/lower.isle +3983 -0
  43. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/s390x/mod.rs +220 -0
  44. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/x64/inst/emit.rs +4297 -0
  45. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/x64/inst/emit_state.rs +65 -0
  46. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/x64/inst/mod.rs +2818 -0
  47. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/x64/inst.isle +5299 -0
  48. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/x64/lower.isle +4819 -0
  49. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/x64/mod.rs +239 -0
  50. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isle_prelude.rs +965 -0
  51. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/legalizer/mod.rs +343 -0
  52. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/lib.rs +106 -0
  53. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/machinst/abi.rs +2427 -0
  54. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/machinst/buffer.rs +2544 -0
  55. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/machinst/helpers.rs +23 -0
  56. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/machinst/isle.rs +908 -0
  57. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/machinst/lower.rs +1462 -0
  58. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/machinst/mod.rs +564 -0
  59. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/machinst/vcode.rs +1840 -0
  60. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/prelude.isle +654 -0
  61. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/prelude_lower.isle +1070 -0
  62. data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/write.rs +660 -0
  63. data/ext/cargo-vendor/cranelift-codegen-meta-0.110.2/.cargo-checksum.json +1 -0
  64. data/ext/cargo-vendor/cranelift-codegen-meta-0.110.2/Cargo.toml +45 -0
  65. data/ext/cargo-vendor/cranelift-codegen-meta-0.110.2/src/cdsl/types.rs +512 -0
  66. data/ext/cargo-vendor/cranelift-codegen-meta-0.110.2/src/cdsl/typevar.rs +980 -0
  67. data/ext/cargo-vendor/cranelift-codegen-meta-0.110.2/src/gen_inst.rs +1278 -0
  68. data/ext/cargo-vendor/cranelift-codegen-meta-0.110.2/src/shared/instructions.rs +3760 -0
  69. data/ext/cargo-vendor/cranelift-codegen-meta-0.110.2/src/shared/types.rs +143 -0
  70. data/ext/cargo-vendor/cranelift-codegen-shared-0.110.2/.cargo-checksum.json +1 -0
  71. data/ext/cargo-vendor/cranelift-codegen-shared-0.110.2/Cargo.toml +31 -0
  72. data/ext/cargo-vendor/cranelift-control-0.110.2/.cargo-checksum.json +1 -0
  73. data/ext/cargo-vendor/cranelift-control-0.110.2/Cargo.toml +39 -0
  74. data/ext/cargo-vendor/cranelift-entity-0.110.2/.cargo-checksum.json +1 -0
  75. data/ext/cargo-vendor/cranelift-entity-0.110.2/Cargo.toml +66 -0
  76. data/ext/cargo-vendor/cranelift-entity-0.110.2/src/set.rs +193 -0
  77. data/ext/cargo-vendor/cranelift-frontend-0.110.2/.cargo-checksum.json +1 -0
  78. data/ext/cargo-vendor/cranelift-frontend-0.110.2/Cargo.toml +87 -0
  79. data/ext/cargo-vendor/cranelift-frontend-0.110.2/src/frontend.rs +2867 -0
  80. data/ext/cargo-vendor/cranelift-isle-0.110.2/.cargo-checksum.json +1 -0
  81. data/ext/cargo-vendor/cranelift-isle-0.110.2/Cargo.toml +60 -0
  82. data/ext/cargo-vendor/cranelift-isle-0.110.2/src/codegen.rs +920 -0
  83. data/ext/cargo-vendor/cranelift-isle-0.110.2/src/parser.rs +562 -0
  84. data/ext/cargo-vendor/cranelift-isle-0.110.2/src/sema.rs +2503 -0
  85. data/ext/cargo-vendor/cranelift-isle-0.110.2/src/trie_again.rs +695 -0
  86. data/ext/cargo-vendor/cranelift-native-0.110.2/.cargo-checksum.json +1 -0
  87. data/ext/cargo-vendor/cranelift-native-0.110.2/Cargo.toml +52 -0
  88. data/ext/cargo-vendor/cranelift-native-0.110.2/src/lib.rs +188 -0
  89. data/ext/cargo-vendor/cranelift-wasm-0.110.2/.cargo-checksum.json +1 -0
  90. data/ext/cargo-vendor/cranelift-wasm-0.110.2/Cargo.toml +119 -0
  91. data/ext/cargo-vendor/cranelift-wasm-0.110.2/src/code_translator/bounds_checks.rs +731 -0
  92. data/ext/cargo-vendor/cranelift-wasm-0.110.2/src/code_translator.rs +3694 -0
  93. data/ext/cargo-vendor/cranelift-wasm-0.110.2/src/heap.rs +119 -0
  94. data/ext/cargo-vendor/cranelift-wasm-0.110.2/src/sections_translator.rs +333 -0
  95. data/ext/cargo-vendor/deterministic-wasi-ctx-0.1.23/.cargo-checksum.json +1 -0
  96. data/ext/cargo-vendor/deterministic-wasi-ctx-0.1.23/Cargo.toml +69 -0
  97. data/ext/cargo-vendor/termcolor-1.4.1/.cargo-checksum.json +1 -0
  98. data/ext/cargo-vendor/termcolor-1.4.1/COPYING +3 -0
  99. data/ext/cargo-vendor/termcolor-1.4.1/Cargo.toml +40 -0
  100. data/ext/cargo-vendor/termcolor-1.4.1/LICENSE-MIT +21 -0
  101. data/ext/cargo-vendor/termcolor-1.4.1/README.md +110 -0
  102. data/ext/cargo-vendor/termcolor-1.4.1/UNLICENSE +24 -0
  103. data/ext/cargo-vendor/termcolor-1.4.1/rustfmt.toml +2 -0
  104. data/ext/cargo-vendor/termcolor-1.4.1/src/lib.rs +2572 -0
  105. data/ext/cargo-vendor/wasi-common-23.0.2/.cargo-checksum.json +1 -0
  106. data/ext/cargo-vendor/wasi-common-23.0.2/Cargo.toml +234 -0
  107. data/ext/cargo-vendor/wasi-common-23.0.2/src/tokio/mod.rs +135 -0
  108. data/ext/cargo-vendor/wasi-common-23.0.2/tests/all/async_.rs +295 -0
  109. data/ext/cargo-vendor/wasi-common-23.0.2/tests/all/sync.rs +284 -0
  110. data/ext/cargo-vendor/wasm-encoder-0.212.0/.cargo-checksum.json +1 -0
  111. data/ext/cargo-vendor/wasm-encoder-0.212.0/Cargo.toml +49 -0
  112. data/ext/cargo-vendor/wasm-encoder-0.212.0/src/component/types.rs +771 -0
  113. data/ext/cargo-vendor/wasm-encoder-0.212.0/src/core/code.rs +3571 -0
  114. data/ext/cargo-vendor/wasm-encoder-0.212.0/src/core/exports.rs +85 -0
  115. data/ext/cargo-vendor/wasm-encoder-0.212.0/src/core/globals.rs +100 -0
  116. data/ext/cargo-vendor/wasm-encoder-0.212.0/src/core/imports.rs +143 -0
  117. data/ext/cargo-vendor/wasm-encoder-0.212.0/src/core/memories.rs +115 -0
  118. data/ext/cargo-vendor/wasm-encoder-0.212.0/src/core/tables.rs +121 -0
  119. data/ext/cargo-vendor/wasm-encoder-0.212.0/src/core/tags.rs +85 -0
  120. data/ext/cargo-vendor/wasm-encoder-0.212.0/src/core/types.rs +663 -0
  121. data/ext/cargo-vendor/wasm-encoder-0.212.0/src/lib.rs +218 -0
  122. data/ext/cargo-vendor/wasm-encoder-0.212.0/src/reencode.rs +1804 -0
  123. data/ext/cargo-vendor/wasm-encoder-0.215.0/.cargo-checksum.json +1 -0
  124. data/ext/cargo-vendor/wasm-encoder-0.215.0/Cargo.toml +65 -0
  125. data/ext/cargo-vendor/wasm-encoder-0.215.0/README.md +80 -0
  126. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/component/aliases.rs +160 -0
  127. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/component/builder.rs +455 -0
  128. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/component/canonicals.rs +159 -0
  129. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/component/components.rs +29 -0
  130. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/component/exports.rs +124 -0
  131. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/component/imports.rs +175 -0
  132. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/component/instances.rs +200 -0
  133. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/component/modules.rs +29 -0
  134. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/component/names.rs +149 -0
  135. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/component/start.rs +52 -0
  136. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/component/types.rs +802 -0
  137. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/component.rs +168 -0
  138. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/core/code.rs +3947 -0
  139. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/core/custom.rs +73 -0
  140. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/core/data.rs +186 -0
  141. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/core/dump.rs +627 -0
  142. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/core/elements.rs +222 -0
  143. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/core/exports.rs +85 -0
  144. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/core/functions.rs +63 -0
  145. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/core/globals.rs +100 -0
  146. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/core/imports.rs +143 -0
  147. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/core/linking.rs +263 -0
  148. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/core/memories.rs +115 -0
  149. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/core/names.rs +298 -0
  150. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/core/producers.rs +181 -0
  151. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/core/start.rs +39 -0
  152. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/core/tables.rs +129 -0
  153. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/core/tags.rs +85 -0
  154. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/core/types.rs +678 -0
  155. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/core.rs +168 -0
  156. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/lib.rs +218 -0
  157. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/raw.rs +30 -0
  158. data/ext/cargo-vendor/wasm-encoder-0.215.0/src/reencode.rs +2002 -0
  159. data/ext/cargo-vendor/wasmparser-0.212.0/.cargo-checksum.json +1 -0
  160. data/ext/cargo-vendor/wasmparser-0.212.0/Cargo.lock +669 -0
  161. data/ext/cargo-vendor/wasmparser-0.212.0/Cargo.toml +112 -0
  162. data/ext/cargo-vendor/wasmparser-0.212.0/src/binary_reader.rs +1968 -0
  163. data/ext/cargo-vendor/wasmparser-0.212.0/src/features.rs +166 -0
  164. data/ext/cargo-vendor/wasmparser-0.212.0/src/lib.rs +814 -0
  165. data/ext/cargo-vendor/wasmparser-0.212.0/src/parser.rs +1682 -0
  166. data/ext/cargo-vendor/wasmparser-0.212.0/src/readers/core/operators.rs +453 -0
  167. data/ext/cargo-vendor/wasmparser-0.212.0/src/readers/core/tables.rs +93 -0
  168. data/ext/cargo-vendor/wasmparser-0.212.0/src/readers/core/types.rs +1941 -0
  169. data/ext/cargo-vendor/wasmparser-0.212.0/src/resources.rs +234 -0
  170. data/ext/cargo-vendor/wasmparser-0.212.0/src/validator/component.rs +3252 -0
  171. data/ext/cargo-vendor/wasmparser-0.212.0/src/validator/core.rs +1454 -0
  172. data/ext/cargo-vendor/wasmparser-0.212.0/src/validator/operators.rs +4230 -0
  173. data/ext/cargo-vendor/wasmparser-0.212.0/src/validator/types.rs +4598 -0
  174. data/ext/cargo-vendor/wasmparser-0.212.0/src/validator.rs +1632 -0
  175. data/ext/cargo-vendor/wasmprinter-0.212.0/.cargo-checksum.json +1 -0
  176. data/ext/cargo-vendor/wasmprinter-0.212.0/Cargo.toml +54 -0
  177. data/ext/cargo-vendor/wasmprinter-0.212.0/src/lib.rs +3221 -0
  178. data/ext/cargo-vendor/wasmprinter-0.212.0/src/operator.rs +1189 -0
  179. data/ext/cargo-vendor/wasmprinter-0.212.0/src/print.rs +190 -0
  180. data/ext/cargo-vendor/wasmprinter-0.212.0/tests/all.rs +48 -0
  181. data/ext/cargo-vendor/wasmtime-23.0.2/.cargo-checksum.json +1 -0
  182. data/ext/cargo-vendor/wasmtime-23.0.2/Cargo.toml +399 -0
  183. data/ext/cargo-vendor/wasmtime-23.0.2/build.rs +38 -0
  184. data/ext/cargo-vendor/wasmtime-23.0.2/src/compile/code_builder.rs +274 -0
  185. data/ext/cargo-vendor/wasmtime-23.0.2/src/compile/runtime.rs +167 -0
  186. data/ext/cargo-vendor/wasmtime-23.0.2/src/compile.rs +881 -0
  187. data/ext/cargo-vendor/wasmtime-23.0.2/src/config.rs +2902 -0
  188. data/ext/cargo-vendor/wasmtime-23.0.2/src/engine/serialization.rs +893 -0
  189. data/ext/cargo-vendor/wasmtime-23.0.2/src/engine.rs +719 -0
  190. data/ext/cargo-vendor/wasmtime-23.0.2/src/lib.rs +406 -0
  191. data/ext/cargo-vendor/wasmtime-23.0.2/src/profiling_agent/jitdump.rs +65 -0
  192. data/ext/cargo-vendor/wasmtime-23.0.2/src/profiling_agent/perfmap.rs +47 -0
  193. data/ext/cargo-vendor/wasmtime-23.0.2/src/profiling_agent/vtune.rs +80 -0
  194. data/ext/cargo-vendor/wasmtime-23.0.2/src/profiling_agent.rs +104 -0
  195. data/ext/cargo-vendor/wasmtime-23.0.2/src/runtime/code_memory.rs +337 -0
  196. data/ext/cargo-vendor/wasmtime-23.0.2/src/runtime/component/bindgen_examples/mod.rs +488 -0
  197. data/ext/cargo-vendor/wasmtime-23.0.2/src/runtime/component/component.rs +811 -0
  198. data/ext/cargo-vendor/wasmtime-23.0.2/src/runtime/component/func/host.rs +439 -0
  199. data/ext/cargo-vendor/wasmtime-23.0.2/src/runtime/component/func/options.rs +552 -0
  200. data/ext/cargo-vendor/wasmtime-23.0.2/src/runtime/component/func/typed.rs +2497 -0
  201. data/ext/cargo-vendor/wasmtime-23.0.2/src/runtime/component/func.rs +688 -0
  202. data/ext/cargo-vendor/wasmtime-23.0.2/src/runtime/component/instance.rs +846 -0
  203. data/ext/cargo-vendor/wasmtime-23.0.2/src/runtime/component/linker.rs +673 -0
  204. data/ext/cargo-vendor/wasmtime-23.0.2/src/runtime/component/matching.rs +216 -0
  205. data/ext/cargo-vendor/wasmtime-23.0.2/src/runtime/component/mod.rs +663 -0
  206. data/ext/cargo-vendor/wasmtime-23.0.2/src/runtime/component/resources.rs +1132 -0
  207. data/ext/cargo-vendor/wasmtime-23.0.2/src/runtime/component/values.rs +979 -0
  208. data/ext/cargo-vendor/wasmtime-23.0.2/src/runtime/coredump.rs +339 -0
  209. data/ext/cargo-vendor/wasmtime-23.0.2/src/runtime/debug.rs +165 -0
  210. data/ext/cargo-vendor/wasmtime-23.0.2/src/runtime/externals/global.rs +310 -0
  211. data/ext/cargo-vendor/wasmtime-23.0.2/src/runtime/externals/table.rs +480 -0
  212. data/ext/cargo-vendor/wasmtime-23.0.2/src/runtime/func/typed.rs +788 -0
  213. data/ext/cargo-vendor/wasmtime-23.0.2/src/runtime/func.rs +2593 -0
  214. data/ext/cargo-vendor/wasmtime-23.0.2/src/runtime/gc/disabled/rooting.rs +224 -0
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  1008. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/riscv64/inst/encode.rs +0 -0
  1009. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/riscv64/inst/imms.rs +0 -0
  1010. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/riscv64/inst/regs.rs +0 -0
  1011. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/riscv64/inst/unwind/systemv.rs +0 -0
  1012. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/riscv64/inst/unwind.rs +0 -0
  1013. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/riscv64/inst/vector.rs +0 -0
  1014. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/riscv64/inst_vector.isle +0 -0
  1015. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/riscv64/lower/isle/generated_code.rs +0 -0
  1016. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/riscv64/lower.rs +0 -0
  1017. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/riscv64/settings.rs +0 -0
  1018. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/s390x/abi.rs +0 -0
  1019. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/s390x/inst/args.rs +0 -0
  1020. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/s390x/inst/emit_tests.rs +0 -0
  1021. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/s390x/inst/imms.rs +0 -0
  1022. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/s390x/inst/regs.rs +0 -0
  1023. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/s390x/inst/unwind/systemv.rs +0 -0
  1024. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/s390x/inst/unwind.rs +0 -0
  1025. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/s390x/inst.isle +0 -0
  1026. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/s390x/lower/isle/generated_code.rs +0 -0
  1027. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/s390x/lower/isle.rs +0 -0
  1028. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/s390x/lower.rs +0 -0
  1029. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/s390x/settings.rs +0 -0
  1030. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/unwind/systemv.rs +0 -0
  1031. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/unwind/winx64.rs +0 -0
  1032. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/unwind.rs +0 -0
  1033. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/x64/abi.rs +0 -0
  1034. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/x64/encoding/evex.rs +0 -0
  1035. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/x64/encoding/mod.rs +0 -0
  1036. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/x64/encoding/rex.rs +0 -0
  1037. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/x64/encoding/vex.rs +0 -0
  1038. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/x64/inst/args.rs +0 -0
  1039. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/x64/inst/emit_tests.rs +0 -0
  1040. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/x64/inst/regs.rs +0 -0
  1041. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/x64/inst/unwind/systemv.rs +0 -0
  1042. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/x64/inst/unwind/winx64.rs +0 -0
  1043. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/x64/inst/unwind.rs +0 -0
  1044. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/x64/lower/isle/generated_code.rs +0 -0
  1045. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/x64/lower/isle.rs +0 -0
  1046. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/x64/lower.rs +0 -0
  1047. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/x64/pcc.rs +0 -0
  1048. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/isa/x64/settings.rs +0 -0
  1049. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/iterators.rs +0 -0
  1050. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/legalizer/globalvalue.rs +0 -0
  1051. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/loop_analysis.rs +0 -0
  1052. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/machinst/blockorder.rs +0 -0
  1053. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/machinst/compile.rs +0 -0
  1054. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/machinst/inst_common.rs +0 -0
  1055. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/machinst/pcc.rs +0 -0
  1056. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/machinst/reg.rs +0 -0
  1057. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/machinst/valueregs.rs +0 -0
  1058. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/nan_canonicalization.rs +0 -0
  1059. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/opts/README.md +0 -0
  1060. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/opts/arithmetic.isle +0 -0
  1061. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/opts/bitops.isle +0 -0
  1062. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/opts/cprop.isle +0 -0
  1063. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/opts/extends.isle +0 -0
  1064. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/opts/generated_code.rs +0 -0
  1065. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/opts/icmp.isle +0 -0
  1066. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/opts/remat.isle +0 -0
  1067. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/opts/selects.isle +0 -0
  1068. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/opts/shifts.isle +0 -0
  1069. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/opts/spaceship.isle +0 -0
  1070. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/opts/spectre.isle +0 -0
  1071. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/opts/vector.isle +0 -0
  1072. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/opts.rs +0 -0
  1073. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/prelude_opt.isle +0 -0
  1074. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/print_errors.rs +0 -0
  1075. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/ranges.rs +0 -0
  1076. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/remove_constant_phis.rs +0 -0
  1077. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/result.rs +0 -0
  1078. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/scoped_hash_map.rs +0 -0
  1079. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/settings.rs +0 -0
  1080. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/souper_harvest.rs +0 -0
  1081. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/timing.rs +0 -0
  1082. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/traversals.rs +0 -0
  1083. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/unionfind.rs +0 -0
  1084. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/unreachable_code.rs +0 -0
  1085. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/value_label.rs +0 -0
  1086. /data/ext/cargo-vendor/{cranelift-codegen-0.109.0 → cranelift-codegen-0.110.2}/src/verifier/mod.rs +0 -0
  1087. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/LICENSE +0 -0
  1088. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/README.md +0 -0
  1089. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/src/cdsl/formats.rs +0 -0
  1090. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/src/cdsl/instructions.rs +0 -0
  1091. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/src/cdsl/isa.rs +0 -0
  1092. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/src/cdsl/mod.rs +0 -0
  1093. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/src/cdsl/operands.rs +0 -0
  1094. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/src/cdsl/settings.rs +0 -0
  1095. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/src/constant_hash.rs +0 -0
  1096. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/src/error.rs +0 -0
  1097. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/src/gen_isle.rs +0 -0
  1098. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/src/gen_settings.rs +0 -0
  1099. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/src/gen_types.rs +0 -0
  1100. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/src/isa/arm64.rs +0 -0
  1101. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/src/isa/mod.rs +0 -0
  1102. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/src/isa/riscv64.rs +0 -0
  1103. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/src/isa/s390x.rs +0 -0
  1104. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/src/isa/x86.rs +0 -0
  1105. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/src/isle.rs +0 -0
  1106. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/src/lib.rs +0 -0
  1107. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/src/shared/entities.rs +0 -0
  1108. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/src/shared/formats.rs +0 -0
  1109. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/src/shared/immediates.rs +0 -0
  1110. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/src/shared/mod.rs +0 -0
  1111. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/src/shared/settings.rs +0 -0
  1112. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/src/srcgen.rs +0 -0
  1113. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.109.0 → cranelift-codegen-meta-0.110.2}/src/unique_table.rs +0 -0
  1114. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.109.0 → cranelift-codegen-shared-0.110.2}/LICENSE +0 -0
  1115. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.109.0 → cranelift-codegen-shared-0.110.2}/README.md +0 -0
  1116. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.109.0 → cranelift-codegen-shared-0.110.2}/src/constant_hash.rs +0 -0
  1117. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.109.0 → cranelift-codegen-shared-0.110.2}/src/constants.rs +0 -0
  1118. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.109.0 → cranelift-codegen-shared-0.110.2}/src/lib.rs +0 -0
  1119. /data/ext/cargo-vendor/{cranelift-control-0.109.0 → cranelift-control-0.110.2}/LICENSE +0 -0
  1120. /data/ext/cargo-vendor/{cranelift-control-0.109.0 → cranelift-control-0.110.2}/README.md +0 -0
  1121. /data/ext/cargo-vendor/{cranelift-control-0.109.0 → cranelift-control-0.110.2}/src/chaos.rs +0 -0
  1122. /data/ext/cargo-vendor/{cranelift-control-0.109.0 → cranelift-control-0.110.2}/src/lib.rs +0 -0
  1123. /data/ext/cargo-vendor/{cranelift-control-0.109.0 → cranelift-control-0.110.2}/src/zero_sized.rs +0 -0
  1124. /data/ext/cargo-vendor/{cranelift-entity-0.109.0 → cranelift-entity-0.110.2}/LICENSE +0 -0
  1125. /data/ext/cargo-vendor/{cranelift-entity-0.109.0 → cranelift-entity-0.110.2}/README.md +0 -0
  1126. /data/ext/cargo-vendor/{cranelift-entity-0.109.0 → cranelift-entity-0.110.2}/src/boxed_slice.rs +0 -0
  1127. /data/ext/cargo-vendor/{cranelift-entity-0.109.0 → cranelift-entity-0.110.2}/src/iter.rs +0 -0
  1128. /data/ext/cargo-vendor/{cranelift-entity-0.109.0 → cranelift-entity-0.110.2}/src/keys.rs +0 -0
  1129. /data/ext/cargo-vendor/{cranelift-entity-0.109.0 → cranelift-entity-0.110.2}/src/lib.rs +0 -0
  1130. /data/ext/cargo-vendor/{cranelift-entity-0.109.0 → cranelift-entity-0.110.2}/src/list.rs +0 -0
  1131. /data/ext/cargo-vendor/{cranelift-entity-0.109.0 → cranelift-entity-0.110.2}/src/map.rs +0 -0
  1132. /data/ext/cargo-vendor/{cranelift-entity-0.109.0 → cranelift-entity-0.110.2}/src/packed_option.rs +0 -0
  1133. /data/ext/cargo-vendor/{cranelift-entity-0.109.0 → cranelift-entity-0.110.2}/src/primary.rs +0 -0
  1134. /data/ext/cargo-vendor/{cranelift-entity-0.109.0 → cranelift-entity-0.110.2}/src/sparse.rs +0 -0
  1135. /data/ext/cargo-vendor/{cranelift-entity-0.109.0 → cranelift-entity-0.110.2}/src/unsigned.rs +0 -0
  1136. /data/ext/cargo-vendor/{cranelift-frontend-0.109.0 → cranelift-frontend-0.110.2}/LICENSE +0 -0
  1137. /data/ext/cargo-vendor/{cranelift-frontend-0.109.0 → cranelift-frontend-0.110.2}/README.md +0 -0
  1138. /data/ext/cargo-vendor/{cranelift-frontend-0.109.0 → cranelift-frontend-0.110.2}/src/lib.rs +0 -0
  1139. /data/ext/cargo-vendor/{cranelift-frontend-0.109.0 → cranelift-frontend-0.110.2}/src/ssa.rs +0 -0
  1140. /data/ext/cargo-vendor/{cranelift-frontend-0.109.0 → cranelift-frontend-0.110.2}/src/switch.rs +0 -0
  1141. /data/ext/cargo-vendor/{cranelift-frontend-0.109.0 → cranelift-frontend-0.110.2}/src/variable.rs +0 -0
  1142. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/README.md +0 -0
  1143. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/build.rs +0 -0
  1144. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/fail/bad_converters.isle +0 -0
  1145. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/fail/bound_var_type_mismatch.isle +0 -0
  1146. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/fail/converter_extractor_constructor.isle +0 -0
  1147. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/fail/error1.isle +0 -0
  1148. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/fail/extra_parens.isle +0 -0
  1149. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/fail/impure_expression.isle +0 -0
  1150. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/fail/impure_rhs.isle +0 -0
  1151. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/fail/multi_internal_etor.isle +0 -0
  1152. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/fail/multi_prio.isle +0 -0
  1153. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/link/borrows.isle +0 -0
  1154. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/link/borrows_main.rs +0 -0
  1155. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/link/iflets.isle +0 -0
  1156. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/link/iflets_main.rs +0 -0
  1157. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/link/multi_constructor.isle +0 -0
  1158. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/link/multi_constructor_main.rs +0 -0
  1159. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/link/multi_extractor.isle +0 -0
  1160. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/link/multi_extractor_main.rs +0 -0
  1161. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/link/test.isle +0 -0
  1162. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/link/test_main.rs +0 -0
  1163. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/pass/bound_var.isle +0 -0
  1164. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/pass/construct_and_extract.isle +0 -0
  1165. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/pass/conversions.isle +0 -0
  1166. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/pass/conversions_extern.isle +0 -0
  1167. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/pass/let.isle +0 -0
  1168. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/pass/nodebug.isle +0 -0
  1169. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/pass/prio_trie_bug.isle +0 -0
  1170. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/pass/test2.isle +0 -0
  1171. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/pass/test3.isle +0 -0
  1172. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/pass/test4.isle +0 -0
  1173. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/pass/tutorial.isle +0 -0
  1174. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/run/iconst.isle +0 -0
  1175. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/run/iconst_main.rs +0 -0
  1176. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/run/let_shadowing.isle +0 -0
  1177. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/isle_examples/run/let_shadowing_main.rs +0 -0
  1178. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/src/ast.rs +0 -0
  1179. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/src/compile.rs +0 -0
  1180. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/src/disjointsets.rs +0 -0
  1181. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/src/error.rs +0 -0
  1182. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/src/lexer.rs +0 -0
  1183. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/src/lib.rs +0 -0
  1184. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/src/log.rs +0 -0
  1185. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/src/overlap.rs +0 -0
  1186. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/src/serialize.rs +0 -0
  1187. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/src/stablemapset.rs +0 -0
  1188. /data/ext/cargo-vendor/{cranelift-isle-0.109.0 → cranelift-isle-0.110.2}/tests/run_tests.rs +0 -0
  1189. /data/ext/cargo-vendor/{cranelift-native-0.109.0 → cranelift-native-0.110.2}/LICENSE +0 -0
  1190. /data/ext/cargo-vendor/{cranelift-native-0.109.0 → cranelift-native-0.110.2}/README.md +0 -0
  1191. /data/ext/cargo-vendor/{cranelift-native-0.109.0 → cranelift-native-0.110.2}/src/riscv.rs +0 -0
  1192. /data/ext/cargo-vendor/{cranelift-wasm-0.109.0 → cranelift-wasm-0.110.2}/LICENSE +0 -0
  1193. /data/ext/cargo-vendor/{cranelift-wasm-0.109.0 → cranelift-wasm-0.110.2}/README.md +0 -0
  1194. /data/ext/cargo-vendor/{cranelift-wasm-0.109.0 → cranelift-wasm-0.110.2}/src/environ/dummy.rs +0 -0
  1195. /data/ext/cargo-vendor/{cranelift-wasm-0.109.0 → cranelift-wasm-0.110.2}/src/environ/mod.rs +0 -0
  1196. /data/ext/cargo-vendor/{cranelift-wasm-0.109.0 → cranelift-wasm-0.110.2}/src/environ/spec.rs +0 -0
  1197. /data/ext/cargo-vendor/{cranelift-wasm-0.109.0 → cranelift-wasm-0.110.2}/src/func_translator.rs +0 -0
  1198. /data/ext/cargo-vendor/{cranelift-wasm-0.109.0 → cranelift-wasm-0.110.2}/src/lib.rs +0 -0
  1199. /data/ext/cargo-vendor/{cranelift-wasm-0.109.0 → cranelift-wasm-0.110.2}/src/module_translator.rs +0 -0
  1200. /data/ext/cargo-vendor/{cranelift-wasm-0.109.0 → cranelift-wasm-0.110.2}/src/state.rs +0 -0
  1201. /data/ext/cargo-vendor/{cranelift-wasm-0.109.0 → cranelift-wasm-0.110.2}/src/table.rs +0 -0
  1202. /data/ext/cargo-vendor/{cranelift-wasm-0.109.0 → cranelift-wasm-0.110.2}/src/translation_utils.rs +0 -0
  1203. /data/ext/cargo-vendor/{deterministic-wasi-ctx-0.1.22 → deterministic-wasi-ctx-0.1.23}/README.md +0 -0
  1204. /data/ext/cargo-vendor/{deterministic-wasi-ctx-0.1.22 → deterministic-wasi-ctx-0.1.23}/src/clocks.rs +0 -0
  1205. /data/ext/cargo-vendor/{deterministic-wasi-ctx-0.1.22 → deterministic-wasi-ctx-0.1.23}/src/lib.rs +0 -0
  1206. /data/ext/cargo-vendor/{deterministic-wasi-ctx-0.1.22 → deterministic-wasi-ctx-0.1.23}/src/noop_scheduler.rs +0 -0
  1207. /data/ext/cargo-vendor/{deterministic-wasi-ctx-0.1.22 → deterministic-wasi-ctx-0.1.23}/tests/clocks.rs +0 -0
  1208. /data/ext/cargo-vendor/{deterministic-wasi-ctx-0.1.22 → deterministic-wasi-ctx-0.1.23}/tests/common/mod.rs +0 -0
  1209. /data/ext/cargo-vendor/{deterministic-wasi-ctx-0.1.22 → deterministic-wasi-ctx-0.1.23}/tests/random.rs +0 -0
  1210. /data/ext/cargo-vendor/{deterministic-wasi-ctx-0.1.22 → deterministic-wasi-ctx-0.1.23}/tests/scheduler.rs +0 -0
  1211. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/LICENSE +0 -0
  1212. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/README.md +0 -0
  1213. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/clocks.rs +0 -0
  1214. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/ctx.rs +0 -0
  1215. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/dir.rs +0 -0
  1216. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/error.rs +0 -0
  1217. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/file.rs +0 -0
  1218. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/lib.rs +0 -0
  1219. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/pipe.rs +0 -0
  1220. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/random.rs +0 -0
  1221. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/sched/subscription.rs +0 -0
  1222. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/sched.rs +0 -0
  1223. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/snapshots/mod.rs +0 -0
  1224. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/snapshots/preview_0.rs +0 -0
  1225. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/snapshots/preview_1/error.rs +0 -0
  1226. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/snapshots/preview_1.rs +0 -0
  1227. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/string_array.rs +0 -0
  1228. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/sync/clocks.rs +0 -0
  1229. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/sync/dir.rs +0 -0
  1230. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/sync/file.rs +0 -0
  1231. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/sync/mod.rs +0 -0
  1232. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/sync/net.rs +0 -0
  1233. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/sync/sched/unix.rs +0 -0
  1234. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/sync/sched/windows.rs +0 -0
  1235. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/sync/sched.rs +0 -0
  1236. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/sync/stdio.rs +0 -0
  1237. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/table.rs +0 -0
  1238. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/tokio/dir.rs +0 -0
  1239. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/tokio/file.rs +0 -0
  1240. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/tokio/net.rs +0 -0
  1241. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/tokio/sched/unix.rs +0 -0
  1242. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/tokio/sched/windows.rs +0 -0
  1243. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/tokio/sched.rs +0 -0
  1244. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/src/tokio/stdio.rs +0 -0
  1245. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/tests/all/main.rs +0 -0
  1246. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/witx/preview0/typenames.witx +0 -0
  1247. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/witx/preview0/wasi_unstable.witx +0 -0
  1248. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/witx/preview1/typenames.witx +0 -0
  1249. /data/ext/cargo-vendor/{wasi-common-22.0.0 → wasi-common-23.0.2}/witx/preview1/wasi_snapshot_preview1.witx +0 -0
  1250. /data/ext/cargo-vendor/{wasm-encoder-0.209.1 → wasm-encoder-0.212.0}/LICENSE +0 -0
  1251. /data/ext/cargo-vendor/{wasm-encoder-0.209.1 → wasm-encoder-0.212.0}/README.md +0 -0
  1252. /data/ext/cargo-vendor/{wasm-encoder-0.209.1 → wasm-encoder-0.212.0}/src/component/aliases.rs +0 -0
  1253. /data/ext/cargo-vendor/{wasm-encoder-0.209.1 → wasm-encoder-0.212.0}/src/component/builder.rs +0 -0
  1254. /data/ext/cargo-vendor/{wasm-encoder-0.209.1 → wasm-encoder-0.212.0}/src/component/canonicals.rs +0 -0
  1255. /data/ext/cargo-vendor/{wasm-encoder-0.209.1 → wasm-encoder-0.212.0}/src/component/components.rs +0 -0
  1256. /data/ext/cargo-vendor/{wasm-encoder-0.209.1 → wasm-encoder-0.212.0}/src/component/exports.rs +0 -0
  1257. /data/ext/cargo-vendor/{wasm-encoder-0.209.1 → wasm-encoder-0.212.0}/src/component/imports.rs +0 -0
  1258. /data/ext/cargo-vendor/{wasm-encoder-0.209.1 → wasm-encoder-0.212.0}/src/component/instances.rs +0 -0
  1259. /data/ext/cargo-vendor/{wasm-encoder-0.209.1 → wasm-encoder-0.212.0}/src/component/modules.rs +0 -0
  1260. /data/ext/cargo-vendor/{wasm-encoder-0.209.1 → wasm-encoder-0.212.0}/src/component/names.rs +0 -0
  1261. /data/ext/cargo-vendor/{wasm-encoder-0.209.1 → wasm-encoder-0.212.0}/src/component/start.rs +0 -0
  1262. /data/ext/cargo-vendor/{wasm-encoder-0.209.1 → wasm-encoder-0.212.0}/src/component.rs +0 -0
  1263. /data/ext/cargo-vendor/{wasm-encoder-0.209.1 → wasm-encoder-0.212.0}/src/core/custom.rs +0 -0
  1264. /data/ext/cargo-vendor/{wasm-encoder-0.209.1 → wasm-encoder-0.212.0}/src/core/data.rs +0 -0
  1265. /data/ext/cargo-vendor/{wasm-encoder-0.209.1 → wasm-encoder-0.212.0}/src/core/dump.rs +0 -0
  1266. /data/ext/cargo-vendor/{wasm-encoder-0.209.1 → wasm-encoder-0.212.0}/src/core/elements.rs +0 -0
  1267. /data/ext/cargo-vendor/{wasm-encoder-0.209.1 → wasm-encoder-0.212.0}/src/core/functions.rs +0 -0
  1268. /data/ext/cargo-vendor/{wasm-encoder-0.209.1 → wasm-encoder-0.212.0}/src/core/linking.rs +0 -0
  1269. /data/ext/cargo-vendor/{wasm-encoder-0.209.1 → wasm-encoder-0.212.0}/src/core/names.rs +0 -0
  1270. /data/ext/cargo-vendor/{wasm-encoder-0.209.1 → wasm-encoder-0.212.0}/src/core/producers.rs +0 -0
  1271. /data/ext/cargo-vendor/{wasm-encoder-0.209.1 → wasm-encoder-0.212.0}/src/core/start.rs +0 -0
  1272. /data/ext/cargo-vendor/{wasm-encoder-0.209.1 → wasm-encoder-0.212.0}/src/core.rs +0 -0
  1273. /data/ext/cargo-vendor/{wasm-encoder-0.209.1 → wasm-encoder-0.212.0}/src/raw.rs +0 -0
  1274. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/README.md +0 -0
  1275. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/benches/benchmark.rs +0 -0
  1276. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/examples/simple.rs +0 -0
  1277. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/collections/hash.rs +0 -0
  1278. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/collections/index_map/detail.rs +0 -0
  1279. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/collections/index_map/tests.rs +0 -0
  1280. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/collections/index_map.rs +0 -0
  1281. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/collections/index_set.rs +0 -0
  1282. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/collections/map.rs +0 -0
  1283. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/collections/mod.rs +0 -0
  1284. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/collections/set.rs +0 -0
  1285. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/limits.rs +0 -0
  1286. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/component/aliases.rs +0 -0
  1287. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/component/canonicals.rs +0 -0
  1288. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/component/exports.rs +0 -0
  1289. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/component/imports.rs +0 -0
  1290. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/component/instances.rs +0 -0
  1291. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/component/names.rs +0 -0
  1292. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/component/start.rs +0 -0
  1293. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/component/types.rs +0 -0
  1294. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/component.rs +0 -0
  1295. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/core/branch_hinting.rs +0 -0
  1296. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/core/code.rs +0 -0
  1297. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/core/coredumps.rs +0 -0
  1298. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/core/custom.rs +0 -0
  1299. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/core/data.rs +0 -0
  1300. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/core/dylink0.rs +0 -0
  1301. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/core/elements.rs +0 -0
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  1303. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/core/functions.rs +0 -0
  1304. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/core/globals.rs +0 -0
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  1306. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/core/init.rs +0 -0
  1307. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/core/linking.rs +0 -0
  1308. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/core/memories.rs +0 -0
  1309. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/core/names.rs +0 -0
  1310. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/core/producers.rs +0 -0
  1311. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/core/reloc.rs +0 -0
  1312. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/core/tags.rs +0 -0
  1313. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/core/types/matches.rs +0 -0
  1314. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers/core.rs +0 -0
  1315. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/readers.rs +0 -0
  1316. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/validator/core/canonical.rs +0 -0
  1317. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/validator/func.rs +0 -0
  1318. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/src/validator/names.rs +0 -0
  1319. /data/ext/cargo-vendor/{wasmparser-0.209.1 → wasmparser-0.212.0}/tests/big-module.rs +0 -0
  1320. /data/ext/cargo-vendor/{wasmprinter-0.209.1 → wasmprinter-0.212.0}/LICENSE +0 -0
  1321. /data/ext/cargo-vendor/{wasmprinter-0.209.1 → wasmprinter-0.212.0}/README.md +0 -0
  1322. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/LICENSE +0 -0
  1323. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/README.md +0 -0
  1324. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/proptest-regressions/runtime/vm/instance/allocator/pooling/memory_pool.txt +0 -0
  1325. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/code.rs +0 -0
  1326. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/component/bindgen_examples/_0_hello_world.rs +0 -0
  1327. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/component/bindgen_examples/_1_world_imports.rs +0 -0
  1328. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/component/bindgen_examples/_2_world_exports.rs +0 -0
  1329. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/component/bindgen_examples/_3_interface_imports.rs +0 -0
  1330. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/component/bindgen_examples/_4_imported_resources.rs +0 -0
  1331. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/component/bindgen_examples/_5_all_world_export_kinds.rs +0 -0
  1332. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/component/bindgen_examples/_6_exported_resources.rs +0 -0
  1333. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/component/resource_table.rs +0 -0
  1334. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/component/storage.rs +0 -0
  1335. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/component/store.rs +0 -0
  1336. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/component/types.rs +0 -0
  1337. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/externals.rs +0 -0
  1338. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/gc/disabled/anyref.rs +0 -0
  1339. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/gc/disabled/externref.rs +0 -0
  1340. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/gc/disabled/i31.rs +0 -0
  1341. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/gc/disabled.rs +0 -0
  1342. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/gc/enabled/anyref.rs +0 -0
  1343. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/gc/enabled/i31.rs +0 -0
  1344. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/gc/enabled.rs +0 -0
  1345. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/gc/noextern.rs +0 -0
  1346. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/gc.rs +0 -0
  1347. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/resources.rs +0 -0
  1348. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/signatures.rs +0 -0
  1349. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/store/context.rs +0 -0
  1350. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/store/func_refs.rs +0 -0
  1351. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/trampoline/global.rs +0 -0
  1352. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/type_registry.rs +0 -0
  1353. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/uninhabited.rs +0 -0
  1354. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/unix.rs +0 -0
  1355. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/v128.rs +0 -0
  1356. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/arch/aarch64.rs +0 -0
  1357. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/arch/mod.rs +0 -0
  1358. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/arch/s390x.S +0 -0
  1359. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/arch/s390x.rs +0 -0
  1360. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/arch/x86_64.rs +0 -0
  1361. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/async_yield.rs +0 -0
  1362. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/debug_builtins.rs +0 -0
  1363. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/export.rs +0 -0
  1364. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/gc/enabled/externref.rs +0 -0
  1365. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/gc/enabled.rs +0 -0
  1366. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/gc/host_data.rs +0 -0
  1367. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/gc/i31.rs +0 -0
  1368. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/helpers.c +0 -0
  1369. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/imports.rs +0 -0
  1370. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/mpk/pkru.rs +0 -0
  1371. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/send_sync_ptr.rs +0 -0
  1372. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/store_box.rs +0 -0
  1373. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/sys/custom/capi.rs +0 -0
  1374. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/sys/custom/traphandlers.rs +0 -0
  1375. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/sys/miri/mod.rs +0 -0
  1376. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/sys/miri/traphandlers.rs +0 -0
  1377. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/sys/miri/vm.rs +0 -0
  1378. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/sys/mod.rs +0 -0
  1379. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/sys/unix/machports.rs +0 -0
  1380. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/sys/unix/macos_traphandlers.rs +0 -0
  1381. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/sys/unix/mod.rs +0 -0
  1382. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/sys/unix/vm.rs +0 -0
  1383. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/sys/windows/mod.rs +0 -0
  1384. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/sys/windows/traphandlers.rs +0 -0
  1385. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/sys/windows/vm.rs +0 -0
  1386. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/threads/mod.rs +0 -0
  1387. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/threads/parking_spot.rs +0 -0
  1388. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/traphandlers/backtrace.rs +0 -0
  1389. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/traphandlers/coredump_disabled.rs +0 -0
  1390. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/vm/traphandlers/coredump_enabled.rs +0 -0
  1391. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/runtime/windows.rs +0 -0
  1392. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/sync_nostd.rs +0 -0
  1393. /data/ext/cargo-vendor/{wasmtime-22.0.0 → wasmtime-23.0.2}/src/sync_std.rs +0 -0
  1394. /data/ext/cargo-vendor/{wasmtime-asm-macros-22.0.0 → wasmtime-asm-macros-23.0.2}/src/lib.rs +0 -0
  1395. /data/ext/cargo-vendor/{wasmtime-cache-22.0.0 → wasmtime-cache-23.0.2}/LICENSE +0 -0
  1396. /data/ext/cargo-vendor/{wasmtime-cache-22.0.0 → wasmtime-cache-23.0.2}/build.rs +0 -0
  1397. /data/ext/cargo-vendor/{wasmtime-cache-22.0.0 → wasmtime-cache-23.0.2}/src/config/tests.rs +0 -0
  1398. /data/ext/cargo-vendor/{wasmtime-cache-22.0.0 → wasmtime-cache-23.0.2}/src/config.rs +0 -0
  1399. /data/ext/cargo-vendor/{wasmtime-cache-22.0.0 → wasmtime-cache-23.0.2}/src/lib.rs +0 -0
  1400. /data/ext/cargo-vendor/{wasmtime-cache-22.0.0 → wasmtime-cache-23.0.2}/src/tests.rs +0 -0
  1401. /data/ext/cargo-vendor/{wasmtime-cache-22.0.0 → wasmtime-cache-23.0.2}/src/worker/tests/system_time_stub.rs +0 -0
  1402. /data/ext/cargo-vendor/{wasmtime-cache-22.0.0 → wasmtime-cache-23.0.2}/src/worker/tests.rs +0 -0
  1403. /data/ext/cargo-vendor/{wasmtime-cache-22.0.0 → wasmtime-cache-23.0.2}/src/worker.rs +0 -0
  1404. /data/ext/cargo-vendor/{wasmtime-cache-22.0.0 → wasmtime-cache-23.0.2}/tests/cache_write_default_config.rs +0 -0
  1405. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/build.rs +0 -0
  1406. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/src/component.rs +0 -0
  1407. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/src/lib.rs +0 -0
  1408. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/char.wit +0 -0
  1409. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/conventions.wit +0 -0
  1410. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/dead-code.wit +0 -0
  1411. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/direct-import.wit +0 -0
  1412. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/empty.wit +0 -0
  1413. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/flags.wit +0 -0
  1414. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/floats.wit +0 -0
  1415. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/function-new.wit +0 -0
  1416. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/integers.wit +0 -0
  1417. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/lists.wit +0 -0
  1418. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/many-arguments.wit +0 -0
  1419. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/multi-return.wit +0 -0
  1420. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/multiversion/deps/v1/root.wit +0 -0
  1421. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/multiversion/deps/v2/root.wit +0 -0
  1422. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/multiversion/root.wit +0 -0
  1423. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/records.wit +0 -0
  1424. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/rename.wit +0 -0
  1425. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/resources-export.wit +0 -0
  1426. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/resources-import.wit +0 -0
  1427. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/share-types.wit +0 -0
  1428. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/simple-functions.wit +0 -0
  1429. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/simple-lists.wit +0 -0
  1430. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/simple-wasi.wit +0 -0
  1431. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/small-anonymous.wit +0 -0
  1432. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/smoke-default.wit +0 -0
  1433. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/smoke-export.wit +0 -0
  1434. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/smoke.wit +0 -0
  1435. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/strings.wit +0 -0
  1436. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/unversioned-foo.wit +0 -0
  1437. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/use-paths.wit +0 -0
  1438. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/variants.wit +0 -0
  1439. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/wat.wit +0 -0
  1440. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen/worlds-with-types.wit +0 -0
  1441. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/codegen_no_std.rs +0 -0
  1442. /data/ext/cargo-vendor/{wasmtime-component-macro-22.0.0 → wasmtime-component-macro-23.0.2}/tests/expanded.rs +0 -0
  1443. /data/ext/cargo-vendor/{wasmtime-component-util-22.0.0 → wasmtime-component-util-23.0.2}/src/lib.rs +0 -0
  1444. /data/ext/cargo-vendor/{wasmtime-cranelift-22.0.0 → wasmtime-cranelift-23.0.2}/LICENSE +0 -0
  1445. /data/ext/cargo-vendor/{wasmtime-cranelift-22.0.0 → wasmtime-cranelift-23.0.2}/SECURITY.md +0 -0
  1446. /data/ext/cargo-vendor/{wasmtime-cranelift-22.0.0 → wasmtime-cranelift-23.0.2}/src/builder.rs +0 -0
  1447. /data/ext/cargo-vendor/{wasmtime-cranelift-22.0.0 → wasmtime-cranelift-23.0.2}/src/compiled_function.rs +0 -0
  1448. /data/ext/cargo-vendor/{wasmtime-cranelift-22.0.0 → wasmtime-cranelift-23.0.2}/src/compiler/component.rs +0 -0
  1449. /data/ext/cargo-vendor/{wasmtime-cranelift-22.0.0 → wasmtime-cranelift-23.0.2}/src/debug/transform/refs.rs +0 -0
  1450. /data/ext/cargo-vendor/{wasmtime-cranelift-22.0.0 → wasmtime-cranelift-23.0.2}/src/gc/disabled.rs +0 -0
  1451. /data/ext/cargo-vendor/{wasmtime-cranelift-22.0.0 → wasmtime-cranelift-23.0.2}/src/gc.rs +0 -0
  1452. /data/ext/cargo-vendor/{wasmtime-cranelift-22.0.0 → wasmtime-cranelift-23.0.2}/src/isa_builder.rs +0 -0
  1453. /data/ext/cargo-vendor/{wasmtime-cranelift-22.0.0 → wasmtime-cranelift-23.0.2}/src/obj.rs +0 -0
  1454. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/LICENSE +0 -0
  1455. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/examples/factc.rs +0 -0
  1456. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/src/address_map.rs +0 -0
  1457. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/src/builtin.rs +0 -0
  1458. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/src/compile/address_map.rs +0 -0
  1459. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/src/compile/module_artifacts.rs +0 -0
  1460. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/src/compile/module_types.rs +0 -0
  1461. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/src/compile/trap_encoding.rs +0 -0
  1462. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/src/component/artifacts.rs +0 -0
  1463. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/src/component/compiler.rs +0 -0
  1464. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/src/component/translate/adapt.rs +0 -0
  1465. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/src/component/types_builder/resources.rs +0 -0
  1466. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/src/component/vmcomponent_offsets.rs +0 -0
  1467. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/src/demangling.rs +0 -0
  1468. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/src/fact/core_types.rs +0 -0
  1469. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/src/fact/signature.rs +0 -0
  1470. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/src/fact/trampoline.rs +0 -0
  1471. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/src/fact/transcode.rs +0 -0
  1472. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/src/fact/traps.rs +0 -0
  1473. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/src/fact.rs +0 -0
  1474. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/src/gc.rs +0 -0
  1475. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/src/module_artifacts.rs +0 -0
  1476. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/src/module_types.rs +0 -0
  1477. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/src/obj.rs +0 -0
  1478. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/src/ref_bits.rs +0 -0
  1479. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/src/scopevec.rs +0 -0
  1480. /data/ext/cargo-vendor/{wasmtime-environ-22.0.0 → wasmtime-environ-23.0.2}/src/trap_encoding.rs +0 -0
  1481. /data/ext/cargo-vendor/{wasmtime-fiber-22.0.0 → wasmtime-fiber-23.0.2}/LICENSE +0 -0
  1482. /data/ext/cargo-vendor/{wasmtime-fiber-22.0.0 → wasmtime-fiber-23.0.2}/build.rs +0 -0
  1483. /data/ext/cargo-vendor/{wasmtime-fiber-22.0.0 → wasmtime-fiber-23.0.2}/src/lib.rs +0 -0
  1484. /data/ext/cargo-vendor/{wasmtime-fiber-22.0.0 → wasmtime-fiber-23.0.2}/src/unix/aarch64.rs +0 -0
  1485. /data/ext/cargo-vendor/{wasmtime-fiber-22.0.0 → wasmtime-fiber-23.0.2}/src/unix/arm.rs +0 -0
  1486. /data/ext/cargo-vendor/{wasmtime-fiber-22.0.0 → wasmtime-fiber-23.0.2}/src/unix/riscv64.rs +0 -0
  1487. /data/ext/cargo-vendor/{wasmtime-fiber-22.0.0 → wasmtime-fiber-23.0.2}/src/unix/s390x.S +0 -0
  1488. /data/ext/cargo-vendor/{wasmtime-fiber-22.0.0 → wasmtime-fiber-23.0.2}/src/unix/x86.rs +0 -0
  1489. /data/ext/cargo-vendor/{wasmtime-fiber-22.0.0 → wasmtime-fiber-23.0.2}/src/unix/x86_64.rs +0 -0
  1490. /data/ext/cargo-vendor/{wasmtime-fiber-22.0.0 → wasmtime-fiber-23.0.2}/src/unix.rs +0 -0
  1491. /data/ext/cargo-vendor/{wasmtime-fiber-22.0.0 → wasmtime-fiber-23.0.2}/src/windows.c +0 -0
  1492. /data/ext/cargo-vendor/{wasmtime-fiber-22.0.0 → wasmtime-fiber-23.0.2}/src/windows.rs +0 -0
  1493. /data/ext/cargo-vendor/{wasmtime-jit-debug-22.0.0 → wasmtime-jit-debug-23.0.2}/README.md +0 -0
  1494. /data/ext/cargo-vendor/{wasmtime-jit-debug-22.0.0 → wasmtime-jit-debug-23.0.2}/src/gdb_jit_int.rs +0 -0
  1495. /data/ext/cargo-vendor/{wasmtime-jit-debug-22.0.0 → wasmtime-jit-debug-23.0.2}/src/lib.rs +0 -0
  1496. /data/ext/cargo-vendor/{wasmtime-jit-debug-22.0.0 → wasmtime-jit-debug-23.0.2}/src/perf_jitdump.rs +0 -0
  1497. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-22.0.0 → wasmtime-jit-icache-coherence-23.0.2}/src/lib.rs +0 -0
  1498. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-22.0.0 → wasmtime-jit-icache-coherence-23.0.2}/src/libc.rs +0 -0
  1499. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-22.0.0 → wasmtime-jit-icache-coherence-23.0.2}/src/miri.rs +0 -0
  1500. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-22.0.0 → wasmtime-jit-icache-coherence-23.0.2}/src/win.rs +0 -0
  1501. /data/ext/cargo-vendor/{wasmtime-slab-22.0.0 → wasmtime-slab-23.0.2}/src/lib.rs +0 -0
  1502. /data/ext/cargo-vendor/{wasmtime-types-22.0.0 → wasmtime-types-23.0.2}/LICENSE +0 -0
  1503. /data/ext/cargo-vendor/{wasmtime-types-22.0.0 → wasmtime-types-23.0.2}/src/error.rs +0 -0
  1504. /data/ext/cargo-vendor/{wasmtime-versioned-export-macros-22.0.0 → wasmtime-versioned-export-macros-23.0.2}/src/lib.rs +0 -0
  1505. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/LICENSE +0 -0
  1506. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/README.md +0 -0
  1507. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/clocks/host.rs +0 -0
  1508. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/clocks.rs +0 -0
  1509. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/ctx.rs +0 -0
  1510. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/error.rs +0 -0
  1511. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/host/clocks.rs +0 -0
  1512. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/host/env.rs +0 -0
  1513. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/host/exit.rs +0 -0
  1514. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/host/filesystem/sync.rs +0 -0
  1515. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/host/instance_network.rs +0 -0
  1516. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/host/mod.rs +0 -0
  1517. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/host/network.rs +0 -0
  1518. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/host/random.rs +0 -0
  1519. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/host/tcp.rs +0 -0
  1520. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/host/tcp_create_socket.rs +0 -0
  1521. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/host/udp.rs +0 -0
  1522. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/host/udp_create_socket.rs +0 -0
  1523. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/ip_name_lookup.rs +0 -0
  1524. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/network.rs +0 -0
  1525. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/pipe.rs +0 -0
  1526. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/poll.rs +0 -0
  1527. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/preview0.rs +0 -0
  1528. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/random.rs +0 -0
  1529. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/runtime.rs +0 -0
  1530. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/stdio/worker_thread_stdin.rs +0 -0
  1531. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/stream.rs +0 -0
  1532. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/tcp.rs +0 -0
  1533. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/udp.rs +0 -0
  1534. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/src/write_stream.rs +0 -0
  1535. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/tests/all/main.rs +0 -0
  1536. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/tests/all/preview1.rs +0 -0
  1537. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/tests/process_stdin.rs +0 -0
  1538. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/command-extended.wit +0 -0
  1539. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/cli/command.wit +0 -0
  1540. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/cli/environment.wit +0 -0
  1541. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/cli/exit.wit +0 -0
  1542. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/cli/imports.wit +0 -0
  1543. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/cli/run.wit +0 -0
  1544. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/cli/stdio.wit +0 -0
  1545. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/cli/terminal.wit +0 -0
  1546. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/clocks/monotonic-clock.wit +0 -0
  1547. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/clocks/wall-clock.wit +0 -0
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  1549. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/filesystem/preopens.wit +0 -0
  1550. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/filesystem/types.wit +0 -0
  1551. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/filesystem/world.wit +0 -0
  1552. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/http/handler.wit +0 -0
  1553. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/http/proxy.wit +0 -0
  1554. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/http/types.wit +0 -0
  1555. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/io/error.wit +0 -0
  1556. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/io/poll.wit +0 -0
  1557. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/io/streams.wit +0 -0
  1558. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/io/world.wit +0 -0
  1559. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/random/insecure-seed.wit +0 -0
  1560. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/random/insecure.wit +0 -0
  1561. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/random/random.wit +0 -0
  1562. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/random/world.wit +0 -0
  1563. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/sockets/instance-network.wit +0 -0
  1564. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/sockets/ip-name-lookup.wit +0 -0
  1565. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/sockets/network.wit +0 -0
  1566. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/sockets/tcp-create-socket.wit +0 -0
  1567. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/sockets/tcp.wit +0 -0
  1568. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/sockets/udp-create-socket.wit +0 -0
  1569. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/sockets/udp.wit +0 -0
  1570. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/deps/sockets/world.wit +0 -0
  1571. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/wit/test.wit +0 -0
  1572. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/witx/preview0/typenames.witx +0 -0
  1573. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/witx/preview0/wasi_unstable.witx +0 -0
  1574. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/witx/preview1/typenames.witx +0 -0
  1575. /data/ext/cargo-vendor/{wasmtime-wasi-22.0.0 → wasmtime-wasi-23.0.2}/witx/preview1/wasi_snapshot_preview1.witx +0 -0
  1576. /data/ext/cargo-vendor/{wasmtime-winch-22.0.0 → wasmtime-winch-23.0.2}/LICENSE +0 -0
  1577. /data/ext/cargo-vendor/{wasmtime-winch-22.0.0 → wasmtime-winch-23.0.2}/src/builder.rs +0 -0
  1578. /data/ext/cargo-vendor/{wasmtime-winch-22.0.0 → wasmtime-winch-23.0.2}/src/lib.rs +0 -0
  1579. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-22.0.0 → wasmtime-wit-bindgen-23.0.2}/src/rust.rs +0 -0
  1580. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-22.0.0 → wasmtime-wit-bindgen-23.0.2}/src/source.rs +0 -0
  1581. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-22.0.0 → wasmtime-wit-bindgen-23.0.2}/src/types.rs +0 -0
  1582. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/README.md +0 -0
  1583. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/src/component/alias.rs +0 -0
  1584. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/src/component/custom.rs +0 -0
  1585. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/src/component/export.rs +0 -0
  1586. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/src/component/func.rs +0 -0
  1587. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/src/component/import.rs +0 -0
  1588. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/src/component/instance.rs +0 -0
  1589. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/src/component/item_ref.rs +0 -0
  1590. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/src/component/module.rs +0 -0
  1591. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/src/component/types.rs +0 -0
  1592. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/src/component/wast.rs +0 -0
  1593. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/src/core/custom.rs +0 -0
  1594. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/src/core/export.rs +0 -0
  1595. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/src/core/func.rs +0 -0
  1596. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/src/core/global.rs +0 -0
  1597. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/src/core/import.rs +0 -0
  1598. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/src/core/resolve/mod.rs +0 -0
  1599. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/src/core/tag.rs +0 -0
  1600. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/src/core/wast.rs +0 -0
  1601. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/src/encode.rs +0 -0
  1602. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/src/error.rs +0 -0
  1603. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/src/gensym.rs +0 -0
  1604. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/src/lexer.rs +0 -0
  1605. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/src/names.rs +0 -0
  1606. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/src/token.rs +0 -0
  1607. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/src/wast.rs +0 -0
  1608. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/tests/annotations.rs +0 -0
  1609. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/tests/comments.rs +0 -0
  1610. /data/ext/cargo-vendor/{wast-209.0.1 → wast-215.0.0}/tests/parse-fail/bad-core-func-alias.wat +0 -0
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  1722. /data/ext/cargo-vendor/{wat-1.209.1 → wat-1.215.0}/README.md +0 -0
  1723. /data/ext/cargo-vendor/{wast-209.0.1 → wiggle-23.0.2}/LICENSE +0 -0
  1724. /data/ext/cargo-vendor/{wiggle-22.0.0 → wiggle-23.0.2}/README.md +0 -0
  1725. /data/ext/cargo-vendor/{wiggle-22.0.0 → wiggle-23.0.2}/src/error.rs +0 -0
  1726. /data/ext/cargo-vendor/{wiggle-22.0.0 → wiggle-23.0.2}/src/guest_type.rs +0 -0
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  1728. /data/ext/cargo-vendor/{wiggle-22.0.0 → wiggle-23.0.2}/src/region.rs +0 -0
  1729. /data/ext/cargo-vendor/{wat-1.209.1 → wiggle-generate-23.0.2}/LICENSE +0 -0
  1730. /data/ext/cargo-vendor/{wiggle-generate-22.0.0 → wiggle-generate-23.0.2}/README.md +0 -0
  1731. /data/ext/cargo-vendor/{wiggle-generate-22.0.0 → wiggle-generate-23.0.2}/src/codegen_settings.rs +0 -0
  1732. /data/ext/cargo-vendor/{wiggle-generate-22.0.0 → wiggle-generate-23.0.2}/src/config.rs +0 -0
  1733. /data/ext/cargo-vendor/{wiggle-generate-22.0.0 → wiggle-generate-23.0.2}/src/funcs.rs +0 -0
  1734. /data/ext/cargo-vendor/{wiggle-generate-22.0.0 → wiggle-generate-23.0.2}/src/lib.rs +0 -0
  1735. /data/ext/cargo-vendor/{wiggle-generate-22.0.0 → wiggle-generate-23.0.2}/src/lifetimes.rs +0 -0
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  1737. /data/ext/cargo-vendor/{wiggle-generate-22.0.0 → wiggle-generate-23.0.2}/src/names.rs +0 -0
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  1739. /data/ext/cargo-vendor/{wiggle-generate-22.0.0 → wiggle-generate-23.0.2}/src/types/flags.rs +0 -0
  1740. /data/ext/cargo-vendor/{wiggle-generate-22.0.0 → wiggle-generate-23.0.2}/src/types/handle.rs +0 -0
  1741. /data/ext/cargo-vendor/{wiggle-generate-22.0.0 → wiggle-generate-23.0.2}/src/types/mod.rs +0 -0
  1742. /data/ext/cargo-vendor/{wiggle-generate-22.0.0 → wiggle-generate-23.0.2}/src/types/record.rs +0 -0
  1743. /data/ext/cargo-vendor/{wiggle-generate-22.0.0 → wiggle-generate-23.0.2}/src/types/variant.rs +0 -0
  1744. /data/ext/cargo-vendor/{wiggle-generate-22.0.0 → wiggle-generate-23.0.2}/src/wasmtime.rs +0 -0
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  1747. /data/ext/cargo-vendor/{wiggle-macro-22.0.0 → wiggle-macro-23.0.2}/src/lib.rs +0 -0
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  1752. /data/ext/cargo-vendor/{winch-codegen-0.20.0 → winch-codegen-0.21.2}/src/codegen/bounds.rs +0 -0
  1753. /data/ext/cargo-vendor/{winch-codegen-0.20.0 → winch-codegen-0.21.2}/src/codegen/builtin.rs +0 -0
  1754. /data/ext/cargo-vendor/{winch-codegen-0.20.0 → winch-codegen-0.21.2}/src/codegen/call.rs +0 -0
  1755. /data/ext/cargo-vendor/{winch-codegen-0.20.0 → winch-codegen-0.21.2}/src/codegen/context.rs +0 -0
  1756. /data/ext/cargo-vendor/{winch-codegen-0.20.0 → winch-codegen-0.21.2}/src/codegen/control.rs +0 -0
  1757. /data/ext/cargo-vendor/{winch-codegen-0.20.0 → winch-codegen-0.21.2}/src/frame/mod.rs +0 -0
  1758. /data/ext/cargo-vendor/{winch-codegen-0.20.0 → winch-codegen-0.21.2}/src/isa/aarch64/abi.rs +0 -0
  1759. /data/ext/cargo-vendor/{winch-codegen-0.20.0 → winch-codegen-0.21.2}/src/isa/aarch64/address.rs +0 -0
  1760. /data/ext/cargo-vendor/{winch-codegen-0.20.0 → winch-codegen-0.21.2}/src/isa/aarch64/asm.rs +0 -0
  1761. /data/ext/cargo-vendor/{winch-codegen-0.20.0 → winch-codegen-0.21.2}/src/isa/aarch64/masm.rs +0 -0
  1762. /data/ext/cargo-vendor/{winch-codegen-0.20.0 → winch-codegen-0.21.2}/src/isa/aarch64/mod.rs +0 -0
  1763. /data/ext/cargo-vendor/{winch-codegen-0.20.0 → winch-codegen-0.21.2}/src/isa/aarch64/regs.rs +0 -0
  1764. /data/ext/cargo-vendor/{winch-codegen-0.20.0 → winch-codegen-0.21.2}/src/isa/mod.rs +0 -0
  1765. /data/ext/cargo-vendor/{winch-codegen-0.20.0 → winch-codegen-0.21.2}/src/isa/reg.rs +0 -0
  1766. /data/ext/cargo-vendor/{winch-codegen-0.20.0 → winch-codegen-0.21.2}/src/isa/x64/abi.rs +0 -0
  1767. /data/ext/cargo-vendor/{winch-codegen-0.20.0 → winch-codegen-0.21.2}/src/isa/x64/address.rs +0 -0
  1768. /data/ext/cargo-vendor/{winch-codegen-0.20.0 → winch-codegen-0.21.2}/src/isa/x64/asm.rs +0 -0
  1769. /data/ext/cargo-vendor/{winch-codegen-0.20.0 → winch-codegen-0.21.2}/src/isa/x64/masm.rs +0 -0
  1770. /data/ext/cargo-vendor/{winch-codegen-0.20.0 → winch-codegen-0.21.2}/src/isa/x64/mod.rs +0 -0
  1771. /data/ext/cargo-vendor/{winch-codegen-0.20.0 → winch-codegen-0.21.2}/src/isa/x64/regs.rs +0 -0
  1772. /data/ext/cargo-vendor/{winch-codegen-0.20.0 → winch-codegen-0.21.2}/src/lib.rs +0 -0
  1773. /data/ext/cargo-vendor/{winch-codegen-0.20.0 → winch-codegen-0.21.2}/src/masm.rs +0 -0
  1774. /data/ext/cargo-vendor/{winch-codegen-0.20.0 → winch-codegen-0.21.2}/src/regalloc.rs +0 -0
  1775. /data/ext/cargo-vendor/{winch-codegen-0.20.0 → winch-codegen-0.21.2}/src/regset.rs +0 -0
  1776. /data/ext/cargo-vendor/{winch-codegen-0.20.0 → winch-codegen-0.21.2}/src/stack.rs +0 -0
  1777. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/README.md +0 -0
  1778. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/src/abi.rs +0 -0
  1779. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/src/ast/toposort.rs +0 -0
  1780. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/src/live.rs +0 -0
  1781. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/src/metadata.rs +0 -0
  1782. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/src/serde_.rs +0 -0
  1783. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/src/sizealign.rs +0 -0
  1784. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/all.rs +0 -0
  1785. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/comments.wit +0 -0
  1786. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/comments.wit.json +0 -0
  1787. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/complex-include/deps/bar/root.wit +0 -0
  1788. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/complex-include/deps/baz/root.wit +0 -0
  1789. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/complex-include/root.wit +0 -0
  1790. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/complex-include.wit.json +0 -0
  1791. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/cross-package-resource/deps/foo/foo.wit +0 -0
  1792. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/cross-package-resource/foo.wit +0 -0
  1793. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/cross-package-resource.wit.json +0 -0
  1794. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/diamond1/deps/dep1/types.wit +0 -0
  1795. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/diamond1/deps/dep2/types.wit +0 -0
  1796. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/diamond1/join.wit +0 -0
  1797. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/diamond1.wit.json +0 -0
  1798. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/disambiguate-diamond/shared1.wit +0 -0
  1799. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/disambiguate-diamond/shared2.wit +0 -0
  1800. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/disambiguate-diamond/world.wit +0 -0
  1801. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/disambiguate-diamond.wit.json +0 -0
  1802. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/empty.wit +0 -0
  1803. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/empty.wit.json +0 -0
  1804. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/feature-gates.wit +0 -0
  1805. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/foreign-deps/deps/another-pkg/other-doc.wit +0 -0
  1806. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/foreign-deps/deps/corp/saas.wit +0 -0
  1807. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/foreign-deps/deps/different-pkg/the-doc.wit +0 -0
  1808. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/foreign-deps/deps/foreign-pkg/the-doc.wit +0 -0
  1809. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/foreign-deps/deps/some-pkg/some-doc.wit +0 -0
  1810. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/foreign-deps/deps/wasi/clocks.wit +0 -0
  1811. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/foreign-deps/deps/wasi/filesystem.wit +0 -0
  1812. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/foreign-deps/root.wit +0 -0
  1813. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/foreign-deps-union/deps/another-pkg/other-doc.wit +0 -0
  1814. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/foreign-deps-union/deps/corp/saas.wit +0 -0
  1815. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/foreign-deps-union/deps/different-pkg/the-doc.wit +0 -0
  1816. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/foreign-deps-union/deps/foreign-pkg/the-doc.wit +0 -0
  1817. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/foreign-deps-union/deps/some-pkg/some-doc.wit +0 -0
  1818. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/foreign-deps-union/deps/wasi/clocks.wit +0 -0
  1819. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/foreign-deps-union/deps/wasi/filesystem.wit +0 -0
  1820. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/foreign-deps-union/deps/wasi/wasi.wit +0 -0
  1821. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/foreign-deps-union/root.wit +0 -0
  1822. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/foreign-deps-union.wit.json +0 -0
  1823. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/foreign-deps.wit.json +0 -0
  1824. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/functions.wit +0 -0
  1825. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/functions.wit.json +0 -0
  1826. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/ignore-files-deps/deps/bar/types.wit +0 -0
  1827. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/ignore-files-deps/deps/ignore-me.txt +0 -0
  1828. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/ignore-files-deps/world.wit +0 -0
  1829. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/ignore-files-deps.wit.json +0 -0
  1830. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/import-export-overlap1.wit +0 -0
  1831. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/import-export-overlap1.wit.json +0 -0
  1832. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/import-export-overlap2.wit +0 -0
  1833. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/import-export-overlap2.wit.json +0 -0
  1834. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/include-reps.wit +0 -0
  1835. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/include-reps.wit.json +0 -0
  1836. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/kebab-name-include-with.wit +0 -0
  1837. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/kebab-name-include-with.wit.json +0 -0
  1838. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/kinds-of-deps/a.wit +0 -0
  1839. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/kinds-of-deps/deps/b/root.wit +0 -0
  1840. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/kinds-of-deps/deps/c.wit +0 -0
  1841. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/kinds-of-deps/deps/d.wat +0 -0
  1842. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/kinds-of-deps/deps/e.wasm +0 -0
  1843. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/kinds-of-deps.wit.json +0 -0
  1844. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/many-names/a.wit +0 -0
  1845. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/many-names/b.wit +0 -0
  1846. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/many-names.wit.json +0 -0
  1847. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/multi-file/bar.wit +0 -0
  1848. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/multi-file/cycle-a.wit +0 -0
  1849. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/multi-file/cycle-b.wit +0 -0
  1850. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/multi-file/foo.wit +0 -0
  1851. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/multi-file.wit.json +0 -0
  1852. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/name-both-resource-and-type/deps/dep/foo.wit +0 -0
  1853. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/name-both-resource-and-type/foo.wit +0 -0
  1854. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/name-both-resource-and-type.wit.json +0 -0
  1855. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/package-syntax1.wit +0 -0
  1856. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/package-syntax1.wit.json +0 -0
  1857. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/package-syntax3.wit +0 -0
  1858. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/package-syntax3.wit.json +0 -0
  1859. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/package-syntax4.wit +0 -0
  1860. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/package-syntax4.wit.json +0 -0
  1861. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/alias-no-type.wit +0 -0
  1862. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/alias-no-type.wit.result +0 -0
  1863. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/async.wit.result +0 -0
  1864. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/async1.wit.result +0 -0
  1865. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-function.wit +0 -0
  1866. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-function.wit.result +0 -0
  1867. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-function2.wit +0 -0
  1868. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-function2.wit.result +0 -0
  1869. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-gate1.wit +0 -0
  1870. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-gate1.wit.result +0 -0
  1871. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-gate2.wit +0 -0
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  1873. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-gate3.wit +0 -0
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  1875. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-gate4.wit +0 -0
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  1877. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-gate5.wit +0 -0
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  1879. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-include1.wit +0 -0
  1880. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-include1.wit.result +0 -0
  1881. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-include2.wit +0 -0
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  1885. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-list.wit +0 -0
  1886. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-list.wit.result +0 -0
  1887. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-pkg1/root.wit +0 -0
  1888. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-pkg1.wit.result +0 -0
  1889. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-pkg2/deps/bar/empty.wit +0 -0
  1890. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-pkg2/root.wit +0 -0
  1891. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-pkg2.wit.result +0 -0
  1892. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-pkg3/deps/bar/baz.wit +0 -0
  1893. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-pkg3/root.wit +0 -0
  1894. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-pkg3.wit.result +0 -0
  1895. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-pkg4/deps/bar/baz.wit +0 -0
  1896. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-pkg4/root.wit +0 -0
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  1898. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-pkg5/deps/bar/baz.wit +0 -0
  1899. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-pkg5/root.wit +0 -0
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  1901. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-pkg6/deps/bar/baz.wit +0 -0
  1902. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-pkg6/root.wit +0 -0
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  1904. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-resource1.wit +0 -0
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  1908. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-resource11.wit +0 -0
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  1911. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-resource12.wit.result +0 -0
  1912. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-resource13.wit +0 -0
  1913. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-resource13.wit.result +0 -0
  1914. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-resource14.wit +0 -0
  1915. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-resource14.wit.result +0 -0
  1916. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-resource15/deps/foo/foo.wit +0 -0
  1917. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-resource15/foo.wit +0 -0
  1918. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-resource15.wit.result +0 -0
  1919. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-resource2.wit +0 -0
  1920. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-resource2.wit.result +0 -0
  1921. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-resource3.wit +0 -0
  1922. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-resource3.wit.result +0 -0
  1923. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-resource4.wit +0 -0
  1924. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-resource4.wit.result +0 -0
  1925. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-resource5.wit +0 -0
  1926. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-resource5.wit.result +0 -0
  1927. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-resource6.wit +0 -0
  1928. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-resource6.wit.result +0 -0
  1929. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-resource7.wit +0 -0
  1930. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-resource7.wit.result +0 -0
  1931. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-resource8.wit +0 -0
  1932. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-resource8.wit.result +0 -0
  1933. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-resource9.wit +0 -0
  1934. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-resource9.wit.result +0 -0
  1935. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-since1.wit +0 -0
  1936. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-since1.wit.result +0 -0
  1937. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-since3.wit +0 -0
  1938. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-since3.wit.result +0 -0
  1939. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-world-type1.wit +0 -0
  1940. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/bad-world-type1.wit.result +0 -0
  1941. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/conflicting-package/a.wit +0 -0
  1942. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/conflicting-package/b.wit +0 -0
  1943. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/conflicting-package.wit.result +0 -0
  1944. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/cycle.wit +0 -0
  1945. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/cycle.wit.result +0 -0
  1946. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/cycle2.wit +0 -0
  1947. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/cycle2.wit.result +0 -0
  1948. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/cycle3.wit +0 -0
  1949. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/cycle3.wit.result +0 -0
  1950. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/cycle4.wit +0 -0
  1951. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/cycle4.wit.result +0 -0
  1952. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/cycle5.wit +0 -0
  1953. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/cycle5.wit.result +0 -0
  1954. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/dangling-type.wit +0 -0
  1955. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/dangling-type.wit.result +0 -0
  1956. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/duplicate-function-params.wit +0 -0
  1957. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/duplicate-function-params.wit.result +0 -0
  1958. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/duplicate-functions.wit +0 -0
  1959. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/duplicate-functions.wit.result +0 -0
  1960. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/duplicate-interface.wit +0 -0
  1961. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/duplicate-interface.wit.result +0 -0
  1962. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/duplicate-interface2/foo.wit +0 -0
  1963. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/duplicate-interface2/foo2.wit +0 -0
  1964. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/duplicate-interface2.wit.result +0 -0
  1965. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/duplicate-type.wit +0 -0
  1966. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/duplicate-type.wit.result +0 -0
  1967. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/empty-enum.wit +0 -0
  1968. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/empty-enum.wit.result +0 -0
  1969. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/empty-variant1.wit +0 -0
  1970. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/empty-variant1.wit.result +0 -0
  1971. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/export-twice.wit +0 -0
  1972. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/export-twice.wit.result +0 -0
  1973. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/import-and-export1.wit +0 -0
  1974. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/import-and-export1.wit.result +0 -0
  1975. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/import-and-export2.wit +0 -0
  1976. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/import-and-export2.wit.result +0 -0
  1977. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/import-and-export3.wit +0 -0
  1978. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/import-and-export3.wit.result +0 -0
  1979. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/import-and-export4.wit +0 -0
  1980. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/import-and-export4.wit.result +0 -0
  1981. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/import-and-export5.wit +0 -0
  1982. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/import-and-export5.wit.result +0 -0
  1983. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/import-twice.wit +0 -0
  1984. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/import-twice.wit.result +0 -0
  1985. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/include-cycle.wit +0 -0
  1986. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/include-cycle.wit.result +0 -0
  1987. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/include-foreign/deps/bar/empty.wit +0 -0
  1988. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/include-foreign/root.wit +0 -0
  1989. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/include-foreign.wit.result +0 -0
  1990. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/include-with-id.wit +0 -0
  1991. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/include-with-id.wit.result +0 -0
  1992. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/include-with-on-id.wit +0 -0
  1993. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/include-with-on-id.wit.result +0 -0
  1994. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/invalid-toplevel.wit +0 -0
  1995. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/invalid-toplevel.wit.result +0 -0
  1996. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/invalid-type-reference.wit +0 -0
  1997. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/invalid-type-reference.wit.result +0 -0
  1998. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/invalid-type-reference2.wit +0 -0
  1999. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/invalid-type-reference2.wit.result +0 -0
  2000. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/kebab-name-include-not-found.wit +0 -0
  2001. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/kebab-name-include-not-found.wit.result +0 -0
  2002. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/kebab-name-include.wit +0 -0
  2003. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/kebab-name-include.wit.result +0 -0
  2004. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/keyword.wit +0 -0
  2005. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/keyword.wit.result +0 -0
  2006. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/missing-package.wit +0 -0
  2007. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/missing-package.wit.result +0 -0
  2008. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/multiple-package-docs/a.wit +0 -0
  2009. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/multiple-package-docs/b.wit +0 -0
  2010. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/multiple-package-docs.wit.result +0 -0
  2011. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/no-access-to-sibling-use/bar.wit +0 -0
  2012. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/no-access-to-sibling-use/foo.wit +0 -0
  2013. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/no-access-to-sibling-use.wit.result +0 -0
  2014. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/non-existance-world-include/deps/bar/baz.wit +0 -0
  2015. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/non-existance-world-include/root.wit +0 -0
  2016. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/non-existance-world-include.wit.result +0 -0
  2017. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/pkg-cycle/deps/a1/root.wit +0 -0
  2018. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/pkg-cycle/root.wit +0 -0
  2019. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/pkg-cycle.wit.result +0 -0
  2020. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/pkg-cycle2/deps/a1/root.wit +0 -0
  2021. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/pkg-cycle2/deps/a2/root.wit +0 -0
  2022. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/pkg-cycle2/root.wit +0 -0
  2023. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/pkg-cycle2.wit.result +0 -0
  2024. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/resources-multiple-returns-borrow.wit +0 -0
  2025. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/resources-multiple-returns-borrow.wit.result +0 -0
  2026. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/resources-return-borrow.wit +0 -0
  2027. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/resources-return-borrow.wit.result +0 -0
  2028. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/return-borrow1.wit +0 -0
  2029. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/return-borrow1.wit.result +0 -0
  2030. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/return-borrow2.wit +0 -0
  2031. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/return-borrow2.wit.result +0 -0
  2032. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/return-borrow3.wit +0 -0
  2033. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/return-borrow3.wit.result +0 -0
  2034. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/return-borrow4.wit +0 -0
  2035. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/return-borrow4.wit.result +0 -0
  2036. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/return-borrow5.wit +0 -0
  2037. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/return-borrow5.wit.result +0 -0
  2038. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/return-borrow6.wit +0 -0
  2039. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/return-borrow6.wit.result +0 -0
  2040. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/return-borrow7.wit +0 -0
  2041. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/return-borrow7.wit.result +0 -0
  2042. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/return-borrow8/deps/baz.wit +0 -0
  2043. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/return-borrow8/foo.wit +0 -0
  2044. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/return-borrow8.wit.result +0 -0
  2045. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/type-and-resource-same-name/deps/dep/foo.wit +0 -0
  2046. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/type-and-resource-same-name/foo.wit +0 -0
  2047. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/type-and-resource-same-name.wit.result +0 -0
  2048. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/undefined-typed.wit +0 -0
  2049. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/undefined-typed.wit.result +0 -0
  2050. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/unknown-interface.wit +0 -0
  2051. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/unknown-interface.wit.result +0 -0
  2052. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/unresolved-interface1.wit +0 -0
  2053. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/unresolved-interface1.wit.result +0 -0
  2054. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/unresolved-interface2.wit +0 -0
  2055. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/unresolved-interface2.wit.result +0 -0
  2056. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/unresolved-interface3.wit +0 -0
  2057. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/unresolved-interface3.wit.result +0 -0
  2058. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/unresolved-interface4.wit +0 -0
  2059. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/unresolved-interface4.wit.result +0 -0
  2060. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/unresolved-use1.wit +0 -0
  2061. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/unresolved-use1.wit.result +0 -0
  2062. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/unresolved-use10/bar.wit +0 -0
  2063. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/unresolved-use10/foo.wit +0 -0
  2064. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/unresolved-use10.wit.result +0 -0
  2065. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/unresolved-use2.wit +0 -0
  2066. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/unresolved-use2.wit.result +0 -0
  2067. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/unresolved-use3.wit +0 -0
  2068. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/unresolved-use3.wit.result +0 -0
  2069. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/unresolved-use7.wit +0 -0
  2070. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/unresolved-use7.wit.result +0 -0
  2071. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/unresolved-use8.wit +0 -0
  2072. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/unresolved-use8.wit.result +0 -0
  2073. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/unresolved-use9.wit +0 -0
  2074. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/unresolved-use9.wit.result +0 -0
  2075. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/unterminated-string.wit.result +0 -0
  2076. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/use-and-include-world/deps/bar/baz.wit +0 -0
  2077. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/use-and-include-world/root.wit +0 -0
  2078. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/use-and-include-world.wit.result +0 -0
  2079. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/use-conflict.wit +0 -0
  2080. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/use-conflict.wit.result +0 -0
  2081. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/use-conflict2.wit +0 -0
  2082. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/use-conflict2.wit.result +0 -0
  2083. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/use-conflict3.wit +0 -0
  2084. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/use-conflict3.wit.result +0 -0
  2085. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/use-cycle1.wit +0 -0
  2086. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/use-cycle1.wit.result +0 -0
  2087. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/use-cycle4.wit +0 -0
  2088. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/use-cycle4.wit.result +0 -0
  2089. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/use-shadow1.wit +0 -0
  2090. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/use-shadow1.wit.result +0 -0
  2091. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/use-world/deps/bar/baz.wit +0 -0
  2092. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/use-world/root.wit +0 -0
  2093. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/use-world.wit.result +0 -0
  2094. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/world-interface-clash.wit +0 -0
  2095. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/world-interface-clash.wit.result +0 -0
  2096. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/world-same-fields2.wit +0 -0
  2097. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/world-same-fields2.wit.result +0 -0
  2098. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/world-same-fields3.wit +0 -0
  2099. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/world-same-fields3.wit.result +0 -0
  2100. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/world-top-level-func.wit +0 -0
  2101. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/world-top-level-func.wit.result +0 -0
  2102. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/world-top-level-func2.wit +0 -0
  2103. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/parse-fail/world-top-level-func2.wit.result +0 -0
  2104. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/random.wit +0 -0
  2105. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/random.wit.json +0 -0
  2106. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/resources-empty.wit +0 -0
  2107. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/resources-empty.wit.json +0 -0
  2108. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/resources-multiple-returns-own.wit +0 -0
  2109. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/resources-multiple-returns-own.wit.json +0 -0
  2110. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/resources-multiple.wit +0 -0
  2111. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/resources-multiple.wit.json +0 -0
  2112. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/resources-return-own.wit +0 -0
  2113. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/resources-return-own.wit.json +0 -0
  2114. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/resources.wit +0 -0
  2115. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/resources.wit.json +0 -0
  2116. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/resources1.wit +0 -0
  2117. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/resources1.wit.json +0 -0
  2118. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/same-name-import-export.wit +0 -0
  2119. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/same-name-import-export.wit.json +0 -0
  2120. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/shared-types.wit +0 -0
  2121. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/shared-types.wit.json +0 -0
  2122. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/simple-wasm-text.wat +0 -0
  2123. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/simple-wasm-text.wit.json +0 -0
  2124. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/since-and-unstable.wit +0 -0
  2125. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/stress-export-elaborate.wit +0 -0
  2126. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/stress-export-elaborate.wit.json +0 -0
  2127. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/type-then-eof.wit +0 -0
  2128. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/type-then-eof.wit.json +0 -0
  2129. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/types.wit +0 -0
  2130. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/types.wit.json +0 -0
  2131. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/union-fuzz-1.wit +0 -0
  2132. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/union-fuzz-1.wit.json +0 -0
  2133. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/union-fuzz-2.wit +0 -0
  2134. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/union-fuzz-2.wit.json +0 -0
  2135. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/use-chain.wit +0 -0
  2136. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/use-chain.wit.json +0 -0
  2137. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/use.wit +0 -0
  2138. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/use.wit.json +0 -0
  2139. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/versions/deps/a1/foo.wit +0 -0
  2140. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/versions/deps/a2/foo.wit +0 -0
  2141. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/versions/foo.wit +0 -0
  2142. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/versions.wit.json +0 -0
  2143. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/wasi.wit +0 -0
  2144. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/wasi.wit.json +0 -0
  2145. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/world-diamond.wit +0 -0
  2146. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/world-diamond.wit.json +0 -0
  2147. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/world-iface-no-collide.wit +0 -0
  2148. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/world-iface-no-collide.wit.json +0 -0
  2149. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/world-implicit-import1.wit +0 -0
  2150. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/world-implicit-import1.wit.json +0 -0
  2151. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/world-implicit-import2.wit +0 -0
  2152. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/world-implicit-import2.wit.json +0 -0
  2153. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/world-implicit-import3.wit +0 -0
  2154. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/world-implicit-import3.wit.json +0 -0
  2155. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/world-same-fields4.wit +0 -0
  2156. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/world-same-fields4.wit.json +0 -0
  2157. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/world-top-level-funcs.wit +0 -0
  2158. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/world-top-level-funcs.wit.json +0 -0
  2159. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/world-top-level-resources.wit +0 -0
  2160. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/world-top-level-resources.wit.json +0 -0
  2161. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/worlds-union-dedup.wit +0 -0
  2162. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/worlds-union-dedup.wit.json +0 -0
  2163. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/worlds-with-types.wit +0 -0
  2164. /data/ext/cargo-vendor/{wit-parser-0.209.1 → wit-parser-0.212.0}/tests/ui/worlds-with-types.wit.json +0 -0
@@ -0,0 +1,3153 @@
1
+ ;; Instruction formats.
2
+ (type MInst
3
+ (enum
4
+ ;; A no-op of zero size.
5
+ (Nop0)
6
+ (Nop4)
7
+
8
+ ;; load immediate
9
+ (Lui
10
+ (rd WritableReg)
11
+ (imm Imm20))
12
+
13
+ (LoadInlineConst
14
+ (rd WritableReg)
15
+ (ty Type)
16
+ (imm u64))
17
+
18
+ (Auipc
19
+ (rd WritableReg)
20
+ (imm Imm20))
21
+
22
+ (Fli
23
+ (ty Type)
24
+ (imm FliConstant)
25
+ (rd WritableReg))
26
+
27
+ ;; An ALU operation with one register sources and a register destination.
28
+ (FpuRR
29
+ (alu_op FpuOPRR)
30
+ (frm FRM)
31
+ (rd WritableReg)
32
+ (rs Reg))
33
+
34
+
35
+ ;; An ALU operation with two register sources and a register destination.
36
+ (AluRRR
37
+ (alu_op AluOPRRR)
38
+ (rd WritableReg)
39
+ (rs1 Reg)
40
+ (rs2 Reg))
41
+
42
+ ;; An ALU operation with two register sources and a register destination.
43
+ (FpuRRR
44
+ (alu_op FpuOPRRR)
45
+ (frm FRM)
46
+ (rd WritableReg)
47
+ (rs1 Reg)
48
+ (rs2 Reg))
49
+
50
+ ;; An ALU operation with three register sources and a register destination.
51
+ (FpuRRRR
52
+ (alu_op FpuOPRRRR)
53
+ (frm FRM)
54
+ (rd WritableReg)
55
+ (rs1 Reg)
56
+ (rs2 Reg)
57
+ (rs3 Reg))
58
+
59
+ ;; An ALU operation with a register source and an immediate-12 source, and a register
60
+ ;; destination.
61
+ (AluRRImm12
62
+ (alu_op AluOPRRI)
63
+ (rd WritableReg)
64
+ (rs Reg)
65
+ (imm12 Imm12))
66
+
67
+ ;; A CSR Reading or Writing instruction with a register source and a register destination.
68
+ (CsrReg
69
+ (op CsrRegOP)
70
+ (rd WritableReg)
71
+ (rs Reg)
72
+ (csr CSR))
73
+
74
+ ;; A CSR Writing instruction with an immediate source and a register destination.
75
+ (CsrImm
76
+ (op CsrImmOP)
77
+ (rd WritableReg)
78
+ (imm UImm5)
79
+ (csr CSR))
80
+
81
+ ;; An load
82
+ (Load
83
+ (rd WritableReg)
84
+ (op LoadOP)
85
+ (flags MemFlags)
86
+ (from AMode))
87
+ ;; An Store
88
+ (Store
89
+ (to AMode)
90
+ (op StoreOP)
91
+ (flags MemFlags)
92
+ (src Reg))
93
+
94
+ ;; A pseudo-instruction that captures register arguments in vregs.
95
+ (Args
96
+ (args VecArgPair))
97
+
98
+ ;; A pseudo-instruction that moves vregs to return registers.
99
+ (Rets
100
+ (rets VecRetPair))
101
+
102
+ (Ret)
103
+
104
+ (Extend
105
+ (rd WritableReg)
106
+ (rn Reg)
107
+ (signed bool)
108
+ (from_bits u8)
109
+ (to_bits u8))
110
+
111
+ (Call
112
+ (info BoxCallInfo))
113
+
114
+ ;; A machine indirect-call instruction.
115
+ (CallInd
116
+ (info BoxCallIndInfo))
117
+
118
+ ;; A direct return-call macro instruction.
119
+ (ReturnCall
120
+ (callee BoxExternalName)
121
+ (info BoxReturnCallInfo))
122
+
123
+ ;; An indirect return-call macro instruction.
124
+ (ReturnCallInd
125
+ (callee Reg)
126
+ (info BoxReturnCallInfo))
127
+
128
+ ;; Emits a trap with the given trap code if the comparison succeeds
129
+ (TrapIf
130
+ (rs1 Reg)
131
+ (rs2 Reg)
132
+ (cc IntCC)
133
+ (trap_code TrapCode))
134
+
135
+ (Jal
136
+ ;; (rd WritableReg) don't use
137
+ (label MachLabel))
138
+
139
+ (CondBr
140
+ (taken CondBrTarget)
141
+ (not_taken CondBrTarget)
142
+ (kind IntegerCompare))
143
+
144
+ ;; Load an inline symbol reference.
145
+ (LoadExtName
146
+ (rd WritableReg)
147
+ (name BoxExternalName)
148
+ (offset i64))
149
+
150
+ ;; Load a TLS symbol address
151
+ (ElfTlsGetAddr
152
+ (rd WritableReg)
153
+ (name BoxExternalName))
154
+
155
+ ;; Load address referenced by `mem` into `rd`.
156
+ (LoadAddr
157
+ (rd WritableReg)
158
+ (mem AMode))
159
+
160
+ ;; A MOV instruction. These are encoded as OrR's (AluRRR form) but we
161
+ ;; keep them separate at the `Inst` level for better pretty-printing
162
+ ;; and faster `is_move()` logic.
163
+ (Mov
164
+ (rd WritableReg)
165
+ (rm Reg)
166
+ (ty Type))
167
+
168
+ ;; A MOV instruction, but where the source register is a non-allocatable
169
+ ;; PReg. It's important that the register be non-allocatable, as regalloc2
170
+ ;; will not see it as used.
171
+ (MovFromPReg
172
+ (rd WritableReg)
173
+ (rm PReg))
174
+
175
+ (Fence
176
+ (pred FenceReq)
177
+ (succ FenceReq))
178
+
179
+ (EBreak)
180
+
181
+ ;; An instruction guaranteed to always be undefined and to trigger an illegal instruction at
182
+ ;; runtime.
183
+ (Udf
184
+ (trap_code TrapCode))
185
+ ;; a jump and link register operation
186
+ (Jalr
187
+ ;;Plain unconditional jumps (assembler pseudo-op J) are encoded as a JAL with rd=x0.
188
+ (rd WritableReg)
189
+ (base Reg)
190
+ (offset Imm12))
191
+
192
+ ;; atomic operations.
193
+ (Atomic
194
+ (op AtomicOP)
195
+ (rd WritableReg)
196
+ (addr Reg)
197
+ (src Reg)
198
+ (amo AMO))
199
+ ;; an atomic store
200
+ (AtomicStore
201
+ (src Reg)
202
+ (ty Type)
203
+ (p Reg))
204
+ ;; an atomic load.
205
+ (AtomicLoad
206
+ (rd WritableReg)
207
+ (ty Type)
208
+ (p Reg))
209
+
210
+ ;; an atomic nand need using loop to implement.
211
+ (AtomicRmwLoop
212
+ (offset Reg)
213
+ (op AtomicRmwOp)
214
+ (dst WritableReg)
215
+ (ty Type)
216
+ (p Reg)
217
+ (x Reg)
218
+ (t0 WritableReg))
219
+
220
+ ;; select x or y base on condition
221
+ (Select
222
+ (dst WritableValueRegs)
223
+ (condition IntegerCompare)
224
+ (x ValueRegs)
225
+ (y ValueRegs))
226
+
227
+ (BrTable
228
+ (index Reg)
229
+ (tmp1 WritableReg)
230
+ (tmp2 WritableReg)
231
+ (targets VecMachLabel))
232
+
233
+ ;; atomic compare and set operation
234
+ (AtomicCas
235
+ (offset Reg)
236
+ (t0 WritableReg)
237
+ (dst WritableReg)
238
+ (e Reg)
239
+ (addr Reg)
240
+ (v Reg)
241
+ (ty Type))
242
+
243
+ (RawData (data VecU8))
244
+
245
+ ;; An unwind pseudo-instruction.
246
+ (Unwind
247
+ (inst UnwindInst))
248
+
249
+ ;; A dummy use, useful to keep a value alive.
250
+ (DummyUse
251
+ (reg Reg))
252
+
253
+ ;; popcnt if target doesn't support extension B
254
+ ;; use iteration to implement.
255
+ (Popcnt
256
+ (sum WritableReg)
257
+ (step WritableReg)
258
+ (tmp WritableReg)
259
+ (rs Reg)
260
+ (ty Type))
261
+
262
+ ;;; counting leading or trailing zeros.
263
+ (Cltz
264
+ ;; leading or trailing.
265
+ (leading bool)
266
+ (sum WritableReg)
267
+ (step WritableReg)
268
+ (tmp WritableReg)
269
+ (rs Reg)
270
+ (ty Type))
271
+
272
+ (Brev8
273
+ (rs Reg)
274
+ (ty Type)
275
+ (step WritableReg)
276
+ (tmp WritableReg)
277
+ (tmp2 WritableReg)
278
+ (rd WritableReg))
279
+ (StackProbeLoop
280
+ (guard_size u32)
281
+ (probe_count u32)
282
+ (tmp WritableReg))
283
+
284
+ (VecAluRRRR
285
+ (op VecAluOpRRRR)
286
+ (vd WritableReg)
287
+ (vd_src Reg)
288
+ (vs2 Reg)
289
+ (vs1 Reg)
290
+ (mask VecOpMasking)
291
+ (vstate VState))
292
+
293
+ (VecAluRRRImm5
294
+ (op VecAluOpRRRImm5)
295
+ (vd WritableReg)
296
+ (vd_src Reg)
297
+ (vs2 Reg)
298
+ (imm Imm5)
299
+ (mask VecOpMasking)
300
+ (vstate VState))
301
+
302
+ (VecAluRRR
303
+ (op VecAluOpRRR)
304
+ (vd WritableReg)
305
+ (vs2 Reg)
306
+ (vs1 Reg)
307
+ (mask VecOpMasking)
308
+ (vstate VState))
309
+
310
+ (VecAluRRImm5
311
+ (op VecAluOpRRImm5)
312
+ (vd WritableReg)
313
+ (vs2 Reg)
314
+ (imm Imm5)
315
+ (mask VecOpMasking)
316
+ (vstate VState))
317
+
318
+ (VecAluRR
319
+ (op VecAluOpRR)
320
+ (vd WritableReg)
321
+ (vs Reg)
322
+ (mask VecOpMasking)
323
+ (vstate VState))
324
+
325
+ (VecAluRImm5
326
+ (op VecAluOpRImm5)
327
+ (vd WritableReg)
328
+ (imm Imm5)
329
+ (mask VecOpMasking)
330
+ (vstate VState))
331
+
332
+ (VecSetState
333
+ (rd WritableReg)
334
+ (vstate VState))
335
+
336
+ (VecLoad
337
+ (eew VecElementWidth)
338
+ (to WritableReg)
339
+ (from VecAMode)
340
+ (flags MemFlags)
341
+ (mask VecOpMasking)
342
+ (vstate VState))
343
+
344
+ (VecStore
345
+ (eew VecElementWidth)
346
+ (to VecAMode)
347
+ (from Reg)
348
+ (flags MemFlags)
349
+ (mask VecOpMasking)
350
+ (vstate VState))
351
+ ))
352
+
353
+ (type AtomicOP (enum
354
+ (LrW)
355
+ (ScW)
356
+ (AmoswapW)
357
+ (AmoaddW)
358
+ (AmoxorW)
359
+ (AmoandW)
360
+ (AmoorW)
361
+ (AmominW)
362
+ (AmomaxW)
363
+ (AmominuW)
364
+ (AmomaxuW)
365
+ (LrD)
366
+ (ScD)
367
+ (AmoswapD)
368
+ (AmoaddD)
369
+ (AmoxorD)
370
+ (AmoandD)
371
+ (AmoorD)
372
+ (AmominD)
373
+ (AmomaxD)
374
+ (AmominuD)
375
+ (AmomaxuD)
376
+ ))
377
+
378
+ (type FpuOPRRRR (enum
379
+ ;; float32
380
+ (FmaddS)
381
+ (FmsubS)
382
+ (FnmsubS)
383
+ (FnmaddS)
384
+ ;; float64
385
+ (FmaddD)
386
+ (FmsubD)
387
+ (FnmsubD)
388
+ (FnmaddD)
389
+ ))
390
+
391
+ (type FClassResult (enum
392
+ ;;0 rs1 is −∞.
393
+ (NegInfinite)
394
+ ;; 1 rs1 is a negative normal number.
395
+ (NegNormal)
396
+ ;; 2 rs1 is a negative subnormal number.
397
+ (NegSubNormal)
398
+ ;; 3 rs1 is −0.
399
+ (NegZero)
400
+ ;; 4 rs1 is +0.
401
+ (PosZero)
402
+ ;; 5 rs1 is a positive subnormal number.
403
+ (PosSubNormal)
404
+ ;; 6 rs1 is a positive normal number.
405
+ (PosNormal)
406
+ ;; 7 rs1 is +∞.
407
+ (PosInfinite)
408
+ ;; 8 rs1 is a signaling NaN.
409
+ (SNaN)
410
+ ;; 9 rs1 is a quiet NaN.
411
+ (QNaN)
412
+ ))
413
+
414
+ (type FliConstant (primitive FliConstant))
415
+
416
+ (type FpuOPRR (enum
417
+ ;; RV32F Standard Extension
418
+ (FsqrtS)
419
+ (FcvtWS)
420
+ (FcvtWuS)
421
+ (FmvXW)
422
+ (FclassS)
423
+ (FcvtSw)
424
+ (FcvtSwU)
425
+ (FmvWX)
426
+
427
+
428
+ ;; RV64F Standard Extension (in addition to RV32F)
429
+ (FcvtLS)
430
+ (FcvtLuS)
431
+ (FcvtSL)
432
+ (FcvtSLU)
433
+
434
+
435
+ ;; RV64D Standard Extension (in addition to RV32D)
436
+ (FcvtLD)
437
+ (FcvtLuD)
438
+ (FmvXD)
439
+ (FcvtDL)
440
+ (FcvtDLu)
441
+ (FmvDX)
442
+
443
+ ;; RV32D Standard Extension
444
+ (FsqrtD)
445
+ (FcvtSD)
446
+ (FcvtDS)
447
+ (FclassD)
448
+ (FcvtWD)
449
+ (FcvtWuD)
450
+ (FcvtDW)
451
+ (FcvtDWU)
452
+
453
+ ;; Zfa Extension
454
+ (FroundS)
455
+ (FroundD)
456
+ ))
457
+
458
+ (type LoadOP (enum
459
+ (Lb)
460
+ (Lh)
461
+ (Lw)
462
+ (Lbu)
463
+ (Lhu)
464
+ (Lwu)
465
+ (Ld)
466
+ (Flw)
467
+ (Fld)
468
+ ))
469
+
470
+ (type StoreOP (enum
471
+ (Sb)
472
+ (Sh)
473
+ (Sw)
474
+ (Sd)
475
+ (Fsw)
476
+ (Fsd)
477
+ ))
478
+
479
+ (type AluOPRRR (enum
480
+ ;; base set
481
+ (Add)
482
+ (Sub)
483
+ (Sll)
484
+ (Slt)
485
+ (SltU)
486
+ (Sgt)
487
+ (Sgtu)
488
+ (Xor)
489
+ (Srl)
490
+ (Sra)
491
+ (Or)
492
+ (And)
493
+
494
+ ;; RV64I Base Instruction Set (in addition to RV32I)
495
+ (Addw)
496
+ (Subw)
497
+ (Sllw)
498
+ (Srlw)
499
+ (Sraw)
500
+
501
+
502
+ ;;RV32M Standard Extension
503
+ (Mul)
504
+ (Mulh)
505
+ (Mulhsu)
506
+ (Mulhu)
507
+ (Div)
508
+ (DivU)
509
+ (Rem)
510
+ (RemU)
511
+
512
+ ;; RV64M Standard Extension (in addition to RV32M)
513
+ (Mulw)
514
+ (Divw)
515
+ (Divuw)
516
+ (Remw)
517
+ (Remuw)
518
+
519
+ ;; Zba: Address Generation Instructions
520
+ (Adduw)
521
+ (Sh1add)
522
+ (Sh1adduw)
523
+ (Sh2add)
524
+ (Sh2adduw)
525
+ (Sh3add)
526
+ (Sh3adduw)
527
+
528
+ ;; Zbb: Bit Manipulation Instructions
529
+ (Andn)
530
+ (Orn)
531
+ (Xnor)
532
+ (Max)
533
+ (Maxu)
534
+ (Min)
535
+ (Minu)
536
+ (Rol)
537
+ (Rolw)
538
+ (Ror)
539
+ (Rorw)
540
+
541
+ ;; Zbs: Single-bit instructions
542
+ (Bclr)
543
+ (Bext)
544
+ (Binv)
545
+ (Bset)
546
+
547
+ ;; Zbc: Carry-less multiplication
548
+ (Clmul)
549
+ (Clmulh)
550
+ (Clmulr)
551
+
552
+ ;; Zbkb: Bit-manipulation for Cryptography
553
+ (Pack)
554
+ (Packw)
555
+ (Packh)
556
+
557
+ ;; ZiCond: Integer Conditional Operations
558
+ (CzeroEqz)
559
+ (CzeroNez)
560
+ ))
561
+
562
+
563
+ (type FpuOPRRR (enum
564
+ ;; RV32F Standard Extension
565
+ (FaddS)
566
+ (FsubS)
567
+ (FmulS)
568
+ (FdivS)
569
+
570
+ (FsgnjS)
571
+ (FsgnjnS)
572
+ (FsgnjxS)
573
+ (FminS)
574
+ (FmaxS)
575
+ (FeqS)
576
+ (FltS)
577
+ (FleS)
578
+
579
+ ;; RV32D Standard Extension
580
+ (FaddD)
581
+ (FsubD)
582
+ (FmulD)
583
+ (FdivD)
584
+ (FsgnjD)
585
+ (FsgnjnD)
586
+ (FsgnjxD)
587
+ (FminD)
588
+ (FmaxD)
589
+ (FeqD)
590
+ (FltD)
591
+ (FleD)
592
+
593
+ ;; Zfa Extension
594
+ (FminmS)
595
+ (FmaxmS)
596
+ (FminmD)
597
+ (FmaxmD)
598
+ ))
599
+
600
+
601
+
602
+ (type AluOPRRI (enum
603
+ ;; Base ISA
604
+ (Addi)
605
+ (Slti)
606
+ (SltiU)
607
+ (Xori)
608
+ (Ori)
609
+ (Andi)
610
+ (Slli)
611
+ (Srli)
612
+ (Srai)
613
+ (Addiw)
614
+ (Slliw)
615
+ (SrliW)
616
+ (Sraiw)
617
+
618
+ ;; Zba: Address Generation Instructions
619
+ (SlliUw)
620
+
621
+ ;; Zbb: Bit Manipulation Instructions
622
+ (Clz)
623
+ (Clzw)
624
+ (Ctz)
625
+ (Ctzw)
626
+ (Cpop)
627
+ (Cpopw)
628
+ (Sextb)
629
+ (Sexth)
630
+ (Zexth)
631
+ (Rori)
632
+ (Roriw)
633
+ (Rev8)
634
+ (Brev8)
635
+ (Orcb)
636
+
637
+ ;; Zbs: Single-bit instructions
638
+ (Bclri)
639
+ (Bexti)
640
+ (Binvi)
641
+ (Bseti)
642
+ ))
643
+
644
+ (type COpcodeSpace (enum
645
+ (C0)
646
+ (C1)
647
+ (C2)
648
+ ))
649
+
650
+ ;; Opcodes for the CR compressed instruction format
651
+ (type CrOp (enum
652
+ (CMv)
653
+ (CAdd)
654
+ (CJr)
655
+ (CJalr)
656
+ ;; c.ebreak technically isn't a CR format instruction, but it's encoding
657
+ ;; lines up with this format.
658
+ (CEbreak)
659
+ ))
660
+
661
+ ;; Opcodes for the CA compressed instruction format
662
+ (type CaOp (enum
663
+ (CAnd)
664
+ (COr)
665
+ (CXor)
666
+ (CSub)
667
+ (CAddw)
668
+ (CSubw)
669
+ (CMul)
670
+ ))
671
+
672
+ ;; Opcodes for the CJ compressed instruction format
673
+ (type CjOp (enum
674
+ (CJ)
675
+ ))
676
+
677
+ ;; Opcodes for the CI compressed instruction format
678
+ (type CiOp (enum
679
+ (CAddi)
680
+ (CAddiw)
681
+ (CAddi16sp)
682
+ (CSlli)
683
+ (CLi)
684
+ (CLui)
685
+ (CLwsp)
686
+ (CLdsp)
687
+ (CFldsp)
688
+ ))
689
+
690
+ ;; Opcodes for the CIW compressed instruction format
691
+ (type CiwOp (enum
692
+ (CAddi4spn)
693
+ ))
694
+
695
+ ;; Opcodes for the CB compressed instruction format
696
+ (type CbOp (enum
697
+ (CSrli)
698
+ (CSrai)
699
+ (CAndi)
700
+ ))
701
+
702
+ ;; Opcodes for the CSS compressed instruction format
703
+ (type CssOp (enum
704
+ (CSwsp)
705
+ (CSdsp)
706
+ (CFsdsp)
707
+ ))
708
+
709
+ ;; Opcodes for the CS compressed instruction format
710
+ (type CsOp (enum
711
+ (CSw)
712
+ (CSd)
713
+ (CFsd)
714
+ ))
715
+
716
+ ;; Opcodes for the CL compressed instruction format
717
+ (type ClOp (enum
718
+ (CLw)
719
+ (CLd)
720
+ (CFld)
721
+ ))
722
+
723
+ ;; Opcodes for the CSZN compressed instruction format
724
+ (type CsznOp (enum
725
+ (CNot)
726
+ (CZextb)
727
+ (CZexth)
728
+ (CZextw)
729
+ (CSextb)
730
+ (CSexth)
731
+ ))
732
+
733
+ ;; This is a mix of all Zcb memory addressing instructions
734
+ ;;
735
+ ;; Technically they are split across 4 different formats.
736
+ ;; But they are all very similar, so we just group them all together.
737
+ (type ZcbMemOp (enum
738
+ (CLbu)
739
+ (CLhu)
740
+ (CLh)
741
+ (CSb)
742
+ (CSh)
743
+ ))
744
+
745
+
746
+ (type CsrRegOP (enum
747
+ ;; Atomic Read/Write CSR
748
+ (CsrRW)
749
+ ;; Atomic Read and Set Bits in CSR
750
+ (CsrRS)
751
+ ;; Atomic Read and Clear Bits in CSR
752
+ (CsrRC)
753
+ ))
754
+
755
+ (type CsrImmOP (enum
756
+ ;; Atomic Read/Write CSR (Immediate Source)
757
+ (CsrRWI)
758
+ ;; Atomic Read and Set Bits in CSR (Immediate Source)
759
+ (CsrRSI)
760
+ ;; Atomic Read and Clear Bits in CSR (Immediate Source)
761
+ (CsrRCI)
762
+ ))
763
+
764
+ ;; Enum of the known CSR registers
765
+ (type CSR (enum
766
+ ;; Floating-Point Dynamic Rounding Mode
767
+ (Frm)
768
+ ))
769
+
770
+
771
+ (type FRM (enum
772
+ ;; Round to Nearest, ties to Even
773
+ (RNE)
774
+ ;; Round towards Zero
775
+ (RTZ)
776
+ ;; Round Down (towards −∞)
777
+ (RDN)
778
+ ;; Round Up (towards +∞)
779
+ (RUP)
780
+ ;; Round to Nearest, ties to Max Magnitude
781
+ (RMM)
782
+ ;; In instruction’s rm field, selects dynamic rounding mode;
783
+ ;;In Rounding Mode register, Invalid.
784
+ (Fcsr)
785
+ ))
786
+
787
+ (decl pure frm_bits (FRM) UImm5)
788
+ (extern constructor frm_bits frm_bits)
789
+ (convert FRM UImm5 frm_bits)
790
+
791
+ (type FFlagsException (enum
792
+ ;; Invalid Operation
793
+ (NV)
794
+ ;; Divide by Zero
795
+ (DZ)
796
+ ;; Overflow
797
+ (OF)
798
+ ;; Underflow
799
+ (UF)
800
+ ;; Inexact
801
+ (NX)
802
+ ))
803
+
804
+ ;;;; input output read write
805
+ ;;;; SI SO SR SW
806
+ ;;;; PI PO PR PW
807
+ ;;;; lowest four bit are used.
808
+ (type FenceReq (primitive u8))
809
+
810
+ (type BoxCallInfo (primitive BoxCallInfo))
811
+ (type BoxCallIndInfo (primitive BoxCallIndInfo))
812
+ (type BoxReturnCallInfo (primitive BoxReturnCallInfo))
813
+ (type IntegerCompare (primitive IntegerCompare))
814
+ (type AMode (primitive AMode))
815
+ (type OptionReg (primitive OptionReg))
816
+ (type OptionImm12 (primitive OptionImm12))
817
+ (type OptionUimm5 (primitive OptionUimm5))
818
+ (type Imm12 (primitive Imm12))
819
+ (type UImm5 (primitive UImm5))
820
+ (type Imm5 (primitive Imm5))
821
+ (type Imm20 (primitive Imm20))
822
+ (type Imm3 (primitive Imm3))
823
+ (type CondBrTarget (primitive CondBrTarget))
824
+ (type VecU8 (primitive VecU8))
825
+ (type AMO (primitive AMO))
826
+ (type VecMachLabel extern (enum))
827
+
828
+
829
+ ;;;; Newtypes for Different Register Classes ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
830
+
831
+ (type XReg (primitive XReg))
832
+ (type WritableXReg (primitive WritableXReg))
833
+ (type FReg (primitive FReg))
834
+ (type WritableFReg (primitive WritableFReg))
835
+ (type VReg (primitive VReg))
836
+ (type WritableVReg (primitive WritableVReg))
837
+
838
+ ;; Construct a new `XReg` from a `Reg`.
839
+ ;;
840
+ ;; Asserts that the register has a Integer RegClass.
841
+ (decl xreg_new (Reg) XReg)
842
+ (extern constructor xreg_new xreg_new)
843
+ (convert Reg XReg xreg_new)
844
+
845
+ ;; Construct a new `WritableXReg` from a `WritableReg`.
846
+ ;;
847
+ ;; Asserts that the register has a Integer RegClass.
848
+ (decl writable_xreg_new (WritableReg) WritableXReg)
849
+ (extern constructor writable_xreg_new writable_xreg_new)
850
+ (convert WritableReg WritableXReg writable_xreg_new)
851
+
852
+ ;; Put a value into a XReg.
853
+ ;;
854
+ ;; Asserts that the value goes into a XReg.
855
+ (decl put_in_xreg (Value) XReg)
856
+ (rule (put_in_xreg val) (xreg_new (put_in_reg val)))
857
+ (convert Value XReg put_in_xreg)
858
+
859
+ ;; Construct an `InstOutput` out of a single XReg register.
860
+ (decl output_xreg (XReg) InstOutput)
861
+ (rule (output_xreg x) (output_reg x))
862
+ (convert XReg InstOutput output_xreg)
863
+
864
+ ;; Convert a `WritableXReg` to an `XReg`.
865
+ (decl pure writable_xreg_to_xreg (WritableXReg) XReg)
866
+ (extern constructor writable_xreg_to_xreg writable_xreg_to_xreg)
867
+ (convert WritableXReg XReg writable_xreg_to_xreg)
868
+
869
+ ;; Convert a `WritableXReg` to an `WritableReg`.
870
+ (decl pure writable_xreg_to_writable_reg (WritableXReg) WritableReg)
871
+ (extern constructor writable_xreg_to_writable_reg writable_xreg_to_writable_reg)
872
+ (convert WritableXReg WritableReg writable_xreg_to_writable_reg)
873
+
874
+ ;; Convert a `WritableXReg` to an `Reg`.
875
+ (decl pure writable_xreg_to_reg (WritableXReg) Reg)
876
+ (rule (writable_xreg_to_reg x) (writable_xreg_to_writable_reg x))
877
+ (convert WritableXReg Reg writable_xreg_to_reg)
878
+
879
+ ;; Convert an `XReg` to a `Reg`.
880
+ (decl pure xreg_to_reg (XReg) Reg)
881
+ (extern constructor xreg_to_reg xreg_to_reg)
882
+ (convert XReg Reg xreg_to_reg)
883
+
884
+ ;; Convert a `XReg` to a `ValueRegs`.
885
+ (decl xreg_to_value_regs (XReg) ValueRegs)
886
+ (rule (xreg_to_value_regs x) (value_reg x))
887
+ (convert XReg ValueRegs xreg_to_reg)
888
+
889
+ ;; Convert a `WritableXReg` to a `ValueRegs`.
890
+ (decl writable_xreg_to_value_regs (WritableXReg) ValueRegs)
891
+ (rule (writable_xreg_to_value_regs x) (value_reg x))
892
+ (convert WritableXReg ValueRegs writable_xreg_to_value_regs)
893
+
894
+ ;; Allocates a new `WritableXReg`.
895
+ (decl temp_writable_xreg () WritableXReg)
896
+ (rule (temp_writable_xreg) (temp_writable_reg $I64))
897
+
898
+
899
+ ;; Construct a new `FReg` from a `Reg`.
900
+ ;;
901
+ ;; Asserts that the register has a Float RegClass.
902
+ (decl freg_new (Reg) FReg)
903
+ (extern constructor freg_new freg_new)
904
+ (convert Reg FReg freg_new)
905
+
906
+ ;; Construct a new `WritableFReg` from a `WritableReg`.
907
+ ;;
908
+ ;; Asserts that the register has a Float RegClass.
909
+ (decl writable_freg_new (WritableReg) WritableFReg)
910
+ (extern constructor writable_freg_new writable_freg_new)
911
+ (convert WritableReg WritableFReg writable_freg_new)
912
+
913
+ ;; Put a value into a FReg.
914
+ ;;
915
+ ;; Asserts that the value goes into a FReg.
916
+ (decl put_in_freg (Value) FReg)
917
+ (rule (put_in_freg val) (freg_new (put_in_reg val)))
918
+ (convert Value FReg put_in_freg)
919
+
920
+ ;; Construct an `InstOutput` out of a single FReg register.
921
+ (decl output_freg (FReg) InstOutput)
922
+ (rule (output_freg x) (output_reg x))
923
+ (convert FReg InstOutput output_freg)
924
+
925
+ ;; Convert a `WritableFReg` to an `FReg`.
926
+ (decl pure writable_freg_to_freg (WritableFReg) FReg)
927
+ (extern constructor writable_freg_to_freg writable_freg_to_freg)
928
+ (convert WritableFReg FReg writable_freg_to_freg)
929
+
930
+ ;; Convert a `WritableFReg` to an `WritableReg`.
931
+ (decl pure writable_freg_to_writable_reg (WritableFReg) WritableReg)
932
+ (extern constructor writable_freg_to_writable_reg writable_freg_to_writable_reg)
933
+ (convert WritableFReg WritableReg writable_freg_to_writable_reg)
934
+
935
+ ;; Convert a `WritableFReg` to an `Reg`.
936
+ (decl pure writable_freg_to_reg (WritableFReg) Reg)
937
+ (rule (writable_freg_to_reg x) (writable_freg_to_writable_reg x))
938
+ (convert WritableFReg Reg writable_freg_to_reg)
939
+
940
+ ;; Convert an `FReg` to a `Reg`.
941
+ (decl pure freg_to_reg (FReg) Reg)
942
+ (extern constructor freg_to_reg freg_to_reg)
943
+ (convert FReg Reg freg_to_reg)
944
+
945
+ ;; Convert a `FReg` to a `ValueRegs`.
946
+ (decl freg_to_value_regs (FReg) ValueRegs)
947
+ (rule (freg_to_value_regs x) (value_reg x))
948
+ (convert FReg ValueRegs xreg_to_reg)
949
+
950
+ ;; Convert a `WritableFReg` to a `ValueRegs`.
951
+ (decl writable_freg_to_value_regs (WritableFReg) ValueRegs)
952
+ (rule (writable_freg_to_value_regs x) (value_reg x))
953
+ (convert WritableFReg ValueRegs writable_freg_to_value_regs)
954
+
955
+ ;; Allocates a new `WritableFReg`.
956
+ (decl temp_writable_freg () WritableFReg)
957
+ (rule (temp_writable_freg) (temp_writable_reg $F64))
958
+
959
+
960
+
961
+ ;; Construct a new `VReg` from a `Reg`.
962
+ ;;
963
+ ;; Asserts that the register has a Vector RegClass.
964
+ (decl vreg_new (Reg) VReg)
965
+ (extern constructor vreg_new vreg_new)
966
+ (convert Reg VReg vreg_new)
967
+
968
+ ;; Construct a new `WritableVReg` from a `WritableReg`.
969
+ ;;
970
+ ;; Asserts that the register has a Vector RegClass.
971
+ (decl writable_vreg_new (WritableReg) WritableVReg)
972
+ (extern constructor writable_vreg_new writable_vreg_new)
973
+ (convert WritableReg WritableVReg writable_vreg_new)
974
+
975
+ ;; Put a value into a VReg.
976
+ ;;
977
+ ;; Asserts that the value goes into a VReg.
978
+ (decl put_in_vreg (Value) VReg)
979
+ (rule (put_in_vreg val) (vreg_new (put_in_reg val)))
980
+ (convert Value VReg put_in_vreg)
981
+
982
+ ;; Construct an `InstOutput` out of a single VReg register.
983
+ (decl output_vreg (VReg) InstOutput)
984
+ (rule (output_vreg x) (output_reg x))
985
+ (convert VReg InstOutput output_vreg)
986
+
987
+ ;; Convert a `WritableVReg` to an `VReg`.
988
+ (decl pure writable_vreg_to_vreg (WritableVReg) VReg)
989
+ (extern constructor writable_vreg_to_vreg writable_vreg_to_vreg)
990
+ (convert WritableVReg VReg writable_vreg_to_vreg)
991
+
992
+ ;; Convert a `WritableVReg` to an `WritableReg`.
993
+ (decl pure writable_vreg_to_writable_reg (WritableVReg) WritableReg)
994
+ (extern constructor writable_vreg_to_writable_reg writable_vreg_to_writable_reg)
995
+ (convert WritableVReg WritableReg writable_vreg_to_writable_reg)
996
+
997
+ ;; Convert a `WritableVReg` to an `Reg`.
998
+ (decl pure writable_vreg_to_reg (WritableVReg) Reg)
999
+ (rule (writable_vreg_to_reg x) (writable_vreg_to_writable_reg x))
1000
+ (convert WritableVReg Reg writable_vreg_to_reg)
1001
+
1002
+ ;; Convert an `VReg` to a `Reg`.
1003
+ (decl pure vreg_to_reg (VReg) Reg)
1004
+ (extern constructor vreg_to_reg vreg_to_reg)
1005
+ (convert VReg Reg vreg_to_reg)
1006
+
1007
+ ;; Convert a `VReg` to a `ValueRegs`.
1008
+ (decl vreg_to_value_regs (VReg) ValueRegs)
1009
+ (rule (vreg_to_value_regs x) (value_reg x))
1010
+ (convert VReg ValueRegs xreg_to_reg)
1011
+
1012
+ ;; Convert a `WritableVReg` to a `ValueRegs`.
1013
+ (decl writable_vreg_to_value_regs (WritableVReg) ValueRegs)
1014
+ (rule (writable_vreg_to_value_regs x) (value_reg x))
1015
+ (convert WritableVReg ValueRegs writable_vreg_to_value_regs)
1016
+
1017
+ ;; Allocates a new `WritableVReg`.
1018
+ (decl temp_writable_vreg () WritableVReg)
1019
+ (rule (temp_writable_vreg) (temp_writable_reg $I8X16))
1020
+
1021
+
1022
+ ;; Converters
1023
+
1024
+ (convert u8 i32 u8_as_i32)
1025
+ (decl u8_as_i32 (u8) i32)
1026
+ (extern constructor u8_as_i32 u8_as_i32)
1027
+
1028
+ ;; ISA Extension helpers
1029
+
1030
+ (decl pure has_m () bool)
1031
+ (extern constructor has_m has_m)
1032
+
1033
+ (decl pure has_v () bool)
1034
+ (extern constructor has_v has_v)
1035
+
1036
+ (decl pure has_zfa () bool)
1037
+ (extern constructor has_zfa has_zfa)
1038
+
1039
+ (decl pure has_zbkb () bool)
1040
+ (extern constructor has_zbkb has_zbkb)
1041
+
1042
+ (decl pure has_zba () bool)
1043
+ (extern constructor has_zba has_zba)
1044
+
1045
+ (decl pure has_zbb () bool)
1046
+ (extern constructor has_zbb has_zbb)
1047
+
1048
+ (decl pure has_zbc () bool)
1049
+ (extern constructor has_zbc has_zbc)
1050
+
1051
+ (decl pure has_zbs () bool)
1052
+ (extern constructor has_zbs has_zbs)
1053
+
1054
+ (decl pure has_zicond () bool)
1055
+ (extern constructor has_zicond has_zicond)
1056
+
1057
+
1058
+ ;;;; Instruction Helpers ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1059
+
1060
+ ;; RV32I Base Integer Instruction Set
1061
+
1062
+ ;; Helper for emitting the `add` instruction.
1063
+ ;; rd ← rs1 + rs2
1064
+ (decl rv_add (XReg XReg) XReg)
1065
+ (rule (rv_add rs1 rs2)
1066
+ (alu_rrr (AluOPRRR.Add) rs1 rs2))
1067
+
1068
+ ;; Helper for emitting the `addi` ("Add Immediate") instruction.
1069
+ ;; rd ← rs1 + sext(imm)
1070
+ (decl rv_addi (XReg Imm12) XReg)
1071
+ (rule (rv_addi rs1 imm)
1072
+ (alu_rr_imm12 (AluOPRRI.Addi) rs1 imm))
1073
+
1074
+ ;; Helper for emitting the `sub` instruction.
1075
+ ;; rd ← rs1 - rs2
1076
+ (decl rv_sub (XReg XReg) XReg)
1077
+ (rule (rv_sub rs1 rs2)
1078
+ (alu_rrr (AluOPRRR.Sub) rs1 rs2))
1079
+
1080
+ ;; Helper for emitting the `neg` instruction.
1081
+ ;; This instruction is a mnemonic for `sub rd, zero, rs1`.
1082
+ (decl rv_neg (XReg) XReg)
1083
+ (rule (rv_neg rs1)
1084
+ (alu_rrr (AluOPRRR.Sub) (zero_reg) rs1))
1085
+
1086
+ ;; Helper for emitting the `sll` ("Shift Left Logical") instruction.
1087
+ ;; rd ← rs1 << rs2
1088
+ (decl rv_sll (XReg XReg) XReg)
1089
+ (rule (rv_sll rs1 rs2)
1090
+ (alu_rrr (AluOPRRR.Sll) rs1 rs2))
1091
+
1092
+ ;; Helper for emitting the `slli` ("Shift Left Logical Immediate") instruction.
1093
+ ;; rd ← rs1 << uext(imm)
1094
+ (decl rv_slli (XReg Imm12) XReg)
1095
+ (rule (rv_slli rs1 imm)
1096
+ (alu_rr_imm12 (AluOPRRI.Slli) rs1 imm))
1097
+
1098
+ ;; Helper for emitting the `srl` ("Shift Right Logical") instruction.
1099
+ ;; rd ← rs1 >> rs2
1100
+ (decl rv_srl (XReg XReg) XReg)
1101
+ (rule (rv_srl rs1 rs2)
1102
+ (alu_rrr (AluOPRRR.Srl) rs1 rs2))
1103
+
1104
+ ;; Helper for emitting the `srli` ("Shift Right Logical Immediate") instruction.
1105
+ ;; rd ← rs1 >> uext(imm)
1106
+ (decl rv_srli (XReg Imm12) XReg)
1107
+ (rule (rv_srli rs1 imm)
1108
+ (alu_rr_imm12 (AluOPRRI.Srli) rs1 imm))
1109
+
1110
+ ;; Helper for emitting the `sra` ("Shift Right Arithmetic") instruction.
1111
+ ;; rd ← rs1 >> rs2
1112
+ (decl rv_sra (XReg XReg) XReg)
1113
+ (rule (rv_sra rs1 rs2)
1114
+ (alu_rrr (AluOPRRR.Sra) rs1 rs2))
1115
+
1116
+ ;; Helper for emitting the `srai` ("Shift Right Arithmetic Immediate") instruction.
1117
+ ;; rd ← rs1 >> uext(imm)
1118
+ (decl rv_srai (XReg Imm12) XReg)
1119
+ (rule (rv_srai rs1 imm)
1120
+ (alu_rr_imm12 (AluOPRRI.Srai) rs1 imm))
1121
+
1122
+ ;; Helper for emitting the `or` instruction.
1123
+ ;; rd ← rs1 ∨ rs2
1124
+ (decl rv_or (XReg XReg) XReg)
1125
+ (rule (rv_or rs1 rs2)
1126
+ (alu_rrr (AluOPRRR.Or) rs1 rs2))
1127
+
1128
+ ;; Helper for emitting the `ori` ("Or Immediate") instruction.
1129
+ ;; rd ← rs1 ∨ uext(imm)
1130
+ (decl rv_ori (XReg Imm12) XReg)
1131
+ (rule (rv_ori rs1 imm)
1132
+ (alu_rr_imm12 (AluOPRRI.Ori) rs1 imm))
1133
+
1134
+ ;; Helper for emitting the `xor` instruction.
1135
+ ;; rd ← rs1 ⊕ rs2
1136
+ (decl rv_xor (XReg XReg) XReg)
1137
+ (rule (rv_xor rs1 rs2)
1138
+ (alu_rrr (AluOPRRR.Xor) rs1 rs2))
1139
+
1140
+ ;; Helper for emitting the `xori` ("Exclusive Or Immediate") instruction.
1141
+ ;; rd ← rs1 ⊕ uext(imm)
1142
+ (decl rv_xori (XReg Imm12) XReg)
1143
+ (rule (rv_xori rs1 imm)
1144
+ (alu_rr_imm12 (AluOPRRI.Xori) rs1 imm))
1145
+
1146
+ ;; Helper for emitting the `not` instruction.
1147
+ ;; This instruction is a mnemonic for `xori rd, rs1, -1`.
1148
+ (decl rv_not (XReg) XReg)
1149
+ (rule (rv_not rs1)
1150
+ (rv_xori rs1 (imm12_const -1)))
1151
+
1152
+ ;; Helper for emitting the `and` instruction.
1153
+ ;; rd ← rs1 ∧ rs2
1154
+ (decl rv_and (XReg XReg) XReg)
1155
+ (rule (rv_and rs1 rs2)
1156
+ (alu_rrr (AluOPRRR.And) rs1 rs2))
1157
+
1158
+ ;; Helper for emitting the `andi` ("And Immediate") instruction.
1159
+ ;; rd ← rs1 ∧ uext(imm)
1160
+ (decl rv_andi (XReg Imm12) XReg)
1161
+ (rule (rv_andi rs1 imm)
1162
+ (alu_rr_imm12 (AluOPRRI.Andi) rs1 imm))
1163
+
1164
+ ;; Helper for emitting the `slt` ("Set Less Than") instruction.
1165
+ ;; rd ← rs1 < rs2
1166
+ (decl rv_slt (XReg XReg) XReg)
1167
+ (rule (rv_slt rs1 rs2)
1168
+ (alu_rrr (AluOPRRR.Slt) rs1 rs2))
1169
+
1170
+ ;; Helper for emitting the `sltu` ("Set Less Than Unsigned") instruction.
1171
+ ;; rd ← rs1 < rs2
1172
+ (decl rv_sltu (XReg XReg) XReg)
1173
+ (rule (rv_sltu rs1 rs2)
1174
+ (alu_rrr (AluOPRRR.SltU) rs1 rs2))
1175
+
1176
+ ;; Helper for emitting the `snez` instruction.
1177
+ ;; This instruction is a mnemonic for `sltu rd, zero, rs`.
1178
+ (decl rv_snez (XReg) XReg)
1179
+ (rule (rv_snez rs1)
1180
+ (rv_sltu (zero_reg) rs1))
1181
+
1182
+ ;; Helper for emitting the `slti` ("Set Less Than Immediate") instruction.
1183
+ ;; rd ← rs1 < imm
1184
+ (decl rv_slti (XReg Imm12) XReg)
1185
+ (rule (rv_slti rs1 imm)
1186
+ (alu_rr_imm12 (AluOPRRI.Slti) rs1 imm))
1187
+
1188
+ ;; Helper for emitting the `sltiu` ("Set Less Than Immediate Unsigned") instruction.
1189
+ ;; rd ← rs1 < imm
1190
+ (decl rv_sltiu (XReg Imm12) XReg)
1191
+ (rule (rv_sltiu rs1 imm)
1192
+ (alu_rr_imm12 (AluOPRRI.SltiU) rs1 imm))
1193
+
1194
+ ;; Helper for emitting the `seqz` instruction.
1195
+ ;; This instruction is a mnemonic for `sltiu rd, rs, 1`.
1196
+ (decl rv_seqz (XReg) XReg)
1197
+ (rule (rv_seqz rs1)
1198
+ (rv_sltiu rs1 (imm12_const 1)))
1199
+
1200
+
1201
+ ;; RV64I Base Integer Instruction Set
1202
+ ;; Unlike RV32I instructions these are only present in the 64bit ISA
1203
+
1204
+ ;; Helper for emitting the `addw` ("Add Word") instruction.
1205
+ ;; rd ← sext32(rs1) + sext32(rs2)
1206
+ (decl rv_addw (XReg XReg) XReg)
1207
+ (rule (rv_addw rs1 rs2)
1208
+ (alu_rrr (AluOPRRR.Addw) rs1 rs2))
1209
+
1210
+ ;; Helper for emitting the `addiw` ("Add Word Immediate") instruction.
1211
+ ;; rd ← sext32(rs1) + imm
1212
+ (decl rv_addiw (XReg Imm12) XReg)
1213
+ (rule (rv_addiw rs1 imm)
1214
+ (alu_rr_imm12 (AluOPRRI.Addiw) rs1 imm))
1215
+
1216
+ ;; Helper for emitting the `sext.w` ("Sign Extend Word") instruction.
1217
+ ;; This instruction is a mnemonic for `addiw rd, rs, zero`.
1218
+ (decl rv_sextw (XReg) XReg)
1219
+ (rule (rv_sextw rs1)
1220
+ (rv_addiw rs1 (imm12_const 0)))
1221
+
1222
+ ;; Helper for emitting the `subw` ("Subtract Word") instruction.
1223
+ ;; rd ← sext32(rs1) - sext32(rs2)
1224
+ (decl rv_subw (XReg XReg) XReg)
1225
+ (rule (rv_subw rs1 rs2)
1226
+ (alu_rrr (AluOPRRR.Subw) rs1 rs2))
1227
+
1228
+ ;; Helper for emitting the `sllw` ("Shift Left Logical Word") instruction.
1229
+ ;; rd ← sext32(uext32(rs1) << rs2)
1230
+ (decl rv_sllw (XReg XReg) XReg)
1231
+ (rule (rv_sllw rs1 rs2)
1232
+ (alu_rrr (AluOPRRR.Sllw) rs1 rs2))
1233
+
1234
+ ;; Helper for emitting the `slliw` ("Shift Left Logical Immediate Word") instruction.
1235
+ ;; rd ← sext32(uext32(rs1) << imm)
1236
+ (decl rv_slliw (XReg Imm12) XReg)
1237
+ (rule (rv_slliw rs1 imm)
1238
+ (alu_rr_imm12 (AluOPRRI.Slliw) rs1 imm))
1239
+
1240
+ ;; Helper for emitting the `srlw` ("Shift Right Logical Word") instruction.
1241
+ ;; rd ← sext32(uext32(rs1) >> rs2)
1242
+ (decl rv_srlw (XReg XReg) XReg)
1243
+ (rule (rv_srlw rs1 rs2)
1244
+ (alu_rrr (AluOPRRR.Srlw) rs1 rs2))
1245
+
1246
+ ;; Helper for emitting the `srliw` ("Shift Right Logical Immediate Word") instruction.
1247
+ ;; rd ← sext32(uext32(rs1) >> imm)
1248
+ (decl rv_srliw (XReg Imm12) XReg)
1249
+ (rule (rv_srliw rs1 imm)
1250
+ (alu_rr_imm12 (AluOPRRI.SrliW) rs1 imm))
1251
+
1252
+ ;; Helper for emitting the `sraw` ("Shift Right Arithmetic Word") instruction.
1253
+ ;; rd ← sext32(rs1 >> rs2)
1254
+ (decl rv_sraw (XReg XReg) XReg)
1255
+ (rule (rv_sraw rs1 rs2)
1256
+ (alu_rrr (AluOPRRR.Sraw) rs1 rs2))
1257
+
1258
+ ;; Helper for emitting the `sraiw` ("Shift Right Arithmetic Immediate Word") instruction.
1259
+ ;; rd ← sext32(rs1 >> imm)
1260
+ (decl rv_sraiw (XReg Imm12) XReg)
1261
+ (rule (rv_sraiw rs1 imm)
1262
+ (alu_rr_imm12 (AluOPRRI.Sraiw) rs1 imm))
1263
+
1264
+
1265
+ ;; RV32M Extension
1266
+ ;; TODO: Enable these instructions only when we have the M extension
1267
+
1268
+ ;; Helper for emitting the `mul` instruction.
1269
+ ;; rd ← rs1 × rs2
1270
+ (decl rv_mul (XReg XReg) XReg)
1271
+ (rule (rv_mul rs1 rs2)
1272
+ (alu_rrr (AluOPRRR.Mul) rs1 rs2))
1273
+
1274
+ ;; Helper for emitting the `mulh` ("Multiply High Signed Signed") instruction.
1275
+ ;; rd ← (sext(rs1) × sext(rs2)) » xlen
1276
+ (decl rv_mulh (XReg XReg) XReg)
1277
+ (rule (rv_mulh rs1 rs2)
1278
+ (alu_rrr (AluOPRRR.Mulh) rs1 rs2))
1279
+
1280
+ ;; Helper for emitting the `mulhu` ("Multiply High Unsigned Unsigned") instruction.
1281
+ ;; rd ← (uext(rs1) × uext(rs2)) » xlen
1282
+ (decl rv_mulhu (XReg XReg) XReg)
1283
+ (rule (rv_mulhu rs1 rs2)
1284
+ (alu_rrr (AluOPRRR.Mulhu) rs1 rs2))
1285
+
1286
+ ;; Helper for emitting the `div` instruction.
1287
+ ;; rd ← rs1 ÷ rs2
1288
+ (decl rv_div (XReg XReg) XReg)
1289
+ (rule (rv_div rs1 rs2)
1290
+ (alu_rrr (AluOPRRR.Div) rs1 rs2))
1291
+
1292
+ ;; Helper for emitting the `divu` ("Divide Unsigned") instruction.
1293
+ ;; rd ← rs1 ÷ rs2
1294
+ (decl rv_divu (XReg XReg) XReg)
1295
+ (rule (rv_divu rs1 rs2)
1296
+ (alu_rrr (AluOPRRR.DivU) rs1 rs2))
1297
+
1298
+ ;; Helper for emitting the `rem` instruction.
1299
+ ;; rd ← rs1 mod rs2
1300
+ (decl rv_rem (XReg XReg) XReg)
1301
+ (rule (rv_rem rs1 rs2)
1302
+ (alu_rrr (AluOPRRR.Rem) rs1 rs2))
1303
+
1304
+ ;; Helper for emitting the `remu` ("Remainder Unsigned") instruction.
1305
+ ;; rd ← rs1 mod rs2
1306
+ (decl rv_remu (XReg XReg) XReg)
1307
+ (rule (rv_remu rs1 rs2)
1308
+ (alu_rrr (AluOPRRR.RemU) rs1 rs2))
1309
+
1310
+ ;; RV64M Extension
1311
+ ;; TODO: Enable these instructions only when we have the M extension
1312
+
1313
+ ;; Helper for emitting the `mulw` ("Multiply Word") instruction.
1314
+ ;; rd ← uext32(rs1) × uext32(rs2)
1315
+ (decl rv_mulw (XReg XReg) XReg)
1316
+ (rule (rv_mulw rs1 rs2)
1317
+ (alu_rrr (AluOPRRR.Mulw) rs1 rs2))
1318
+
1319
+ ;; Helper for emitting the `divw` ("Divide Word") instruction.
1320
+ ;; rd ← sext32(rs1) ÷ sext32(rs2)
1321
+ (decl rv_divw (XReg XReg) XReg)
1322
+ (rule (rv_divw rs1 rs2)
1323
+ (alu_rrr (AluOPRRR.Divw) rs1 rs2))
1324
+
1325
+ ;; Helper for emitting the `divuw` ("Divide Unsigned Word") instruction.
1326
+ ;; rd ← uext32(rs1) ÷ uext32(rs2)
1327
+ (decl rv_divuw (XReg XReg) XReg)
1328
+ (rule (rv_divuw rs1 rs2)
1329
+ (alu_rrr (AluOPRRR.Divuw) rs1 rs2))
1330
+
1331
+ ;; Helper for emitting the `remw` ("Remainder Word") instruction.
1332
+ ;; rd ← sext32(rs1) mod sext32(rs2)
1333
+ (decl rv_remw (XReg XReg) XReg)
1334
+ (rule (rv_remw rs1 rs2)
1335
+ (alu_rrr (AluOPRRR.Remw) rs1 rs2))
1336
+
1337
+ ;; Helper for emitting the `remuw` ("Remainder Unsigned Word") instruction.
1338
+ ;; rd ← uext32(rs1) mod uext32(rs2)
1339
+ (decl rv_remuw (XReg XReg) XReg)
1340
+ (rule (rv_remuw rs1 rs2)
1341
+ (alu_rrr (AluOPRRR.Remuw) rs1 rs2))
1342
+
1343
+
1344
+ ;; F and D Extensions
1345
+ ;; TODO: Enable these instructions only when we have the F or D extensions
1346
+
1347
+ ;; Helper for emitting the `fadd` instruction.
1348
+ (decl rv_fadd (Type FRM FReg FReg) FReg)
1349
+ (rule (rv_fadd $F32 frm rs1 rs2) (fpu_rrr (FpuOPRRR.FaddS) $F32 frm rs1 rs2))
1350
+ (rule (rv_fadd $F64 frm rs1 rs2) (fpu_rrr (FpuOPRRR.FaddD) $F64 frm rs1 rs2))
1351
+
1352
+ ;; Helper for emitting the `fsub` instruction.
1353
+ (decl rv_fsub (Type FRM FReg FReg) FReg)
1354
+ (rule (rv_fsub $F32 frm rs1 rs2) (fpu_rrr (FpuOPRRR.FsubS) $F32 frm rs1 rs2))
1355
+ (rule (rv_fsub $F64 frm rs1 rs2) (fpu_rrr (FpuOPRRR.FsubD) $F64 frm rs1 rs2))
1356
+
1357
+ ;; Helper for emitting the `fmul` instruction.
1358
+ (decl rv_fmul (Type FRM FReg FReg) FReg)
1359
+ (rule (rv_fmul $F32 frm rs1 rs2) (fpu_rrr (FpuOPRRR.FmulS) $F32 frm rs1 rs2))
1360
+ (rule (rv_fmul $F64 frm rs1 rs2) (fpu_rrr (FpuOPRRR.FmulD) $F64 frm rs1 rs2))
1361
+
1362
+ ;; Helper for emitting the `fdiv` instruction.
1363
+ (decl rv_fdiv (Type FRM FReg FReg) FReg)
1364
+ (rule (rv_fdiv $F32 frm rs1 rs2) (fpu_rrr (FpuOPRRR.FdivS) $F32 frm rs1 rs2))
1365
+ (rule (rv_fdiv $F64 frm rs1 rs2) (fpu_rrr (FpuOPRRR.FdivD) $F64 frm rs1 rs2))
1366
+
1367
+ ;; Helper for emitting the `fsqrt` instruction.
1368
+ (decl rv_fsqrt (Type FRM FReg) FReg)
1369
+ (rule (rv_fsqrt $F32 frm rs1) (fpu_rr (FpuOPRR.FsqrtS) $F32 frm rs1))
1370
+ (rule (rv_fsqrt $F64 frm rs1) (fpu_rr (FpuOPRR.FsqrtD) $F64 frm rs1))
1371
+
1372
+ ;; Helper for emitting the `fmadd` instruction.
1373
+ (decl rv_fmadd (Type FRM FReg FReg FReg) FReg)
1374
+ (rule (rv_fmadd $F32 frm rs1 rs2 rs3) (fpu_rrrr (FpuOPRRRR.FmaddS) $F32 frm rs1 rs2 rs3))
1375
+ (rule (rv_fmadd $F64 frm rs1 rs2 rs3) (fpu_rrrr (FpuOPRRRR.FmaddD) $F64 frm rs1 rs2 rs3))
1376
+
1377
+ ;; Helper for emitting the `fmsub` instruction.
1378
+ (decl rv_fmsub (Type FRM FReg FReg FReg) FReg)
1379
+ (rule (rv_fmsub $F32 frm rs1 rs2 rs3) (fpu_rrrr (FpuOPRRRR.FmsubS) $F32 frm rs1 rs2 rs3))
1380
+ (rule (rv_fmsub $F64 frm rs1 rs2 rs3) (fpu_rrrr (FpuOPRRRR.FmsubD) $F64 frm rs1 rs2 rs3))
1381
+
1382
+ ;; Helper for emitting the `fnmadd` instruction.
1383
+ (decl rv_fnmadd (Type FRM FReg FReg FReg) FReg)
1384
+ (rule (rv_fnmadd $F32 frm rs1 rs2 rs3) (fpu_rrrr (FpuOPRRRR.FnmaddS) $F32 frm rs1 rs2 rs3))
1385
+ (rule (rv_fnmadd $F64 frm rs1 rs2 rs3) (fpu_rrrr (FpuOPRRRR.FnmaddD) $F64 frm rs1 rs2 rs3))
1386
+
1387
+ ;; Helper for emitting the `fnmsub` instruction.
1388
+ (decl rv_fnmsub (Type FRM FReg FReg FReg) FReg)
1389
+ (rule (rv_fnmsub $F32 frm rs1 rs2 rs3) (fpu_rrrr (FpuOPRRRR.FnmsubS) $F32 frm rs1 rs2 rs3))
1390
+ (rule (rv_fnmsub $F64 frm rs1 rs2 rs3) (fpu_rrrr (FpuOPRRRR.FnmsubD) $F64 frm rs1 rs2 rs3))
1391
+
1392
+ ;; Helper for emitting the `fmv.x.w` instruction.
1393
+ (decl rv_fmvxw (FReg) XReg)
1394
+ (rule (rv_fmvxw r) (fpu_rr (FpuOPRR.FmvXW) $I32 (FRM.RNE) r))
1395
+
1396
+ ;; Helper for emitting the `fmv.x.d` instruction.
1397
+ (decl rv_fmvxd (FReg) XReg)
1398
+ (rule (rv_fmvxd r) (fpu_rr (FpuOPRR.FmvXD) $I64 (FRM.RNE) r))
1399
+
1400
+ ;; Helper for emitting the `fmv.w.x` instruction.
1401
+ (decl rv_fmvwx (XReg) FReg)
1402
+ (rule (rv_fmvwx r) (fpu_rr (FpuOPRR.FmvWX) $F32 (FRM.RNE) r))
1403
+
1404
+ ;; Helper for emitting the `fmv.d.x` instruction.
1405
+ (decl rv_fmvdx (XReg) FReg)
1406
+ (rule (rv_fmvdx r) (fpu_rr (FpuOPRR.FmvDX) $F64 (FRM.RNE) r))
1407
+
1408
+ ;; Helper for emitting the `fcvt.d.s` ("Float Convert Double to Single") instruction.
1409
+ (decl rv_fcvtds (FReg) FReg)
1410
+ (rule (rv_fcvtds rs1) (fpu_rr (FpuOPRR.FcvtDS) $F32 (FRM.RNE) rs1))
1411
+
1412
+ ;; Helper for emitting the `fcvt.s.d` ("Float Convert Single to Double") instruction.
1413
+ (decl rv_fcvtsd (FRM FReg) FReg)
1414
+ (rule (rv_fcvtsd frm rs1) (fpu_rr (FpuOPRR.FcvtSD) $F64 frm rs1))
1415
+
1416
+ ;; Helper for emitting the `fcvt.s.w` instruction.
1417
+ (decl rv_fcvtsw (FRM XReg) FReg)
1418
+ (rule (rv_fcvtsw frm rs1) (fpu_rr (FpuOPRR.FcvtSw) $F32 frm rs1))
1419
+
1420
+ ;; Helper for emitting the `fcvt.s.wu` instruction.
1421
+ (decl rv_fcvtswu (FRM XReg) FReg)
1422
+ (rule (rv_fcvtswu frm rs1) (fpu_rr (FpuOPRR.FcvtSwU) $F32 frm rs1))
1423
+
1424
+ ;; Helper for emitting the `fcvt.d.w` instruction.
1425
+ (decl rv_fcvtdw (XReg) FReg)
1426
+ (rule (rv_fcvtdw rs1) (fpu_rr (FpuOPRR.FcvtDW) $F32 (FRM.RNE) rs1))
1427
+
1428
+ ;; Helper for emitting the `fcvt.d.wu` instruction.
1429
+ (decl rv_fcvtdwu (XReg) FReg)
1430
+ (rule (rv_fcvtdwu rs1) (fpu_rr (FpuOPRR.FcvtDWU) $F32 (FRM.RNE) rs1))
1431
+
1432
+ ;; Helper for emitting the `fcvt.s.l` instruction.
1433
+ (decl rv_fcvtsl (FRM XReg) FReg)
1434
+ (rule (rv_fcvtsl frm rs1) (fpu_rr (FpuOPRR.FcvtSL) $F32 frm rs1))
1435
+
1436
+ ;; Helper for emitting the `fcvt.s.lu` instruction.
1437
+ (decl rv_fcvtslu (FRM XReg) FReg)
1438
+ (rule (rv_fcvtslu frm rs1) (fpu_rr (FpuOPRR.FcvtSLU) $F32 frm rs1))
1439
+
1440
+ ;; Helper for emitting the `fcvt.d.l` instruction.
1441
+ (decl rv_fcvtdl (FRM XReg) FReg)
1442
+ (rule (rv_fcvtdl frm rs1) (fpu_rr (FpuOPRR.FcvtDL) $F32 frm rs1))
1443
+
1444
+ ;; Helper for emitting the `fcvt.d.lu` instruction.
1445
+ (decl rv_fcvtdlu (FRM XReg) FReg)
1446
+ (rule (rv_fcvtdlu frm rs1) (fpu_rr (FpuOPRR.FcvtDLu) $F32 frm rs1))
1447
+
1448
+ ;; Helper for emitting the `fcvt.w.s` instruction.
1449
+ (decl rv_fcvtws (FRM FReg) XReg)
1450
+ (rule (rv_fcvtws frm rs1) (fpu_rr (FpuOPRR.FcvtWS) $I64 frm rs1))
1451
+
1452
+ ;; Helper for emitting the `fcvt.l.s` instruction.
1453
+ (decl rv_fcvtls (FRM FReg) XReg)
1454
+ (rule (rv_fcvtls frm rs1) (fpu_rr (FpuOPRR.FcvtLS) $I64 frm rs1))
1455
+
1456
+ ;; Helper for emitting the `fcvt.wu.s` instruction.
1457
+ (decl rv_fcvtwus (FRM FReg) XReg)
1458
+ (rule (rv_fcvtwus frm rs1) (fpu_rr (FpuOPRR.FcvtWuS) $I64 frm rs1))
1459
+
1460
+ ;; Helper for emitting the `fcvt.lu.s` instruction.
1461
+ (decl rv_fcvtlus (FRM FReg) XReg)
1462
+ (rule (rv_fcvtlus frm rs1) (fpu_rr (FpuOPRR.FcvtLuS) $I64 frm rs1))
1463
+
1464
+ ;; Helper for emitting the `fcvt.w.d` instruction.
1465
+ (decl rv_fcvtwd (FRM FReg) XReg)
1466
+ (rule (rv_fcvtwd frm rs1) (fpu_rr (FpuOPRR.FcvtWD) $I64 frm rs1))
1467
+
1468
+ ;; Helper for emitting the `fcvt.l.d` instruction.
1469
+ (decl rv_fcvtld (FRM FReg) XReg)
1470
+ (rule (rv_fcvtld frm rs1) (fpu_rr (FpuOPRR.FcvtLD) $I64 frm rs1))
1471
+
1472
+ ;; Helper for emitting the `fcvt.wu.d` instruction.
1473
+ (decl rv_fcvtwud (FRM FReg) XReg)
1474
+ (rule (rv_fcvtwud frm rs1) (fpu_rr (FpuOPRR.FcvtWuD) $I64 frm rs1))
1475
+
1476
+ ;; Helper for emitting the `fcvt.lu.d` instruction.
1477
+ (decl rv_fcvtlud (FRM FReg) XReg)
1478
+ (rule (rv_fcvtlud frm rs1) (fpu_rr (FpuOPRR.FcvtLuD) $I64 frm rs1))
1479
+
1480
+ ;; Helper for emitting the `fcvt.w.*` instructions.
1481
+ (decl rv_fcvtw (Type FRM FReg) XReg)
1482
+ (rule (rv_fcvtw $F32 frm rs1) (rv_fcvtws frm rs1))
1483
+ (rule (rv_fcvtw $F64 frm rs1) (rv_fcvtwd frm rs1))
1484
+
1485
+ ;; Helper for emitting the `fcvt.l.*` instructions.
1486
+ (decl rv_fcvtl (Type FRM FReg) XReg)
1487
+ (rule (rv_fcvtl $F32 frm rs1) (rv_fcvtls frm rs1))
1488
+ (rule (rv_fcvtl $F64 frm rs1) (rv_fcvtld frm rs1))
1489
+
1490
+ ;; Helper for emitting the `fcvt.wu.*` instructions.
1491
+ (decl rv_fcvtwu (Type FRM FReg) XReg)
1492
+ (rule (rv_fcvtwu $F32 frm rs1) (rv_fcvtwus frm rs1))
1493
+ (rule (rv_fcvtwu $F64 frm rs1) (rv_fcvtwud frm rs1))
1494
+
1495
+ ;; Helper for emitting the `fcvt.lu.*` instructions.
1496
+ (decl rv_fcvtlu (Type FRM FReg) XReg)
1497
+ (rule (rv_fcvtlu $F32 frm rs1) (rv_fcvtlus frm rs1))
1498
+ (rule (rv_fcvtlu $F64 frm rs1) (rv_fcvtlud frm rs1))
1499
+
1500
+ ;; Helper for emitting the `fsgnj` ("Floating Point Sign Injection") instruction.
1501
+ ;; The output of this instruction is `rs1` with the sign bit from `rs2`
1502
+ ;; This implements the `copysign` operation
1503
+ (decl rv_fsgnj (Type FReg FReg) FReg)
1504
+ (rule (rv_fsgnj $F32 rs1 rs2) (fpu_rrr (FpuOPRRR.FsgnjS) $F32 (FRM.RNE) rs1 rs2))
1505
+ (rule (rv_fsgnj $F64 rs1 rs2) (fpu_rrr (FpuOPRRR.FsgnjD) $F64 (FRM.RNE) rs1 rs2))
1506
+
1507
+ ;; Helper for emitting the `fsgnjn` ("Floating Point Sign Injection Negated") instruction.
1508
+ ;; The output of this instruction is `rs1` with the negated sign bit from `rs2`
1509
+ ;; When `rs1 == rs2` this implements the `neg` operation
1510
+ (decl rv_fsgnjn (Type FReg FReg) FReg)
1511
+ (rule (rv_fsgnjn $F32 rs1 rs2) (fpu_rrr (FpuOPRRR.FsgnjnS) $F32 (FRM.RTZ) rs1 rs2))
1512
+ (rule (rv_fsgnjn $F64 rs1 rs2) (fpu_rrr (FpuOPRRR.FsgnjnD) $F64 (FRM.RTZ) rs1 rs2))
1513
+
1514
+ ;; Helper for emitting the `fneg` ("Floating Point Negate") instruction.
1515
+ ;; This instruction is a mnemonic for `fsgnjn rd, rs1, rs1`
1516
+ (decl rv_fneg (Type FReg) FReg)
1517
+ (rule (rv_fneg ty rs1) (rv_fsgnjn ty rs1 rs1))
1518
+
1519
+ ;; Helper for emitting the `fsgnjx` ("Floating Point Sign Injection Exclusive") instruction.
1520
+ ;; The output of this instruction is `rs1` with the XOR of the sign bits from `rs1` and `rs2`.
1521
+ ;; When `rs1 == rs2` this implements `fabs`
1522
+ (decl rv_fsgnjx (Type FReg FReg) FReg)
1523
+ (rule (rv_fsgnjx $F32 rs1 rs2) (fpu_rrr (FpuOPRRR.FsgnjxS) $F32 (FRM.RDN) rs1 rs2))
1524
+ (rule (rv_fsgnjx $F64 rs1 rs2) (fpu_rrr (FpuOPRRR.FsgnjxD) $F64 (FRM.RDN) rs1 rs2))
1525
+
1526
+ ;; Helper for emitting the `fabs` ("Floating Point Absolute") instruction.
1527
+ ;; This instruction is a mnemonic for `fsgnjx rd, rs1, rs1`
1528
+ (decl rv_fabs (Type FReg) FReg)
1529
+ (rule (rv_fabs ty rs1) (rv_fsgnjx ty rs1 rs1))
1530
+
1531
+ ;; Helper for emitting the `feq` ("Float Equal") instruction.
1532
+ (decl rv_feq (Type FReg FReg) XReg)
1533
+ (rule (rv_feq $F32 rs1 rs2) (fpu_rrr (FpuOPRRR.FeqS) $I64 (FRM.RDN) rs1 rs2))
1534
+ (rule (rv_feq $F64 rs1 rs2) (fpu_rrr (FpuOPRRR.FeqD) $I64 (FRM.RDN) rs1 rs2))
1535
+
1536
+ ;; Helper for emitting the `flt` ("Float Less Than") instruction.
1537
+ (decl rv_flt (Type FReg FReg) XReg)
1538
+ (rule (rv_flt $F32 rs1 rs2) (fpu_rrr (FpuOPRRR.FltS) $I64 (FRM.RTZ) rs1 rs2))
1539
+ (rule (rv_flt $F64 rs1 rs2) (fpu_rrr (FpuOPRRR.FltD) $I64 (FRM.RTZ) rs1 rs2))
1540
+
1541
+ ;; Helper for emitting the `fle` ("Float Less Than or Equal") instruction.
1542
+ (decl rv_fle (Type FReg FReg) XReg)
1543
+ (rule (rv_fle $F32 rs1 rs2) (fpu_rrr (FpuOPRRR.FleS) $I64 (FRM.RNE) rs1 rs2))
1544
+ (rule (rv_fle $F64 rs1 rs2) (fpu_rrr (FpuOPRRR.FleD) $I64 (FRM.RNE) rs1 rs2))
1545
+
1546
+ ;; Helper for emitting the `fgt` ("Float Greater Than") instruction.
1547
+ ;; Note: The arguments are reversed
1548
+ (decl rv_fgt (Type FReg FReg) XReg)
1549
+ (rule (rv_fgt ty rs1 rs2) (rv_flt ty rs2 rs1))
1550
+
1551
+ ;; Helper for emitting the `fge` ("Float Greater Than or Equal") instruction.
1552
+ ;; Note: The arguments are reversed
1553
+ (decl rv_fge (Type FReg FReg) XReg)
1554
+ (rule (rv_fge ty rs1 rs2) (rv_fle ty rs2 rs1))
1555
+
1556
+ ;; Helper for emitting the `fmin` instruction.
1557
+ (decl rv_fmin (Type FReg FReg) FReg)
1558
+ (rule (rv_fmin $F32 rs1 rs2) (fpu_rrr (FpuOPRRR.FminS) $F32 (FRM.RNE) rs1 rs2))
1559
+ (rule (rv_fmin $F64 rs1 rs2) (fpu_rrr (FpuOPRRR.FminD) $F64 (FRM.RNE) rs1 rs2))
1560
+
1561
+ ;; Helper for emitting the `fmax` instruction.
1562
+ (decl rv_fmax (Type FReg FReg) FReg)
1563
+ (rule (rv_fmax $F32 rs1 rs2) (fpu_rrr (FpuOPRRR.FmaxS) $F32 (FRM.RTZ) rs1 rs2))
1564
+ (rule (rv_fmax $F64 rs1 rs2) (fpu_rrr (FpuOPRRR.FmaxD) $F64 (FRM.RTZ) rs1 rs2))
1565
+
1566
+ ;; `Zfa` Extension Instructions
1567
+
1568
+ ;; Helper for emitting the `fminm` instruction.
1569
+ (decl rv_fminm (Type FReg FReg) FReg)
1570
+ (rule (rv_fminm $F32 rs1 rs2) (fpu_rrr (FpuOPRRR.FminmS) $F32 (FRM.RDN) rs1 rs2))
1571
+ (rule (rv_fminm $F64 rs1 rs2) (fpu_rrr (FpuOPRRR.FminmD) $F64 (FRM.RDN) rs1 rs2))
1572
+
1573
+ ;; Helper for emitting the `fmaxm` instruction.
1574
+ (decl rv_fmaxm (Type FReg FReg) FReg)
1575
+ (rule (rv_fmaxm $F32 rs1 rs2) (fpu_rrr (FpuOPRRR.FmaxmS) $F32 (FRM.RUP) rs1 rs2))
1576
+ (rule (rv_fmaxm $F64 rs1 rs2) (fpu_rrr (FpuOPRRR.FmaxmD) $F64 (FRM.RUP) rs1 rs2))
1577
+
1578
+ ;; Helper for emitting the `fround` instruction.
1579
+ (decl rv_fround (Type FRM FReg) FReg)
1580
+ (rule (rv_fround $F32 frm rs) (fpu_rr (FpuOPRR.FroundS) $F32 frm rs))
1581
+ (rule (rv_fround $F64 frm rs) (fpu_rr (FpuOPRR.FroundD) $F64 frm rs))
1582
+
1583
+ ;; Helper for emitting the `fli` instruction.
1584
+ (decl rv_fli (Type FliConstant) FReg)
1585
+ (rule (rv_fli ty imm)
1586
+ (let ((dst WritableFReg (temp_writable_freg))
1587
+ (_ Unit (emit (MInst.Fli ty
1588
+ imm
1589
+ dst))))
1590
+ dst))
1591
+
1592
+ ;; `Zba` Extension Instructions
1593
+
1594
+ ;; Helper for emitting the `adduw` ("Add Unsigned Word") instruction.
1595
+ ;; rd ← uext32(rs1) + uext32(rs2)
1596
+ (decl rv_adduw (XReg XReg) XReg)
1597
+ (rule (rv_adduw rs1 rs2)
1598
+ (alu_rrr (AluOPRRR.Adduw) rs1 rs2))
1599
+
1600
+ ;; Helper for emitting the `zext.w` ("Zero Extend Word") instruction.
1601
+ ;; This instruction is a mnemonic for `adduw rd, rs1, zero`.
1602
+ ;; rd ← uext32(rs1)
1603
+ (decl rv_zextw (XReg) XReg)
1604
+ (rule (rv_zextw rs1)
1605
+ (rv_adduw rs1 (zero_reg)))
1606
+
1607
+ ;; Helper for emitting the `slli.uw` ("Shift Left Logical Immediate Unsigned Word") instruction.
1608
+ ;; rd ← uext32(rs1) << imm
1609
+ (decl rv_slliuw (XReg Imm12) XReg)
1610
+ (rule (rv_slliuw rs1 imm)
1611
+ (alu_rr_imm12 (AluOPRRI.SlliUw) rs1 imm))
1612
+
1613
+
1614
+ ;; `Zbb` Extension Instructions
1615
+
1616
+ ;; Helper for emitting the `andn` ("And Negated") instruction.
1617
+ ;; rd ← rs1 ∧ ~(rs2)
1618
+ (decl rv_andn (XReg XReg) XReg)
1619
+ (rule (rv_andn rs1 rs2)
1620
+ (if-let $true (has_zbb))
1621
+ (alu_rrr (AluOPRRR.Andn) rs1 rs2))
1622
+ (rule (rv_andn rs1 rs2)
1623
+ (if-let $false (has_zbb))
1624
+ (rv_and rs1 (rv_not rs2)))
1625
+
1626
+ ;; Helper for emitting the `orn` ("Or Negated") instruction.
1627
+ ;; rd ← rs1 ∨ ~(rs2)
1628
+ (decl rv_orn (XReg XReg) XReg)
1629
+ (rule (rv_orn rs1 rs2)
1630
+ (alu_rrr (AluOPRRR.Orn) rs1 rs2))
1631
+
1632
+ ;; Helper for emitting the `xnor` ("Exclusive NOR") instruction.
1633
+ ;; rd ← ~(rs1 ^ rs2)
1634
+ (decl rv_xnor (XReg XReg) XReg)
1635
+ (rule (rv_xnor rs1 rs2)
1636
+ (alu_rrr (AluOPRRR.Xnor) rs1 rs2))
1637
+
1638
+ ;; Helper for emitting the `clz` ("Count Leading Zero Bits") instruction.
1639
+ (decl rv_clz (XReg) XReg)
1640
+ (rule (rv_clz rs1)
1641
+ (alu_rr_funct12 (AluOPRRI.Clz) rs1))
1642
+
1643
+ ;; Helper for emitting the `clzw` ("Count Leading Zero Bits in Word") instruction.
1644
+ (decl rv_clzw (XReg) XReg)
1645
+ (rule (rv_clzw rs1)
1646
+ (alu_rr_funct12 (AluOPRRI.Clzw) rs1))
1647
+
1648
+ ;; Helper for emitting the `ctz` ("Count Trailing Zero Bits") instruction.
1649
+ (decl rv_ctz (XReg) XReg)
1650
+ (rule (rv_ctz rs1)
1651
+ (alu_rr_funct12 (AluOPRRI.Ctz) rs1))
1652
+
1653
+ ;; Helper for emitting the `ctzw` ("Count Trailing Zero Bits in Word") instruction.
1654
+ (decl rv_ctzw (XReg) XReg)
1655
+ (rule (rv_ctzw rs1)
1656
+ (alu_rr_funct12 (AluOPRRI.Ctzw) rs1))
1657
+
1658
+ ;; Helper for emitting the `cpop` ("Count Population") instruction.
1659
+ (decl rv_cpop (XReg) XReg)
1660
+ (rule (rv_cpop rs1)
1661
+ (alu_rr_funct12 (AluOPRRI.Cpop) rs1))
1662
+
1663
+ ;; Helper for emitting the `cpopw` ("Count Population") instruction.
1664
+ (decl rv_cpopw (XReg) XReg)
1665
+ (rule (rv_cpopw rs1)
1666
+ (alu_rr_funct12 (AluOPRRI.Cpopw) rs1))
1667
+
1668
+ ;; Helper for emitting the `max` instruction.
1669
+ (decl rv_max (XReg XReg) XReg)
1670
+ (rule (rv_max rs1 rs2)
1671
+ (alu_rrr (AluOPRRR.Max) rs1 rs2))
1672
+
1673
+ ;; Helper for emitting the `maxu` instruction.
1674
+ (decl rv_maxu (XReg XReg) XReg)
1675
+ (rule (rv_maxu rs1 rs2)
1676
+ (alu_rrr (AluOPRRR.Maxu) rs1 rs2))
1677
+
1678
+ ;; Helper for emitting the `min` instruction.
1679
+ (decl rv_min (XReg XReg) XReg)
1680
+ (rule (rv_min rs1 rs2)
1681
+ (alu_rrr (AluOPRRR.Min) rs1 rs2))
1682
+
1683
+ ;; Helper for emitting the `minu` instruction.
1684
+ (decl rv_minu (XReg XReg) XReg)
1685
+ (rule (rv_minu rs1 rs2)
1686
+ (alu_rrr (AluOPRRR.Minu) rs1 rs2))
1687
+
1688
+ ;; Helper for emitting the `sext.b` instruction.
1689
+ (decl rv_sextb (XReg) XReg)
1690
+ (rule (rv_sextb rs1)
1691
+ (alu_rr_imm12 (AluOPRRI.Sextb) rs1 (imm12_const 0)))
1692
+
1693
+ ;; Helper for emitting the `sext.h` instruction.
1694
+ (decl rv_sexth (XReg) XReg)
1695
+ (rule (rv_sexth rs1)
1696
+ (alu_rr_imm12 (AluOPRRI.Sexth) rs1 (imm12_const 0)))
1697
+
1698
+ ;; Helper for emitting the `zext.h` instruction.
1699
+ (decl rv_zexth (XReg) XReg)
1700
+ (rule (rv_zexth rs1)
1701
+ (alu_rr_imm12 (AluOPRRI.Zexth) rs1 (imm12_const 0)))
1702
+
1703
+ ;; Helper for emitting the `rol` ("Rotate Left") instruction.
1704
+ (decl rv_rol (XReg XReg) XReg)
1705
+ (rule (rv_rol rs1 rs2)
1706
+ (alu_rrr (AluOPRRR.Rol) rs1 rs2))
1707
+
1708
+ ;; Helper for emitting the `rolw` ("Rotate Left Word") instruction.
1709
+ (decl rv_rolw (XReg XReg) XReg)
1710
+ (rule (rv_rolw rs1 rs2)
1711
+ (alu_rrr (AluOPRRR.Rolw) rs1 rs2))
1712
+
1713
+ ;; Helper for emitting the `ror` ("Rotate Right") instruction.
1714
+ (decl rv_ror (XReg XReg) XReg)
1715
+ (rule (rv_ror rs1 rs2)
1716
+ (alu_rrr (AluOPRRR.Ror) rs1 rs2))
1717
+
1718
+ ;; Helper for emitting the `rorw` ("Rotate Right Word") instruction.
1719
+ (decl rv_rorw (XReg XReg) XReg)
1720
+ (rule (rv_rorw rs1 rs2)
1721
+ (alu_rrr (AluOPRRR.Rorw) rs1 rs2))
1722
+
1723
+ ;; Helper for emitting the `rori` ("Rotate Right") instruction.
1724
+ (decl rv_rori (XReg Imm12) XReg)
1725
+ (rule (rv_rori rs1 rs2)
1726
+ (alu_rr_imm12 (AluOPRRI.Rori) rs1 rs2))
1727
+
1728
+ ;; Helper for emitting the `roriw` ("Rotate Right Word") instruction.
1729
+ (decl rv_roriw (XReg Imm12) XReg)
1730
+ (rule (rv_roriw rs1 rs2)
1731
+ (alu_rr_imm12 (AluOPRRI.Roriw) rs1 rs2))
1732
+
1733
+ ;; Helper for emitting the `rev8` ("Byte Reverse") instruction.
1734
+ (decl rv_rev8 (XReg) XReg)
1735
+ (rule (rv_rev8 rs1)
1736
+ (alu_rr_funct12 (AluOPRRI.Rev8) rs1))
1737
+
1738
+ ;; Helper for emitting the `brev8` ("Bit Reverse Inside Bytes") instruction.
1739
+ ;; TODO: This instruction is mentioned in some older versions of the
1740
+ ;; spec, but has since disappeared, we should follow up on this.
1741
+ ;; It probably was renamed to `rev.b` which seems to be the closest match.
1742
+ (decl rv_brev8 (XReg) XReg)
1743
+ (rule (rv_brev8 rs1)
1744
+ (alu_rr_funct12 (AluOPRRI.Brev8) rs1))
1745
+
1746
+ ;; `Zbs` Extension Instructions
1747
+
1748
+ (decl rv_bclr (XReg XReg) XReg)
1749
+ (rule (rv_bclr rs1 rs2)
1750
+ (alu_rrr (AluOPRRR.Bclr) rs1 rs2))
1751
+
1752
+ (decl rv_bclri (XReg Imm12) XReg)
1753
+ (rule (rv_bclri rs1 imm)
1754
+ (alu_rr_imm12 (AluOPRRI.Bclri) rs1 imm))
1755
+
1756
+ (decl rv_bext (XReg XReg) XReg)
1757
+ (rule (rv_bext rs1 rs2)
1758
+ (alu_rrr (AluOPRRR.Bext) rs1 rs2))
1759
+
1760
+ (decl rv_bexti (XReg Imm12) XReg)
1761
+ (rule (rv_bexti rs1 imm)
1762
+ (alu_rr_imm12 (AluOPRRI.Bexti) rs1 imm))
1763
+
1764
+ (decl rv_binv (XReg XReg) XReg)
1765
+ (rule (rv_binv rs1 rs2)
1766
+ (alu_rrr (AluOPRRR.Binv) rs1 rs2))
1767
+
1768
+ (decl rv_binvi (XReg Imm12) XReg)
1769
+ (rule (rv_binvi rs1 imm)
1770
+ (alu_rr_imm12 (AluOPRRI.Binvi) rs1 imm))
1771
+
1772
+ (decl rv_bset (XReg XReg) XReg)
1773
+ (rule (rv_bset rs1 rs2)
1774
+ (alu_rrr (AluOPRRR.Bset) rs1 rs2))
1775
+
1776
+ ;; Helper for emitting the `bseti` ("Single-Bit Set Immediate") instruction.
1777
+ (decl rv_bseti (XReg Imm12) XReg)
1778
+ (rule (rv_bseti rs1 imm)
1779
+ (alu_rr_imm12 (AluOPRRI.Bseti) rs1 imm))
1780
+
1781
+ ;; `Zbkb` Extension Instructions
1782
+
1783
+ ;; Helper for emitting the `pack` ("Pack low halves of registers") instruction.
1784
+ (decl rv_pack (XReg XReg) XReg)
1785
+ (rule (rv_pack rs1 rs2)
1786
+ (alu_rrr (AluOPRRR.Pack) rs1 rs2))
1787
+
1788
+ ;; Helper for emitting the `packw` ("Pack low 16-bits of registers") instruction.
1789
+ (decl rv_packw (XReg XReg) XReg)
1790
+ (rule (rv_packw rs1 rs2)
1791
+ (alu_rrr (AluOPRRR.Packw) rs1 rs2))
1792
+
1793
+ ;; `ZiCond` Extension Instructions
1794
+
1795
+ ;; Helper for emitting the `czero.eqz` ("Conditional zero, if condition is equal to zero") instruction.
1796
+ ;; RS1 is the data source
1797
+ ;; RS2 is the condition
1798
+ ;;
1799
+ ;; rd = (rs2 == 0) ? 0 : rs1
1800
+ (decl rv_czero_eqz (XReg XReg) XReg)
1801
+ (rule (rv_czero_eqz rs1 rs2)
1802
+ (alu_rrr (AluOPRRR.CzeroEqz) rs1 rs2))
1803
+
1804
+ ;; Helper for emitting the `czero.nez` ("Conditional zero, if condition is nonzero") instruction.
1805
+ ;; RS1 is the data source
1806
+ ;; RS2 is the condition
1807
+ ;;
1808
+ ;; rd = (rs2 != 0) ? 0 : rs1
1809
+ (decl rv_czero_nez (XReg XReg) XReg)
1810
+ (rule (rv_czero_nez rs1 rs2)
1811
+ (alu_rrr (AluOPRRR.CzeroNez) rs1 rs2))
1812
+
1813
+
1814
+ ;; `Zicsr` Extension Instructions
1815
+
1816
+ ;; Helper for emitting the `csrrwi` instruction.
1817
+ (decl rv_csrrwi (CSR UImm5) XReg)
1818
+ (rule (rv_csrrwi csr imm)
1819
+ (csr_imm (CsrImmOP.CsrRWI) csr imm))
1820
+
1821
+ ;; This is a special case of `csrrwi` when the CSR is the `frm` CSR.
1822
+ (decl rv_fsrmi (FRM) XReg)
1823
+ (rule (rv_fsrmi frm) (rv_csrrwi (CSR.Frm) frm))
1824
+
1825
+
1826
+ ;; Helper for emitting the `csrw` instruction. This is a special case of
1827
+ ;; `csrrw` where the destination register is always `x0`.
1828
+ (decl rv_csrw (CSR XReg) Unit)
1829
+ (rule (rv_csrw csr rs)
1830
+ (csr_reg_dst_zero (CsrRegOP.CsrRW) csr rs))
1831
+
1832
+ ;; This is a special case of `csrw` when the CSR is the `frm` CSR.
1833
+ (decl rv_fsrm (XReg) Unit)
1834
+ (rule (rv_fsrm rs) (rv_csrw (CSR.Frm) rs))
1835
+
1836
+
1837
+
1838
+
1839
+
1840
+
1841
+ ;; Helper for generating a FliConstant from a u64 constant
1842
+ (decl pure partial fli_constant_from_u64 (Type u64) FliConstant)
1843
+ (extern constructor fli_constant_from_u64 fli_constant_from_u64)
1844
+
1845
+ ;; Helper for generating a FliConstant from a u64 negated constant
1846
+ (decl pure partial fli_constant_from_negated_u64 (Type u64) FliConstant)
1847
+ (extern constructor fli_constant_from_negated_u64 fli_constant_from_negated_u64)
1848
+
1849
+ ;; Helper for generating a i64 from a pair of Imm20 and Imm12 constants
1850
+ (decl i64_generate_imm (Imm20 Imm12) i64)
1851
+ (extern extractor i64_generate_imm i64_generate_imm)
1852
+
1853
+ ;; Helper for generating a i64 from a shift of a Imm20 constant with LUI
1854
+ (decl i64_shift_for_lui (u64 Imm12) i64)
1855
+ (extern extractor i64_shift_for_lui i64_shift_for_lui)
1856
+
1857
+ ;; Helper for generating a i64 from a shift of a Imm20 constant
1858
+ (decl i64_shift (i64 Imm12) i64)
1859
+ (extern extractor i64_shift i64_shift)
1860
+
1861
+ ;; Immediate Loading rules
1862
+ ;; TODO: Loading the zero reg directly causes a bunch of regalloc errors, we should look into it.
1863
+ ;; TODO: Load floats using `fld` instead of `ld`
1864
+ (decl imm (Type u64) Reg)
1865
+
1866
+ ;; Special-case 0.0 for floats to use the `(zero_reg)` directly.
1867
+ ;; See #7162 for why this doesn't fall out of the rules below.
1868
+ (rule 8 (imm $F32 0) (gen_bitcast (zero_reg) $I32 $F32))
1869
+ (rule 8 (imm $F64 0) (gen_bitcast (zero_reg) $I64 $F64))
1870
+
1871
+ ;; If Zfa is enabled, we can load certain constants with the `fli` instruction.
1872
+ (rule 7 (imm (ty_scalar_float ty) imm)
1873
+ (if-let $true (has_zfa))
1874
+ (if-let const (fli_constant_from_u64 ty imm))
1875
+ (rv_fli ty const))
1876
+
1877
+ ;; It is beneficial to load the negated constant with `fli` and then negate it
1878
+ ;; in a register.
1879
+ ;;
1880
+ ;; For f64's this saves one instruction, and for f32's it avoids
1881
+ ;; having to allocate an integer register, reducing integer register pressure.
1882
+ (rule 6 (imm (ty_scalar_float ty) imm)
1883
+ (if-let $true (has_zfa))
1884
+ (if-let const (fli_constant_from_negated_u64 ty imm))
1885
+ (rv_fneg ty (rv_fli ty const)))
1886
+
1887
+ ;; Otherwise floats get loaded as integers and then moved into an F register.
1888
+ (rule 5 (imm $F32 c) (gen_bitcast (imm $I32 c) $I32 $F32))
1889
+ (rule 5 (imm $F64 c) (gen_bitcast (imm $I64 c) $I64 $F64))
1890
+
1891
+ ;; Refs get loaded as integers.
1892
+ (rule 5 (imm $R32 c) (imm $I32 c))
1893
+ (rule 5 (imm $R64 c) (imm $I64 c))
1894
+
1895
+ ;; Try to match just an imm12
1896
+ (rule 4 (imm (ty_int ty) c)
1897
+ (if-let (i64_generate_imm (imm20_is_zero) imm12) (i64_sextend_u64 ty c))
1898
+ (rv_addi (zero_reg) imm12))
1899
+
1900
+ ;; We can also try to load using a single LUI.
1901
+ ;; LUI takes a 20 bit immediate, places it on bits 13 to 32 of the register.
1902
+ ;; In RV64 this value is then sign extended to 64bits.
1903
+ (rule 3 (imm (ty_int ty) c)
1904
+ (if-let (i64_generate_imm imm20 (imm12_is_zero)) (i64_sextend_u64 ty c))
1905
+ (rv_lui imm20))
1906
+
1907
+ ;; We can combo addi + lui to represent all 32-bit immediates
1908
+ ;; And some 64-bit immediates as well.
1909
+ (rule 2 (imm (ty_int ty) c)
1910
+ (if-let (i64_generate_imm imm20 imm12) (i64_sextend_u64 ty c))
1911
+ (rv_addi (rv_lui imm20) imm12))
1912
+
1913
+ ;; If the non-zero bits of the immediate fit in 20 bits, we can use LUI + shift
1914
+ (rule 1 (imm (ty_int ty) c)
1915
+ (if-let (i64_shift_for_lui (imm20_from_u64 base) shift) (i64_sextend_u64 ty c))
1916
+ (rv_slli (rv_lui base) shift))
1917
+
1918
+ ;; Combine one of the above rules with a shift-left if possible, This chops off
1919
+ ;; all trailing zeros from the input constant and then attempts if the resulting
1920
+ ;; constant can itself use one of the above rules via the `i64_generate_imm`
1921
+ ;; matcher. This will then recurse on the above rules to materialize a smaller
1922
+ ;; constant which is then shifted left to create the desired constant.
1923
+ (rule 0 (imm (ty_int ty) c)
1924
+ (if-let (i64_shift c_shifted shift) (i64_sextend_u64 ty c)) ;; constant to make
1925
+ (if-let (i64_generate_imm _ _) c_shifted) ;; can the smaller constant be made?
1926
+ (rv_slli (imm ty (i64_as_u64 c_shifted)) shift))
1927
+
1928
+ ;; Otherwise we fall back to loading the immediate from the constant pool.
1929
+ (rule -1 (imm (ty_int ty) c)
1930
+ (gen_load
1931
+ (gen_const_amode (emit_u64_le_const c))
1932
+ (LoadOP.Ld)
1933
+ (mem_flags_trusted)))
1934
+
1935
+ ;; Imm12 Rules
1936
+
1937
+ (decl pure imm12_zero () Imm12)
1938
+ (rule (imm12_zero) (imm12_const 0))
1939
+
1940
+ (decl pure imm12_const (i32) Imm12)
1941
+ (extern constructor imm12_const imm12_const)
1942
+
1943
+ (decl load_imm12 (i32) Reg)
1944
+ (rule
1945
+ (load_imm12 x)
1946
+ (rv_addi (zero_reg) (imm12_const x)))
1947
+
1948
+ ;; for load immediate
1949
+ (decl imm_from_bits (u64) Imm12)
1950
+ (extern constructor imm_from_bits imm_from_bits)
1951
+
1952
+ (decl imm_from_neg_bits (i64) Imm12)
1953
+ (extern constructor imm_from_neg_bits imm_from_neg_bits)
1954
+
1955
+ (decl imm12_const_add (i32 i32) Imm12)
1956
+ (extern constructor imm12_const_add imm12_const_add)
1957
+
1958
+ ;; Performs a fallible add of the `Imm12` value and the 32-bit value provided.
1959
+ (decl pure partial imm12_add (Imm12 i32) Imm12)
1960
+ (extern constructor imm12_add imm12_add)
1961
+
1962
+ (decl imm12_and (Imm12 u64) Imm12)
1963
+ (extern constructor imm12_and imm12_and)
1964
+
1965
+ ;; Imm12 Extractors
1966
+
1967
+ ;; Helper to go directly from a `Value`, when it's an `iconst`, to an `Imm12`.
1968
+ (decl imm12_from_value (Imm12) Value)
1969
+ (extractor (imm12_from_value n) (i64_from_iconst (imm12_from_i64 n)))
1970
+
1971
+ ;; Conceptually the same as `imm12_from_value`, but tries negating the constant
1972
+ ;; value (first sign-extending to handle narrow widths).
1973
+ (decl pure partial imm12_from_negated_value (Value) Imm12)
1974
+ (rule
1975
+ (imm12_from_negated_value (has_type ty (iconst n)))
1976
+ (if-let (imm12_from_u64 imm) (i64_as_u64 (i64_neg (i64_sextend_imm64 ty n))))
1977
+ imm)
1978
+
1979
+ (decl imm12_from_u64 (Imm12) u64)
1980
+ (extern extractor imm12_from_u64 imm12_from_u64)
1981
+
1982
+ (decl imm12_from_i64 (Imm12) i64)
1983
+ (extern extractor imm12_from_i64 imm12_from_i64)
1984
+
1985
+ (decl pure partial u64_to_imm12 (u64) Imm12)
1986
+ (rule (u64_to_imm12 (imm12_from_u64 n)) n)
1987
+
1988
+ (decl pure imm12_is_zero () Imm12)
1989
+ (extern extractor imm12_is_zero imm12_is_zero)
1990
+
1991
+ ;; Imm20
1992
+
1993
+ ;; Extractor that matches if a Imm20 is zero
1994
+ (decl pure imm20_is_zero () Imm20)
1995
+ (extern extractor imm20_is_zero imm20_is_zero)
1996
+
1997
+ (decl imm20_from_u64 (Imm20) u64)
1998
+ (extern extractor imm20_from_u64 imm20_from_u64)
1999
+
2000
+ (decl imm20_from_i64 (Imm20) i64)
2001
+ (extern extractor imm20_from_i64 imm20_from_i64)
2002
+
2003
+
2004
+ ;; Imm5 Extractors
2005
+
2006
+ (decl imm5_from_u64 (Imm5) u64)
2007
+ (extern extractor imm5_from_u64 imm5_from_u64)
2008
+
2009
+ (decl imm5_from_i64 (Imm5) i64)
2010
+ (extern extractor imm5_from_i64 imm5_from_i64)
2011
+
2012
+ ;; Construct a Imm5 from an i8
2013
+ (decl pure partial i8_to_imm5 (i8) Imm5)
2014
+ (extern constructor i8_to_imm5 i8_to_imm5)
2015
+
2016
+ ;; Helper to go directly from a `Value` to an `Imm5`.
2017
+ (decl imm5_from_value (Imm5) Value)
2018
+ (extractor (imm5_from_value n) (i64_from_iconst (imm5_from_i64 n)))
2019
+
2020
+ ;; Like imm5_from_value, but first negates the `Value`.
2021
+ (decl pure partial imm5_from_negated_value (Value) Imm5)
2022
+ (rule (imm5_from_negated_value (has_type ty (iconst n)))
2023
+ (if-let (imm5_from_i64 imm) (i64_neg (i64_sextend_imm64 ty n)))
2024
+ imm)
2025
+
2026
+ ;; Constructor that matches a `Value` equivalent to a replicated Imm5 on all lanes.
2027
+ (decl pure partial replicated_imm5 (Value) Imm5)
2028
+ (rule (replicated_imm5 (splat (imm5_from_value n))) n)
2029
+ (rule (replicated_imm5 (vconst (u128_from_constant n128)))
2030
+ (if-let (u128_replicated_u64 n64) n128)
2031
+ (if-let (u64_replicated_u32 n32) n64)
2032
+ (if-let (u32_replicated_u16 n16) n32)
2033
+ (if-let (u16_replicated_u8 n8) n16)
2034
+ (if-let n (i8_to_imm5 (u8_as_i8 n8)))
2035
+ n)
2036
+
2037
+ ;; Like replicated_imm5, but first negates the `Value`.
2038
+ (decl pure partial negated_replicated_imm5 (Value) Imm5)
2039
+ (rule (negated_replicated_imm5 (splat n))
2040
+ (if-let imm5 (imm5_from_negated_value n))
2041
+ imm5)
2042
+ (rule (negated_replicated_imm5 (vconst (u128_from_constant n128)))
2043
+ (if-let (u128_replicated_u64 n64) n128)
2044
+ (if-let (u64_replicated_u32 n32) n64)
2045
+ (if-let (u32_replicated_u16 n16) n32)
2046
+ (if-let (u16_replicated_u8 n8) n16)
2047
+ (if-let n (i8_to_imm5 (i8_neg (u8_as_i8 n8))))
2048
+ n)
2049
+
2050
+ ;; UImm5 Helpers
2051
+
2052
+ ;; Constructor that matches a `Value` equivalent to a replicated UImm5 on all lanes.
2053
+ (decl pure partial replicated_uimm5 (Value) UImm5)
2054
+ (rule (replicated_uimm5 (splat (uimm5_from_value n))) n)
2055
+ (rule 1 (replicated_uimm5 (vconst (u128_from_constant n128)))
2056
+ (if-let (u128_replicated_u64 n64) n128)
2057
+ (if-let (u64_replicated_u32 n32) n64)
2058
+ (if-let (u32_replicated_u16 n16) n32)
2059
+ (if-let (u16_replicated_u8 n8) n16)
2060
+ (if-let (uimm5_from_u8 n) n8)
2061
+ n)
2062
+
2063
+ ;; Helper to go directly from a `Value`, when it's an `iconst`, to an `UImm5`.
2064
+ (decl uimm5_from_value (UImm5) Value)
2065
+ (extractor (uimm5_from_value n)
2066
+ (iconst (u64_from_imm64 (uimm5_from_u64 n))))
2067
+
2068
+ ;; Extract a `UImm5` from an `u8`.
2069
+ (decl pure partial uimm5_from_u8 (UImm5) u8)
2070
+ (extern extractor uimm5_from_u8 uimm5_from_u8)
2071
+
2072
+ ;; Extract a `UImm5` from an `u64`.
2073
+ (decl pure partial uimm5_from_u64 (UImm5) u64)
2074
+ (extern extractor uimm5_from_u64 uimm5_from_u64)
2075
+
2076
+ ;; Convert a `u64` into an `UImm5`
2077
+ (decl pure partial u64_to_uimm5 (u64) UImm5)
2078
+ (rule (u64_to_uimm5 (uimm5_from_u64 n)) n)
2079
+
2080
+ (decl uimm5_bitcast_to_imm5 (UImm5) Imm5)
2081
+ (extern constructor uimm5_bitcast_to_imm5 uimm5_bitcast_to_imm5)
2082
+
2083
+ ;; Float Helpers
2084
+
2085
+ ;; Returns the bitpattern of the Canonical NaN for the given type.
2086
+ (decl pure canonical_nan_u64 (Type) u64)
2087
+ (rule (canonical_nan_u64 $F32) 0x7fc00000)
2088
+ (rule (canonical_nan_u64 $F64) 0x7ff8000000000000)
2089
+
2090
+ ;; Helper for emitting `MInst.FpuRR` instructions.
2091
+ (decl fpu_rr (FpuOPRR Type FRM Reg) Reg)
2092
+ (rule (fpu_rr op ty frm src)
2093
+ (let ((dst WritableReg (temp_writable_reg ty))
2094
+ (_ Unit (emit (MInst.FpuRR op frm dst src))))
2095
+ dst))
2096
+
2097
+ ;; Helper for emitting `MInst.AluRRR` instructions.
2098
+ (decl alu_rrr (AluOPRRR Reg Reg) Reg)
2099
+ (rule (alu_rrr op src1 src2)
2100
+ (let ((dst WritableXReg (temp_writable_xreg))
2101
+ (_ Unit (emit (MInst.AluRRR op dst src1 src2))))
2102
+ dst))
2103
+
2104
+ ;; Helper for emitting `MInst.AluRRR` instructions.
2105
+ (decl fpu_rrr (FpuOPRRR Type FRM Reg Reg) Reg)
2106
+ (rule (fpu_rrr op ty frm src1 src2)
2107
+ (let ((dst WritableReg (temp_writable_reg ty))
2108
+ (_ Unit (emit (MInst.FpuRRR op frm dst src1 src2))))
2109
+ dst))
2110
+
2111
+ ;; Helper for emitting `MInst.FpuRRRR` instructions.
2112
+ (decl fpu_rrrr (FpuOPRRRR Type FRM Reg Reg Reg) Reg)
2113
+ (rule (fpu_rrrr op ty frm src1 src2 src3)
2114
+ (let ((dst WritableReg (temp_writable_reg ty))
2115
+ (_ Unit (emit (MInst.FpuRRRR op frm dst src1 src2 src3))))
2116
+ dst))
2117
+
2118
+
2119
+ ;; Helper for emitting `MInst.AluRRImm12` instructions.
2120
+ (decl alu_rr_imm12 (AluOPRRI Reg Imm12) Reg)
2121
+ (rule (alu_rr_imm12 op src imm)
2122
+ (let ((dst WritableXReg (temp_writable_xreg))
2123
+ (_ Unit (emit (MInst.AluRRImm12 op dst src imm))))
2124
+ dst))
2125
+
2126
+ ;; some instruction use imm12 as funct12.
2127
+ ;; so we don't need the imm12 parameter.
2128
+ (decl alu_rr_funct12 (AluOPRRI Reg) Reg)
2129
+ (rule (alu_rr_funct12 op src)
2130
+ (let ((dst WritableXReg (temp_writable_xreg))
2131
+ (_ Unit (emit (MInst.AluRRImm12 op dst src (imm12_zero)))))
2132
+ dst))
2133
+
2134
+ ;; Helper for emitting the `Lui` instruction.
2135
+ ;; TODO: This should be something like `emit_u_type`. And should share the
2136
+ ;; `MInst` with `auipc` since these instructions share the U-Type format.
2137
+ (decl rv_lui (Imm20) XReg)
2138
+ (rule (rv_lui imm)
2139
+ (let ((dst WritableXReg (temp_writable_xreg))
2140
+ (_ Unit (emit (MInst.Lui dst imm))))
2141
+ dst))
2142
+
2143
+ ;; Helper for emitting `MInst.CsrImm` instructions.
2144
+ (decl csr_imm (CsrImmOP CSR UImm5) XReg)
2145
+ (rule (csr_imm op csr imm)
2146
+ (let ((dst WritableXReg (temp_writable_xreg))
2147
+ (_ Unit (emit (MInst.CsrImm op dst imm csr))))
2148
+ dst))
2149
+
2150
+ ;; Helper for emitting a `MInst.CsrReg` instruction that writes the result to x0.
2151
+ (decl csr_reg_dst_zero (CsrRegOP CSR XReg) Unit)
2152
+ (rule (csr_reg_dst_zero op csr rs)
2153
+ (emit (MInst.CsrReg op (writable_zero_reg) rs csr)))
2154
+
2155
+
2156
+
2157
+ (decl select_addi (Type) AluOPRRI)
2158
+ (rule 1 (select_addi (fits_in_32 ty)) (AluOPRRI.Addiw))
2159
+ (rule (select_addi (fits_in_64 ty)) (AluOPRRI.Addi))
2160
+
2161
+
2162
+ (decl gen_andi (XReg u64) XReg)
2163
+ (rule 1 (gen_andi x (imm12_from_u64 y))
2164
+ (rv_andi x y))
2165
+
2166
+ (rule 0 (gen_andi x y)
2167
+ (rv_and x (imm $I64 y)))
2168
+
2169
+
2170
+ (decl gen_or (Type ValueRegs ValueRegs) ValueRegs)
2171
+ (rule 1 (gen_or $I128 x y)
2172
+ (value_regs
2173
+ (rv_or (value_regs_get x 0) (value_regs_get y 0))
2174
+ (rv_or (value_regs_get x 1) (value_regs_get y 1))))
2175
+
2176
+ (rule 0 (gen_or (fits_in_64 _) x y)
2177
+ (rv_or (value_regs_get x 0) (value_regs_get y 0)))
2178
+
2179
+
2180
+ (decl lower_ctz (Type Reg) Reg)
2181
+ (rule (lower_ctz ty x)
2182
+ (gen_cltz $false x ty))
2183
+
2184
+ (rule 1 (lower_ctz (fits_in_16 ty) x)
2185
+ (if-let $true (has_zbb))
2186
+ (let ((tmp Reg (gen_bseti x (ty_bits ty))))
2187
+ (rv_ctzw tmp)))
2188
+
2189
+ (rule 2 (lower_ctz $I32 x)
2190
+ (if-let $true (has_zbb))
2191
+ (rv_ctzw x))
2192
+
2193
+ (rule 2 (lower_ctz $I64 x)
2194
+ (if-let $true (has_zbb))
2195
+ (rv_ctz x))
2196
+
2197
+ ;; Count leading zeros from a i128 bit value.
2198
+ ;; We count both halves separately and conditionally add them if it makes sense.
2199
+
2200
+ (decl gen_cltz (bool XReg Type) XReg)
2201
+ (rule (gen_cltz leading rs ty)
2202
+ (let ((tmp WritableXReg (temp_writable_xreg))
2203
+ (step WritableXReg (temp_writable_xreg))
2204
+ (sum WritableXReg (temp_writable_xreg))
2205
+ (_ Unit (emit (MInst.Cltz leading sum step tmp rs ty))))
2206
+ sum))
2207
+
2208
+ ;; Performs a zero extension of the given value
2209
+ (decl zext (Value) XReg)
2210
+
2211
+ ;; In the most generic case, we shift left and then shift right.
2212
+ (rule 0 (zext val @ (value_type (fits_in_32 ty)))
2213
+ (let ((shift Imm12 (imm_from_bits (u64_sub 64 (ty_bits ty)))))
2214
+ (rv_srli (rv_slli val shift) shift)))
2215
+
2216
+ ;; If we are zero extending a U8 we can use a `andi` instruction.
2217
+ (rule 1 (zext val @ (value_type $I8))
2218
+ (rv_andi val (imm12_const 0xff)))
2219
+
2220
+ ;; No point in trying to use `packh` here to zero extend 8 bit values
2221
+ ;; since we can just use `andi` instead which is part of the base ISA.
2222
+
2223
+ ;; If we have the `zbkb` extension `packw` can be used to zero extend 16 bit values
2224
+ (rule 1 (zext val @ (value_type $I16))
2225
+ (if-let $true (has_zbkb))
2226
+ (rv_packw val (zero_reg)))
2227
+
2228
+ ;; If we have the `zbkb` extension `pack` can be used to zero extend 32 bit registers
2229
+ (rule 1 (zext val @ (value_type $I32))
2230
+ (if-let $true (has_zbkb))
2231
+ (rv_pack val (zero_reg)))
2232
+
2233
+ ;; If we have the `zbb` extension we can use the dedicated `zext.h` instruction.
2234
+ (rule 2 (zext val @ (value_type $I16))
2235
+ (if-let $true (has_zbb))
2236
+ (rv_zexth val))
2237
+
2238
+ ;; With `zba` we have a `zext.w` instruction
2239
+ (rule 2 (zext val @ (value_type $I32))
2240
+ (if-let $true (has_zba))
2241
+ (rv_zextw val))
2242
+
2243
+ ;; Ignore sign extensions for values whose representation is already the full
2244
+ ;; register width.
2245
+ (rule 3 (zext val)
2246
+ (if (val_already_extended (ExtendOp.Zero) val))
2247
+ val)
2248
+
2249
+ ;; Performs a signed extension of the given value
2250
+ (decl sext (Value) XReg)
2251
+
2252
+ ;; Same base case as `zext`, shift left-then-right.
2253
+ (rule 0 (sext val @ (value_type (fits_in_32 ty)))
2254
+ (let ((shift Imm12 (imm_from_bits (u64_sub 64 (ty_bits ty)))))
2255
+ (rv_srai (rv_slli val shift) shift)))
2256
+
2257
+ ;; If we have the `zbb` extension we can use the dedicated `sext.b` instruction.
2258
+ (rule 1 (sext val @ (value_type $I8))
2259
+ (if-let $true (has_zbb))
2260
+ (rv_sextb val))
2261
+
2262
+ ;; If we have the `zbb` extension we can use the dedicated `sext.h` instruction.
2263
+ (rule 1 (sext val @ (value_type $I16))
2264
+ (if-let $true (has_zbb))
2265
+ (rv_sexth val))
2266
+
2267
+ ;; When signed extending from 32 to 64 bits we can use a
2268
+ ;; `addiw val 0`. Also known as a `sext.w`
2269
+ (rule 1 (sext val @ (value_type $I32))
2270
+ (rv_sextw val))
2271
+
2272
+ ;; Ignore sign extensions for values whose representation is already the full
2273
+ ;; register width.
2274
+ (rule 2 (sext val)
2275
+ (if (val_already_extended (ExtendOp.Signed) val))
2276
+ val)
2277
+
2278
+ ;; Helper matcher for when a value's representation is already sign or zero
2279
+ ;; extended to the full 64-bit register representation. This is used by `zext`
2280
+ ;; and `sext` above to skip the extension instruction entirely in some
2281
+ ;; circumstances.
2282
+ (decl pure partial val_already_extended (ExtendOp Value) bool)
2283
+ (rule 0 (val_already_extended _ v @ (value_type $I64)) $true)
2284
+
2285
+ ;; When extending our backend always extends to the full register width, so
2286
+ ;; there's no need to extend-an-extend.
2287
+ (rule 1 (val_already_extended (ExtendOp.Zero) (uextend _)) $true)
2288
+ (rule 1 (val_already_extended (ExtendOp.Signed) (sextend _)) $true)
2289
+
2290
+ ;; The result of `icmp`/`fcmp` is zero or one, meaning that it's already sign
2291
+ ;; extended to the full register width.
2292
+ (rule 1 (val_already_extended _ (icmp _ _ _)) $true)
2293
+ (rule 1 (val_already_extended _ (fcmp _ _ _)) $true)
2294
+
2295
+ ;; The lowering for these operations always sign-extend their results due to the
2296
+ ;; use of the `*w` instructions in RV64I. Note that this requires that the
2297
+ ;; extension is from 32 to 64, 16/8-bit operations are explicitly excluded here.
2298
+ ;; There are no native instructions for the 16/8 bit operations so they must
2299
+ ;; fall through to actual sign extension above.
2300
+ (rule 1 (val_already_extended (ExtendOp.Signed) (has_type $I32 (ishl _ _))) $true)
2301
+ (rule 1 (val_already_extended (ExtendOp.Signed) (has_type $I32 (ushr _ _))) $true)
2302
+ (rule 1 (val_already_extended (ExtendOp.Signed) (has_type $I32 (sshr _ _))) $true)
2303
+ (rule 1 (val_already_extended (ExtendOp.Signed) (has_type $I32 (iadd _ _))) $true)
2304
+ (rule 1 (val_already_extended (ExtendOp.Signed) (has_type $I32 (isub _ _))) $true)
2305
+
2306
+ (type ExtendOp
2307
+ (enum
2308
+ (Zero)
2309
+ (Signed)))
2310
+
2311
+ (decl lower_b128_binary (AluOPRRR ValueRegs ValueRegs) ValueRegs)
2312
+ (rule
2313
+ (lower_b128_binary op a b)
2314
+ (let
2315
+ ( ;; low part.
2316
+ (low XReg (alu_rrr op (value_regs_get a 0) (value_regs_get b 0)))
2317
+ ;; high part.
2318
+ (high XReg (alu_rrr op (value_regs_get a 1) (value_regs_get b 1))))
2319
+ (value_regs low high)))
2320
+
2321
+ (decl lower_smlhi (Type XReg XReg) XReg)
2322
+ (rule 1
2323
+ (lower_smlhi $I64 rs1 rs2)
2324
+ (rv_mulh rs1 rs2))
2325
+
2326
+ (rule
2327
+ (lower_smlhi ty rs1 rs2)
2328
+ (let
2329
+ ((tmp XReg (rv_mul rs1 rs2)))
2330
+ (rv_srli tmp (imm12_const (ty_bits ty)))))
2331
+
2332
+ ;;;; construct shift amount.rotl on i128 will use shift to implement. So can call this function.
2333
+ ;;;; this will return shift amount and (ty_bits - "shift amount")
2334
+ ;;;; if ty_bits is greater than 64 like i128, then shmat will fallback to 64.because We are 64 bit platform.
2335
+ (decl gen_shamt (Type XReg) ValueRegs)
2336
+ (extern constructor gen_shamt gen_shamt)
2337
+
2338
+ ;; bseti: Set a single bit in a register, indexed by a constant.
2339
+ (decl gen_bseti (Reg u64) Reg)
2340
+ (rule (gen_bseti val bit)
2341
+ (if-let $false (has_zbs))
2342
+ (if-let $false (u64_le bit 12))
2343
+ (let ((const XReg (imm $I64 (u64_shl 1 bit))))
2344
+ (rv_or val const)))
2345
+
2346
+ (rule (gen_bseti val bit)
2347
+ (if-let $false (has_zbs))
2348
+ (if-let $true (u64_le bit 12))
2349
+ (rv_ori val (imm12_const (u64_as_i32 (u64_shl 1 bit)))))
2350
+
2351
+ (rule (gen_bseti val bit)
2352
+ (if-let $true (has_zbs))
2353
+ (rv_bseti val (imm12_const (u64_as_i32 bit))))
2354
+
2355
+
2356
+ (decl gen_popcnt (XReg) Reg)
2357
+ (rule (gen_popcnt rs)
2358
+ (let
2359
+ ((tmp WritableXReg (temp_writable_xreg))
2360
+ (step WritableXReg (temp_writable_xreg))
2361
+ (sum WritableXReg (temp_writable_xreg))
2362
+ (_ Unit (emit (MInst.Popcnt sum step tmp rs $I64))))
2363
+ (writable_reg_to_reg sum)))
2364
+
2365
+ ;; Generates a AMode that points to a register plus an offset.
2366
+ (decl gen_reg_offset_amode (Reg i64) AMode)
2367
+ (extern constructor gen_reg_offset_amode gen_reg_offset_amode)
2368
+
2369
+ ;; Generates a AMode that an offset from the stack pointer.
2370
+ (decl gen_sp_offset_amode (i64) AMode)
2371
+ (extern constructor gen_sp_offset_amode gen_sp_offset_amode)
2372
+
2373
+ ;; Generates a AMode that an offset from the frame pointer.
2374
+ (decl gen_fp_offset_amode (i64) AMode)
2375
+ (extern constructor gen_fp_offset_amode gen_fp_offset_amode)
2376
+
2377
+ ;; Generates an AMode that points to a stack slot + offset.
2378
+ (decl gen_stack_slot_amode (StackSlot i64) AMode)
2379
+ (extern constructor gen_stack_slot_amode gen_stack_slot_amode)
2380
+
2381
+ ;; Generates a AMode that points to a constant in the constant pool.
2382
+ (decl gen_const_amode (VCodeConstant) AMode)
2383
+ (extern constructor gen_const_amode gen_const_amode)
2384
+
2385
+
2386
+
2387
+ ;; Tries to match a Value + Offset into an AMode
2388
+ (decl amode (Value i32) AMode)
2389
+ (rule 0 (amode addr offset) (amode_inner addr offset))
2390
+
2391
+ ;; If we are adding a constant offset with an iadd we can instead make that
2392
+ ;; offset part of the amode offset.
2393
+ ;;
2394
+ ;; We can't recurse into `amode` again since that could cause stack overflows.
2395
+ ;; See: https://github.com/bytecodealliance/wasmtime/pull/6968
2396
+ (rule 1 (amode (iadd addr (i32_from_iconst y)) offset)
2397
+ (if-let new_offset (s32_add_fallible y offset))
2398
+ (amode_inner addr new_offset))
2399
+ (rule 2 (amode (iadd (i32_from_iconst x) addr) offset)
2400
+ (if-let new_offset (s32_add_fallible x offset))
2401
+ (amode_inner addr new_offset))
2402
+
2403
+
2404
+ ;; These are the normal rules for generating an AMode.
2405
+ (decl amode_inner (Value i32) AMode)
2406
+
2407
+ ;; In the simplest case we just lower into a Reg+Offset
2408
+ (rule 0 (amode_inner r @ (value_type (ty_addr64 _)) offset)
2409
+ (gen_reg_offset_amode r offset))
2410
+
2411
+ ;; If the value is a `get_frame_pointer`, we can just use the offset from that.
2412
+ (rule 1 (amode_inner (get_frame_pointer) offset)
2413
+ (gen_fp_offset_amode offset))
2414
+
2415
+ ;; If the value is a `get_stack_pointer`, we can just use the offset from that.
2416
+ (rule 1 (amode_inner (get_stack_pointer) offset)
2417
+ (gen_sp_offset_amode offset))
2418
+
2419
+ ;; Similarly if the value is a `stack_addr` we can also turn that into an sp offset.
2420
+ (rule 1 (amode_inner (stack_addr ss ss_offset) amode_offset)
2421
+ (if-let combined_offset (s32_add_fallible ss_offset amode_offset))
2422
+ (gen_stack_slot_amode ss combined_offset))
2423
+
2424
+
2425
+ ;; Helpers for sinkable loads ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2426
+
2427
+ ;; RISC-V doesen't really have sinkable loads. But the regular load instructions
2428
+ ;; sign / zero extend their results to 64 bits. So we can pretend they are
2429
+ ;; an extend instruction with a sinkable load. This allows us to have better
2430
+ ;; lowerings on these cases.
2431
+
2432
+ ;; Extract a sinkable instruction from a value operand.
2433
+ (decl sinkable_inst (Inst) Value)
2434
+ (extern extractor sinkable_inst sinkable_inst)
2435
+
2436
+ ;; Matches a sinkable load.
2437
+ (decl sinkable_load (Inst Type MemFlags Value Offset32) Value)
2438
+ (extractor (sinkable_load inst ty flags addr offset)
2439
+ (and
2440
+ (load flags addr offset)
2441
+ (sinkable_inst (has_type ty inst))))
2442
+
2443
+ ;; Returns a canonical type for a LoadOP. We only return I64 or F64.
2444
+ (decl load_op_reg_type (LoadOP) Type)
2445
+ (rule 1 (load_op_reg_type (LoadOP.Fld)) $F64)
2446
+ (rule 1 (load_op_reg_type (LoadOP.Flw)) $F64)
2447
+ (rule 0 (load_op_reg_type _) $I64)
2448
+
2449
+ ;; Helper constructor to build a load instruction.
2450
+ (decl gen_load (AMode LoadOP MemFlags) Reg)
2451
+ (rule (gen_load amode op flags)
2452
+ (let ((dst WritableReg (temp_writable_reg (load_op_reg_type op)))
2453
+ (_ Unit (emit (MInst.Load dst op flags amode))))
2454
+ dst))
2455
+
2456
+ ;; Similar to `gen_load` but marks `Inst` as sunk at the current point.
2457
+ ;;
2458
+ ;; This is only useful for load op's that perform some additional computation
2459
+ ;; such as extending the loaded value.
2460
+ (decl gen_sunk_load (Inst AMode LoadOP MemFlags) Reg)
2461
+ (rule (gen_sunk_load inst amode op flags)
2462
+ (let ((_ Unit (sink_inst inst)))
2463
+ (gen_load amode op flags)))
2464
+
2465
+
2466
+ ;; Helper constructor to build a store instruction.
2467
+ ;;
2468
+ ;; This helper contains a special-case for zero constants stored to memory to
2469
+ ;; directly store the `zero` register to memory. See #7162 for some discussion
2470
+ ;; on why this doesn't just fall out.
2471
+ (decl gen_store (AMode MemFlags Value) InstOutput)
2472
+ (rule 1 (gen_store amode flags val @ (value_type ty))
2473
+ (if-let (u64_from_iconst 0) val)
2474
+ (rv_store amode (store_op ty) flags (zero_reg)))
2475
+ (rule 0 (gen_store amode flags val @ (value_type ty))
2476
+ (rv_store amode (store_op ty) flags val))
2477
+
2478
+ ;; Emit a raw instruction to store a register into memory.
2479
+ ;;
2480
+ ;; Note that the `src` operand must have the correct type for the `op`
2481
+ ;; specified.
2482
+ (decl rv_store (AMode StoreOP MemFlags Reg) InstOutput)
2483
+ (rule (rv_store amode op flags src)
2484
+ (side_effect (SideEffectNoResult.Inst (MInst.Store amode op flags src))))
2485
+
2486
+
2487
+
2488
+
2489
+ (decl valid_atomic_transaction (Type) Type)
2490
+ (extern extractor valid_atomic_transaction valid_atomic_transaction)
2491
+
2492
+ ;;helper function.
2493
+ ;;construct an atomic instruction.
2494
+ (decl gen_atomic (AtomicOP Reg Reg AMO) Reg)
2495
+ (rule
2496
+ (gen_atomic op addr src amo)
2497
+ (let
2498
+ ((tmp WritableXReg (temp_writable_xreg))
2499
+ (_ Unit (emit (MInst.Atomic op tmp addr src amo))))
2500
+ tmp))
2501
+
2502
+ ;; helper function
2503
+ (decl get_atomic_rmw_op (Type AtomicRmwOp) AtomicOP)
2504
+ (rule
2505
+ (get_atomic_rmw_op $I32 (AtomicRmwOp.Add))
2506
+ (AtomicOP.AmoaddW))
2507
+ (rule
2508
+ (get_atomic_rmw_op $I64 (AtomicRmwOp.Add))
2509
+ (AtomicOP.AmoaddD))
2510
+
2511
+ (rule
2512
+ (get_atomic_rmw_op $I32 (AtomicRmwOp.And))
2513
+ (AtomicOP.AmoandW))
2514
+
2515
+ (rule
2516
+ (get_atomic_rmw_op $I64 (AtomicRmwOp.And))
2517
+ (AtomicOP.AmoandD))
2518
+
2519
+ (rule
2520
+ (get_atomic_rmw_op $I32 (AtomicRmwOp.Or))
2521
+ (AtomicOP.AmoorW))
2522
+
2523
+ (rule
2524
+ (get_atomic_rmw_op $I64 (AtomicRmwOp.Or))
2525
+ (AtomicOP.AmoorD))
2526
+
2527
+ (rule
2528
+ (get_atomic_rmw_op $I32 (AtomicRmwOp.Smax))
2529
+ (AtomicOP.AmomaxW))
2530
+
2531
+ (rule
2532
+ (get_atomic_rmw_op $I64 (AtomicRmwOp.Smax))
2533
+ (AtomicOP.AmomaxD))
2534
+
2535
+ (rule
2536
+ (get_atomic_rmw_op $I32 (AtomicRmwOp.Smin))
2537
+ (AtomicOP.AmominW))
2538
+
2539
+ (rule
2540
+ (get_atomic_rmw_op $I64 (AtomicRmwOp.Smin))
2541
+ (AtomicOP.AmominD))
2542
+
2543
+ (rule
2544
+ (get_atomic_rmw_op $I32 (AtomicRmwOp.Umax))
2545
+ (AtomicOP.AmomaxuW)
2546
+ )
2547
+
2548
+ (rule
2549
+ (get_atomic_rmw_op $I64 (AtomicRmwOp.Umax))
2550
+ (AtomicOP.AmomaxuD))
2551
+
2552
+ (rule
2553
+ (get_atomic_rmw_op $I32 (AtomicRmwOp.Umin))
2554
+ (AtomicOP.AmominuW))
2555
+
2556
+ (rule
2557
+ (get_atomic_rmw_op $I64 (AtomicRmwOp.Umin))
2558
+ (AtomicOP.AmominuD))
2559
+
2560
+ (rule
2561
+ (get_atomic_rmw_op $I32 (AtomicRmwOp.Xchg))
2562
+ (AtomicOP.AmoswapW))
2563
+
2564
+ (rule
2565
+ (get_atomic_rmw_op $I64 (AtomicRmwOp.Xchg))
2566
+ (AtomicOP.AmoswapD))
2567
+
2568
+ (rule
2569
+ (get_atomic_rmw_op $I32 (AtomicRmwOp.Xor))
2570
+ (AtomicOP.AmoxorW))
2571
+
2572
+ (rule
2573
+ (get_atomic_rmw_op $I64 (AtomicRmwOp.Xor))
2574
+ (AtomicOP.AmoxorD))
2575
+
2576
+ (decl atomic_amo () AMO)
2577
+ (extern constructor atomic_amo atomic_amo)
2578
+
2579
+
2580
+ (decl gen_atomic_load (Reg Type) Reg)
2581
+ (rule
2582
+ (gen_atomic_load p ty)
2583
+ (let
2584
+ ((tmp WritableXReg (temp_writable_xreg))
2585
+ (_ Unit (emit (MInst.AtomicLoad tmp ty p))))
2586
+ (writable_reg_to_reg tmp)))
2587
+
2588
+ ;;;
2589
+ (decl gen_atomic_store (Reg Type Reg) InstOutput)
2590
+ (rule
2591
+ (gen_atomic_store p ty src)
2592
+ (side_effect (SideEffectNoResult.Inst (MInst.AtomicStore src ty p)))
2593
+ )
2594
+
2595
+
2596
+ ;; Rounds a FReg by converting the value into an integer and back with a specified
2597
+ ;; float rounding mode.
2598
+ (decl float_round_fcvt (Type FRM FReg) FReg)
2599
+ (rule (float_round_fcvt $F32 frm rs) (rv_fcvtsw frm (rv_fcvtws frm rs)))
2600
+ (rule (float_round_fcvt $F64 frm rs) (rv_fcvtdl frm (rv_fcvtld frm rs)))
2601
+
2602
+ (decl gen_float_round (FRM FReg Type) FReg)
2603
+ (rule 0 (gen_float_round frm rs ty)
2604
+ (let (;; if rs is NaN/+-Infinity/+-Zero or if the exponent is larger than # of bits
2605
+ ;; in mantissa, the result is the same as src, check for these cases first.
2606
+ (max FReg (imm ty (float_int_max ty)))
2607
+ (abs FReg (rv_fabs ty rs))
2608
+ (exact XReg (rv_flt ty abs max))
2609
+
2610
+ ;; Manually round the value using the fcvt instructions
2611
+ ;; to move the value to an integer register and back.
2612
+ (fcvt FReg (float_round_fcvt ty frm rs))
2613
+ ;; Restore the sign bit from the initial value.
2614
+ (rounded FReg (rv_fsgnj ty fcvt rs))
2615
+
2616
+ ;; We want to return a arithmetic nan if the input is a canonical nan.
2617
+ ;; Convert them by adding 0.0 to the input.
2618
+ (float_zero FReg (gen_bitcast (zero_reg) (float_int_of_same_size ty) ty))
2619
+ (corrected_nan FReg (rv_fadd ty (FRM.RNE) rs float_zero)))
2620
+
2621
+ ;; Check if the value cannot be rounded exactly and return the source input if so
2622
+ (gen_select_freg (cmp_eqz exact) corrected_nan rounded)))
2623
+
2624
+ ;; With Zfa we can use the dedicated `fround` instruction.
2625
+ (rule 1 (gen_float_round frm rs ty)
2626
+ (if-let $true (has_zfa))
2627
+ (rv_fround ty frm rs))
2628
+
2629
+
2630
+
2631
+ (decl gen_stack_addr (StackSlot Offset32) Reg)
2632
+ (extern constructor gen_stack_addr gen_stack_addr)
2633
+
2634
+ (decl gen_select_xreg (IntegerCompare XReg XReg) XReg)
2635
+
2636
+ (rule 6 (gen_select_xreg (int_compare_decompose cc x y) x y)
2637
+ (if-let (IntCC.UnsignedLessThan) (intcc_without_eq cc))
2638
+ (if-let $true (has_zbb))
2639
+ (rv_minu x y))
2640
+
2641
+ (rule 6 (gen_select_xreg (int_compare_decompose cc x y) x y)
2642
+ (if-let (IntCC.SignedLessThan) (intcc_without_eq cc))
2643
+ (if-let $true (has_zbb))
2644
+ (rv_min x y))
2645
+
2646
+ (rule 6 (gen_select_xreg (int_compare_decompose cc x y) x y)
2647
+ (if-let (IntCC.UnsignedGreaterThan) (intcc_without_eq cc))
2648
+ (if-let $true (has_zbb))
2649
+ (rv_maxu x y))
2650
+
2651
+ (rule 6 (gen_select_xreg (int_compare_decompose cc x y) x y)
2652
+ (if-let (IntCC.SignedGreaterThan) (intcc_without_eq cc))
2653
+ (if-let $true (has_zbb))
2654
+ (rv_max x y))
2655
+
2656
+ ;; Rotate Zero Reg to the right. This allows us to write fewer rules
2657
+ ;; below when matching the zero register
2658
+ ;;
2659
+ ;; Additionally prevent this rule from recursing infinitely by only
2660
+ ;; matching when one of the inputs is the zero register, but not both.
2661
+
2662
+ (rule 5 (gen_select_xreg (int_compare_decompose cc a @ (zero_reg) b @ (non_zero_reg)) x y)
2663
+ (if-let $true (has_zicond))
2664
+ (gen_select_xreg (int_compare (intcc_swap_args cc) b a) x y))
2665
+
2666
+ (rule 4 (gen_select_xreg c @ (int_compare_decompose cc a b) x @ (zero_reg) y @ (non_zero_reg))
2667
+ (if-let $true (has_zicond))
2668
+ (gen_select_xreg (int_compare (intcc_complement cc) a b) y x))
2669
+
2670
+ (rule 3 (gen_select_xreg (int_compare_decompose (IntCC.Equal) c (zero_reg)) x (zero_reg))
2671
+ (if-let $true (has_zicond))
2672
+ (rv_czero_nez x c))
2673
+
2674
+ (rule 3 (gen_select_xreg (int_compare_decompose (IntCC.NotEqual) c (zero_reg)) x (zero_reg))
2675
+ (if-let $true (has_zicond))
2676
+ (rv_czero_eqz x c))
2677
+
2678
+ (rule 2 (gen_select_xreg (int_compare_decompose (IntCC.Equal) c (zero_reg)) x y)
2679
+ (if-let $true (has_zicond))
2680
+ (rv_or
2681
+ (rv_czero_nez x c)
2682
+ (rv_czero_eqz y c)))
2683
+
2684
+ (rule 2 (gen_select_xreg (int_compare_decompose (IntCC.NotEqual) c (zero_reg)) x y)
2685
+ (if-let $true (has_zicond))
2686
+ (rv_or
2687
+ (rv_czero_eqz x c)
2688
+ (rv_czero_nez y c)))
2689
+
2690
+ ;; It is still beneficial to emit the full compare instruction, and then the 3 instruction
2691
+ ;; select using zicond, so do that here as a last resort.
2692
+ (rule 1 (gen_select_xreg compare x y)
2693
+ (if-let $true (has_zicond))
2694
+ (gen_select_xreg (cmp_nez (lower_int_compare compare)) x y))
2695
+
2696
+ ;; In the base case we emit a conditional branch and a few moves.
2697
+
2698
+ (rule 0 (gen_select_xreg c x y)
2699
+ (let
2700
+ ((dst WritableReg (temp_writable_xreg))
2701
+ (_ Unit (emit (MInst.Select dst c x y))))
2702
+ (writable_reg_to_reg dst)))
2703
+
2704
+
2705
+ (decl gen_select_vreg (IntegerCompare VReg VReg) VReg)
2706
+ (rule (gen_select_vreg c x y)
2707
+ (let
2708
+ ((dst WritableReg (temp_writable_vreg))
2709
+ (_ Unit (emit (MInst.Select dst c (vreg_to_reg x) (vreg_to_reg y)))))
2710
+ (writable_reg_to_reg dst)))
2711
+ (decl gen_select_freg (IntegerCompare FReg FReg) FReg)
2712
+ (rule (gen_select_freg c x y)
2713
+ (let
2714
+ ((dst WritableReg (temp_writable_freg))
2715
+ (_ Unit (emit (MInst.Select dst c (freg_to_reg x) (freg_to_reg y)))))
2716
+ (writable_reg_to_reg dst)))
2717
+ (decl gen_select_regs (IntegerCompare ValueRegs ValueRegs) ValueRegs)
2718
+ (rule (gen_select_regs c x y)
2719
+ (let
2720
+ ((dst1 WritableReg (temp_writable_xreg))
2721
+ (dst2 WritableReg (temp_writable_xreg))
2722
+ (_ Unit (emit (MInst.Select (writable_value_regs dst1 dst2) c x y))))
2723
+ (value_regs dst1 dst2)))
2724
+
2725
+ (decl udf (TrapCode) InstOutput)
2726
+ (rule
2727
+ (udf code)
2728
+ (side_effect (SideEffectNoResult.Inst (MInst.Udf code))))
2729
+
2730
+ (decl load_op (Type) LoadOP)
2731
+ (extern constructor load_op load_op)
2732
+
2733
+ (decl store_op (Type) StoreOP)
2734
+ (extern constructor store_op store_op)
2735
+
2736
+
2737
+ ;;;; load extern name
2738
+ (decl load_ext_name (ExternalName i64) Reg)
2739
+ (extern constructor load_ext_name load_ext_name)
2740
+
2741
+ (decl elf_tls_get_addr (ExternalName) Reg)
2742
+ (rule (elf_tls_get_addr name)
2743
+ (let ((dst WritableReg (temp_writable_reg $I64))
2744
+ (_ Unit (emit (MInst.ElfTlsGetAddr dst name))))
2745
+ dst))
2746
+
2747
+ ;;; some float binary operation
2748
+ ;;; 1. need move into x register.
2749
+ ;;; 2. do the operation.
2750
+ ;;; 3. move back.
2751
+ (decl lower_float_binary (AluOPRRR FReg FReg Type) FReg)
2752
+ (rule
2753
+ (lower_float_binary op rs1 rs2 ty)
2754
+ (let ((x_rs1 XReg (move_f_to_x rs1 ty))
2755
+ (x_rs2 XReg (move_f_to_x rs2 ty))
2756
+ (tmp XReg (alu_rrr op x_rs1 x_rs2)))
2757
+ (move_x_to_f tmp (float_int_of_same_size ty))))
2758
+
2759
+
2760
+ (decl i128_sub (ValueRegs ValueRegs) ValueRegs)
2761
+ (rule
2762
+ (i128_sub x y )
2763
+ (let
2764
+ (;; low part.
2765
+ (low XReg (rv_sub (value_regs_get x 0) (value_regs_get y 0)))
2766
+ ;; compute borrow.
2767
+ (borrow XReg (rv_sltu (value_regs_get x 0) low))
2768
+ ;;
2769
+ (high_tmp XReg (rv_sub (value_regs_get x 1) (value_regs_get y 1)))
2770
+ ;;
2771
+ (high XReg (rv_sub high_tmp borrow)))
2772
+ (value_regs low high)))
2773
+
2774
+ ;; Consume a CmpResult, producing a branch on its result.
2775
+ (decl cond_br (IntegerCompare CondBrTarget CondBrTarget) SideEffectNoResult)
2776
+ (rule (cond_br cmp then else)
2777
+ (SideEffectNoResult.Inst
2778
+ (MInst.CondBr then else cmp)))
2779
+
2780
+ ;; Helper for emitting the `j` mnemonic, an unconditional jump to label.
2781
+ (decl rv_j (MachLabel) SideEffectNoResult)
2782
+ (rule (rv_j label)
2783
+ (SideEffectNoResult.Inst (MInst.Jal label)))
2784
+
2785
+ ;; Construct an IntegerCompare value.
2786
+ (decl int_compare (IntCC XReg XReg) IntegerCompare)
2787
+ (extern constructor int_compare int_compare)
2788
+
2789
+ ;; Extract the components of an `IntegerCompare`
2790
+ (decl int_compare_decompose (IntCC XReg XReg) IntegerCompare)
2791
+ (extern extractor infallible int_compare_decompose int_compare_decompose)
2792
+
2793
+ (decl label_to_br_target (MachLabel) CondBrTarget)
2794
+ (extern constructor label_to_br_target label_to_br_target)
2795
+ (convert MachLabel CondBrTarget label_to_br_target)
2796
+
2797
+ (decl cmp_eqz (XReg) IntegerCompare)
2798
+ (rule (cmp_eqz r) (int_compare (IntCC.Equal) r (zero_reg)))
2799
+
2800
+ (decl cmp_nez (XReg) IntegerCompare)
2801
+ (rule (cmp_nez r) (int_compare (IntCC.NotEqual) r (zero_reg)))
2802
+
2803
+ (decl cmp_eq (XReg XReg) IntegerCompare)
2804
+ (rule (cmp_eq rs1 rs2) (int_compare (IntCC.Equal) rs1 rs2))
2805
+
2806
+ (decl cmp_ne (XReg XReg) IntegerCompare)
2807
+ (rule (cmp_ne rs1 rs2) (int_compare (IntCC.NotEqual) rs1 rs2))
2808
+
2809
+ (decl cmp_lt (XReg XReg) IntegerCompare)
2810
+ (rule (cmp_lt rs1 rs2) (int_compare (IntCC.SignedLessThan) rs1 rs2))
2811
+
2812
+ (decl cmp_ltz (XReg) IntegerCompare)
2813
+ (rule (cmp_ltz rs) (int_compare (IntCC.SignedLessThan) rs (zero_reg)))
2814
+
2815
+ (decl cmp_gt (XReg XReg) IntegerCompare)
2816
+ (rule (cmp_gt rs1 rs2) (int_compare (IntCC.SignedGreaterThan) rs1 rs2))
2817
+
2818
+ (decl cmp_ge (XReg XReg) IntegerCompare)
2819
+ (rule (cmp_ge rs1 rs2) (int_compare (IntCC.SignedGreaterThanOrEqual) rs1 rs2))
2820
+
2821
+ (decl cmp_le (XReg XReg) IntegerCompare)
2822
+ (rule (cmp_le rs1 rs2) (int_compare (IntCC.SignedLessThanOrEqual) rs1 rs2))
2823
+
2824
+ (decl cmp_gtu (XReg XReg) IntegerCompare)
2825
+ (rule (cmp_gtu rs1 rs2) (int_compare (IntCC.UnsignedGreaterThan) rs1 rs2))
2826
+
2827
+ (decl cmp_geu (XReg XReg) IntegerCompare)
2828
+ (rule (cmp_geu rs1 rs2) (int_compare (IntCC.UnsignedGreaterThanOrEqual) rs1 rs2))
2829
+
2830
+ (decl cmp_ltu (XReg XReg) IntegerCompare)
2831
+ (rule (cmp_ltu rs1 rs2) (int_compare (IntCC.UnsignedLessThan) rs1 rs2))
2832
+
2833
+ (decl cmp_leu (XReg XReg) IntegerCompare)
2834
+ (rule (cmp_leu rs1 rs2) (int_compare (IntCC.UnsignedLessThanOrEqual) rs1 rs2))
2835
+
2836
+ ;; Helper to generate an `IntegerCompare` which represents the "truthy" value of
2837
+ ;; the input provided.
2838
+ ;;
2839
+ ;; This is used in `Select` and `brif` for example to generate conditional
2840
+ ;; branches. The returned comparison, when taken, represents that `Value` is
2841
+ ;; nonzero. When not taken the input `Value` is zero.
2842
+ (decl is_nonzero_cmp (Value) IntegerCompare)
2843
+
2844
+ ;; Base case - convert to a "truthy" value and compare it against zero.
2845
+ ;;
2846
+ ;; Note that non-64-bit types need to be extended since the upper bits from
2847
+ ;; Cranelift's point of view are undefined. Favor a zero extension for 8-bit
2848
+ ;; types because that's a single `andi` instruction, but favor sign-extension
2849
+ ;; for 16 and 32-bit types because many RISC-V which operate on the low 32-bits.
2850
+ ;; Additionally the base 64-bit ISA has a single instruction for sign-extending
2851
+ ;; from 32 to 64-bits which makes that a bit cheaper if used.
2852
+ ;; of registers sign-extend the results.
2853
+ (rule 0 (is_nonzero_cmp val @ (value_type (fits_in_64 _)))
2854
+ (cmp_nez (sext val)))
2855
+ (rule 1 (is_nonzero_cmp val @ (value_type $I8))
2856
+ (cmp_nez (zext val)))
2857
+ (rule 1 (is_nonzero_cmp val @ (value_type $I128))
2858
+ (cmp_nez (rv_or (value_regs_get val 0) (value_regs_get val 1))))
2859
+
2860
+ ;; If the input value is itself an `icmp` or `fcmp` we can avoid generating the
2861
+ ;; result of the comparison and instead move the comparison directly into the
2862
+ ;; `IntegerCompare` that's returned.
2863
+ (rule 2 (is_nonzero_cmp (maybe_uextend (icmp cc a b @ (value_type (fits_in_64 _)))))
2864
+ (icmp_to_int_compare cc a b))
2865
+ (rule 2 (is_nonzero_cmp (maybe_uextend (fcmp cc a @ (value_type ty) b)))
2866
+ (fcmp_to_float_compare cc ty a b))
2867
+
2868
+ ;; Creates an `IntegerCompare` from an `icmp` node's parts. This will extend
2869
+ ;; values as necessary to their full register width to perform the
2870
+ ;; comparison. The returned `IntegerCompare` is suitable to use in conditional
2871
+ ;; branches for example.
2872
+ ;;
2873
+ ;; Note that this should ideally only be used when the `IntegerCompare` returned
2874
+ ;; is fed into a branch. If `IntegerCompare` is materialized this will miss out
2875
+ ;; on optimizations to compare against constants using some native instructions.
2876
+ (decl icmp_to_int_compare (IntCC Value Value) IntegerCompare)
2877
+ (rule 0 (icmp_to_int_compare cc a b @ (value_type (fits_in_64 in_ty)))
2878
+ (int_compare cc (put_value_in_reg_for_icmp cc a) (put_value_in_reg_for_icmp cc b)))
2879
+ (rule 1 (icmp_to_int_compare cc a b @ (value_type $I128))
2880
+ (cmp_nez (lower_icmp_i128 cc a b)))
2881
+
2882
+ ;; Places a `Value` into a full register width to prepare for a comparison
2883
+ ;; using `IntCC`.
2884
+ ;;
2885
+ ;; This is largely a glorified means of choosing sign-extension or
2886
+ ;; zero-extension for the `Value` input.
2887
+ (decl put_value_in_reg_for_icmp (IntCC Value) XReg)
2888
+
2889
+ ;; Base cases, use the `cc` to determine whether to zero or sign extend.
2890
+ (rule 0 (put_value_in_reg_for_icmp cc val)
2891
+ (zext val))
2892
+ (rule 1 (put_value_in_reg_for_icmp cc val)
2893
+ (if (signed_cond_code cc))
2894
+ (sext val))
2895
+
2896
+ ;; For equality and inequality favor sign extension since it's generally
2897
+ ;; easier to perform sign extension on RV64 via native instructions. For 8-bit
2898
+ ;; types though use zero-extension since that's a single instruction `and`.
2899
+ (rule 2 (put_value_in_reg_for_icmp (IntCC.Equal) val @ (value_type (fits_in_64 _)))
2900
+ (sext val))
2901
+ (rule 2 (put_value_in_reg_for_icmp (IntCC.NotEqual) val @ (value_type (fits_in_64 _)))
2902
+ (sext val))
2903
+ (rule 3 (put_value_in_reg_for_icmp (IntCC.Equal) val @ (value_type $I8))
2904
+ (zext val))
2905
+ (rule 3 (put_value_in_reg_for_icmp (IntCC.NotEqual) val @ (value_type $I8))
2906
+ (zext val))
2907
+
2908
+ ;; As a special case use `x0` directly if a constant is 0.
2909
+ (rule 4 (put_value_in_reg_for_icmp _ (i64_from_iconst 0))
2910
+ (zero_reg))
2911
+
2912
+
2913
+ (decl partial lower_branch (Inst MachLabelSlice) Unit)
2914
+ (rule (lower_branch (jump _) (single_target label))
2915
+ (emit_side_effect (rv_j label)))
2916
+
2917
+ (rule (lower_branch (brif v _ _) (two_targets then else))
2918
+ (emit_side_effect (cond_br (is_nonzero_cmp v) then else)))
2919
+
2920
+ (decl lower_br_table (Reg MachLabelSlice) Unit)
2921
+ (extern constructor lower_br_table lower_br_table)
2922
+
2923
+ (rule (lower_branch (br_table index _) targets)
2924
+ (lower_br_table index targets))
2925
+
2926
+ (decl load_ra () Reg)
2927
+ (extern constructor load_ra load_ra)
2928
+
2929
+
2930
+ ;; Generates a bitcast instruction.
2931
+ ;; Args are: src, src_ty, dst_ty
2932
+ (decl gen_bitcast (Reg Type Type) Reg)
2933
+ (rule 5 (gen_bitcast r (ty_scalar_float src_ty) (ty_vec_fits_in_register _)) (rv_vfmv_sf r src_ty))
2934
+ (rule 4 (gen_bitcast r (ty_int_ref_scalar_64 src_ty) (ty_vec_fits_in_register _)) (rv_vmv_sx r src_ty))
2935
+ (rule 3 (gen_bitcast r (ty_vec_fits_in_register _) (ty_scalar_float dst_ty)) (rv_vfmv_fs r dst_ty))
2936
+ (rule 2 (gen_bitcast r (ty_vec_fits_in_register _) (ty_int_ref_scalar_64 dst_ty)) (rv_vmv_xs r dst_ty))
2937
+ (rule 1 (gen_bitcast r $F32 $I32) (rv_fmvxw r))
2938
+ (rule 1 (gen_bitcast r $F64 $I64) (rv_fmvxd r))
2939
+ (rule 1 (gen_bitcast r $I32 $F32) (rv_fmvwx r))
2940
+ (rule 1 (gen_bitcast r $I64 $F64) (rv_fmvdx r))
2941
+ (rule 1 (gen_bitcast r $I64 $R64) (copy_reg r $I64))
2942
+ (rule 1 (gen_bitcast r $R64 $I64) (copy_reg r $I64))
2943
+ (rule (gen_bitcast r _ _) r)
2944
+
2945
+ (decl move_f_to_x (FReg Type) XReg)
2946
+ (rule (move_f_to_x r $F32) (gen_bitcast r $F32 $I32))
2947
+ (rule (move_f_to_x r $F64) (gen_bitcast r $F64 $I64))
2948
+
2949
+ (decl move_x_to_f (XReg Type) FReg)
2950
+ (rule (move_x_to_f r $I32) (gen_bitcast r $I32 $F32))
2951
+ (rule (move_x_to_f r $I64) (gen_bitcast r $I64 $F64))
2952
+
2953
+ (decl float_int_of_same_size (Type) Type)
2954
+ (rule (float_int_of_same_size $F32) $I32)
2955
+ (rule (float_int_of_same_size $F64) $I64)
2956
+
2957
+
2958
+ (decl gen_brev8 (Reg Type) Reg)
2959
+ (rule 1
2960
+ (gen_brev8 rs _)
2961
+ (if-let $true (has_zbkb))
2962
+ (rv_brev8 rs))
2963
+ (rule
2964
+ (gen_brev8 rs ty)
2965
+ (if-let $false (has_zbkb))
2966
+ (let
2967
+ ((tmp WritableXReg (temp_writable_xreg))
2968
+ (tmp2 WritableXReg (temp_writable_xreg))
2969
+ (step WritableXReg (temp_writable_xreg))
2970
+ (rd WritableXReg (temp_writable_xreg))
2971
+ (_ Unit (emit (MInst.Brev8 rs ty step tmp tmp2 rd))))
2972
+ (writable_reg_to_reg rd)))
2973
+
2974
+ ;; Negates x
2975
+ ;; Equivalent to 0 - x
2976
+ (decl neg (Type ValueRegs) ValueRegs)
2977
+ (rule 1 (neg (fits_in_64 (ty_int ty)) val)
2978
+ (value_reg
2979
+ (rv_neg (value_regs_get val 0))))
2980
+
2981
+ (rule 2 (neg $I128 val)
2982
+ (i128_sub (value_regs_zero) val))
2983
+
2984
+
2985
+ ;; Builds an instruction sequence that traps if the comparison succeeds.
2986
+ (decl gen_trapif (IntCC XReg XReg TrapCode) InstOutput)
2987
+ (rule (gen_trapif cc a b trap_code)
2988
+ (side_effect (SideEffectNoResult.Inst (MInst.TrapIf a b cc trap_code))))
2989
+
2990
+ ;; Builds an instruction sequence that traps if the input is non-zero.
2991
+ (decl gen_trapnz (XReg TrapCode) InstOutput)
2992
+ (rule (gen_trapnz test trap_code)
2993
+ (gen_trapif (IntCC.NotEqual) test (zero_reg) trap_code))
2994
+
2995
+ ;; Builds an instruction sequence that traps if the input is zero.
2996
+ (decl gen_trapz (XReg TrapCode) InstOutput)
2997
+ (rule (gen_trapz test trap_code)
2998
+ (gen_trapif (IntCC.Equal) test (zero_reg) trap_code))
2999
+
3000
+ ;;;; Helpers for Emitting Calls ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3001
+
3002
+ (decl gen_call (SigRef ExternalName RelocDistance ValueSlice) InstOutput)
3003
+ (extern constructor gen_call gen_call)
3004
+
3005
+ (decl gen_call_indirect (SigRef Value ValueSlice) InstOutput)
3006
+ (extern constructor gen_call_indirect gen_call_indirect)
3007
+
3008
+ ;;; this is trying to imitate aarch64 `madd` instruction.
3009
+ (decl madd (XReg XReg XReg) XReg)
3010
+ (rule
3011
+ (madd n m a)
3012
+ (let
3013
+ ((t XReg (rv_mul n m)))
3014
+ (rv_add t a)))
3015
+
3016
+ ;;;; Helpers for bmask ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3017
+
3018
+ ;; Generates either 0 if `Value` is zero or -1 otherwise.
3019
+ (decl gen_bmask (Value) XReg)
3020
+
3021
+ ;; Base cases: use `snez` after a sign extension to ensure that the entire
3022
+ ;; register is defined. For i128 we test both the upper and lower half.
3023
+ (rule 0 (gen_bmask val @ (value_type (fits_in_64 _)))
3024
+ (let ((non_zero XReg (rv_snez (sext val))))
3025
+ (rv_neg non_zero)))
3026
+ (rule 1 (gen_bmask val @ (value_type $I128))
3027
+ (let ((non_zero XReg (rv_snez (rv_or (value_regs_get val 0) (value_regs_get val 1)))))
3028
+ (rv_neg non_zero)))
3029
+
3030
+ ;; If the input value is an `icmp` or an `fcmp` directly then the `snez` can
3031
+ ;; be omitted because the result of the icmp or fcmp is a 0 or 1 directly. This
3032
+ ;; means we can go straight to the `neg` instruction to produce the final
3033
+ ;; result.
3034
+ (rule 2 (gen_bmask val @ (maybe_uextend (icmp _ _ _))) (rv_neg val))
3035
+ (rule 2 (gen_bmask val @ (maybe_uextend (fcmp _ _ _))) (rv_neg val))
3036
+
3037
+ (decl lower_bmask (Value Type) ValueRegs)
3038
+ (rule 0 (lower_bmask val (fits_in_64 _))
3039
+ (value_reg (gen_bmask val)))
3040
+ (rule 1 (lower_bmask val $I128)
3041
+ (let ((bits XReg (gen_bmask val)))
3042
+ (value_regs bits bits)))
3043
+
3044
+ ;;;; Helpers for physical registers ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3045
+
3046
+ (decl gen_mov_from_preg (PReg) Reg)
3047
+
3048
+ (rule
3049
+ (gen_mov_from_preg rm)
3050
+ (let ((rd WritableXReg (temp_writable_xreg))
3051
+ (_ Unit (emit (MInst.MovFromPReg rd rm))))
3052
+ rd))
3053
+
3054
+ ;; Copy a register of the given type to a new register.
3055
+ ;;
3056
+ ;; Generally, regalloc should take care of this kind of thing for us. This is
3057
+ ;; only useful for implementing things like `bitcast` from an `r64` to an `i64`
3058
+ ;; to avoid conflicting constraints on a single aliased value by splitting the
3059
+ ;; value into two parts.
3060
+ (decl copy_reg (XReg Type) XReg)
3061
+ (rule (copy_reg src ty)
3062
+ (let ((dst WritableXReg (temp_writable_xreg))
3063
+ (_ Unit (emit (MInst.Mov dst
3064
+ src
3065
+ ty))))
3066
+ dst))
3067
+
3068
+ (decl fp_reg () PReg)
3069
+ (extern constructor fp_reg fp_reg)
3070
+
3071
+ (decl sp_reg () PReg)
3072
+ (extern constructor sp_reg sp_reg)
3073
+
3074
+ ;; Extractor that matches all registers, except the zero register
3075
+ (decl non_zero_reg () XReg)
3076
+ (extern extractor non_zero_reg is_non_zero_reg)
3077
+
3078
+ ;; Helper for creating the zero register.
3079
+ (decl zero_reg () XReg)
3080
+ (extern constructor zero_reg zero_reg)
3081
+ (extern extractor zero_reg is_zero_reg)
3082
+
3083
+ (decl value_regs_zero () ValueRegs)
3084
+ (rule (value_regs_zero)
3085
+ (value_regs (imm $I64 0) (imm $I64 0)))
3086
+
3087
+ (decl writable_zero_reg () WritableReg)
3088
+ (extern constructor writable_zero_reg writable_zero_reg)
3089
+
3090
+
3091
+ ;;;; Helpers for floating point comparisons ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3092
+
3093
+ (type FloatCompare (enum
3094
+ ;; The comparison succeeded if `r` is one
3095
+ (One (r XReg))
3096
+ ;; The comparison succeeded if `r` is zero
3097
+ (Zero (r XReg))
3098
+ ))
3099
+
3100
+ (decl float_compare_invert (FloatCompare) FloatCompare)
3101
+ (rule (float_compare_invert (FloatCompare.One r)) (FloatCompare.Zero r))
3102
+ (rule (float_compare_invert (FloatCompare.Zero r)) (FloatCompare.One r))
3103
+
3104
+ (decl float_to_int_compare (FloatCompare) IntegerCompare)
3105
+ (rule (float_to_int_compare (FloatCompare.One r)) (cmp_nez r))
3106
+ (rule (float_to_int_compare (FloatCompare.Zero r)) (cmp_eqz r))
3107
+ (convert FloatCompare IntegerCompare float_to_int_compare)
3108
+
3109
+ ;; Compare two floating point numbers and return a zero/non-zero result.
3110
+ (decl fcmp_to_float_compare (FloatCC Type FReg FReg) FloatCompare)
3111
+
3112
+ ;; Direct codegen for unordered comparisons is not that efficient, so invert
3113
+ ;; the comparison to get an ordered comparison and generate that. Then invert
3114
+ ;; the result to produce the final fcmp result.
3115
+ (rule 0 (fcmp_to_float_compare cc ty a b)
3116
+ (if-let $true (floatcc_unordered cc))
3117
+ (float_compare_invert (fcmp_to_float_compare (floatcc_complement cc) ty a b)))
3118
+
3119
+ ;; a is not nan && b is not nan
3120
+ (rule 1 (fcmp_to_float_compare (FloatCC.Ordered) ty a b)
3121
+ (FloatCompare.One (rv_and (is_not_nan ty a) (is_not_nan ty b))))
3122
+
3123
+ (decl is_not_nan (Type FReg) XReg)
3124
+ (rule (is_not_nan ty a) (rv_feq ty a a))
3125
+
3126
+ ;; a == b
3127
+ (rule 1 (fcmp_to_float_compare (FloatCC.Equal) ty a b)
3128
+ (FloatCompare.One (rv_feq ty a b)))
3129
+
3130
+ ;; a != b
3131
+ ;; == !(a == b)
3132
+ (rule 1 (fcmp_to_float_compare (FloatCC.NotEqual) ty a b)
3133
+ (FloatCompare.Zero (rv_feq ty a b)))
3134
+
3135
+ ;; a < b || a > b
3136
+ (rule 1 (fcmp_to_float_compare (FloatCC.OrderedNotEqual) ty a b)
3137
+ (FloatCompare.One (rv_or (rv_flt ty a b) (rv_fgt ty a b))))
3138
+
3139
+ ;; a < b
3140
+ (rule 1 (fcmp_to_float_compare (FloatCC.LessThan) ty a b)
3141
+ (FloatCompare.One (rv_flt ty a b)))
3142
+
3143
+ ;; a <= b
3144
+ (rule 1 (fcmp_to_float_compare (FloatCC.LessThanOrEqual) ty a b)
3145
+ (FloatCompare.One (rv_fle ty a b)))
3146
+
3147
+ ;; a > b
3148
+ (rule 1 (fcmp_to_float_compare (FloatCC.GreaterThan) ty a b)
3149
+ (FloatCompare.One (rv_fgt ty a b)))
3150
+
3151
+ ;; a >= b
3152
+ (rule 1 (fcmp_to_float_compare (FloatCC.GreaterThanOrEqual) ty a b)
3153
+ (FloatCompare.One (rv_fge ty a b)))