udb 0.1.16 → 0.1.18
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/.data/cfgs/example_rv64_with_overlay.yaml +157 -2
- data/.data/cfgs/mc100-32-full-example.yaml +6 -0
- data/.data/cfgs/profile/RVA23S64.yaml +1 -1
- data/.data/cfgs/profile/RVA23p1S64.yaml +217 -0
- data/.data/cfgs/profile/RVB23S64.yaml +1 -1
- data/.data/cfgs/profile/RVB23p1S64.yaml +179 -0
- data/.data/cfgs/qc_iu.yaml +14 -0
- data/.data/cfgs/rv32-riscv-tests.yaml +143 -0
- data/.data/cfgs/rv32-vector.yaml +144 -1
- data/.data/cfgs/rv64-riscv-tests.yaml +143 -0
- data/.data/cfgs/rv64-vector.yaml +145 -2
- data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.mva01s.yaml +2 -2
- data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.mvsa01.yaml +2 -2
- data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.pop.yaml +2 -2
- data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.popret.yaml +2 -2
- data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.popretz.yaml +2 -2
- data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.push.yaml +2 -2
- data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.pushfp.yaml +2 -2
- data/.data/spec/schemas/README.adoc +4 -1
- data/.data/spec/schemas/csr_schema.json +2 -2
- data/.data/spec/schemas/schema_defs.json +4 -1
- data/.data/spec/std/isa/csr/H/hgeie.yaml +38 -0
- data/.data/spec/std/isa/csr/H/hgeip.yaml +33 -0
- data/.data/spec/std/isa/csr/H/hideleg.yaml +120 -0
- data/.data/spec/std/isa/csr/H/hie.yaml +74 -0
- data/.data/spec/std/isa/csr/H/hip.yaml +88 -0
- data/.data/spec/std/isa/csr/H/hvip.yaml +46 -0
- data/.data/spec/std/isa/csr/H/vsie.yaml +86 -0
- data/.data/spec/std/isa/csr/H/vsip.yaml +98 -0
- data/.data/spec/std/isa/csr/H/vsscratch.yaml +29 -0
- data/.data/spec/std/isa/csr/I/mcounteren.layout +7 -0
- data/.data/spec/std/isa/csr/I/mcounteren.yaml +7 -0
- data/.data/spec/std/isa/csr/I/pmpaddr0.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr1.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr10.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr11.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr12.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr13.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr14.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr15.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr16.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr17.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr18.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr19.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr2.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr20.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr21.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr22.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr23.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr24.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr25.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr26.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr27.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr28.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr29.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr3.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr30.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr31.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr32.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr33.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr34.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr35.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr36.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr37.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr38.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr39.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr4.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr40.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr41.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr42.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr43.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr44.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr45.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr46.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr47.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr48.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr49.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr5.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr50.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr51.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr52.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr53.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr54.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr55.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr56.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr57.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr58.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr59.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr6.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr60.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr61.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr62.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr63.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr7.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr8.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr9.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddrN.layout +7 -7
- data/.data/spec/std/isa/csr/Smcdeleg/scountinhibit.layout +111 -0
- data/.data/spec/std/isa/csr/Smcdeleg/scountinhibit.yaml +840 -0
- data/.data/spec/std/isa/csr/Smcntrpmf/mcyclecfg.yaml +2 -0
- data/.data/spec/std/isa/csr/Smcntrpmf/mcyclecfgh.yaml +2 -0
- data/.data/spec/std/isa/csr/Smcntrpmf/minstretcfg.yaml +2 -0
- data/.data/spec/std/isa/csr/Smcntrpmf/minstretcfgh.yaml +2 -0
- data/.data/spec/std/isa/csr/Smcsrind/mireg.yaml +2 -2
- data/.data/spec/std/isa/csr/Smcsrind/mireg2.yaml +2 -2
- data/.data/spec/std/isa/csr/Smcsrind/mireg3.yaml +2 -2
- data/.data/spec/std/isa/csr/Smcsrind/mireg4.yaml +2 -2
- data/.data/spec/std/isa/csr/Smcsrind/mireg5.yaml +2 -2
- data/.data/spec/std/isa/csr/Smcsrind/mireg6.yaml +2 -2
- data/.data/spec/std/isa/csr/Smcsrind/sireg.yaml +2 -2
- data/.data/spec/std/isa/csr/Smcsrind/sireg2.yaml +2 -2
- data/.data/spec/std/isa/csr/Smcsrind/sireg3.yaml +2 -2
- data/.data/spec/std/isa/csr/Smcsrind/sireg4.yaml +2 -2
- data/.data/spec/std/isa/csr/Smcsrind/sireg5.yaml +2 -2
- data/.data/spec/std/isa/csr/Smcsrind/sireg6.yaml +2 -2
- data/.data/spec/std/isa/csr/Smcsrind/vsireg.yaml +2 -2
- data/.data/spec/std/isa/csr/Smcsrind/vsireg2.yaml +2 -2
- data/.data/spec/std/isa/csr/Smcsrind/vsireg3.yaml +2 -2
- data/.data/spec/std/isa/csr/Smcsrind/vsireg4.yaml +2 -2
- data/.data/spec/std/isa/csr/Smcsrind/vsireg5.yaml +2 -2
- data/.data/spec/std/isa/csr/Smcsrind/vsireg6.yaml +2 -2
- data/.data/spec/std/isa/csr/Smctr/sctrctl.yaml +1 -1
- data/.data/spec/std/isa/csr/Smctr/sctrdepth.yaml +43 -0
- data/.data/spec/std/isa/csr/Smctr/sctrstatus.yaml +37 -0
- data/.data/spec/std/isa/csr/Smctr/vsctrctl.yaml +3 -1
- data/.data/spec/std/isa/csr/Sscofpmf/scountovf.layout +7 -0
- data/.data/spec/std/isa/csr/Sscofpmf/scountovf.yaml +7 -0
- data/.data/spec/std/isa/csr/Sstc/stimecmp.yaml +42 -0
- data/.data/spec/std/isa/csr/Sstc/stimecmph.yaml +43 -0
- data/.data/spec/std/isa/csr/Sstc/vstimecmp.yaml +45 -0
- data/.data/spec/std/isa/csr/Sstc/vstimecmph.yaml +46 -0
- data/.data/spec/std/isa/csr/V/vcsr.yaml +1 -1
- data/.data/spec/std/isa/csr/V/vl.yaml +1 -1
- data/.data/spec/std/isa/csr/V/vlenb.yaml +1 -1
- data/.data/spec/std/isa/csr/V/vstart.yaml +1 -1
- data/.data/spec/std/isa/csr/V/vtype.yaml +20 -1
- data/.data/spec/std/isa/csr/V/vxrm.yaml +1 -1
- data/.data/spec/std/isa/csr/V/vxsat.yaml +1 -1
- data/.data/spec/std/isa/csr/Zicntr/mcountinhibit.layout +1 -15
- data/.data/spec/std/isa/csr/Zicntr/mcountinhibit.yaml +29 -267
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter10.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter10h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter11.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter11h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter12.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter12h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter13.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter13h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter14.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter14h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter15.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter15h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter16.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter16h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter17.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter17h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter18.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter18h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter19.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter19h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter20.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter20h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter21.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter21h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter22.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter22h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter23.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter23h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter24.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter24h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter25.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter25h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter26.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter26h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter27.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter27h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter28.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter28h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter29.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter29h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter3.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter30.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter30h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter31.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter31h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter3h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter4.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter4h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter5.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter5h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter6.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter6h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter7.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter7h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter8.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter8h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter9.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounter9h.yaml +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounterN.layout +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmcounterNh.layout +2 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent10.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent10h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent11.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent11h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent12.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent12h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent13.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent13h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent14.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent14h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent15.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent15h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent16.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent16h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent17.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent17h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent18.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent18h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent19.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent19h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent20.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent20h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent21.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent21h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent22.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent22h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent23.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent23h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent24.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent24h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent25.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent25h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent26.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent26h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent27.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent27h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent28.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent28h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent29.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent29h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent3.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent30.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent30h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent31.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent31h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent3h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent4.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent4h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent5.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent5h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent6.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent6h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent7.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent7h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent8.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent8h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent9.yaml +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmevent9h.yaml +4 -4
- data/.data/spec/std/isa/csr/Zihpm/mhpmeventN.layout +4 -7
- data/.data/spec/std/isa/csr/Zihpm/mhpmeventNh.layout +4 -4
- data/.data/spec/std/isa/csr/Zkr/seed.yaml +75 -0
- data/.data/spec/std/isa/csr/hcontext.yaml +4 -4
- data/.data/spec/std/isa/csr/mcontext.yaml +4 -4
- data/.data/spec/std/isa/csr/mcycle.yaml +2 -0
- data/.data/spec/std/isa/csr/mcycleh.yaml +2 -0
- data/.data/spec/std/isa/csr/medeleg.yaml +72 -36
- data/.data/spec/std/isa/csr/menvcfg.yaml +12 -1
- data/.data/spec/std/isa/csr/menvcfgh.yaml +12 -0
- data/.data/spec/std/isa/csr/mideleg.yaml +37 -12
- data/.data/spec/std/isa/csr/mie.yaml +12 -6
- data/.data/spec/std/isa/csr/minstret.yaml +2 -0
- data/.data/spec/std/isa/csr/minstreth.yaml +2 -0
- data/.data/spec/std/isa/csr/mip.yaml +15 -7
- data/.data/spec/std/isa/csr/misa.yaml +14 -30
- data/.data/spec/std/isa/csr/mseccfg.yaml +27 -1
- data/.data/spec/std/isa/csr/mstatus.yaml +10 -4
- data/.data/spec/std/isa/csr/schema.adoc +10 -4
- data/.data/spec/std/isa/csr/scontext.yaml +8 -4
- data/.data/spec/std/isa/csr/senvcfg.yaml +6 -12
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- data/.data/spec/std/isa/inst/Zabha/amoand.h.yaml +1 -5
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- data/.data/spec/std/isa/inst/Zabha/amomax.b.rl.yaml +1 -5
- data/.data/spec/std/isa/inst/Zabha/amomax.b.yaml +1 -5
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- data/.data/spec/std/isa/inst/Zabha/amomax.h.rl.yaml +1 -5
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- data/.data/spec/std/isa/inst/Zabha/amomaxu.b.rl.yaml +1 -5
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- data/.data/spec/std/isa/inst/Zabha/amomaxu.h.rl.yaml +1 -5
- data/.data/spec/std/isa/inst/Zabha/amomaxu.h.yaml +1 -5
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- data/.data/spec/std/isa/inst/Zabha/amomin.b.rl.yaml +1 -5
- data/.data/spec/std/isa/inst/Zabha/amomin.b.yaml +1 -5
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- data/.data/spec/std/isa/inst/Zabha/amomin.h.rl.yaml +1 -5
- data/.data/spec/std/isa/inst/Zabha/amomin.h.yaml +1 -5
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- data/.data/spec/std/isa/inst/Zabha/amominu.b.rl.yaml +1 -5
- data/.data/spec/std/isa/inst/Zabha/amominu.b.yaml +1 -5
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- data/.data/spec/std/isa/inst/Zabha/amominu.h.rl.yaml +1 -5
- data/.data/spec/std/isa/inst/Zabha/amominu.h.yaml +1 -5
- data/.data/spec/std/isa/inst/Zabha/amoor.b.aq.yaml +1 -5
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- data/.data/spec/std/isa/inst/Zabha/amoor.b.rl.yaml +1 -5
- data/.data/spec/std/isa/inst/Zabha/amoor.b.yaml +1 -5
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- data/.data/spec/std/isa/inst/Zabha/amoor.h.rl.yaml +1 -5
- data/.data/spec/std/isa/inst/Zabha/amoor.h.yaml +1 -5
- data/.data/spec/std/isa/inst/Zabha/amoswap.b.aq.yaml +1 -5
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- data/.data/spec/std/isa/inst/Zabha/amoswap.b.rl.yaml +1 -5
- data/.data/spec/std/isa/inst/Zabha/amoswap.b.yaml +1 -5
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- data/.data/spec/std/isa/inst/Zabha/amoswap.h.rl.yaml +1 -5
- data/.data/spec/std/isa/inst/Zabha/amoswap.h.yaml +1 -5
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- data/.data/spec/std/isa/inst/Zabha/amoxor.b.rl.yaml +1 -5
- data/.data/spec/std/isa/inst/Zabha/amoxor.b.yaml +1 -5
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- data/.data/spec/std/isa/inst/Zabha/amoxor.h.rl.yaml +1 -5
- data/.data/spec/std/isa/inst/Zabha/amoxor.h.yaml +1 -5
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- data/.data/spec/std/isa/inst/Zalrsc/lr.d.rl.yaml +0 -6
- data/.data/spec/std/isa/inst/Zalrsc/lr.d.yaml +0 -6
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- data/.data/spec/std/isa/inst/Zalrsc/lr.w.aqrl.yaml +1 -11
- data/.data/spec/std/isa/inst/Zalrsc/lr.w.rl.yaml +1 -11
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- data/.data/spec/std/isa/inst/Zalrsc/sc.d.aqrl.yaml +4 -10
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- data/.data/spec/std/isa/inst/Zba/sh1add.yaml +0 -4
- data/.data/spec/std/isa/inst/Zba/sh2add.uw.yaml +0 -4
- data/.data/spec/std/isa/inst/Zba/sh2add.yaml +0 -4
- data/.data/spec/std/isa/inst/Zba/sh3add.uw.yaml +0 -4
- data/.data/spec/std/isa/inst/Zba/sh3add.yaml +0 -4
- data/.data/spec/std/isa/inst/Zba/slli.uw.yaml +0 -4
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- data/.data/spec/std/isa/inst/Zbb/clzw.yaml +0 -4
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- data/.data/spec/std/isa/inst/Zbb/cpopw.yaml +0 -4
- data/.data/spec/std/isa/inst/Zbb/ctz.yaml +0 -4
- data/.data/spec/std/isa/inst/Zbb/ctzw.yaml +0 -4
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- data/.data/spec/std/isa/inst/Zbb/maxu.yaml +0 -4
- data/.data/spec/std/isa/inst/Zbb/min.yaml +0 -4
- data/.data/spec/std/isa/inst/Zbb/minu.yaml +0 -4
- data/.data/spec/std/isa/inst/Zbb/orc.b.yaml +0 -4
- data/.data/spec/std/isa/inst/Zbb/sext.b.yaml +0 -4
- data/.data/spec/std/isa/inst/Zbb/sext.h.yaml +0 -4
- data/.data/spec/std/isa/inst/Zbb/zext.h.yaml +0 -4
- data/.data/spec/std/isa/inst/Zbc/clmulr.yaml +0 -4
- data/.data/spec/std/isa/inst/{B → Zbkc}/clmul.yaml +1 -7
- data/.data/spec/std/isa/inst/{B → Zbkc}/clmulh.yaml +1 -7
- data/.data/spec/std/isa/inst/Zbs/bclr.yaml +0 -4
- data/.data/spec/std/isa/inst/Zbs/bclri.yaml +0 -4
- data/.data/spec/std/isa/inst/Zbs/bext.yaml +0 -4
- data/.data/spec/std/isa/inst/Zbs/bexti.yaml +0 -4
- data/.data/spec/std/isa/inst/Zbs/binv.yaml +0 -4
- data/.data/spec/std/isa/inst/Zbs/binvi.yaml +0 -4
- data/.data/spec/std/isa/inst/Zbs/bset.yaml +0 -4
- data/.data/spec/std/isa/inst/Zbs/bseti.yaml +0 -4
- data/.data/spec/std/isa/inst/Zcb/c.lbu.yaml +2 -2
- data/.data/spec/std/isa/inst/Zcb/c.lh.yaml +2 -2
- data/.data/spec/std/isa/inst/Zcb/c.lhu.yaml +2 -2
- data/.data/spec/std/isa/inst/Zcb/c.mul.yaml +2 -6
- data/.data/spec/std/isa/inst/Zcb/c.not.yaml +2 -2
- data/.data/spec/std/isa/inst/Zcb/c.sb.yaml +2 -2
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- data/.data/spec/std/isa/inst/Zcb/c.zext.w.yaml +2 -6
- data/.data/spec/std/isa/inst/Zcd/c.fld.yaml +3 -3
- data/.data/spec/std/isa/inst/Zcd/c.fldsp.yaml +4 -4
- data/.data/spec/std/isa/inst/Zcd/c.fsd.yaml +3 -3
- data/.data/spec/std/isa/inst/Zcd/c.fsdsp.yaml +4 -4
- data/.data/spec/std/isa/inst/Zcf/c.flw.yaml +3 -3
- data/.data/spec/std/isa/inst/Zcf/c.flwsp.yaml +4 -4
- data/.data/spec/std/isa/inst/Zcf/c.fsw.yaml +3 -3
- data/.data/spec/std/isa/inst/Zcf/c.fswsp.yaml +4 -4
- data/.data/spec/std/isa/inst/Zcmp/cm.mva01s.yaml +2 -2
- data/.data/spec/std/isa/inst/Zcmp/cm.mvsa01.yaml +2 -2
- data/.data/spec/std/isa/inst/Zcmp/cm.pop.yaml +2 -2
- data/.data/spec/std/isa/inst/Zcmp/cm.popret.yaml +2 -2
- data/.data/spec/std/isa/inst/Zcmp/cm.popretz.yaml +2 -2
- data/.data/spec/std/isa/inst/Zcmp/cm.push.yaml +2 -2
- data/.data/spec/std/isa/inst/Zfh/fcvt.h.s.yaml +28 -20
- data/.data/spec/std/isa/inst/Zfh/fcvt.s.h.yaml +35 -20
- data/.data/spec/std/isa/inst/Zicbom/cbo.clean.yaml +2 -2
- data/.data/spec/std/isa/inst/Zicbom/cbo.flush.yaml +2 -2
- data/.data/spec/std/isa/inst/Zicbom/cbo.inval.yaml +2 -2
- data/.data/spec/std/isa/inst/Zicboz/cbo.zero.yaml +2 -2
- data/.data/spec/std/isa/inst/Zvabd/vabd.vv.yaml +3 -3
- data/.data/spec/std/isa/inst/Zvabd/vabd.vx.yaml +69 -0
- data/.data/spec/std/isa/inst/Zvabd/vabdu.vv.yaml +3 -3
- data/.data/spec/std/isa/inst/Zvabd/{vabs.v.yaml → vabdu.vx.yaml} +17 -11
- data/.data/spec/std/isa/inst/Zvabd/vwabda.vv.yaml +1 -1
- data/.data/spec/std/isa/inst/Zvabd/vwabda.vx.yaml +73 -0
- data/.data/spec/std/isa/inst/Zvabd/vwabdau.vv.yaml +1 -1
- data/.data/spec/std/isa/inst/Zvabd/vwabdau.vx.yaml +74 -0
- data/.data/spec/std/isa/inst/Zvfbdota32f/vfbdota.vv.yaml +68 -0
- data/.data/spec/std/isa/inst/Zvfbfmin/vfncvtbf16.f.f.w.yaml +3 -1
- data/.data/spec/std/isa/inst/Zvfbfmin/vfwcvtbf16.f.f.v.yaml +3 -1
- data/.data/spec/std/isa/inst/Zvfofp4min/vfext.vf2.yaml +35 -0
- data/.data/spec/std/isa/inst/Zvfofp8min/vfncvt.f.f.q.yaml +31 -0
- data/.data/spec/std/isa/inst/Zvfofp8min/vfncvt.sat.f.f.q.yaml +32 -0
- data/.data/spec/std/isa/inst/Zvfofp8min/vfncvtbf16.sat.f.f.w.yaml +32 -0
- data/.data/spec/std/isa/inst/Zvzip/vpaire.vv.yaml +36 -0
- data/.data/spec/std/isa/inst/Zvzip/vpairo.vv.yaml +37 -0
- data/.data/spec/std/isa/inst/Zvzip/vunzipe.v.yaml +33 -0
- data/.data/spec/std/isa/inst/Zvzip/vunzipo.v.yaml +33 -0
- data/.data/spec/std/isa/inst/Zvzip/vzip.vv.yaml +37 -0
- data/.data/spec/std/isa/isa/builtin_functions.idl +54 -1
- data/.data/spec/std/isa/isa/globals.isa +117 -5
- data/.data/spec/std/isa/isa/util.idl +1 -0
- data/.data/spec/std/isa/param/COUNTINHIBIT_EN.yaml +2 -10
- data/.data/spec/std/isa/param/HCONTEXT_IMPLEMENTED.yaml +29 -0
- data/.data/spec/std/isa/param/HCOUNTENABLE_EN.yaml +2 -5
- data/.data/spec/std/isa/param/HPM_COUNTER10_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER11_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER12_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER13_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER14_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER15_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER16_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER17_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER18_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER19_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER20_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER21_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER22_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER23_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER24_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER25_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER26_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER27_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER28_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER29_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER30_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER31_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER3_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER4_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER5_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER6_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER7_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER8_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTER9_WIDTH.yaml +29 -0
- data/.data/spec/std/isa/param/HPM_COUNTERN_WIDTH.layout +27 -0
- data/.data/spec/std/isa/param/HW_MSTATUS_FS_DIRTY_UPDATE.yaml +2 -4
- data/.data/spec/std/isa/param/HW_MSTATUS_VS_DIRTY_UPDATE.yaml +2 -4
- data/.data/spec/std/isa/param/LRSC_FAIL_ON_NON_EXACT_LRSC.yaml +1 -1
- data/.data/spec/std/isa/param/LRSC_FAIL_ON_VA_SYNONYM.yaml +1 -1
- data/.data/spec/std/isa/param/LRSC_MISALIGNED_BEHAVIOR.yaml +4 -4
- data/.data/spec/std/isa/param/LRSC_RESERVATION_STRATEGY.yaml +1 -1
- data/.data/spec/std/isa/param/{MCONTEXT_AVAILABLE.yaml → MCONTEXT_IMPLEMENTED.yaml} +3 -3
- data/.data/spec/std/isa/param/MCOUNTENABLE_EN.yaml +2 -5
- data/.data/spec/std/isa/param/MEDELEG_DELEGATABLE.yaml +121 -0
- data/.data/spec/std/isa/param/MEI_INTR_IMPL.yaml +28 -0
- data/.data/spec/std/isa/param/MIDELEG_DELEGATABLE.yaml +177 -0
- data/.data/spec/std/isa/param/MSI_INTR_IMPL.yaml +28 -0
- data/.data/spec/std/isa/param/MSTATUS_FS_LEGAL_VALUES.yaml +8 -15
- data/.data/spec/std/isa/param/MSTATUS_VS_LEGAL_VALUES.yaml +7 -15
- data/.data/spec/std/isa/param/MTI_INTR_IMPL.yaml +28 -0
- data/.data/spec/std/isa/param/MTVAL_WIDTH.yaml +17 -5
- data/.data/spec/std/isa/param/MUTABLE_MISA_A.yaml +1 -1
- data/.data/spec/std/isa/param/MUTABLE_MISA_B.yaml +1 -1
- data/.data/spec/std/isa/param/MUTABLE_MISA_C.yaml +1 -1
- data/.data/spec/std/isa/param/MUTABLE_MISA_D.yaml +1 -1
- data/.data/spec/std/isa/param/MUTABLE_MISA_F.yaml +1 -1
- data/.data/spec/std/isa/param/MUTABLE_MISA_M.yaml +1 -1
- data/.data/spec/std/isa/param/MUTABLE_MISA_Q.yaml +1 -1
- data/.data/spec/std/isa/param/MUTABLE_MISA_U.yaml +1 -1
- data/.data/spec/std/isa/param/MUTABLE_MISA_V.yaml +1 -1
- data/.data/spec/std/isa/param/{HCONTEXT_AVAILABLE.yaml → NON_STANDARD_EXTENSION_IMPLEMENTED.yaml} +5 -7
- data/.data/spec/std/isa/param/NUM_EXTERNAL_GUEST_INTERRUPTS.yaml +1 -1
- data/.data/spec/std/isa/param/NUM_PMP_ENTRIES.yaml +1 -1
- data/.data/spec/std/isa/param/REPORT_CAUSE_IN_MTVAL_ON_LANDING_PAD_SOFTWARE_CHECK.yaml +1 -1
- data/.data/spec/std/isa/param/REPORT_CAUSE_IN_STVAL_ON_LANDING_PAD_SOFTWARE_CHECK.yaml +1 -1
- data/.data/spec/std/isa/param/REPORT_CAUSE_IN_VSTVAL_ON_LANDING_PAD_SOFTWARE_CHECK.yaml +1 -1
- data/.data/spec/std/isa/param/SCONTEXT_IMPLEMENTED.yaml +18 -0
- data/.data/spec/std/isa/param/SCOUNTENABLE_EN.yaml +2 -6
- data/.data/spec/std/isa/param/SCTRDEPTH_DEPTH_LEGAL_VALUES.yaml +27 -0
- data/.data/spec/std/isa/param/SDTRIG_BREAKPOINT_REENTRANCY.yaml +45 -0
- data/.data/spec/std/isa/param/SDTRIG_ETRIGGER_SUPPORTED_EXCEPTIONS.yaml +37 -0
- data/.data/spec/std/isa/param/SDTRIG_ETRIGGER_SUPPORTED_TRIGGERS.yaml +25 -0
- data/.data/spec/std/isa/param/SDTRIG_ICOUNT_COUNT_HARDWIRED_1.yaml +23 -0
- data/.data/spec/std/isa/param/SDTRIG_ICOUNT_SELF_WRITE_SETS_PENDING.yaml +23 -0
- data/.data/spec/std/isa/param/SDTRIG_ICOUNT_SUPPORTED_TRIGGERS.yaml +25 -0
- data/.data/spec/std/isa/param/SDTRIG_ITRIGGER_SUPPORTED_INTERRUPTS.yaml +37 -0
- data/.data/spec/std/isa/param/SDTRIG_ITRIGGER_SUPPORTED_TRIGGERS.yaml +25 -0
- data/.data/spec/std/isa/param/SDTRIG_MAX_CHAIN_LENGTH.yaml +33 -0
- data/.data/spec/std/isa/param/SDTRIG_MCONTROL6_EXECUTE_WRITABLE.yaml +22 -0
- data/.data/spec/std/isa/param/SDTRIG_MCONTROL6_LOAD_WRITABLE.yaml +22 -0
- data/.data/spec/std/isa/param/SDTRIG_MCONTROL6_MASKMAX6.yaml +26 -0
- data/.data/spec/std/isa/param/SDTRIG_MCONTROL6_MATCH_LEGAL_VALUES.yaml +41 -0
- data/.data/spec/std/isa/param/SDTRIG_MCONTROL6_SELECT_WRITABLE.yaml +22 -0
- data/.data/spec/std/isa/param/SDTRIG_MCONTROL6_SIZE_LEGAL_VALUES.yaml +38 -0
- data/.data/spec/std/isa/param/SDTRIG_MCONTROL6_STORE_WRITABLE.yaml +22 -0
- data/.data/spec/std/isa/param/SDTRIG_MCONTROL6_SUPPORTED_TRIGGERS.yaml +25 -0
- data/.data/spec/std/isa/param/SDTRIG_M_WRITABLE.yaml +17 -0
- data/.data/spec/std/isa/param/SDTRIG_NUM_TRIGGERS.yaml +22 -0
- data/.data/spec/std/isa/param/SDTRIG_S_WRITABLE.yaml +19 -0
- data/.data/spec/std/isa/param/SDTRIG_TEXTRA_MHSELECT_MCONTEXT_MATCH.yaml +24 -0
- data/.data/spec/std/isa/param/SDTRIG_TEXTRA_MHSELECT_VMID_MATCH.yaml +23 -0
- data/.data/spec/std/isa/param/SDTRIG_TEXTRA_MHVALUE_LEN.yaml +26 -0
- data/.data/spec/std/isa/param/SDTRIG_TEXTRA_SSELECT_ASID_MATCH.yaml +23 -0
- data/.data/spec/std/isa/param/SDTRIG_TEXTRA_SSELECT_SCONTEXT_MATCH.yaml +26 -0
- data/.data/spec/std/isa/param/SDTRIG_TEXTRA_SVALUE_LEN.yaml +26 -0
- data/.data/spec/std/isa/param/SDTRIG_U_WRITABLE.yaml +19 -0
- data/.data/spec/std/isa/param/SDTRIG_VS_WRITABLE.yaml +19 -0
- data/.data/spec/std/isa/param/SDTRIG_VU_WRITABLE.yaml +19 -0
- data/.data/spec/std/isa/param/SEI_INTR_IMPL.yaml +28 -0
- data/.data/spec/std/isa/param/SSEED_READ_ONLY_ZERO.yaml +28 -0
- data/.data/spec/std/isa/param/SSI_INTR_IMPL.yaml +28 -0
- data/.data/spec/std/isa/param/STI_INTR_IMPL.yaml +33 -0
- data/.data/spec/std/isa/param/STVAL_WIDTH.yaml +81 -0
- data/.data/spec/std/isa/param/SUPPORTED_PMLEN_SMMPM.yaml +40 -0
- data/.data/spec/std/isa/param/SUPPORTED_PMLEN_SMNPM.yaml +42 -0
- data/.data/spec/std/isa/param/SUPPORTED_PMLEN_SSNPM.yaml +42 -0
- data/.data/spec/std/isa/param/TCONTROL_IMPLEMENTED.yaml +16 -0
- data/.data/spec/std/isa/param/TDATA2_IMPLEMENTED.yaml +26 -0
- data/.data/spec/std/isa/param/TDATA3_IMPLEMENTED.yaml +29 -0
- data/.data/spec/std/isa/param/TRAP_ON_ECALL_FROM_S.yaml +1 -1
- data/.data/spec/std/isa/param/TRAP_ON_ECALL_FROM_U.yaml +1 -1
- data/.data/spec/std/isa/param/TRAP_ON_ECALL_FROM_VS.yaml +1 -1
- data/.data/spec/std/isa/param/TRAP_ON_SFENCE_VMA_WHEN_SATP_MODE_IS_READ_ONLY.yaml +1 -1
- data/.data/spec/std/isa/param/USEED_READ_ONLY_ZERO.yaml +28 -0
- data/.data/spec/std/isa/param/WFI_FINITE.yaml +20 -0
- data/.data/spec/std/isa/param/WFI_U_MODE.yaml +20 -0
- data/.data/spec/std/isa/profile/RVA23p1S64.yaml +37 -0
- data/.data/spec/std/isa/profile/RVB23p1S64.yaml +39 -0
- data/.data/spec/std/isa/profile_family/RVA.yaml +3 -1
- data/.data/spec/std/isa/profile_family/RVB.yaml +3 -1
- data/.data/spec/std/isa/profile_release/RVA23p1.yaml +30 -0
- data/.data/spec/std/isa/profile_release/RVB23p1.yaml +30 -0
- data/lib/udb/Z3_VERSION +1 -1
- data/lib/udb/log.rb +16 -0
- data/lib/udb/obj/csr.rb +38 -45
- data/lib/udb/obj/database_obj.rb +1 -1
- data/lib/udb/obj/exception_code.rb +3 -3
- data/lib/udb/version.rb +1 -1
- metadata +139 -13
- data/.data/spec/std/isa/param/PMLEN.yaml +0 -20
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# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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# WARNING: This file is auto-generated from spec/std/isa/csr/Smcdeleg/scountinhibit.layout
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# SPDX-License-Identifier: BSD-3-Clause-Clear
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# yaml-language-server: $schema=../../../../schemas/csr_schema.json
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$schema: csr_schema.json#
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kind: csr
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name: scountinhibit
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long_name: Supervisor Counter Inhibit
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address: 0x120
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writable: true
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priv_mode: S
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length: 32
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description: |
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`scountinhibit` is a masked alias of `mcountinhibit`. For counters delegated to S-mode,
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the associated `mcountinhibit` bits can be accessed via `scountinhibit`. For counters
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not delegated to S-mode, the associated bits in `scountinhibit` are read-only zero.
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A counter _i_ is delegated to S-mode when `mcounteren`[_i_]=1 and `menvcfg.CDE`=1.
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When `menvcfg.CDE`=0, attempts to access `scountinhibit` raise an `Illegal Instruction`
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exception. When Supervisor Counter Delegation is enabled, attempts to access
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`scountinhibit` from VS-mode or VU-mode raise a `Virtual Instruction` exception.
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definedBy:
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allOf:
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- extension:
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name: Ssccfg
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- param:
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name: MCOUNTINHIBIT_IMPLEMENTED
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equal: true
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sw_read(): |
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if (CSR[menvcfg].CDE == 1'b0) {
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raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
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}
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if (virtual_mode?()) {
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raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
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}
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return $bits(CSR[mcountinhibit]) & $bits(CSR[mcounteren]);
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fields:
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CY:
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location: 0
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alias: mcountinhibit.CY
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description: |
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Alias of `mcountinhibit.CY` when `mcycle` is delegated to S-mode (`mcounteren.CY`=1);
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otherwise read-only zero.
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type(): |
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return COUNTINHIBIT_EN[0] ? CsrFieldType::RWR : CsrFieldType::RO;
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reset_value(): |
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return COUNTINHIBIT_EN[0] ? UNDEFINED_LEGAL : 0;
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sw_write(csr_value): |
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if (CSR[menvcfg].CDE == 1'b0) {
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raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
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}
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if (virtual_mode?()) {
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raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
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}
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if (CSR[mcounteren].CY == 1'b1) {
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CSR[mcountinhibit].CY = csr_value.CY;
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return csr_value.CY;
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}
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return 1'b0;
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IR:
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location: 2
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alias: mcountinhibit.IR
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description: |
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Alias of `mcountinhibit.IR` when `minstret` is delegated to S-mode (`mcounteren.IR`=1);
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otherwise read-only zero.
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type(): |
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return COUNTINHIBIT_EN[2] ? CsrFieldType::RWR : CsrFieldType::RO;
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reset_value(): |
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return COUNTINHIBIT_EN[2] ? UNDEFINED_LEGAL : 0;
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sw_write(csr_value): |
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if (CSR[menvcfg].CDE == 1'b0) {
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raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
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}
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if (virtual_mode?()) {
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raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
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}
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if (CSR[mcounteren].IR == 1'b1) {
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CSR[mcountinhibit].IR = csr_value.IR;
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return csr_value.IR;
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}
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return 1'b0;
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HPM3:
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location: 3
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alias: mcountinhibit.HPM3
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description: |
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[when="COUNTINHIBIT_EN[3] == true"]
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Alias of `mcountinhibit.HPM3` when `mhpmcounter3` is delegated to S-mode
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(`mcounteren.HPM3`=1); otherwise read-only zero.
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[when="COUNTINHIBIT_EN[3] == false"]
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Since `mcountinhibit.HPM3` is not writable, this field is read-only zero.
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type(): |
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return COUNTINHIBIT_EN[3] ? CsrFieldType::RWR : CsrFieldType::RO;
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reset_value(): |
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return COUNTINHIBIT_EN[3] ? UNDEFINED_LEGAL : 0;
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sw_write(csr_value): |
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if (CSR[menvcfg].CDE == 1'b0) {
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raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
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}
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if (virtual_mode?()) {
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raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
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}
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if (CSR[mcounteren].HPM3 == 1'b1) {
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CSR[mcountinhibit].HPM3 = csr_value.HPM3;
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return csr_value.HPM3;
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}
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return 1'b0;
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HPM4:
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location: 4
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alias: mcountinhibit.HPM4
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description: |
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[when="COUNTINHIBIT_EN[4] == true"]
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Alias of `mcountinhibit.HPM4` when `mhpmcounter4` is delegated to S-mode
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(`mcounteren.HPM4`=1); otherwise read-only zero.
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[when="COUNTINHIBIT_EN[4] == false"]
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Since `mcountinhibit.HPM4` is not writable, this field is read-only zero.
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type(): |
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return COUNTINHIBIT_EN[4] ? CsrFieldType::RWR : CsrFieldType::RO;
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reset_value(): |
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return COUNTINHIBIT_EN[4] ? UNDEFINED_LEGAL : 0;
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sw_write(csr_value): |
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if (CSR[menvcfg].CDE == 1'b0) {
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raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
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}
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if (virtual_mode?()) {
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raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
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}
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if (CSR[mcounteren].HPM4 == 1'b1) {
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CSR[mcountinhibit].HPM4 = csr_value.HPM4;
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return csr_value.HPM4;
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}
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return 1'b0;
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HPM5:
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location: 5
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alias: mcountinhibit.HPM5
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description: |
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[when="COUNTINHIBIT_EN[5] == true"]
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Alias of `mcountinhibit.HPM5` when `mhpmcounter5` is delegated to S-mode
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(`mcounteren.HPM5`=1); otherwise read-only zero.
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[when="COUNTINHIBIT_EN[5] == false"]
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Since `mcountinhibit.HPM5` is not writable, this field is read-only zero.
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type(): |
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return COUNTINHIBIT_EN[5] ? CsrFieldType::RWR : CsrFieldType::RO;
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reset_value(): |
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return COUNTINHIBIT_EN[5] ? UNDEFINED_LEGAL : 0;
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sw_write(csr_value): |
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if (CSR[menvcfg].CDE == 1'b0) {
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raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
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}
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if (virtual_mode?()) {
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raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
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}
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if (CSR[mcounteren].HPM5 == 1'b1) {
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CSR[mcountinhibit].HPM5 = csr_value.HPM5;
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return csr_value.HPM5;
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}
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return 1'b0;
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HPM6:
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location: 6
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alias: mcountinhibit.HPM6
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description: |
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[when="COUNTINHIBIT_EN[6] == true"]
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Alias of `mcountinhibit.HPM6` when `mhpmcounter6` is delegated to S-mode
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(`mcounteren.HPM6`=1); otherwise read-only zero.
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[when="COUNTINHIBIT_EN[6] == false"]
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Since `mcountinhibit.HPM6` is not writable, this field is read-only zero.
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type(): |
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return COUNTINHIBIT_EN[6] ? CsrFieldType::RWR : CsrFieldType::RO;
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reset_value(): |
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return COUNTINHIBIT_EN[6] ? UNDEFINED_LEGAL : 0;
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sw_write(csr_value): |
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if (CSR[menvcfg].CDE == 1'b0) {
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raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
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}
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if (virtual_mode?()) {
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raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
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}
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if (CSR[mcounteren].HPM6 == 1'b1) {
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CSR[mcountinhibit].HPM6 = csr_value.HPM6;
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return csr_value.HPM6;
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}
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return 1'b0;
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HPM7:
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location: 7
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alias: mcountinhibit.HPM7
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description: |
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[when="COUNTINHIBIT_EN[7] == true"]
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Alias of `mcountinhibit.HPM7` when `mhpmcounter7` is delegated to S-mode
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(`mcounteren.HPM7`=1); otherwise read-only zero.
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[when="COUNTINHIBIT_EN[7] == false"]
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Since `mcountinhibit.HPM7` is not writable, this field is read-only zero.
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type(): |
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return COUNTINHIBIT_EN[7] ? CsrFieldType::RWR : CsrFieldType::RO;
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reset_value(): |
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return COUNTINHIBIT_EN[7] ? UNDEFINED_LEGAL : 0;
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sw_write(csr_value): |
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if (CSR[menvcfg].CDE == 1'b0) {
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raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
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}
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if (virtual_mode?()) {
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raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
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}
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if (CSR[mcounteren].HPM7 == 1'b1) {
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CSR[mcountinhibit].HPM7 = csr_value.HPM7;
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return csr_value.HPM7;
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}
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return 1'b0;
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HPM8:
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location: 8
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alias: mcountinhibit.HPM8
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description: |
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[when="COUNTINHIBIT_EN[8] == true"]
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Alias of `mcountinhibit.HPM8` when `mhpmcounter8` is delegated to S-mode
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(`mcounteren.HPM8`=1); otherwise read-only zero.
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[when="COUNTINHIBIT_EN[8] == false"]
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Since `mcountinhibit.HPM8` is not writable, this field is read-only zero.
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type(): |
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return COUNTINHIBIT_EN[8] ? CsrFieldType::RWR : CsrFieldType::RO;
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reset_value(): |
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return COUNTINHIBIT_EN[8] ? UNDEFINED_LEGAL : 0;
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sw_write(csr_value): |
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if (CSR[menvcfg].CDE == 1'b0) {
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raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
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}
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if (virtual_mode?()) {
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raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
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}
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if (CSR[mcounteren].HPM8 == 1'b1) {
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CSR[mcountinhibit].HPM8 = csr_value.HPM8;
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return csr_value.HPM8;
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}
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return 1'b0;
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HPM9:
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location: 9
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alias: mcountinhibit.HPM9
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description: |
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[when="COUNTINHIBIT_EN[9] == true"]
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Alias of `mcountinhibit.HPM9` when `mhpmcounter9` is delegated to S-mode
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(`mcounteren.HPM9`=1); otherwise read-only zero.
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[when="COUNTINHIBIT_EN[9] == false"]
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Since `mcountinhibit.HPM9` is not writable, this field is read-only zero.
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type(): |
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return COUNTINHIBIT_EN[9] ? CsrFieldType::RWR : CsrFieldType::RO;
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reset_value(): |
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return COUNTINHIBIT_EN[9] ? UNDEFINED_LEGAL : 0;
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sw_write(csr_value): |
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if (CSR[menvcfg].CDE == 1'b0) {
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raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
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}
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if (virtual_mode?()) {
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raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
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}
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|
+
if (CSR[mcounteren].HPM9 == 1'b1) {
|
|
265
|
+
CSR[mcountinhibit].HPM9 = csr_value.HPM9;
|
|
266
|
+
return csr_value.HPM9;
|
|
267
|
+
}
|
|
268
|
+
return 1'b0;
|
|
269
|
+
HPM10:
|
|
270
|
+
location: 10
|
|
271
|
+
alias: mcountinhibit.HPM10
|
|
272
|
+
description: |
|
|
273
|
+
[when="COUNTINHIBIT_EN[10] == true"]
|
|
274
|
+
Alias of `mcountinhibit.HPM10` when `mhpmcounter10` is delegated to S-mode
|
|
275
|
+
(`mcounteren.HPM10`=1); otherwise read-only zero.
|
|
276
|
+
|
|
277
|
+
[when="COUNTINHIBIT_EN[10] == false"]
|
|
278
|
+
Since `mcountinhibit.HPM10` is not writable, this field is read-only zero.
|
|
279
|
+
type(): |
|
|
280
|
+
return COUNTINHIBIT_EN[10] ? CsrFieldType::RWR : CsrFieldType::RO;
|
|
281
|
+
reset_value(): |
|
|
282
|
+
return COUNTINHIBIT_EN[10] ? UNDEFINED_LEGAL : 0;
|
|
283
|
+
sw_write(csr_value): |
|
|
284
|
+
if (CSR[menvcfg].CDE == 1'b0) {
|
|
285
|
+
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
|
|
286
|
+
}
|
|
287
|
+
if (virtual_mode?()) {
|
|
288
|
+
raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
|
|
289
|
+
}
|
|
290
|
+
if (CSR[mcounteren].HPM10 == 1'b1) {
|
|
291
|
+
CSR[mcountinhibit].HPM10 = csr_value.HPM10;
|
|
292
|
+
return csr_value.HPM10;
|
|
293
|
+
}
|
|
294
|
+
return 1'b0;
|
|
295
|
+
HPM11:
|
|
296
|
+
location: 11
|
|
297
|
+
alias: mcountinhibit.HPM11
|
|
298
|
+
description: |
|
|
299
|
+
[when="COUNTINHIBIT_EN[11] == true"]
|
|
300
|
+
Alias of `mcountinhibit.HPM11` when `mhpmcounter11` is delegated to S-mode
|
|
301
|
+
(`mcounteren.HPM11`=1); otherwise read-only zero.
|
|
302
|
+
|
|
303
|
+
[when="COUNTINHIBIT_EN[11] == false"]
|
|
304
|
+
Since `mcountinhibit.HPM11` is not writable, this field is read-only zero.
|
|
305
|
+
type(): |
|
|
306
|
+
return COUNTINHIBIT_EN[11] ? CsrFieldType::RWR : CsrFieldType::RO;
|
|
307
|
+
reset_value(): |
|
|
308
|
+
return COUNTINHIBIT_EN[11] ? UNDEFINED_LEGAL : 0;
|
|
309
|
+
sw_write(csr_value): |
|
|
310
|
+
if (CSR[menvcfg].CDE == 1'b0) {
|
|
311
|
+
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
|
|
312
|
+
}
|
|
313
|
+
if (virtual_mode?()) {
|
|
314
|
+
raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
|
|
315
|
+
}
|
|
316
|
+
if (CSR[mcounteren].HPM11 == 1'b1) {
|
|
317
|
+
CSR[mcountinhibit].HPM11 = csr_value.HPM11;
|
|
318
|
+
return csr_value.HPM11;
|
|
319
|
+
}
|
|
320
|
+
return 1'b0;
|
|
321
|
+
HPM12:
|
|
322
|
+
location: 12
|
|
323
|
+
alias: mcountinhibit.HPM12
|
|
324
|
+
description: |
|
|
325
|
+
[when="COUNTINHIBIT_EN[12] == true"]
|
|
326
|
+
Alias of `mcountinhibit.HPM12` when `mhpmcounter12` is delegated to S-mode
|
|
327
|
+
(`mcounteren.HPM12`=1); otherwise read-only zero.
|
|
328
|
+
|
|
329
|
+
[when="COUNTINHIBIT_EN[12] == false"]
|
|
330
|
+
Since `mcountinhibit.HPM12` is not writable, this field is read-only zero.
|
|
331
|
+
type(): |
|
|
332
|
+
return COUNTINHIBIT_EN[12] ? CsrFieldType::RWR : CsrFieldType::RO;
|
|
333
|
+
reset_value(): |
|
|
334
|
+
return COUNTINHIBIT_EN[12] ? UNDEFINED_LEGAL : 0;
|
|
335
|
+
sw_write(csr_value): |
|
|
336
|
+
if (CSR[menvcfg].CDE == 1'b0) {
|
|
337
|
+
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
|
|
338
|
+
}
|
|
339
|
+
if (virtual_mode?()) {
|
|
340
|
+
raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
|
|
341
|
+
}
|
|
342
|
+
if (CSR[mcounteren].HPM12 == 1'b1) {
|
|
343
|
+
CSR[mcountinhibit].HPM12 = csr_value.HPM12;
|
|
344
|
+
return csr_value.HPM12;
|
|
345
|
+
}
|
|
346
|
+
return 1'b0;
|
|
347
|
+
HPM13:
|
|
348
|
+
location: 13
|
|
349
|
+
alias: mcountinhibit.HPM13
|
|
350
|
+
description: |
|
|
351
|
+
[when="COUNTINHIBIT_EN[13] == true"]
|
|
352
|
+
Alias of `mcountinhibit.HPM13` when `mhpmcounter13` is delegated to S-mode
|
|
353
|
+
(`mcounteren.HPM13`=1); otherwise read-only zero.
|
|
354
|
+
|
|
355
|
+
[when="COUNTINHIBIT_EN[13] == false"]
|
|
356
|
+
Since `mcountinhibit.HPM13` is not writable, this field is read-only zero.
|
|
357
|
+
type(): |
|
|
358
|
+
return COUNTINHIBIT_EN[13] ? CsrFieldType::RWR : CsrFieldType::RO;
|
|
359
|
+
reset_value(): |
|
|
360
|
+
return COUNTINHIBIT_EN[13] ? UNDEFINED_LEGAL : 0;
|
|
361
|
+
sw_write(csr_value): |
|
|
362
|
+
if (CSR[menvcfg].CDE == 1'b0) {
|
|
363
|
+
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
|
|
364
|
+
}
|
|
365
|
+
if (virtual_mode?()) {
|
|
366
|
+
raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
|
|
367
|
+
}
|
|
368
|
+
if (CSR[mcounteren].HPM13 == 1'b1) {
|
|
369
|
+
CSR[mcountinhibit].HPM13 = csr_value.HPM13;
|
|
370
|
+
return csr_value.HPM13;
|
|
371
|
+
}
|
|
372
|
+
return 1'b0;
|
|
373
|
+
HPM14:
|
|
374
|
+
location: 14
|
|
375
|
+
alias: mcountinhibit.HPM14
|
|
376
|
+
description: |
|
|
377
|
+
[when="COUNTINHIBIT_EN[14] == true"]
|
|
378
|
+
Alias of `mcountinhibit.HPM14` when `mhpmcounter14` is delegated to S-mode
|
|
379
|
+
(`mcounteren.HPM14`=1); otherwise read-only zero.
|
|
380
|
+
|
|
381
|
+
[when="COUNTINHIBIT_EN[14] == false"]
|
|
382
|
+
Since `mcountinhibit.HPM14` is not writable, this field is read-only zero.
|
|
383
|
+
type(): |
|
|
384
|
+
return COUNTINHIBIT_EN[14] ? CsrFieldType::RWR : CsrFieldType::RO;
|
|
385
|
+
reset_value(): |
|
|
386
|
+
return COUNTINHIBIT_EN[14] ? UNDEFINED_LEGAL : 0;
|
|
387
|
+
sw_write(csr_value): |
|
|
388
|
+
if (CSR[menvcfg].CDE == 1'b0) {
|
|
389
|
+
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
|
|
390
|
+
}
|
|
391
|
+
if (virtual_mode?()) {
|
|
392
|
+
raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
|
|
393
|
+
}
|
|
394
|
+
if (CSR[mcounteren].HPM14 == 1'b1) {
|
|
395
|
+
CSR[mcountinhibit].HPM14 = csr_value.HPM14;
|
|
396
|
+
return csr_value.HPM14;
|
|
397
|
+
}
|
|
398
|
+
return 1'b0;
|
|
399
|
+
HPM15:
|
|
400
|
+
location: 15
|
|
401
|
+
alias: mcountinhibit.HPM15
|
|
402
|
+
description: |
|
|
403
|
+
[when="COUNTINHIBIT_EN[15] == true"]
|
|
404
|
+
Alias of `mcountinhibit.HPM15` when `mhpmcounter15` is delegated to S-mode
|
|
405
|
+
(`mcounteren.HPM15`=1); otherwise read-only zero.
|
|
406
|
+
|
|
407
|
+
[when="COUNTINHIBIT_EN[15] == false"]
|
|
408
|
+
Since `mcountinhibit.HPM15` is not writable, this field is read-only zero.
|
|
409
|
+
type(): |
|
|
410
|
+
return COUNTINHIBIT_EN[15] ? CsrFieldType::RWR : CsrFieldType::RO;
|
|
411
|
+
reset_value(): |
|
|
412
|
+
return COUNTINHIBIT_EN[15] ? UNDEFINED_LEGAL : 0;
|
|
413
|
+
sw_write(csr_value): |
|
|
414
|
+
if (CSR[menvcfg].CDE == 1'b0) {
|
|
415
|
+
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
|
|
416
|
+
}
|
|
417
|
+
if (virtual_mode?()) {
|
|
418
|
+
raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
|
|
419
|
+
}
|
|
420
|
+
if (CSR[mcounteren].HPM15 == 1'b1) {
|
|
421
|
+
CSR[mcountinhibit].HPM15 = csr_value.HPM15;
|
|
422
|
+
return csr_value.HPM15;
|
|
423
|
+
}
|
|
424
|
+
return 1'b0;
|
|
425
|
+
HPM16:
|
|
426
|
+
location: 16
|
|
427
|
+
alias: mcountinhibit.HPM16
|
|
428
|
+
description: |
|
|
429
|
+
[when="COUNTINHIBIT_EN[16] == true"]
|
|
430
|
+
Alias of `mcountinhibit.HPM16` when `mhpmcounter16` is delegated to S-mode
|
|
431
|
+
(`mcounteren.HPM16`=1); otherwise read-only zero.
|
|
432
|
+
|
|
433
|
+
[when="COUNTINHIBIT_EN[16] == false"]
|
|
434
|
+
Since `mcountinhibit.HPM16` is not writable, this field is read-only zero.
|
|
435
|
+
type(): |
|
|
436
|
+
return COUNTINHIBIT_EN[16] ? CsrFieldType::RWR : CsrFieldType::RO;
|
|
437
|
+
reset_value(): |
|
|
438
|
+
return COUNTINHIBIT_EN[16] ? UNDEFINED_LEGAL : 0;
|
|
439
|
+
sw_write(csr_value): |
|
|
440
|
+
if (CSR[menvcfg].CDE == 1'b0) {
|
|
441
|
+
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
|
|
442
|
+
}
|
|
443
|
+
if (virtual_mode?()) {
|
|
444
|
+
raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
|
|
445
|
+
}
|
|
446
|
+
if (CSR[mcounteren].HPM16 == 1'b1) {
|
|
447
|
+
CSR[mcountinhibit].HPM16 = csr_value.HPM16;
|
|
448
|
+
return csr_value.HPM16;
|
|
449
|
+
}
|
|
450
|
+
return 1'b0;
|
|
451
|
+
HPM17:
|
|
452
|
+
location: 17
|
|
453
|
+
alias: mcountinhibit.HPM17
|
|
454
|
+
description: |
|
|
455
|
+
[when="COUNTINHIBIT_EN[17] == true"]
|
|
456
|
+
Alias of `mcountinhibit.HPM17` when `mhpmcounter17` is delegated to S-mode
|
|
457
|
+
(`mcounteren.HPM17`=1); otherwise read-only zero.
|
|
458
|
+
|
|
459
|
+
[when="COUNTINHIBIT_EN[17] == false"]
|
|
460
|
+
Since `mcountinhibit.HPM17` is not writable, this field is read-only zero.
|
|
461
|
+
type(): |
|
|
462
|
+
return COUNTINHIBIT_EN[17] ? CsrFieldType::RWR : CsrFieldType::RO;
|
|
463
|
+
reset_value(): |
|
|
464
|
+
return COUNTINHIBIT_EN[17] ? UNDEFINED_LEGAL : 0;
|
|
465
|
+
sw_write(csr_value): |
|
|
466
|
+
if (CSR[menvcfg].CDE == 1'b0) {
|
|
467
|
+
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
|
|
468
|
+
}
|
|
469
|
+
if (virtual_mode?()) {
|
|
470
|
+
raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
|
|
471
|
+
}
|
|
472
|
+
if (CSR[mcounteren].HPM17 == 1'b1) {
|
|
473
|
+
CSR[mcountinhibit].HPM17 = csr_value.HPM17;
|
|
474
|
+
return csr_value.HPM17;
|
|
475
|
+
}
|
|
476
|
+
return 1'b0;
|
|
477
|
+
HPM18:
|
|
478
|
+
location: 18
|
|
479
|
+
alias: mcountinhibit.HPM18
|
|
480
|
+
description: |
|
|
481
|
+
[when="COUNTINHIBIT_EN[18] == true"]
|
|
482
|
+
Alias of `mcountinhibit.HPM18` when `mhpmcounter18` is delegated to S-mode
|
|
483
|
+
(`mcounteren.HPM18`=1); otherwise read-only zero.
|
|
484
|
+
|
|
485
|
+
[when="COUNTINHIBIT_EN[18] == false"]
|
|
486
|
+
Since `mcountinhibit.HPM18` is not writable, this field is read-only zero.
|
|
487
|
+
type(): |
|
|
488
|
+
return COUNTINHIBIT_EN[18] ? CsrFieldType::RWR : CsrFieldType::RO;
|
|
489
|
+
reset_value(): |
|
|
490
|
+
return COUNTINHIBIT_EN[18] ? UNDEFINED_LEGAL : 0;
|
|
491
|
+
sw_write(csr_value): |
|
|
492
|
+
if (CSR[menvcfg].CDE == 1'b0) {
|
|
493
|
+
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
|
|
494
|
+
}
|
|
495
|
+
if (virtual_mode?()) {
|
|
496
|
+
raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
|
|
497
|
+
}
|
|
498
|
+
if (CSR[mcounteren].HPM18 == 1'b1) {
|
|
499
|
+
CSR[mcountinhibit].HPM18 = csr_value.HPM18;
|
|
500
|
+
return csr_value.HPM18;
|
|
501
|
+
}
|
|
502
|
+
return 1'b0;
|
|
503
|
+
HPM19:
|
|
504
|
+
location: 19
|
|
505
|
+
alias: mcountinhibit.HPM19
|
|
506
|
+
description: |
|
|
507
|
+
[when="COUNTINHIBIT_EN[19] == true"]
|
|
508
|
+
Alias of `mcountinhibit.HPM19` when `mhpmcounter19` is delegated to S-mode
|
|
509
|
+
(`mcounteren.HPM19`=1); otherwise read-only zero.
|
|
510
|
+
|
|
511
|
+
[when="COUNTINHIBIT_EN[19] == false"]
|
|
512
|
+
Since `mcountinhibit.HPM19` is not writable, this field is read-only zero.
|
|
513
|
+
type(): |
|
|
514
|
+
return COUNTINHIBIT_EN[19] ? CsrFieldType::RWR : CsrFieldType::RO;
|
|
515
|
+
reset_value(): |
|
|
516
|
+
return COUNTINHIBIT_EN[19] ? UNDEFINED_LEGAL : 0;
|
|
517
|
+
sw_write(csr_value): |
|
|
518
|
+
if (CSR[menvcfg].CDE == 1'b0) {
|
|
519
|
+
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
|
|
520
|
+
}
|
|
521
|
+
if (virtual_mode?()) {
|
|
522
|
+
raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
|
|
523
|
+
}
|
|
524
|
+
if (CSR[mcounteren].HPM19 == 1'b1) {
|
|
525
|
+
CSR[mcountinhibit].HPM19 = csr_value.HPM19;
|
|
526
|
+
return csr_value.HPM19;
|
|
527
|
+
}
|
|
528
|
+
return 1'b0;
|
|
529
|
+
HPM20:
|
|
530
|
+
location: 20
|
|
531
|
+
alias: mcountinhibit.HPM20
|
|
532
|
+
description: |
|
|
533
|
+
[when="COUNTINHIBIT_EN[20] == true"]
|
|
534
|
+
Alias of `mcountinhibit.HPM20` when `mhpmcounter20` is delegated to S-mode
|
|
535
|
+
(`mcounteren.HPM20`=1); otherwise read-only zero.
|
|
536
|
+
|
|
537
|
+
[when="COUNTINHIBIT_EN[20] == false"]
|
|
538
|
+
Since `mcountinhibit.HPM20` is not writable, this field is read-only zero.
|
|
539
|
+
type(): |
|
|
540
|
+
return COUNTINHIBIT_EN[20] ? CsrFieldType::RWR : CsrFieldType::RO;
|
|
541
|
+
reset_value(): |
|
|
542
|
+
return COUNTINHIBIT_EN[20] ? UNDEFINED_LEGAL : 0;
|
|
543
|
+
sw_write(csr_value): |
|
|
544
|
+
if (CSR[menvcfg].CDE == 1'b0) {
|
|
545
|
+
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
|
|
546
|
+
}
|
|
547
|
+
if (virtual_mode?()) {
|
|
548
|
+
raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
|
|
549
|
+
}
|
|
550
|
+
if (CSR[mcounteren].HPM20 == 1'b1) {
|
|
551
|
+
CSR[mcountinhibit].HPM20 = csr_value.HPM20;
|
|
552
|
+
return csr_value.HPM20;
|
|
553
|
+
}
|
|
554
|
+
return 1'b0;
|
|
555
|
+
HPM21:
|
|
556
|
+
location: 21
|
|
557
|
+
alias: mcountinhibit.HPM21
|
|
558
|
+
description: |
|
|
559
|
+
[when="COUNTINHIBIT_EN[21] == true"]
|
|
560
|
+
Alias of `mcountinhibit.HPM21` when `mhpmcounter21` is delegated to S-mode
|
|
561
|
+
(`mcounteren.HPM21`=1); otherwise read-only zero.
|
|
562
|
+
|
|
563
|
+
[when="COUNTINHIBIT_EN[21] == false"]
|
|
564
|
+
Since `mcountinhibit.HPM21` is not writable, this field is read-only zero.
|
|
565
|
+
type(): |
|
|
566
|
+
return COUNTINHIBIT_EN[21] ? CsrFieldType::RWR : CsrFieldType::RO;
|
|
567
|
+
reset_value(): |
|
|
568
|
+
return COUNTINHIBIT_EN[21] ? UNDEFINED_LEGAL : 0;
|
|
569
|
+
sw_write(csr_value): |
|
|
570
|
+
if (CSR[menvcfg].CDE == 1'b0) {
|
|
571
|
+
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
|
|
572
|
+
}
|
|
573
|
+
if (virtual_mode?()) {
|
|
574
|
+
raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
|
|
575
|
+
}
|
|
576
|
+
if (CSR[mcounteren].HPM21 == 1'b1) {
|
|
577
|
+
CSR[mcountinhibit].HPM21 = csr_value.HPM21;
|
|
578
|
+
return csr_value.HPM21;
|
|
579
|
+
}
|
|
580
|
+
return 1'b0;
|
|
581
|
+
HPM22:
|
|
582
|
+
location: 22
|
|
583
|
+
alias: mcountinhibit.HPM22
|
|
584
|
+
description: |
|
|
585
|
+
[when="COUNTINHIBIT_EN[22] == true"]
|
|
586
|
+
Alias of `mcountinhibit.HPM22` when `mhpmcounter22` is delegated to S-mode
|
|
587
|
+
(`mcounteren.HPM22`=1); otherwise read-only zero.
|
|
588
|
+
|
|
589
|
+
[when="COUNTINHIBIT_EN[22] == false"]
|
|
590
|
+
Since `mcountinhibit.HPM22` is not writable, this field is read-only zero.
|
|
591
|
+
type(): |
|
|
592
|
+
return COUNTINHIBIT_EN[22] ? CsrFieldType::RWR : CsrFieldType::RO;
|
|
593
|
+
reset_value(): |
|
|
594
|
+
return COUNTINHIBIT_EN[22] ? UNDEFINED_LEGAL : 0;
|
|
595
|
+
sw_write(csr_value): |
|
|
596
|
+
if (CSR[menvcfg].CDE == 1'b0) {
|
|
597
|
+
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
|
|
598
|
+
}
|
|
599
|
+
if (virtual_mode?()) {
|
|
600
|
+
raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
|
|
601
|
+
}
|
|
602
|
+
if (CSR[mcounteren].HPM22 == 1'b1) {
|
|
603
|
+
CSR[mcountinhibit].HPM22 = csr_value.HPM22;
|
|
604
|
+
return csr_value.HPM22;
|
|
605
|
+
}
|
|
606
|
+
return 1'b0;
|
|
607
|
+
HPM23:
|
|
608
|
+
location: 23
|
|
609
|
+
alias: mcountinhibit.HPM23
|
|
610
|
+
description: |
|
|
611
|
+
[when="COUNTINHIBIT_EN[23] == true"]
|
|
612
|
+
Alias of `mcountinhibit.HPM23` when `mhpmcounter23` is delegated to S-mode
|
|
613
|
+
(`mcounteren.HPM23`=1); otherwise read-only zero.
|
|
614
|
+
|
|
615
|
+
[when="COUNTINHIBIT_EN[23] == false"]
|
|
616
|
+
Since `mcountinhibit.HPM23` is not writable, this field is read-only zero.
|
|
617
|
+
type(): |
|
|
618
|
+
return COUNTINHIBIT_EN[23] ? CsrFieldType::RWR : CsrFieldType::RO;
|
|
619
|
+
reset_value(): |
|
|
620
|
+
return COUNTINHIBIT_EN[23] ? UNDEFINED_LEGAL : 0;
|
|
621
|
+
sw_write(csr_value): |
|
|
622
|
+
if (CSR[menvcfg].CDE == 1'b0) {
|
|
623
|
+
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
|
|
624
|
+
}
|
|
625
|
+
if (virtual_mode?()) {
|
|
626
|
+
raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
|
|
627
|
+
}
|
|
628
|
+
if (CSR[mcounteren].HPM23 == 1'b1) {
|
|
629
|
+
CSR[mcountinhibit].HPM23 = csr_value.HPM23;
|
|
630
|
+
return csr_value.HPM23;
|
|
631
|
+
}
|
|
632
|
+
return 1'b0;
|
|
633
|
+
HPM24:
|
|
634
|
+
location: 24
|
|
635
|
+
alias: mcountinhibit.HPM24
|
|
636
|
+
description: |
|
|
637
|
+
[when="COUNTINHIBIT_EN[24] == true"]
|
|
638
|
+
Alias of `mcountinhibit.HPM24` when `mhpmcounter24` is delegated to S-mode
|
|
639
|
+
(`mcounteren.HPM24`=1); otherwise read-only zero.
|
|
640
|
+
|
|
641
|
+
[when="COUNTINHIBIT_EN[24] == false"]
|
|
642
|
+
Since `mcountinhibit.HPM24` is not writable, this field is read-only zero.
|
|
643
|
+
type(): |
|
|
644
|
+
return COUNTINHIBIT_EN[24] ? CsrFieldType::RWR : CsrFieldType::RO;
|
|
645
|
+
reset_value(): |
|
|
646
|
+
return COUNTINHIBIT_EN[24] ? UNDEFINED_LEGAL : 0;
|
|
647
|
+
sw_write(csr_value): |
|
|
648
|
+
if (CSR[menvcfg].CDE == 1'b0) {
|
|
649
|
+
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
|
|
650
|
+
}
|
|
651
|
+
if (virtual_mode?()) {
|
|
652
|
+
raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
|
|
653
|
+
}
|
|
654
|
+
if (CSR[mcounteren].HPM24 == 1'b1) {
|
|
655
|
+
CSR[mcountinhibit].HPM24 = csr_value.HPM24;
|
|
656
|
+
return csr_value.HPM24;
|
|
657
|
+
}
|
|
658
|
+
return 1'b0;
|
|
659
|
+
HPM25:
|
|
660
|
+
location: 25
|
|
661
|
+
alias: mcountinhibit.HPM25
|
|
662
|
+
description: |
|
|
663
|
+
[when="COUNTINHIBIT_EN[25] == true"]
|
|
664
|
+
Alias of `mcountinhibit.HPM25` when `mhpmcounter25` is delegated to S-mode
|
|
665
|
+
(`mcounteren.HPM25`=1); otherwise read-only zero.
|
|
666
|
+
|
|
667
|
+
[when="COUNTINHIBIT_EN[25] == false"]
|
|
668
|
+
Since `mcountinhibit.HPM25` is not writable, this field is read-only zero.
|
|
669
|
+
type(): |
|
|
670
|
+
return COUNTINHIBIT_EN[25] ? CsrFieldType::RWR : CsrFieldType::RO;
|
|
671
|
+
reset_value(): |
|
|
672
|
+
return COUNTINHIBIT_EN[25] ? UNDEFINED_LEGAL : 0;
|
|
673
|
+
sw_write(csr_value): |
|
|
674
|
+
if (CSR[menvcfg].CDE == 1'b0) {
|
|
675
|
+
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
|
|
676
|
+
}
|
|
677
|
+
if (virtual_mode?()) {
|
|
678
|
+
raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
|
|
679
|
+
}
|
|
680
|
+
if (CSR[mcounteren].HPM25 == 1'b1) {
|
|
681
|
+
CSR[mcountinhibit].HPM25 = csr_value.HPM25;
|
|
682
|
+
return csr_value.HPM25;
|
|
683
|
+
}
|
|
684
|
+
return 1'b0;
|
|
685
|
+
HPM26:
|
|
686
|
+
location: 26
|
|
687
|
+
alias: mcountinhibit.HPM26
|
|
688
|
+
description: |
|
|
689
|
+
[when="COUNTINHIBIT_EN[26] == true"]
|
|
690
|
+
Alias of `mcountinhibit.HPM26` when `mhpmcounter26` is delegated to S-mode
|
|
691
|
+
(`mcounteren.HPM26`=1); otherwise read-only zero.
|
|
692
|
+
|
|
693
|
+
[when="COUNTINHIBIT_EN[26] == false"]
|
|
694
|
+
Since `mcountinhibit.HPM26` is not writable, this field is read-only zero.
|
|
695
|
+
type(): |
|
|
696
|
+
return COUNTINHIBIT_EN[26] ? CsrFieldType::RWR : CsrFieldType::RO;
|
|
697
|
+
reset_value(): |
|
|
698
|
+
return COUNTINHIBIT_EN[26] ? UNDEFINED_LEGAL : 0;
|
|
699
|
+
sw_write(csr_value): |
|
|
700
|
+
if (CSR[menvcfg].CDE == 1'b0) {
|
|
701
|
+
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
|
|
702
|
+
}
|
|
703
|
+
if (virtual_mode?()) {
|
|
704
|
+
raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
|
|
705
|
+
}
|
|
706
|
+
if (CSR[mcounteren].HPM26 == 1'b1) {
|
|
707
|
+
CSR[mcountinhibit].HPM26 = csr_value.HPM26;
|
|
708
|
+
return csr_value.HPM26;
|
|
709
|
+
}
|
|
710
|
+
return 1'b0;
|
|
711
|
+
HPM27:
|
|
712
|
+
location: 27
|
|
713
|
+
alias: mcountinhibit.HPM27
|
|
714
|
+
description: |
|
|
715
|
+
[when="COUNTINHIBIT_EN[27] == true"]
|
|
716
|
+
Alias of `mcountinhibit.HPM27` when `mhpmcounter27` is delegated to S-mode
|
|
717
|
+
(`mcounteren.HPM27`=1); otherwise read-only zero.
|
|
718
|
+
|
|
719
|
+
[when="COUNTINHIBIT_EN[27] == false"]
|
|
720
|
+
Since `mcountinhibit.HPM27` is not writable, this field is read-only zero.
|
|
721
|
+
type(): |
|
|
722
|
+
return COUNTINHIBIT_EN[27] ? CsrFieldType::RWR : CsrFieldType::RO;
|
|
723
|
+
reset_value(): |
|
|
724
|
+
return COUNTINHIBIT_EN[27] ? UNDEFINED_LEGAL : 0;
|
|
725
|
+
sw_write(csr_value): |
|
|
726
|
+
if (CSR[menvcfg].CDE == 1'b0) {
|
|
727
|
+
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
|
|
728
|
+
}
|
|
729
|
+
if (virtual_mode?()) {
|
|
730
|
+
raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
|
|
731
|
+
}
|
|
732
|
+
if (CSR[mcounteren].HPM27 == 1'b1) {
|
|
733
|
+
CSR[mcountinhibit].HPM27 = csr_value.HPM27;
|
|
734
|
+
return csr_value.HPM27;
|
|
735
|
+
}
|
|
736
|
+
return 1'b0;
|
|
737
|
+
HPM28:
|
|
738
|
+
location: 28
|
|
739
|
+
alias: mcountinhibit.HPM28
|
|
740
|
+
description: |
|
|
741
|
+
[when="COUNTINHIBIT_EN[28] == true"]
|
|
742
|
+
Alias of `mcountinhibit.HPM28` when `mhpmcounter28` is delegated to S-mode
|
|
743
|
+
(`mcounteren.HPM28`=1); otherwise read-only zero.
|
|
744
|
+
|
|
745
|
+
[when="COUNTINHIBIT_EN[28] == false"]
|
|
746
|
+
Since `mcountinhibit.HPM28` is not writable, this field is read-only zero.
|
|
747
|
+
type(): |
|
|
748
|
+
return COUNTINHIBIT_EN[28] ? CsrFieldType::RWR : CsrFieldType::RO;
|
|
749
|
+
reset_value(): |
|
|
750
|
+
return COUNTINHIBIT_EN[28] ? UNDEFINED_LEGAL : 0;
|
|
751
|
+
sw_write(csr_value): |
|
|
752
|
+
if (CSR[menvcfg].CDE == 1'b0) {
|
|
753
|
+
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
|
|
754
|
+
}
|
|
755
|
+
if (virtual_mode?()) {
|
|
756
|
+
raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
|
|
757
|
+
}
|
|
758
|
+
if (CSR[mcounteren].HPM28 == 1'b1) {
|
|
759
|
+
CSR[mcountinhibit].HPM28 = csr_value.HPM28;
|
|
760
|
+
return csr_value.HPM28;
|
|
761
|
+
}
|
|
762
|
+
return 1'b0;
|
|
763
|
+
HPM29:
|
|
764
|
+
location: 29
|
|
765
|
+
alias: mcountinhibit.HPM29
|
|
766
|
+
description: |
|
|
767
|
+
[when="COUNTINHIBIT_EN[29] == true"]
|
|
768
|
+
Alias of `mcountinhibit.HPM29` when `mhpmcounter29` is delegated to S-mode
|
|
769
|
+
(`mcounteren.HPM29`=1); otherwise read-only zero.
|
|
770
|
+
|
|
771
|
+
[when="COUNTINHIBIT_EN[29] == false"]
|
|
772
|
+
Since `mcountinhibit.HPM29` is not writable, this field is read-only zero.
|
|
773
|
+
type(): |
|
|
774
|
+
return COUNTINHIBIT_EN[29] ? CsrFieldType::RWR : CsrFieldType::RO;
|
|
775
|
+
reset_value(): |
|
|
776
|
+
return COUNTINHIBIT_EN[29] ? UNDEFINED_LEGAL : 0;
|
|
777
|
+
sw_write(csr_value): |
|
|
778
|
+
if (CSR[menvcfg].CDE == 1'b0) {
|
|
779
|
+
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
|
|
780
|
+
}
|
|
781
|
+
if (virtual_mode?()) {
|
|
782
|
+
raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
|
|
783
|
+
}
|
|
784
|
+
if (CSR[mcounteren].HPM29 == 1'b1) {
|
|
785
|
+
CSR[mcountinhibit].HPM29 = csr_value.HPM29;
|
|
786
|
+
return csr_value.HPM29;
|
|
787
|
+
}
|
|
788
|
+
return 1'b0;
|
|
789
|
+
HPM30:
|
|
790
|
+
location: 30
|
|
791
|
+
alias: mcountinhibit.HPM30
|
|
792
|
+
description: |
|
|
793
|
+
[when="COUNTINHIBIT_EN[30] == true"]
|
|
794
|
+
Alias of `mcountinhibit.HPM30` when `mhpmcounter30` is delegated to S-mode
|
|
795
|
+
(`mcounteren.HPM30`=1); otherwise read-only zero.
|
|
796
|
+
|
|
797
|
+
[when="COUNTINHIBIT_EN[30] == false"]
|
|
798
|
+
Since `mcountinhibit.HPM30` is not writable, this field is read-only zero.
|
|
799
|
+
type(): |
|
|
800
|
+
return COUNTINHIBIT_EN[30] ? CsrFieldType::RWR : CsrFieldType::RO;
|
|
801
|
+
reset_value(): |
|
|
802
|
+
return COUNTINHIBIT_EN[30] ? UNDEFINED_LEGAL : 0;
|
|
803
|
+
sw_write(csr_value): |
|
|
804
|
+
if (CSR[menvcfg].CDE == 1'b0) {
|
|
805
|
+
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
|
|
806
|
+
}
|
|
807
|
+
if (virtual_mode?()) {
|
|
808
|
+
raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
|
|
809
|
+
}
|
|
810
|
+
if (CSR[mcounteren].HPM30 == 1'b1) {
|
|
811
|
+
CSR[mcountinhibit].HPM30 = csr_value.HPM30;
|
|
812
|
+
return csr_value.HPM30;
|
|
813
|
+
}
|
|
814
|
+
return 1'b0;
|
|
815
|
+
HPM31:
|
|
816
|
+
location: 31
|
|
817
|
+
alias: mcountinhibit.HPM31
|
|
818
|
+
description: |
|
|
819
|
+
[when="COUNTINHIBIT_EN[31] == true"]
|
|
820
|
+
Alias of `mcountinhibit.HPM31` when `mhpmcounter31` is delegated to S-mode
|
|
821
|
+
(`mcounteren.HPM31`=1); otherwise read-only zero.
|
|
822
|
+
|
|
823
|
+
[when="COUNTINHIBIT_EN[31] == false"]
|
|
824
|
+
Since `mcountinhibit.HPM31` is not writable, this field is read-only zero.
|
|
825
|
+
type(): |
|
|
826
|
+
return COUNTINHIBIT_EN[31] ? CsrFieldType::RWR : CsrFieldType::RO;
|
|
827
|
+
reset_value(): |
|
|
828
|
+
return COUNTINHIBIT_EN[31] ? UNDEFINED_LEGAL : 0;
|
|
829
|
+
sw_write(csr_value): |
|
|
830
|
+
if (CSR[menvcfg].CDE == 1'b0) {
|
|
831
|
+
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
|
|
832
|
+
}
|
|
833
|
+
if (virtual_mode?()) {
|
|
834
|
+
raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
|
|
835
|
+
}
|
|
836
|
+
if (CSR[mcounteren].HPM31 == 1'b1) {
|
|
837
|
+
CSR[mcountinhibit].HPM31 = csr_value.HPM31;
|
|
838
|
+
return csr_value.HPM31;
|
|
839
|
+
}
|
|
840
|
+
return 1'b0;
|