udb 0.1.16 → 0.1.18

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (856) hide show
  1. checksums.yaml +4 -4
  2. data/.data/cfgs/example_rv64_with_overlay.yaml +157 -2
  3. data/.data/cfgs/mc100-32-full-example.yaml +6 -0
  4. data/.data/cfgs/profile/RVA23S64.yaml +1 -1
  5. data/.data/cfgs/profile/RVA23p1S64.yaml +217 -0
  6. data/.data/cfgs/profile/RVB23S64.yaml +1 -1
  7. data/.data/cfgs/profile/RVB23p1S64.yaml +179 -0
  8. data/.data/cfgs/qc_iu.yaml +14 -0
  9. data/.data/cfgs/rv32-riscv-tests.yaml +143 -0
  10. data/.data/cfgs/rv32-vector.yaml +144 -1
  11. data/.data/cfgs/rv64-riscv-tests.yaml +143 -0
  12. data/.data/cfgs/rv64-vector.yaml +145 -2
  13. data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.mva01s.yaml +2 -2
  14. data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.mvsa01.yaml +2 -2
  15. data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.pop.yaml +2 -2
  16. data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.popret.yaml +2 -2
  17. data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.popretz.yaml +2 -2
  18. data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.push.yaml +2 -2
  19. data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.pushfp.yaml +2 -2
  20. data/.data/spec/schemas/README.adoc +4 -1
  21. data/.data/spec/schemas/csr_schema.json +2 -2
  22. data/.data/spec/schemas/schema_defs.json +4 -1
  23. data/.data/spec/std/isa/csr/H/hgeie.yaml +38 -0
  24. data/.data/spec/std/isa/csr/H/hgeip.yaml +33 -0
  25. data/.data/spec/std/isa/csr/H/hideleg.yaml +120 -0
  26. data/.data/spec/std/isa/csr/H/hie.yaml +74 -0
  27. data/.data/spec/std/isa/csr/H/hip.yaml +88 -0
  28. data/.data/spec/std/isa/csr/H/hvip.yaml +46 -0
  29. data/.data/spec/std/isa/csr/H/vsie.yaml +86 -0
  30. data/.data/spec/std/isa/csr/H/vsip.yaml +98 -0
  31. data/.data/spec/std/isa/csr/H/vsscratch.yaml +29 -0
  32. data/.data/spec/std/isa/csr/I/mcounteren.layout +7 -0
  33. data/.data/spec/std/isa/csr/I/mcounteren.yaml +7 -0
  34. data/.data/spec/std/isa/csr/I/pmpaddr0.yaml +7 -7
  35. data/.data/spec/std/isa/csr/I/pmpaddr1.yaml +7 -7
  36. data/.data/spec/std/isa/csr/I/pmpaddr10.yaml +7 -7
  37. data/.data/spec/std/isa/csr/I/pmpaddr11.yaml +7 -7
  38. data/.data/spec/std/isa/csr/I/pmpaddr12.yaml +7 -7
  39. data/.data/spec/std/isa/csr/I/pmpaddr13.yaml +7 -7
  40. data/.data/spec/std/isa/csr/I/pmpaddr14.yaml +7 -7
  41. data/.data/spec/std/isa/csr/I/pmpaddr15.yaml +7 -7
  42. data/.data/spec/std/isa/csr/I/pmpaddr16.yaml +7 -7
  43. data/.data/spec/std/isa/csr/I/pmpaddr17.yaml +7 -7
  44. data/.data/spec/std/isa/csr/I/pmpaddr18.yaml +7 -7
  45. data/.data/spec/std/isa/csr/I/pmpaddr19.yaml +7 -7
  46. data/.data/spec/std/isa/csr/I/pmpaddr2.yaml +7 -7
  47. data/.data/spec/std/isa/csr/I/pmpaddr20.yaml +7 -7
  48. data/.data/spec/std/isa/csr/I/pmpaddr21.yaml +7 -7
  49. data/.data/spec/std/isa/csr/I/pmpaddr22.yaml +7 -7
  50. data/.data/spec/std/isa/csr/I/pmpaddr23.yaml +7 -7
  51. data/.data/spec/std/isa/csr/I/pmpaddr24.yaml +7 -7
  52. data/.data/spec/std/isa/csr/I/pmpaddr25.yaml +7 -7
  53. data/.data/spec/std/isa/csr/I/pmpaddr26.yaml +7 -7
  54. data/.data/spec/std/isa/csr/I/pmpaddr27.yaml +7 -7
  55. data/.data/spec/std/isa/csr/I/pmpaddr28.yaml +7 -7
  56. data/.data/spec/std/isa/csr/I/pmpaddr29.yaml +7 -7
  57. data/.data/spec/std/isa/csr/I/pmpaddr3.yaml +7 -7
  58. data/.data/spec/std/isa/csr/I/pmpaddr30.yaml +7 -7
  59. data/.data/spec/std/isa/csr/I/pmpaddr31.yaml +7 -7
  60. data/.data/spec/std/isa/csr/I/pmpaddr32.yaml +7 -7
  61. data/.data/spec/std/isa/csr/I/pmpaddr33.yaml +7 -7
  62. data/.data/spec/std/isa/csr/I/pmpaddr34.yaml +7 -7
  63. data/.data/spec/std/isa/csr/I/pmpaddr35.yaml +7 -7
  64. data/.data/spec/std/isa/csr/I/pmpaddr36.yaml +7 -7
  65. data/.data/spec/std/isa/csr/I/pmpaddr37.yaml +7 -7
  66. data/.data/spec/std/isa/csr/I/pmpaddr38.yaml +7 -7
  67. data/.data/spec/std/isa/csr/I/pmpaddr39.yaml +7 -7
  68. data/.data/spec/std/isa/csr/I/pmpaddr4.yaml +7 -7
  69. data/.data/spec/std/isa/csr/I/pmpaddr40.yaml +7 -7
  70. data/.data/spec/std/isa/csr/I/pmpaddr41.yaml +7 -7
  71. data/.data/spec/std/isa/csr/I/pmpaddr42.yaml +7 -7
  72. data/.data/spec/std/isa/csr/I/pmpaddr43.yaml +7 -7
  73. data/.data/spec/std/isa/csr/I/pmpaddr44.yaml +7 -7
  74. data/.data/spec/std/isa/csr/I/pmpaddr45.yaml +7 -7
  75. data/.data/spec/std/isa/csr/I/pmpaddr46.yaml +7 -7
  76. data/.data/spec/std/isa/csr/I/pmpaddr47.yaml +7 -7
  77. data/.data/spec/std/isa/csr/I/pmpaddr48.yaml +7 -7
  78. data/.data/spec/std/isa/csr/I/pmpaddr49.yaml +7 -7
  79. data/.data/spec/std/isa/csr/I/pmpaddr5.yaml +7 -7
  80. data/.data/spec/std/isa/csr/I/pmpaddr50.yaml +7 -7
  81. data/.data/spec/std/isa/csr/I/pmpaddr51.yaml +7 -7
  82. data/.data/spec/std/isa/csr/I/pmpaddr52.yaml +7 -7
  83. data/.data/spec/std/isa/csr/I/pmpaddr53.yaml +7 -7
  84. data/.data/spec/std/isa/csr/I/pmpaddr54.yaml +7 -7
  85. data/.data/spec/std/isa/csr/I/pmpaddr55.yaml +7 -7
  86. data/.data/spec/std/isa/csr/I/pmpaddr56.yaml +7 -7
  87. data/.data/spec/std/isa/csr/I/pmpaddr57.yaml +7 -7
  88. data/.data/spec/std/isa/csr/I/pmpaddr58.yaml +7 -7
  89. data/.data/spec/std/isa/csr/I/pmpaddr59.yaml +7 -7
  90. data/.data/spec/std/isa/csr/I/pmpaddr6.yaml +7 -7
  91. data/.data/spec/std/isa/csr/I/pmpaddr60.yaml +7 -7
  92. data/.data/spec/std/isa/csr/I/pmpaddr61.yaml +7 -7
  93. data/.data/spec/std/isa/csr/I/pmpaddr62.yaml +7 -7
  94. data/.data/spec/std/isa/csr/I/pmpaddr63.yaml +7 -7
  95. data/.data/spec/std/isa/csr/I/pmpaddr7.yaml +7 -7
  96. data/.data/spec/std/isa/csr/I/pmpaddr8.yaml +7 -7
  97. data/.data/spec/std/isa/csr/I/pmpaddr9.yaml +7 -7
  98. data/.data/spec/std/isa/csr/I/pmpaddrN.layout +7 -7
  99. data/.data/spec/std/isa/csr/Smcdeleg/scountinhibit.layout +111 -0
  100. data/.data/spec/std/isa/csr/Smcdeleg/scountinhibit.yaml +840 -0
  101. data/.data/spec/std/isa/csr/Smcntrpmf/mcyclecfg.yaml +2 -0
  102. data/.data/spec/std/isa/csr/Smcntrpmf/mcyclecfgh.yaml +2 -0
  103. data/.data/spec/std/isa/csr/Smcntrpmf/minstretcfg.yaml +2 -0
  104. data/.data/spec/std/isa/csr/Smcntrpmf/minstretcfgh.yaml +2 -0
  105. data/.data/spec/std/isa/csr/Smcsrind/mireg.yaml +2 -2
  106. data/.data/spec/std/isa/csr/Smcsrind/mireg2.yaml +2 -2
  107. data/.data/spec/std/isa/csr/Smcsrind/mireg3.yaml +2 -2
  108. data/.data/spec/std/isa/csr/Smcsrind/mireg4.yaml +2 -2
  109. data/.data/spec/std/isa/csr/Smcsrind/mireg5.yaml +2 -2
  110. data/.data/spec/std/isa/csr/Smcsrind/mireg6.yaml +2 -2
  111. data/.data/spec/std/isa/csr/Smcsrind/sireg.yaml +2 -2
  112. data/.data/spec/std/isa/csr/Smcsrind/sireg2.yaml +2 -2
  113. data/.data/spec/std/isa/csr/Smcsrind/sireg3.yaml +2 -2
  114. data/.data/spec/std/isa/csr/Smcsrind/sireg4.yaml +2 -2
  115. data/.data/spec/std/isa/csr/Smcsrind/sireg5.yaml +2 -2
  116. data/.data/spec/std/isa/csr/Smcsrind/sireg6.yaml +2 -2
  117. data/.data/spec/std/isa/csr/Smcsrind/vsireg.yaml +2 -2
  118. data/.data/spec/std/isa/csr/Smcsrind/vsireg2.yaml +2 -2
  119. data/.data/spec/std/isa/csr/Smcsrind/vsireg3.yaml +2 -2
  120. data/.data/spec/std/isa/csr/Smcsrind/vsireg4.yaml +2 -2
  121. data/.data/spec/std/isa/csr/Smcsrind/vsireg5.yaml +2 -2
  122. data/.data/spec/std/isa/csr/Smcsrind/vsireg6.yaml +2 -2
  123. data/.data/spec/std/isa/csr/Smctr/sctrctl.yaml +1 -1
  124. data/.data/spec/std/isa/csr/Smctr/sctrdepth.yaml +43 -0
  125. data/.data/spec/std/isa/csr/Smctr/sctrstatus.yaml +37 -0
  126. data/.data/spec/std/isa/csr/Smctr/vsctrctl.yaml +3 -1
  127. data/.data/spec/std/isa/csr/Sscofpmf/scountovf.layout +7 -0
  128. data/.data/spec/std/isa/csr/Sscofpmf/scountovf.yaml +7 -0
  129. data/.data/spec/std/isa/csr/Sstc/stimecmp.yaml +42 -0
  130. data/.data/spec/std/isa/csr/Sstc/stimecmph.yaml +43 -0
  131. data/.data/spec/std/isa/csr/Sstc/vstimecmp.yaml +45 -0
  132. data/.data/spec/std/isa/csr/Sstc/vstimecmph.yaml +46 -0
  133. data/.data/spec/std/isa/csr/V/vcsr.yaml +1 -1
  134. data/.data/spec/std/isa/csr/V/vl.yaml +1 -1
  135. data/.data/spec/std/isa/csr/V/vlenb.yaml +1 -1
  136. data/.data/spec/std/isa/csr/V/vstart.yaml +1 -1
  137. data/.data/spec/std/isa/csr/V/vtype.yaml +20 -1
  138. data/.data/spec/std/isa/csr/V/vxrm.yaml +1 -1
  139. data/.data/spec/std/isa/csr/V/vxsat.yaml +1 -1
  140. data/.data/spec/std/isa/csr/Zicntr/mcountinhibit.layout +1 -15
  141. data/.data/spec/std/isa/csr/Zicntr/mcountinhibit.yaml +29 -267
  142. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter10.yaml +4 -7
  143. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter10h.yaml +2 -4
  144. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter11.yaml +4 -7
  145. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter11h.yaml +2 -4
  146. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter12.yaml +4 -7
  147. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter12h.yaml +2 -4
  148. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter13.yaml +4 -7
  149. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter13h.yaml +2 -4
  150. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter14.yaml +4 -7
  151. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter14h.yaml +2 -4
  152. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter15.yaml +4 -7
  153. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter15h.yaml +2 -4
  154. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter16.yaml +4 -7
  155. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter16h.yaml +2 -4
  156. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter17.yaml +4 -7
  157. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter17h.yaml +2 -4
  158. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter18.yaml +4 -7
  159. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter18h.yaml +2 -4
  160. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter19.yaml +4 -7
  161. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter19h.yaml +2 -4
  162. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter20.yaml +4 -7
  163. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter20h.yaml +2 -4
  164. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter21.yaml +4 -7
  165. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter21h.yaml +2 -4
  166. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter22.yaml +4 -7
  167. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter22h.yaml +2 -4
  168. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter23.yaml +4 -7
  169. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter23h.yaml +2 -4
  170. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter24.yaml +4 -7
  171. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter24h.yaml +2 -4
  172. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter25.yaml +4 -7
  173. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter25h.yaml +2 -4
  174. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter26.yaml +4 -7
  175. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter26h.yaml +2 -4
  176. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter27.yaml +4 -7
  177. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter27h.yaml +2 -4
  178. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter28.yaml +4 -7
  179. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter28h.yaml +2 -4
  180. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter29.yaml +4 -7
  181. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter29h.yaml +2 -4
  182. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter3.yaml +4 -7
  183. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter30.yaml +4 -7
  184. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter30h.yaml +2 -4
  185. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter31.yaml +4 -7
  186. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter31h.yaml +2 -4
  187. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter3h.yaml +2 -4
  188. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter4.yaml +4 -7
  189. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter4h.yaml +2 -4
  190. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter5.yaml +4 -7
  191. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter5h.yaml +2 -4
  192. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter6.yaml +4 -7
  193. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter6h.yaml +2 -4
  194. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter7.yaml +4 -7
  195. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter7h.yaml +2 -4
  196. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter8.yaml +4 -7
  197. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter8h.yaml +2 -4
  198. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter9.yaml +4 -7
  199. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter9h.yaml +2 -4
  200. data/.data/spec/std/isa/csr/Zihpm/mhpmcounterN.layout +4 -7
  201. data/.data/spec/std/isa/csr/Zihpm/mhpmcounterNh.layout +2 -4
  202. data/.data/spec/std/isa/csr/Zihpm/mhpmevent10.yaml +4 -7
  203. data/.data/spec/std/isa/csr/Zihpm/mhpmevent10h.yaml +4 -4
  204. data/.data/spec/std/isa/csr/Zihpm/mhpmevent11.yaml +4 -7
  205. data/.data/spec/std/isa/csr/Zihpm/mhpmevent11h.yaml +4 -4
  206. data/.data/spec/std/isa/csr/Zihpm/mhpmevent12.yaml +4 -7
  207. data/.data/spec/std/isa/csr/Zihpm/mhpmevent12h.yaml +4 -4
  208. data/.data/spec/std/isa/csr/Zihpm/mhpmevent13.yaml +4 -7
  209. data/.data/spec/std/isa/csr/Zihpm/mhpmevent13h.yaml +4 -4
  210. data/.data/spec/std/isa/csr/Zihpm/mhpmevent14.yaml +4 -7
  211. data/.data/spec/std/isa/csr/Zihpm/mhpmevent14h.yaml +4 -4
  212. data/.data/spec/std/isa/csr/Zihpm/mhpmevent15.yaml +4 -7
  213. data/.data/spec/std/isa/csr/Zihpm/mhpmevent15h.yaml +4 -4
  214. data/.data/spec/std/isa/csr/Zihpm/mhpmevent16.yaml +4 -7
  215. data/.data/spec/std/isa/csr/Zihpm/mhpmevent16h.yaml +4 -4
  216. data/.data/spec/std/isa/csr/Zihpm/mhpmevent17.yaml +4 -7
  217. data/.data/spec/std/isa/csr/Zihpm/mhpmevent17h.yaml +4 -4
  218. data/.data/spec/std/isa/csr/Zihpm/mhpmevent18.yaml +4 -7
  219. data/.data/spec/std/isa/csr/Zihpm/mhpmevent18h.yaml +4 -4
  220. data/.data/spec/std/isa/csr/Zihpm/mhpmevent19.yaml +4 -7
  221. data/.data/spec/std/isa/csr/Zihpm/mhpmevent19h.yaml +4 -4
  222. data/.data/spec/std/isa/csr/Zihpm/mhpmevent20.yaml +4 -7
  223. data/.data/spec/std/isa/csr/Zihpm/mhpmevent20h.yaml +4 -4
  224. data/.data/spec/std/isa/csr/Zihpm/mhpmevent21.yaml +4 -7
  225. data/.data/spec/std/isa/csr/Zihpm/mhpmevent21h.yaml +4 -4
  226. data/.data/spec/std/isa/csr/Zihpm/mhpmevent22.yaml +4 -7
  227. data/.data/spec/std/isa/csr/Zihpm/mhpmevent22h.yaml +4 -4
  228. data/.data/spec/std/isa/csr/Zihpm/mhpmevent23.yaml +4 -7
  229. data/.data/spec/std/isa/csr/Zihpm/mhpmevent23h.yaml +4 -4
  230. data/.data/spec/std/isa/csr/Zihpm/mhpmevent24.yaml +4 -7
  231. data/.data/spec/std/isa/csr/Zihpm/mhpmevent24h.yaml +4 -4
  232. data/.data/spec/std/isa/csr/Zihpm/mhpmevent25.yaml +4 -7
  233. data/.data/spec/std/isa/csr/Zihpm/mhpmevent25h.yaml +4 -4
  234. data/.data/spec/std/isa/csr/Zihpm/mhpmevent26.yaml +4 -7
  235. data/.data/spec/std/isa/csr/Zihpm/mhpmevent26h.yaml +4 -4
  236. data/.data/spec/std/isa/csr/Zihpm/mhpmevent27.yaml +4 -7
  237. data/.data/spec/std/isa/csr/Zihpm/mhpmevent27h.yaml +4 -4
  238. data/.data/spec/std/isa/csr/Zihpm/mhpmevent28.yaml +4 -7
  239. data/.data/spec/std/isa/csr/Zihpm/mhpmevent28h.yaml +4 -4
  240. data/.data/spec/std/isa/csr/Zihpm/mhpmevent29.yaml +4 -7
  241. data/.data/spec/std/isa/csr/Zihpm/mhpmevent29h.yaml +4 -4
  242. data/.data/spec/std/isa/csr/Zihpm/mhpmevent3.yaml +4 -7
  243. data/.data/spec/std/isa/csr/Zihpm/mhpmevent30.yaml +4 -7
  244. data/.data/spec/std/isa/csr/Zihpm/mhpmevent30h.yaml +4 -4
  245. data/.data/spec/std/isa/csr/Zihpm/mhpmevent31.yaml +4 -7
  246. data/.data/spec/std/isa/csr/Zihpm/mhpmevent31h.yaml +4 -4
  247. data/.data/spec/std/isa/csr/Zihpm/mhpmevent3h.yaml +4 -4
  248. data/.data/spec/std/isa/csr/Zihpm/mhpmevent4.yaml +4 -7
  249. data/.data/spec/std/isa/csr/Zihpm/mhpmevent4h.yaml +4 -4
  250. data/.data/spec/std/isa/csr/Zihpm/mhpmevent5.yaml +4 -7
  251. data/.data/spec/std/isa/csr/Zihpm/mhpmevent5h.yaml +4 -4
  252. data/.data/spec/std/isa/csr/Zihpm/mhpmevent6.yaml +4 -7
  253. data/.data/spec/std/isa/csr/Zihpm/mhpmevent6h.yaml +4 -4
  254. data/.data/spec/std/isa/csr/Zihpm/mhpmevent7.yaml +4 -7
  255. data/.data/spec/std/isa/csr/Zihpm/mhpmevent7h.yaml +4 -4
  256. data/.data/spec/std/isa/csr/Zihpm/mhpmevent8.yaml +4 -7
  257. data/.data/spec/std/isa/csr/Zihpm/mhpmevent8h.yaml +4 -4
  258. data/.data/spec/std/isa/csr/Zihpm/mhpmevent9.yaml +4 -7
  259. data/.data/spec/std/isa/csr/Zihpm/mhpmevent9h.yaml +4 -4
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  599. data/.data/spec/std/isa/inst/Zabha/amoor.b.aq.yaml +1 -5
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  607. data/.data/spec/std/isa/inst/Zabha/amoswap.b.aq.yaml +1 -5
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  624. data/.data/spec/std/isa/inst/Zalrsc/lr.d.aq.yaml +0 -6
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  663. data/.data/spec/std/isa/inst/Zbc/clmulr.yaml +0 -4
  664. data/.data/spec/std/isa/inst/{B → Zbkc}/clmul.yaml +1 -7
  665. data/.data/spec/std/isa/inst/{B → Zbkc}/clmulh.yaml +1 -7
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  674. data/.data/spec/std/isa/inst/Zcb/c.lbu.yaml +2 -2
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  686. data/.data/spec/std/isa/inst/Zcd/c.fld.yaml +3 -3
  687. data/.data/spec/std/isa/inst/Zcd/c.fldsp.yaml +4 -4
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  690. data/.data/spec/std/isa/inst/Zcf/c.flw.yaml +3 -3
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  694. data/.data/spec/std/isa/inst/Zcmp/cm.mva01s.yaml +2 -2
  695. data/.data/spec/std/isa/inst/Zcmp/cm.mvsa01.yaml +2 -2
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  700. data/.data/spec/std/isa/inst/Zfh/fcvt.h.s.yaml +28 -20
  701. data/.data/spec/std/isa/inst/Zfh/fcvt.s.h.yaml +35 -20
  702. data/.data/spec/std/isa/inst/Zicbom/cbo.clean.yaml +2 -2
  703. data/.data/spec/std/isa/inst/Zicbom/cbo.flush.yaml +2 -2
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  705. data/.data/spec/std/isa/inst/Zicboz/cbo.zero.yaml +2 -2
  706. data/.data/spec/std/isa/inst/Zvabd/vabd.vv.yaml +3 -3
  707. data/.data/spec/std/isa/inst/Zvabd/vabd.vx.yaml +69 -0
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  709. data/.data/spec/std/isa/inst/Zvabd/{vabs.v.yaml → vabdu.vx.yaml} +17 -11
  710. data/.data/spec/std/isa/inst/Zvabd/vwabda.vv.yaml +1 -1
  711. data/.data/spec/std/isa/inst/Zvabd/vwabda.vx.yaml +73 -0
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  713. data/.data/spec/std/isa/inst/Zvabd/vwabdau.vx.yaml +74 -0
  714. data/.data/spec/std/isa/inst/Zvfbdota32f/vfbdota.vv.yaml +68 -0
  715. data/.data/spec/std/isa/inst/Zvfbfmin/vfncvtbf16.f.f.w.yaml +3 -1
  716. data/.data/spec/std/isa/inst/Zvfbfmin/vfwcvtbf16.f.f.v.yaml +3 -1
  717. data/.data/spec/std/isa/inst/Zvfofp4min/vfext.vf2.yaml +35 -0
  718. data/.data/spec/std/isa/inst/Zvfofp8min/vfncvt.f.f.q.yaml +31 -0
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  721. data/.data/spec/std/isa/inst/Zvzip/vpaire.vv.yaml +36 -0
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  724. data/.data/spec/std/isa/inst/Zvzip/vunzipo.v.yaml +33 -0
  725. data/.data/spec/std/isa/inst/Zvzip/vzip.vv.yaml +37 -0
  726. data/.data/spec/std/isa/isa/builtin_functions.idl +54 -1
  727. data/.data/spec/std/isa/isa/globals.isa +117 -5
  728. data/.data/spec/std/isa/isa/util.idl +1 -0
  729. data/.data/spec/std/isa/param/COUNTINHIBIT_EN.yaml +2 -10
  730. data/.data/spec/std/isa/param/HCONTEXT_IMPLEMENTED.yaml +29 -0
  731. data/.data/spec/std/isa/param/HCOUNTENABLE_EN.yaml +2 -5
  732. data/.data/spec/std/isa/param/HPM_COUNTER10_WIDTH.yaml +29 -0
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  761. data/.data/spec/std/isa/param/HPM_COUNTERN_WIDTH.layout +27 -0
  762. data/.data/spec/std/isa/param/HW_MSTATUS_FS_DIRTY_UPDATE.yaml +2 -4
  763. data/.data/spec/std/isa/param/HW_MSTATUS_VS_DIRTY_UPDATE.yaml +2 -4
  764. data/.data/spec/std/isa/param/LRSC_FAIL_ON_NON_EXACT_LRSC.yaml +1 -1
  765. data/.data/spec/std/isa/param/LRSC_FAIL_ON_VA_SYNONYM.yaml +1 -1
  766. data/.data/spec/std/isa/param/LRSC_MISALIGNED_BEHAVIOR.yaml +4 -4
  767. data/.data/spec/std/isa/param/LRSC_RESERVATION_STRATEGY.yaml +1 -1
  768. data/.data/spec/std/isa/param/{MCONTEXT_AVAILABLE.yaml → MCONTEXT_IMPLEMENTED.yaml} +3 -3
  769. data/.data/spec/std/isa/param/MCOUNTENABLE_EN.yaml +2 -5
  770. data/.data/spec/std/isa/param/MEDELEG_DELEGATABLE.yaml +121 -0
  771. data/.data/spec/std/isa/param/MEI_INTR_IMPL.yaml +28 -0
  772. data/.data/spec/std/isa/param/MIDELEG_DELEGATABLE.yaml +177 -0
  773. data/.data/spec/std/isa/param/MSI_INTR_IMPL.yaml +28 -0
  774. data/.data/spec/std/isa/param/MSTATUS_FS_LEGAL_VALUES.yaml +8 -15
  775. data/.data/spec/std/isa/param/MSTATUS_VS_LEGAL_VALUES.yaml +7 -15
  776. data/.data/spec/std/isa/param/MTI_INTR_IMPL.yaml +28 -0
  777. data/.data/spec/std/isa/param/MTVAL_WIDTH.yaml +17 -5
  778. data/.data/spec/std/isa/param/MUTABLE_MISA_A.yaml +1 -1
  779. data/.data/spec/std/isa/param/MUTABLE_MISA_B.yaml +1 -1
  780. data/.data/spec/std/isa/param/MUTABLE_MISA_C.yaml +1 -1
  781. data/.data/spec/std/isa/param/MUTABLE_MISA_D.yaml +1 -1
  782. data/.data/spec/std/isa/param/MUTABLE_MISA_F.yaml +1 -1
  783. data/.data/spec/std/isa/param/MUTABLE_MISA_M.yaml +1 -1
  784. data/.data/spec/std/isa/param/MUTABLE_MISA_Q.yaml +1 -1
  785. data/.data/spec/std/isa/param/MUTABLE_MISA_U.yaml +1 -1
  786. data/.data/spec/std/isa/param/MUTABLE_MISA_V.yaml +1 -1
  787. data/.data/spec/std/isa/param/{HCONTEXT_AVAILABLE.yaml → NON_STANDARD_EXTENSION_IMPLEMENTED.yaml} +5 -7
  788. data/.data/spec/std/isa/param/NUM_EXTERNAL_GUEST_INTERRUPTS.yaml +1 -1
  789. data/.data/spec/std/isa/param/NUM_PMP_ENTRIES.yaml +1 -1
  790. data/.data/spec/std/isa/param/REPORT_CAUSE_IN_MTVAL_ON_LANDING_PAD_SOFTWARE_CHECK.yaml +1 -1
  791. data/.data/spec/std/isa/param/REPORT_CAUSE_IN_STVAL_ON_LANDING_PAD_SOFTWARE_CHECK.yaml +1 -1
  792. data/.data/spec/std/isa/param/REPORT_CAUSE_IN_VSTVAL_ON_LANDING_PAD_SOFTWARE_CHECK.yaml +1 -1
  793. data/.data/spec/std/isa/param/SCONTEXT_IMPLEMENTED.yaml +18 -0
  794. data/.data/spec/std/isa/param/SCOUNTENABLE_EN.yaml +2 -6
  795. data/.data/spec/std/isa/param/SCTRDEPTH_DEPTH_LEGAL_VALUES.yaml +27 -0
  796. data/.data/spec/std/isa/param/SDTRIG_BREAKPOINT_REENTRANCY.yaml +45 -0
  797. data/.data/spec/std/isa/param/SDTRIG_ETRIGGER_SUPPORTED_EXCEPTIONS.yaml +37 -0
  798. data/.data/spec/std/isa/param/SDTRIG_ETRIGGER_SUPPORTED_TRIGGERS.yaml +25 -0
  799. data/.data/spec/std/isa/param/SDTRIG_ICOUNT_COUNT_HARDWIRED_1.yaml +23 -0
  800. data/.data/spec/std/isa/param/SDTRIG_ICOUNT_SELF_WRITE_SETS_PENDING.yaml +23 -0
  801. data/.data/spec/std/isa/param/SDTRIG_ICOUNT_SUPPORTED_TRIGGERS.yaml +25 -0
  802. data/.data/spec/std/isa/param/SDTRIG_ITRIGGER_SUPPORTED_INTERRUPTS.yaml +37 -0
  803. data/.data/spec/std/isa/param/SDTRIG_ITRIGGER_SUPPORTED_TRIGGERS.yaml +25 -0
  804. data/.data/spec/std/isa/param/SDTRIG_MAX_CHAIN_LENGTH.yaml +33 -0
  805. data/.data/spec/std/isa/param/SDTRIG_MCONTROL6_EXECUTE_WRITABLE.yaml +22 -0
  806. data/.data/spec/std/isa/param/SDTRIG_MCONTROL6_LOAD_WRITABLE.yaml +22 -0
  807. data/.data/spec/std/isa/param/SDTRIG_MCONTROL6_MASKMAX6.yaml +26 -0
  808. data/.data/spec/std/isa/param/SDTRIG_MCONTROL6_MATCH_LEGAL_VALUES.yaml +41 -0
  809. data/.data/spec/std/isa/param/SDTRIG_MCONTROL6_SELECT_WRITABLE.yaml +22 -0
  810. data/.data/spec/std/isa/param/SDTRIG_MCONTROL6_SIZE_LEGAL_VALUES.yaml +38 -0
  811. data/.data/spec/std/isa/param/SDTRIG_MCONTROL6_STORE_WRITABLE.yaml +22 -0
  812. data/.data/spec/std/isa/param/SDTRIG_MCONTROL6_SUPPORTED_TRIGGERS.yaml +25 -0
  813. data/.data/spec/std/isa/param/SDTRIG_M_WRITABLE.yaml +17 -0
  814. data/.data/spec/std/isa/param/SDTRIG_NUM_TRIGGERS.yaml +22 -0
  815. data/.data/spec/std/isa/param/SDTRIG_S_WRITABLE.yaml +19 -0
  816. data/.data/spec/std/isa/param/SDTRIG_TEXTRA_MHSELECT_MCONTEXT_MATCH.yaml +24 -0
  817. data/.data/spec/std/isa/param/SDTRIG_TEXTRA_MHSELECT_VMID_MATCH.yaml +23 -0
  818. data/.data/spec/std/isa/param/SDTRIG_TEXTRA_MHVALUE_LEN.yaml +26 -0
  819. data/.data/spec/std/isa/param/SDTRIG_TEXTRA_SSELECT_ASID_MATCH.yaml +23 -0
  820. data/.data/spec/std/isa/param/SDTRIG_TEXTRA_SSELECT_SCONTEXT_MATCH.yaml +26 -0
  821. data/.data/spec/std/isa/param/SDTRIG_TEXTRA_SVALUE_LEN.yaml +26 -0
  822. data/.data/spec/std/isa/param/SDTRIG_U_WRITABLE.yaml +19 -0
  823. data/.data/spec/std/isa/param/SDTRIG_VS_WRITABLE.yaml +19 -0
  824. data/.data/spec/std/isa/param/SDTRIG_VU_WRITABLE.yaml +19 -0
  825. data/.data/spec/std/isa/param/SEI_INTR_IMPL.yaml +28 -0
  826. data/.data/spec/std/isa/param/SSEED_READ_ONLY_ZERO.yaml +28 -0
  827. data/.data/spec/std/isa/param/SSI_INTR_IMPL.yaml +28 -0
  828. data/.data/spec/std/isa/param/STI_INTR_IMPL.yaml +33 -0
  829. data/.data/spec/std/isa/param/STVAL_WIDTH.yaml +81 -0
  830. data/.data/spec/std/isa/param/SUPPORTED_PMLEN_SMMPM.yaml +40 -0
  831. data/.data/spec/std/isa/param/SUPPORTED_PMLEN_SMNPM.yaml +42 -0
  832. data/.data/spec/std/isa/param/SUPPORTED_PMLEN_SSNPM.yaml +42 -0
  833. data/.data/spec/std/isa/param/TCONTROL_IMPLEMENTED.yaml +16 -0
  834. data/.data/spec/std/isa/param/TDATA2_IMPLEMENTED.yaml +26 -0
  835. data/.data/spec/std/isa/param/TDATA3_IMPLEMENTED.yaml +29 -0
  836. data/.data/spec/std/isa/param/TRAP_ON_ECALL_FROM_S.yaml +1 -1
  837. data/.data/spec/std/isa/param/TRAP_ON_ECALL_FROM_U.yaml +1 -1
  838. data/.data/spec/std/isa/param/TRAP_ON_ECALL_FROM_VS.yaml +1 -1
  839. data/.data/spec/std/isa/param/TRAP_ON_SFENCE_VMA_WHEN_SATP_MODE_IS_READ_ONLY.yaml +1 -1
  840. data/.data/spec/std/isa/param/USEED_READ_ONLY_ZERO.yaml +28 -0
  841. data/.data/spec/std/isa/param/WFI_FINITE.yaml +20 -0
  842. data/.data/spec/std/isa/param/WFI_U_MODE.yaml +20 -0
  843. data/.data/spec/std/isa/profile/RVA23p1S64.yaml +37 -0
  844. data/.data/spec/std/isa/profile/RVB23p1S64.yaml +39 -0
  845. data/.data/spec/std/isa/profile_family/RVA.yaml +3 -1
  846. data/.data/spec/std/isa/profile_family/RVB.yaml +3 -1
  847. data/.data/spec/std/isa/profile_release/RVA23p1.yaml +30 -0
  848. data/.data/spec/std/isa/profile_release/RVB23p1.yaml +30 -0
  849. data/lib/udb/Z3_VERSION +1 -1
  850. data/lib/udb/log.rb +16 -0
  851. data/lib/udb/obj/csr.rb +38 -45
  852. data/lib/udb/obj/database_obj.rb +1 -1
  853. data/lib/udb/obj/exception_code.rb +3 -3
  854. data/lib/udb/version.rb +1 -1
  855. metadata +139 -13
  856. data/.data/spec/std/isa/param/PMLEN.yaml +0 -20
data/.data/cfgs/rv32-riscv-tests.yaml CHANGED
@@ -248,3 +248,146 @@ params:
248
248
  # MSTATEEN_JVT_TYPE: rw
249
249
  HW_MSTATUS_FS_DIRTY_UPDATE: precise
250
250
  MUTABLE_MISA_F: false
251
+ MEI_INTR_IMPL: false
252
+ MSI_INTR_IMPL: false
253
+ MTI_INTR_IMPL: false
254
+ SEI_INTR_IMPL: false
255
+ SSI_INTR_IMPL: false
256
+ STI_INTR_IMPL: false
257
+ WFI_U_MODE: false
258
+ WFI_FINITE: true
259
+ NON_STANDARD_EXTENSION_IMPLEMENTED: false
260
+ MEDELEG_DELEGATABLE:
261
+ [
262
+ true,
263
+ true,
264
+ true,
265
+ true,
266
+ true,
267
+ true,
268
+ true,
269
+ true,
270
+ true,
271
+ true,
272
+ false,
273
+ false,
274
+ true,
275
+ true,
276
+ false,
277
+ true,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
290
+ false,
291
+ false,
292
+ false,
293
+ false,
294
+ false,
295
+ false,
296
+ false,
297
+ false,
298
+ false,
299
+ false,
300
+ false,
301
+ false,
302
+ false,
303
+ false,
304
+ false,
305
+ false,
306
+ false,
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+ false,
308
+ false,
309
+ false,
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+ false,
311
+ false,
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+ false,
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+ false,
314
+ false,
315
+ false,
316
+ false,
317
+ false,
318
+ false,
319
+ false,
320
+ false,
321
+ false,
322
+ false,
323
+ false,
324
+ false,
325
+ false,
326
+ ]
327
+ MIDELEG_DELEGATABLE:
328
+ [
329
+ false,
330
+ false,
331
+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
337
+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
381
+ false,
382
+ false,
383
+ false,
384
+ false,
385
+ false,
386
+ false,
387
+ false,
388
+ false,
389
+ false,
390
+ false,
391
+ false,
392
+ false,
393
+ ]
data/.data/cfgs/rv32-vector.yaml CHANGED
@@ -221,7 +221,7 @@ params:
221
221
  MSTATEEN_ENVCFG_TYPE: rw
222
222
  # Zvl32b parameters
223
223
  MUTABLE_MISA_V: false
224
- HW_MSTATUS_VS_DIRTY_UPDATE: never
224
+ HW_MSTATUS_VS_DIRTY_UPDATE: imprecise
225
225
  RVV_VL_WHEN_AVL_LT_DOUBLE_VLMAX: "VLMAX"
226
226
  FOLLOW_VTYPE_RESET_RECOMMENDATION: true
227
227
  VLEN: 128
@@ -282,3 +282,146 @@ params:
282
282
  false,
283
283
  false,
284
284
  ]
285
+ MEI_INTR_IMPL: false
286
+ MSI_INTR_IMPL: false
287
+ MTI_INTR_IMPL: false
288
+ SEI_INTR_IMPL: false
289
+ SSI_INTR_IMPL: false
290
+ STI_INTR_IMPL: false
291
+ WFI_U_MODE: false
292
+ WFI_FINITE: true
293
+ NON_STANDARD_EXTENSION_IMPLEMENTED: false
294
+ MEDELEG_DELEGATABLE:
295
+ [
296
+ true,
297
+ true,
298
+ true,
299
+ true,
300
+ true,
301
+ true,
302
+ true,
303
+ true,
304
+ true,
305
+ true,
306
+ false,
307
+ false,
308
+ true,
309
+ true,
310
+ false,
311
+ true,
312
+ false,
313
+ false,
314
+ false,
315
+ false,
316
+ false,
317
+ false,
318
+ false,
319
+ false,
320
+ false,
321
+ false,
322
+ false,
323
+ false,
324
+ false,
325
+ false,
326
+ false,
327
+ false,
328
+ false,
329
+ false,
330
+ false,
331
+ false,
332
+ false,
333
+ false,
334
+ false,
335
+ false,
336
+ false,
337
+ false,
338
+ false,
339
+ false,
340
+ false,
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+ false,
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+ false,
343
+ false,
344
+ false,
345
+ false,
346
+ false,
347
+ false,
348
+ false,
349
+ false,
350
+ false,
351
+ false,
352
+ false,
353
+ false,
354
+ false,
355
+ false,
356
+ false,
357
+ false,
358
+ false,
359
+ false,
360
+ ]
361
+ MIDELEG_DELEGATABLE:
362
+ [
363
+ false,
364
+ false,
365
+ false,
366
+ false,
367
+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
395
+ false,
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+ false,
397
+ false,
398
+ false,
399
+ false,
400
+ false,
401
+ false,
402
+ false,
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+ false,
404
+ false,
405
+ false,
406
+ false,
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+ false,
408
+ false,
409
+ false,
410
+ false,
411
+ false,
412
+ false,
413
+ false,
414
+ false,
415
+ false,
416
+ false,
417
+ false,
418
+ false,
419
+ false,
420
+ false,
421
+ false,
422
+ false,
423
+ false,
424
+ false,
425
+ false,
426
+ false,
427
+ ]
data/.data/cfgs/rv64-riscv-tests.yaml CHANGED
@@ -241,3 +241,146 @@ params:
241
241
  false,
242
242
  false,
243
243
  ]
244
+ MEI_INTR_IMPL: false
245
+ MSI_INTR_IMPL: false
246
+ MTI_INTR_IMPL: false
247
+ SEI_INTR_IMPL: false
248
+ SSI_INTR_IMPL: false
249
+ STI_INTR_IMPL: false
250
+ WFI_U_MODE: false
251
+ WFI_FINITE: true
252
+ NON_STANDARD_EXTENSION_IMPLEMENTED: false
253
+ MEDELEG_DELEGATABLE:
254
+ [
255
+ true,
256
+ true,
257
+ true,
258
+ true,
259
+ true,
260
+ true,
261
+ true,
262
+ true,
263
+ true,
264
+ true,
265
+ false,
266
+ false,
267
+ true,
268
+ true,
269
+ false,
270
+ true,
271
+ false,
272
+ false,
273
+ false,
274
+ false,
275
+ false,
276
+ false,
277
+ false,
278
+ false,
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+ false,
280
+ false,
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+ false,
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+ false,
283
+ false,
284
+ false,
285
+ false,
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+ false,
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+ false,
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+ false,
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+ false,
290
+ false,
291
+ false,
292
+ false,
293
+ false,
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+ false,
295
+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
312
+ false,
313
+ false,
314
+ false,
315
+ false,
316
+ false,
317
+ false,
318
+ false,
319
+ ]
320
+ MIDELEG_DELEGATABLE:
321
+ [
322
+ false,
323
+ false,
324
+ false,
325
+ false,
326
+ false,
327
+ false,
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+ false,
329
+ false,
330
+ false,
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+ false,
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+ false,
333
+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
340
+ false,
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+ false,
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+ false,
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+ false,
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+ false,
345
+ false,
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+ false,
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+ false,
348
+ false,
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+ false,
350
+ false,
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+ false,
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+ false,
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+ false,
354
+ false,
355
+ false,
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+ false,
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+ false,
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+ false,
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+ false,
360
+ false,
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+ false,
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+ false,
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+ false,
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+ false,
365
+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
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+ false,
375
+ false,
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+ false,
377
+ false,
378
+ false,
379
+ false,
380
+ false,
381
+ false,
382
+ false,
383
+ false,
384
+ false,
385
+ false,
386
+ ]
data/.data/cfgs/rv64-vector.yaml CHANGED
@@ -218,7 +218,7 @@ params:
218
218
  MSTATEEN_ENVCFG_TYPE: rw
219
219
  # Zvl32b parameters
220
220
  MUTABLE_MISA_V: false
221
- HW_MSTATUS_VS_DIRTY_UPDATE: never
221
+ HW_MSTATUS_VS_DIRTY_UPDATE: imprecise
222
222
  RVV_VL_WHEN_AVL_LT_DOUBLE_VLMAX: "VLMAX"
223
223
  FOLLOW_VTYPE_RESET_RECOMMENDATION: true
224
224
  VLEN: 128
@@ -244,7 +244,7 @@ params:
244
244
  VFREDUSUM_INACTIVE_NODE_ELEMENT_BEHAVIOR: "additive_identity"
245
245
  VFREDUSUM_FINAL_NODE_ELEMENT_BEHAVIOR: "additive_identity"
246
246
  IMPRECISE_VECTOR_TRAP_SETTABLE: false
247
- HW_MSTATUS_FS_DIRTY_UPDATE: never
247
+ HW_MSTATUS_FS_DIRTY_UPDATE: imprecise
248
248
  MUTABLE_MISA_F: false
249
249
  HPM_COUNTER_EN:
250
250
  [
@@ -281,3 +281,146 @@ params:
281
281
  false,
282
282
  false,
283
283
  ]
284
+ MEI_INTR_IMPL: false
285
+ MSI_INTR_IMPL: false
286
+ MTI_INTR_IMPL: false
287
+ SEI_INTR_IMPL: false
288
+ SSI_INTR_IMPL: false
289
+ STI_INTR_IMPL: false
290
+ WFI_U_MODE: false
291
+ WFI_FINITE: true
292
+ NON_STANDARD_EXTENSION_IMPLEMENTED: false
293
+ MEDELEG_DELEGATABLE:
294
+ [
295
+ true,
296
+ true,
297
+ true,
298
+ true,
299
+ true,
300
+ true,
301
+ true,
302
+ true,
303
+ true,
304
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+ false,
354
+ false,
355
+ false,
356
+ false,
357
+ false,
358
+ false,
359
+ ]
360
+ MIDELEG_DELEGATABLE:
361
+ [
362
+ false,
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+ false,
411
+ false,
412
+ false,
413
+ false,
414
+ false,
415
+ false,
416
+ false,
417
+ false,
418
+ false,
419
+ false,
420
+ false,
421
+ false,
422
+ false,
423
+ false,
424
+ false,
425
+ false,
426
+ ]
data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.mva01s.yaml CHANGED
@@ -27,8 +27,8 @@ access:
27
27
  vs: always
28
28
  vu: always
29
29
  operation(): |
30
- if (implemented?(ExtensionName::Zcmp) && (CSR[misa].C == 1'b0)) {
31
- raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
30
+ if (implemented?(ExtensionName::Zcmp) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
31
+ reserved_instruction($encoding);
32
32
  }
33
33
  XReg xreg1 = (r1s[2:1]>0) ? {1,0,r1s[2:0]} : {0,1,r1s[2:0]};
34
34
  XReg xreg2 = (r2s[2:1]>0) ? {1,0,r2s[2:0]} : {0,1,r2s[2:0]};
data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.mvsa01.yaml CHANGED
@@ -29,8 +29,8 @@ access:
29
29
  vs: always
30
30
  vu: always
31
31
  operation(): |
32
- if (implemented?(ExtensionName::Zcmp) && (CSR[misa].C == 1'b0)) {
33
- raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
32
+ if (implemented?(ExtensionName::Zcmp) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
33
+ reserved_instruction($encoding);
34
34
  }
35
35
  XReg xreg1 = (r1s[2:1]>0) ? {1,0,r1s[2:0]} : {0,1,r1s[2:0]};
36
36
  XReg xreg2 = (r2s[2:1]>0) ? {1,0,r2s[2:0]} : {0,1,r2s[2:0]};
data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.pop.yaml CHANGED
@@ -36,8 +36,8 @@ access:
36
36
  vs: always
37
37
  vu: always
38
38
  operation(): |
39
- if (implemented?(ExtensionName::Xqccmp) && (CSR[misa].C == 1'b0)) {
40
- raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
39
+ if (implemented?(ExtensionName::Xqccmp) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
40
+ reserved_instruction($encoding);
41
41
  }
42
42
 
43
43
  XReg virtual_address_sp = get_and_validate_stack_pointer(X[2], $encoding);
data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.popret.yaml CHANGED
@@ -36,8 +36,8 @@ access:
36
36
  vs: always
37
37
  vu: always
38
38
  operation(): |
39
- if (implemented?(ExtensionName::Xqccmp) && (CSR[misa].C == 1'b0)) {
40
- raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
39
+ if (implemented?(ExtensionName::Xqccmp) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
40
+ reserved_instruction($encoding);
41
41
  }
42
42
 
43
43
  XReg virtual_address_sp = get_and_validate_stack_pointer(X[2], $encoding);
data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.popretz.yaml CHANGED
@@ -36,8 +36,8 @@ access:
36
36
  vs: always
37
37
  vu: always
38
38
  operation(): |
39
- if (implemented?(ExtensionName::Xqccmp) && (CSR[misa].C == 1'b0)) {
40
- raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
39
+ if (implemented?(ExtensionName::Xqccmp) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
40
+ reserved_instruction($encoding);
41
41
  }
42
42
 
43
43
  XReg virtual_address_sp = get_and_validate_stack_pointer(X[2], $encoding);
data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.push.yaml CHANGED
@@ -37,8 +37,8 @@ access:
37
37
  vs: always
38
38
  vu: always
39
39
  operation(): |
40
- if (implemented?(ExtensionName::Xqccmp) && (CSR[misa].C == 1'b0)) {
41
- raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
40
+ if (implemented?(ExtensionName::Xqccmp) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
41
+ reserved_instruction($encoding);
42
42
  }
43
43
 
44
44
  XReg virtual_address_sp = get_and_validate_stack_pointer(X[2], $encoding);
data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.pushfp.yaml CHANGED
@@ -38,8 +38,8 @@ access:
38
38
  vs: always
39
39
  vu: always
40
40
  operation(): |
41
- if (implemented?(ExtensionName::Xqccmp) && (CSR[misa].C == 1'b0)) {
42
- raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
41
+ if (implemented?(ExtensionName::Xqccmp) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
42
+ reserved_instruction($encoding);
43
43
  }
44
44
 
45
45
  XReg virtual_address_sp = get_and_validate_stack_pointer(X[2], $encoding);
data/.data/spec/schemas/README.adoc CHANGED
@@ -36,8 +36,11 @@ published as GitHub releases under the tag `schemas/<schema_name>/<version>`.
36
36
  | 0.1 (current for all schemas except csr_schema.json)
37
37
  | https://riscv.github.io/riscv-unified-db/schemas/ext_schema.json/v0.1/ext_schema.json (example)
38
38
 
39
- | 0.2 (current for csr_schema.json)
39
+ | 0.2 (current for csr_schema.json except indirect_address description fix)
40
40
  | https://riscv.github.io/riscv-unified-db/schemas/csr_schema.json/v0.2/csr_schema.json
41
+
42
+ | 0.3 (current for csr_schema.json)
43
+ | https://riscv.github.io/riscv-unified-db/schemas/csr_schema.json/v0.3/csr_schema.json
41
44
  |===
42
45
 
43
46
  == Schema Identification (`$id`)
data/.data/spec/schemas/csr_schema.json CHANGED
@@ -1,6 +1,6 @@
1
1
  {
2
2
  "$schema": "http://json-schema.org/draft-07/schema#",
3
- "$id": "v0.2",
3
+ "$id": "v0.3",
4
4
  "title": "CSR description",
5
5
  "description": "A CSR register specification",
6
6
  "$defs": {
@@ -225,7 +225,7 @@
225
225
  },
226
226
  "indirect_address": {
227
227
  "type": "integer",
228
- "description": "Indirect address of the CSR, as given to the indirect CSRs of the `Smcsrind`/`Sscdrind` extensions"
228
+ "description": "Indirect address of the CSR, as given to the indirect CSRs of the `Smcsrind`/`Sscsrind` extensions"
229
229
  },
230
230
  "indirect_slot": {
231
231
  "type": "integer",