udb 0.1.16 → 0.1.18

data/.data/spec/std/isa/param/SDTRIG_TEXTRA_SVALUE_LEN.yaml

@@ -0,0 +1,26 @@
+# Copyright (C) 2026 Harvey Mudd College
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/param_schema.json
+
+$schema: param_schema.json#
+kind: parameter
+name: SDTRIG_TEXTRA_SVALUE_LEN
+description: |
+  The number of implemented textra.svalue bits. Bits above these are read-only zero.
+long_name: Number of implemented textra.svalue bits
+schema:
+  type: integer
+  minimum: 0
+  maximum: 32
+requirements:
+  idl(): |
+    MXLEN == 32 -> SDTRIG_TEXTRA_SVALUE_LEN <= 16;
+  reason: textra32.svalue is 16 bits wide.
+definedBy:
+  allOf:
+    - extension:
+        name: Sdtrig
+    - param:
+        name: TDATA3_IMPLEMENTED
+        equal: true

data/.data/spec/std/isa/param/SDTRIG_U_WRITABLE.yaml

@@ -0,0 +1,19 @@
+# Copyright (C) 2026 Harvey Mudd College
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/param_schema.json
+
+$schema: param_schema.json#
+kind: parameter
+name: SDTRIG_U_WRITABLE
+description: |
+  If true, the U bit in every trigger type that has one (mcontrol, mcontrol6, icount, itrigger, etrigger) can be set to 1, so triggers can match in U-mode.
+  If false, the U bit is read-only 0. Since the U bit resets to 0, 0 is always supported.
+long_name: Trigger U bit is writable
+schema:
+  type: boolean
+definedBy:
+  extension:
+    allOf:
+      - name: Sdtrig
+      - name: U

data/.data/spec/std/isa/param/SDTRIG_VS_WRITABLE.yaml

@@ -0,0 +1,19 @@
+# Copyright (C) 2026 Harvey Mudd College
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/param_schema.json
+
+$schema: param_schema.json#
+kind: parameter
+name: SDTRIG_VS_WRITABLE
+description: |
+  If true, the VS bit in every trigger type that has one (mcontrol, mcontrol6, icount, itrigger, etrigger) can be set to 1, so triggers can match in VS-mode.
+  If false, the VS bit is read-only 0. Since the VS bit resets to 0, 0 is always supported.
+long_name: Trigger VS bit is writable
+schema:
+  type: boolean
+definedBy:
+  extension:
+    allOf:
+      - name: Sdtrig
+      - name: H

data/.data/spec/std/isa/param/SDTRIG_VU_WRITABLE.yaml

@@ -0,0 +1,19 @@
+# Copyright (C) 2026 Harvey Mudd College
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/param_schema.json
+
+$schema: param_schema.json#
+kind: parameter
+name: SDTRIG_VU_WRITABLE
+description: |
+  If true, the VU bit in every trigger type that has one (mcontrol, mcontrol6, icount, itrigger, etrigger) can be set to 1, so triggers can match in VU-mode.
+  If false, the VU bit is read-only 0. Since the VU bit resets to 0, 0 is always supported.
+long_name: Trigger VU bit is writable
+schema:
+  type: boolean
+definedBy:
+  extension:
+    allOf:
+      - name: Sdtrig
+      - name: H

data/.data/spec/std/isa/param/SEI_INTR_IMPL.yaml

@@ -0,0 +1,28 @@
+# Copyright (c) David_Harris@hmc.edu 13 July 2026
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/param_schema.json
+
+$schema: param_schema.json#
+kind: parameter
+name: SEI_INTR_IMPL
+description: |
+  Whether or not supervisor-level external interrupts are implemented.
+
+  Possible values:
+
+  true::
+    Supervisor-level external interrupts are implemented.
+    `mie.SEIE` is writable, and `mideleg.SEI` is writable if `MIDELEG_DELEGATABLE[9]` is true.
+
+  false::
+    Supervisor-level external interrupts are not implemented.
+    `mie.SEIE`, `mip.SEIP`, and `mideleg.SEI` are read-only zero.
+long_name: Supervisor-level external interrupts are implemented
+schema:
+  type: boolean
+definedBy:
+  extension:
+    allOf:
+      - name: Zicsr
+      - name: S

data/.data/spec/std/isa/param/SSEED_READ_ONLY_ZERO.yaml

@@ -0,0 +1,28 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/param_schema.json
+
+$schema: param_schema.json#
+kind: parameter
+name: SSEED_READ_ONLY_ZERO
+long_name: Whether `mseccfg.SSEED` is read-only zero
+description: |
+  Indicates whether the `mseccfg.SSEED` field is hardwired read-only zero.
+
+  Options:
+
+    true::
+      `mseccfg.SSEED` is read-only zero.
+
+    false::
+      `mseccfg.SSEED` is writable.
+schema:
+  type: boolean
+definedBy:
+  extension:
+    allOf:
+      - name: Sm
+        version: ">= 1.12"
+      - name: Zkr
+      - name: S

data/.data/spec/std/isa/param/SSI_INTR_IMPL.yaml

@@ -0,0 +1,28 @@
+# Copyright (c) David_Harris@hmc.edu 13 July 2026
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/param_schema.json
+
+$schema: param_schema.json#
+kind: parameter
+name: SSI_INTR_IMPL
+description: |
+  Whether or not supervisor-level software interrupts are implemented.
+
+  Possible values:
+
+  true::
+    Supervisor-level software interrupts are implemented.
+    `mie.SSIE` is writable, and `mideleg.SSI` is writable if `MIDELEG_DELEGATABLE[1]` is true.
+
+  false::
+    Supervisor-level software interrupts are not implemented.
+    `mie.SSIE`, `mip.SSIP`, and `mideleg.SSI` are read-only zero.
+long_name: Supervisor-level software interrupts are implemented
+schema:
+  type: boolean
+definedBy:
+  extension:
+    allOf:
+      - name: Zicsr
+      - name: S

data/.data/spec/std/isa/param/STI_INTR_IMPL.yaml

@@ -0,0 +1,33 @@
+# Copyright (c) David_Harris@hmc.edu 13 July 2026
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/param_schema.json
+
+$schema: param_schema.json#
+kind: parameter
+name: STI_INTR_IMPL
+description: |
+  Whether or not supervisor-level timer interrupts are implemented.
+  If Sstc is implemented, then STI_INTR_IMPL must be true.
+
+  Possible values:
+
+  true::
+    Supervisor-level timer interrupts are implemented.
+    `mie.STIE` is writable, and `mideleg.STI` is writable if `MIDELEG_DELEGATABLE[5]` is true.
+
+  false::
+    Supervisor-level timer interrupts are not implemented.
+    `mie.STIE`, `mip.STIP`, and `mideleg.STI` are read-only zero.
+long_name: Supervisor-level timer interrupts are implemented
+schema:
+  type: boolean
+requirements:
+  idl(): |
+    implemented?(ExtensionName::Sstc) -> STI_INTR_IMPL;
+  reason: "When the Sstc extension is implemented, STIP reflects the timer interrupt signal resulting from `stimecmp`."
+definedBy:
+  extension:
+    allOf:
+      - name: Zicsr
+      - name: S

data/.data/spec/std/isa/param/STVAL_WIDTH.yaml

@@ -18,3 +18,84 @@ schema:
 definedBy:
   extension:
     name: S
+requirements:
+  idl(): |
+    ($array_size(SXLEN) == 1 && SXLEN[0] == 32) -> STVAL_WIDTH <= 32;
+
+    # in RV32, STVAL must be able to hold a physical address if S-mode takes an exception
+    # that reports an address
+    # Since physical address width can be larger than 32 with Sv32, need to downsize STVAL in that case
+    (
+      ($array_size(SXLEN) == 1 && SXLEN[0] == 32) &&
+      PHYS_ADDR_WIDTH > 32 &&
+        (
+          implemented?(ExtensionName::Sdext) ||
+          implemented?(ExtensionName::Sstvala) ||
+          REPORT_VA_IN_STVAL_ON_BREAKPOINT ||
+          REPORT_ENCODING_IN_STVAL_ON_ILLEGAL_INSTRUCTION ||
+          REPORT_VA_IN_STVAL_ON_LOAD_MISALIGNED ||
+          REPORT_VA_IN_STVAL_ON_STORE_AMO_MISALIGNED ||
+          REPORT_VA_IN_STVAL_ON_INSTRUCTION_MISALIGNED ||
+          REPORT_VA_IN_STVAL_ON_LOAD_ACCESS_FAULT ||
+          REPORT_VA_IN_STVAL_ON_STORE_AMO_ACCESS_FAULT ||
+          REPORT_VA_IN_STVAL_ON_INSTRUCTION_ACCESS_FAULT ||
+          REPORT_VA_IN_STVAL_ON_LOAD_PAGE_FAULT ||
+          REPORT_VA_IN_STVAL_ON_STORE_AMO_PAGE_FAULT ||
+          REPORT_VA_IN_STVAL_ON_INSTRUCTION_PAGE_FAULT
+        )
+    ) -> (STVAL_WIDTH == 32);
+
+    # TODO: uncomment when we have support for parameter/function comparison
+    #       on the RHS of a constraint.
+    # (
+    #   (
+    #     $array_includes?(SXLEN, 64) ||
+    #     (
+    #       ($array_size(SXLEN) == 1 && SXLEN[0] == 32) &&
+    #       PHYS_ADDR_WIDTH <= 32
+    #     )
+    #   ) &&
+    #     (
+    #       implemented?(ExtensionName::Sdext) ||
+    #       implemented?(ExtensionName::Sstvala) ||
+    #       REPORT_VA_IN_STVAL_ON_BREAKPOINT ||
+    #       REPORT_ENCODING_IN_STVAL_ON_ILLEGAL_INSTRUCTION ||
+    #       REPORT_VA_IN_STVAL_ON_LOAD_MISALIGNED ||
+    #       REPORT_VA_IN_STVAL_ON_STORE_AMO_MISALIGNED ||
+    #       REPORT_VA_IN_STVAL_ON_INSTRUCTION_MISALIGNED ||
+    #       REPORT_VA_IN_STVAL_ON_LOAD_ACCESS_FAULT ||
+    #       REPORT_VA_IN_STVAL_ON_STORE_AMO_ACCESS_FAULT ||
+    #       REPORT_VA_IN_STVAL_ON_INSTRUCTION_ACCESS_FAULT ||
+    #       REPORT_VA_IN_STVAL_ON_LOAD_PAGE_FAULT ||
+    #       REPORT_VA_IN_STVAL_ON_STORE_AMO_PAGE_FAULT ||
+    #       REPORT_VA_IN_STVAL_ON_INSTRUCTION_PAGE_FAULT
+    #     )
+    # ) -> (STVAL_WIDTH >= PHYS_ADDR_WIDTH);
+
+    # TODO: uncomment when we have support for parameter/function comparison
+    #       on the RHS of a constraint.
+    # (
+    #   implemented?(ExtensionName::S) &&
+    #   (
+    #     implemented?(ExtensionName::Sdext) ||
+    #     implemented?(ExtensionName::Sstvala) ||
+    #     REPORT_VA_IN_STVAL_ON_BREAKPOINT ||
+    #     REPORT_ENCODING_IN_STVAL_ON_ILLEGAL_INSTRUCTION ||
+    #     REPORT_VA_IN_STVAL_ON_LOAD_MISALIGNED ||
+    #     REPORT_VA_IN_STVAL_ON_STORE_AMO_MISALIGNED ||
+    #     REPORT_VA_IN_STVAL_ON_INSTRUCTION_MISALIGNED ||
+    #     REPORT_VA_IN_STVAL_ON_LOAD_ACCESS_FAULT ||
+    #     REPORT_VA_IN_STVAL_ON_STORE_AMO_ACCESS_FAULT ||
+    #     REPORT_VA_IN_STVAL_ON_INSTRUCTION_ACCESS_FAULT ||
+    #     REPORT_VA_IN_STVAL_ON_LOAD_PAGE_FAULT ||
+    #     REPORT_VA_IN_STVAL_ON_STORE_AMO_PAGE_FAULT ||
+    #     REPORT_VA_IN_STVAL_ON_INSTRUCTION_PAGE_FAULT
+    #   )
+    # ) -> (STVAL_WIDTH >= max_va_size());
+
+    (
+      implemented?(ExtensionName::Sstvala) ||
+      REPORT_ENCODING_IN_STVAL_ON_ILLEGAL_INSTRUCTION
+    ) -> (STVAL_WIDTH >= INSTR_ENC_SIZE);
+  reason: |
+    `stval` must be able to hold physical and/or virtual addresses

data/.data/spec/std/isa/param/SUPPORTED_PMLEN_SMMPM.yaml

@@ -0,0 +1,40 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/param_schema.json
+
+$schema: param_schema.json#
+kind: parameter
+name: SUPPORTED_PMLEN_SMMPM
+description: |
+  The `PMLEN` values supported by the `Smmpm` pointer masking facility
+  for M-mode, selected via the `PMM` field in `mseccfg`. `PMLEN` is the
+  number of high-order bits of an address that are masked.
+
+  Options:
+
+    0::
+      PMLEN=0 (pointer masking is disabled)
+    7::
+      PMLEN=XLEN-57 (i.e., PMLEN=7 on RV64)
+    16::
+      PMLEN=XLEN-48 (i.e., PMLEN=16 on RV64)
+
+  The current standard only supports these values (`zpm.adoc`, tag
+  `norm:pmlen_supported_values`). `PMM`=00 (pointer masking disabled,
+  PMLEN=0) is mandatory and always available, so it is mandatory
+  here.
+long_name: Pointer mask length for M mode
+schema:
+  type: array
+  items:
+    type: integer
+    enum: [0, 7, 16]
+  contains:
+    const: 0
+  minItems: 1
+  maxItems: 3
+  uniqueItems: true
+definedBy:
+  extension:
+    name: Smmpm

data/.data/spec/std/isa/param/SUPPORTED_PMLEN_SMNPM.yaml

@@ -0,0 +1,42 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/param_schema.json
+
+$schema: param_schema.json#
+kind: parameter
+name: SUPPORTED_PMLEN_SMNPM
+description: |
+  The `PMLEN` values supported by the `Smnpm` pointer masking facility
+  for the next privilege mode below M-mode (S/HS if S-mode is
+  implemented, or U-mode otherwise), selected via the `PMM` field in
+  `menvcfg`. `PMLEN` is the number of high-order bits of an address
+  that are masked.
+
+  Options:
+
+    0::
+      PMLEN=0 (pointer masking is disabled)
+    7::
+      PMLEN=XLEN-57 (i.e., PMLEN=7 on RV64)
+    16::
+      PMLEN=XLEN-48 (i.e., PMLEN=16 on RV64)
+
+  The current standard only supports these values (`zpm.adoc`, tag
+  `norm:pmlen_supported_values`). `PMM`=00 (pointer masking disabled,
+  PMLEN=0) is mandatory and always available, so it is mandatory
+  here.
+long_name: Pointer mask length for next mode below M mode
+schema:
+  type: array
+  items:
+    type: integer
+    enum: [0, 7, 16]
+  contains:
+    const: 0
+  minItems: 1
+  maxItems: 3
+  uniqueItems: true
+definedBy:
+  extension:
+    name: Smnpm

data/.data/spec/std/isa/param/SUPPORTED_PMLEN_SSNPM.yaml

@@ -0,0 +1,42 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/param_schema.json
+
+$schema: param_schema.json#
+kind: parameter
+name: SUPPORTED_PMLEN_SSNPM
+description: |
+  The `PMLEN` values supported by the `Ssnpm` pointer masking facility
+  for the next privilege mode below S-mode (U-mode, and VS-/VU-modes if
+  the H extension is present), selected via the `PMM` field in
+  `senvcfg`. `PMLEN` is the number of high-order bits of an address
+  that are masked.
+
+  Options:
+
+    0::
+      PMLEN=0 (pointer masking is disabled)
+    7::
+      PMLEN=XLEN-57 (i.e., PMLEN=7 on RV64)
+    16::
+      PMLEN=XLEN-48 (i.e., PMLEN=16 on RV64)
+
+  The current standard only supports these values (`zpm.adoc`, tag
+  `norm:pmlen_supported_values`). `PMM`=00 (pointer masking disabled,
+  PMLEN=0) is mandatory and always available, so it is mandatory
+  here.
+long_name: Pointer mask length for next mode below S-mode
+schema:
+  type: array
+  items:
+    type: integer
+    enum: [0, 7, 16]
+  contains:
+    const: 0
+  minItems: 1
+  maxItems: 3
+  uniqueItems: true
+definedBy:
+  extension:
+    name: Ssnpm

data/.data/spec/std/isa/param/TCONTROL_IMPLEMENTED.yaml

@@ -0,0 +1,16 @@
+# Copyright (C) 2026 Harvey Mudd College
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/param_schema.json
+
+$schema: param_schema.json#
+kind: parameter
+name: TCONTROL_IMPLEMENTED
+description: |
+  Specifies if the tcontrol CSR is implemented
+long_name: tcontrol CSR is implemented
+schema:
+  type: boolean
+definedBy:
+  extension:
+    name: Sdtrig

data/.data/spec/std/isa/param/TDATA2_IMPLEMENTED.yaml

@@ -0,0 +1,26 @@
+# Copyright (C) 2026 Harvey Mudd College
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/param_schema.json
+
+$schema: param_schema.json#
+kind: parameter
+name: TDATA2_IMPLEMENTED
+description: |
+  Specifies if the tdata2 CSR is implemented.
+
+  Debug spec 1.0, tdata2: "This register is optional if no implemented triggers use it."
+long_name: tdata2 CSR is implemented
+schema:
+  type: boolean
+requirements:
+  idl(): |
+    (
+      $array_includes?(SDTRIG_MCONTROL6_SUPPORTED_TRIGGERS, true) ||
+      $array_includes?(SDTRIG_ITRIGGER_SUPPORTED_TRIGGERS, true) ||
+      $array_includes?(SDTRIG_ETRIGGER_SUPPORTED_TRIGGERS, true)
+    ) -> TDATA2_IMPLEMENTED;
+  reason: These trigger types require the tdata2 CSR.
+definedBy:
+  extension:
+    name: Sdtrig

data/.data/spec/std/isa/param/TDATA3_IMPLEMENTED.yaml

@@ -0,0 +1,29 @@
+# Copyright (C) 2026 Harvey Mudd College
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/param_schema.json
+
+$schema: param_schema.json#
+kind: parameter
+name: TDATA3_IMPLEMENTED
+description: |
+  Specifies if the tdata3 CSR is implemented.
+
+  Debug spec 1.0, tdata3: "This register is optional if no implemented triggers use it."
+
+  Must be true if any trigger supports type 2-6 (mcontrol, icount, itrigger, etrigger, mcontrol6).
+long_name: tdata3 CSR is implemented
+schema:
+  type: boolean
+requirements:
+  idl(): |
+    (
+      $array_includes?(SDTRIG_MCONTROL6_SUPPORTED_TRIGGERS, true) ||
+      $array_includes?(SDTRIG_ICOUNT_SUPPORTED_TRIGGERS, true) ||
+      $array_includes?(SDTRIG_ITRIGGER_SUPPORTED_TRIGGERS, true) ||
+      $array_includes?(SDTRIG_ETRIGGER_SUPPORTED_TRIGGERS, true)
+    ) -> TDATA3_IMPLEMENTED;
+  reason: Trigger types 2-6 (mcontrol, icount, itrigger, etrigger, mcontrol6) use tdata3.
+definedBy:
+  extension:
+    name: Sdtrig

data/.data/spec/std/isa/param/TRAP_ON_ECALL_FROM_S.yaml

@@ -11,7 +11,7 @@ description: |
 
   The spec states that implementations may handle ECALLs transparently
   without raising a trap, in which case the EEI must provide a builtin.
-long_name: TODO
+long_name: "Trap on ECALL from S-mode"
 schema:
   type: boolean
   default: true

data/.data/spec/std/isa/param/TRAP_ON_ECALL_FROM_U.yaml

@@ -11,7 +11,7 @@ description: |
 
   The spec states that implementations may handle ECALLs transparently
   without raising a trap, in which case the EEI must provide a builtin.
-long_name: TODO
+long_name: "Trap on ECALL from U-mode"
 schema:
   type: boolean
   default: true

data/.data/spec/std/isa/param/TRAP_ON_ECALL_FROM_VS.yaml

@@ -11,7 +11,7 @@ description: |
 
   The spec states that implementations may handle ECALLs transparently
   without raising a trap, in which case the EEI must provide a builtin.
-long_name: TODO
+long_name: "Trap on ECALL from VS-mode"
 schema:
   type: boolean
   default: true

data/.data/spec/std/isa/param/TRAP_ON_SFENCE_VMA_WHEN_SATP_MODE_IS_READ_ONLY.yaml

@@ -17,7 +17,7 @@ description: |
 
   TRAP_ON_SFENCE_VMA_WHEN_SATP_MODE_IS_READ_ONLY has no effect when
   some virtual translation mode is supported.
-long_name: TODO
+long_name: "Trap on SFENCE.VMA when satp.MODE is read-only"
 schema:
   type: boolean
   default: false

data/.data/spec/std/isa/param/USEED_READ_ONLY_ZERO.yaml

@@ -0,0 +1,28 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/param_schema.json
+
+$schema: param_schema.json#
+kind: parameter
+name: USEED_READ_ONLY_ZERO
+long_name: Whether `mseccfg.USEED` is read-only zero
+description: |
+  Indicates whether the `mseccfg.USEED` field is hardwired read-only zero.
+
+  Options:
+
+    true::
+      `mseccfg.USEED` is read-only zero.
+
+    false::
+      `mseccfg.USEED` is writable.
+schema:
+  type: boolean
+definedBy:
+  extension:
+    allOf:
+      - name: Sm
+        version: ">= 1.12"
+      - name: Zkr
+      - name: U

data/.data/spec/std/isa/param/WFI_FINITE.yaml

@@ -0,0 +1,20 @@
+# Copyright (c) 2026 Neel Kumar
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/param_schema.json
+
+$schema: param_schema.json#
+kind: parameter
+name: WFI_FINITE
+long_name: |
+  Whether WFI resumes execution after a finite amount of time
+definedBy:
+  extension:
+    name: Sm
+description: |
+  Options:
+
+    * true: WFI resumes execution after waiting for a finite amount of time
+    * false: WFI may continue waiting until another event causes execution to resume
+schema:
+  type: boolean

data/.data/spec/std/isa/param/WFI_U_MODE.yaml

@@ -0,0 +1,20 @@
+# Copyright (c) 2026 Neel Kumar
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/param_schema.json
+
+$schema: param_schema.json#
+kind: parameter
+name: WFI_U_MODE
+long_name: |
+  Whether WFI is supported in U mode
+definedBy:
+  extension:
+    name: Sm
+description: |
+  Options:
+
+    * true: WFI can be executed in U mode
+    * false: Executing WFI in U mode raises an illegal instruction exception
+schema:
+  type: boolean

data/.data/spec/std/isa/profile/RVA23p1S64.yaml

@@ -0,0 +1,37 @@
+# Copyright (c) 2026 RISC-V International
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/profile_schema.json
+
+$schema: profile_schema.json#
+kind: profile
+name: RVA23p1S64
+long_name: S-mode extensions for version 23.1 of the 64-bit Apps Processor profile
+marketing_name: RVA23p1S64
+$inherits: "profile/RVA23S64.yaml#"
+release: { $ref: profile_release/RVA23p1.yaml# }
+introduction: |
+  The RVA23p1S64 profile specifies the ISA features available to a
+  supervisor-mode execution environment in 64-bit application processors.
+  RVA23p1S64 is based on and requires an RVA23S64 implementation.
+extensions:
+  Svrsw60t59b:
+    presence:
+      optional: development
+    version: ~> 1.0
+  Ssdbltrp:
+    presence:
+      optional: development
+    version: ~> 1.0
+  Ssccfg:
+    presence:
+      optional: development
+    version: ~> 1.0
+  Ssctr:
+    presence:
+      optional: expansion
+    version: ~> 1.0
+  Ssqosid:
+    presence:
+      optional: expansion
+    version: ~> 1.0