udb 0.1.16 → 0.1.18

data/.data/spec/std/isa/inst/Zfh/fcvt.h.s.yaml

@@ -6,7 +6,7 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: fcvt.h.s
-long_name: Convert half-precision float to a single-precision float
+long_name: Convert single-precision float to a half-precision float
 definedBy:
   extension:
     oneOf:
@@ -14,7 +14,7 @@ definedBy:
       - name: Zhinxmin
 assembly: fd, fs1, rm
 description: |
-  Converts a half-precision number in floating-point register _fs1_ into a single-precision floating-point number in
+  Converts a single-precision number in floating-point register _fs1_ into a half-precision floating-point number in
   floating-point register _fd_.
 
   `fcvt.h.s` rounds according to the _rm_ field.
@@ -39,34 +39,42 @@ access:
 operation(): |
   check_f_ok($encoding);
 
-  Bits<16> hp_value = F[fs1][15:0];
+  # STATUS: INCOMPLETE. Narrowing single -> half loses precision, so it needs
+  # IEEE 754 rounding (per _rm_), overflow/underflow and inexact handling.
+  # Only the NaN, infinity and zero cases below are handled. Every other
+  # input hits the assert(false) TODO. softfloat_roundPackToF16 does not exist
+  # in fp.idl yet.
+  Bits<32> sp_value = F[fs1][31:0];
 
-  Bits<1> sign = hp_value[15];
-  Bits<5> exp = hp_value[14:10];
-  Bits<10> frac = hp_value[9:0];
+  Bits<1> sign = sp_value[31];
+  Bits<8> exp = sp_value[30:23];
+  Bits<23> frac = sp_value[22:0];
 
-  if (exp == 0x1F) {
+  if (exp == 0xFF) {
     if (frac != 0) {
-      if ((hp_value & 0x0200) != 0) {
+      # NaN. A signaling NaN has the quiet bit (frac[22]) clear and raises NV.
+      if ((sp_value & 0x00400000) == 0) {
         set_fp_flag(FpFlag::NV);
       }
-      F[fd] = HP_CANONICAL_NAN;
+      F[fd] = nan_box(16, FLEN, HP_CANONICAL_NAN);
     } else {
-      F[fd] = packToF32UI(sign, 0xFF, 0);
+      F[fd] = nan_box(16, FLEN, packToF16UI( sign, 0x1F, 0 ));
     }
   } else {
-    if (exp != 0) {
-      if (frac != 0) {
-        F[fd] = packToF32UI(sign, 0, 0);
-      } else {
-        Bits<6> norm_exp;
-        (norm_exp, frac) = softfloat_normSubnormalF16Sig( frac );
-        exp = norm_exp - 1;
-        F[fd] = packToF32UI(sign, exp + 0x70, frac << 13);
-      }
+
+    # frac is a 24-bit significand, the bottom 9 bits LSB are extracted and OR-red
+    # into a sticky flag, the top 15 MSBs are extracted, the LSB of this top slice
+    # is OR-red with the sticky
+    Bits<16> frac16 = (frac >> 9) | ((frac & 0x1ff) != 0 ? 1 : 0);
+    if ((exp | frac16) == 0) {
+      F[fd] = nan_box(16, FLEN, packToF16UI( sign, 0, 0 ));
     } else {
-      F[fd] = packToF32UI(sign, exp + 0x70, frac << 13);
+      # TODO: finite nonzero inputs need softfloat_roundPackToF16, which is not implemented.
+      # The frac16/sticky computation above is unverified draft code.
+      assert(false, "TODO: implement roundPackToF16");
+      # F[fd] = softfloat_roundPackToF16(sign, exp - 0x71, frac16 | 0x4000);
     }
+
   }
 
   mark_f_state_dirty();

data/.data/spec/std/isa/inst/Zfh/fcvt.s.h.yaml

@@ -6,7 +6,7 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: fcvt.s.h
-long_name: Convert single-precision float to a half-precision float
+long_name: Convert half-precision float to a single-precision float
 definedBy:
   extension:
     oneOf:
@@ -14,7 +14,7 @@ definedBy:
       - name: Zhinxmin
 assembly: fd, fs1, rm
 description: |
-  Converts a single-precision number in floating-point register _fs1_ into a half-precision floating-point number in
+  Converts a half-precision number in floating-point register _fs1_ into a single-precision floating-point number in
   floating-point register _fd_.
 
   `fcvt.s.h` will never round, and so the 'rm' field is effectively ignored.
@@ -36,34 +36,49 @@ access:
 operation(): |
   check_f_ok($encoding);
 
-  Bits<32> sp_value = F[fs1][31:0];
+  Bits<16> hp_value = F[fs1][15:0];
 
-  Bits<1> sign = sp_value[31];
-  Bits<8> exp = sp_value[30:23];
-  Bits<23> frac = sp_value[22:0];
+  Bits<1> sign = hp_value[15];
+  Bits<5> exp = hp_value[14:10];
+  Bits<10> frac = hp_value[9:0];
 
-  if (exp == 0xFF) {
+  Bits<32> sp_value = 0;
+
+  # Widening half -> single is always exact, so no rounding is needed.
+  if (exp == 0x1F) {
     if (frac != 0) {
-      if ((sp_value & 0x00400000) != 0) {
+      # NaN. A signaling NaN has the quiet bit (frac[9]) clear and raises NV.
+      # Either way the result is the canonical single-precision NaN.
+      if ((hp_value & 0x0200) == 0) {
         set_fp_flag(FpFlag::NV);
       }
-      F[fd] = nan_box(16, FLEN, HP_CANONICAL_NAN);
+      sp_value = SP_CANONICAL_NAN;
     } else {
-      F[fd] = nan_box(16, FLEN, packToF16UI( sign, 0x1F, 0 ));
+      sp_value = packToF32UI(sign, 0xFF, 0);
     }
-  } else {
-
-    # frac is a 24-bit significand, the bottom 9 bits LSB are extracted and OR-red
-    # into a sticky flag, the top 15 MSBs are extracted, the LSB of this top slice
-    # is OR-red with the sticky
-    Bits<16> frac16 = (frac >> 9) | ((frac & 0x1ff) != 0 ? 1 : 0);
-    if ((exp | frac16) == 0) {
-      F[fd] = nan_box(16, FLEN, packToF16UI( sign, 0, 0 ));
+  } else if (exp == 0) {
+    if (frac == 0) {
+      sp_value = packToF32UI(sign, 0, 0);
     } else {
-      assert(false, "TODO: implement roundPackToF16");
-      # F[fd] = soffloat_roundPackToF16(sign, exp - 0x71, frac16 | 0x4000);
+      # Subnormal half: value = frac * 2^-24. Shift the leading 1 of frac up to
+      # bit 10 (the implicit-bit position), drop it, and rebias the exponent.
+      Bits<16> frac16 = frac;
+      Bits<8> shift_dist = count_leading_zeros(16, frac16) - 5;
+      Bits<32> norm_frac = ((frac16 << shift_dist) & 0x3FF);
+      sp_value = packToF32UI(sign, 0x71 - shift_dist, norm_frac << 13);
     }
+  } else {
+    # Normal half: rebias the exponent (127 - 15 = 0x70) and widen the fraction
+    # from 10 to 23 bits.
+    Bits<8> sp_exp = exp;
+    Bits<32> frac32 = frac;
+    sp_value = packToF32UI(sign, sp_exp + 0x70, frac32 << 13);
+  }
 
+  if (implemented?(ExtensionName::D)) {
+    F[fd] = nan_box(32, 64, sp_value);
+  } else {
+    F[fd] = sp_value;
   }
 
   mark_f_state_dirty();

data/.data/spec/std/isa/inst/Zicbom/cbo.clean.yaml

@@ -18,7 +18,7 @@ description: |
 
   `cbo.clean` is ordered by `FENCE` instructions but not `FENCE.I` or `SFENCE.VMA`.
 
-  <%- if CACHE_BLOCK_SIZE.bit_length > [PMP_GRANULARITY, PMA_GRANULARITY].min -%>
+  <%- if (CACHE_BLOCK_SIZE.bit_length - 1) > [PMP_GRANULARITY, PMA_GRANULARITY].min -%>
   Both PMP and PMA access control must be the same for all bytes in the block; otherwise, `cbo.clean` has UNSPECIFIED behavior.
   <%- end -%>
 
@@ -31,7 +31,7 @@ description: |
     * `Store/AMO Page Fault` if virtual memory translation fails <% if ext?(:H) %>when V=0 or during VS-stage translation<% end %>
     * `Store/AMO Access Fault` if a PMP or PMA access check fails
 
-  <%- if CACHE_BLOCK_SIZE.bit_length <= [PMP_GRANULARITY, PMA_GRANULARITY].min -%>
+  <%- if (CACHE_BLOCK_SIZE.bit_length - 1) <= [PMP_GRANULARITY, PMA_GRANULARITY].min -%>
   Because cache blocks are naturally aligned and always fit in a single PMP or PMA regions, the PMP
   and PMA access checks only need to check a single address in the line.
   <%- end -%>

data/.data/spec/std/isa/inst/Zicbom/cbo.flush.yaml

@@ -12,7 +12,7 @@ description: |
 
   `cbo.flush` is ordered by `FENCE` instructions but not `FENCE.I` or `SFENCE.VMA`.
 
-  <%- if CACHE_BLOCK_SIZE.bit_length > [PMP_GRANULARITY, PMA_GRANULARITY].min -%>
+  <%- if (CACHE_BLOCK_SIZE.bit_length - 1) > [PMP_GRANULARITY, PMA_GRANULARITY].min -%>
   Both PMP and PMA access control must be the same for all bytes in the block; otherwise, `cbo.flush` has UNSPECIFIED behavior.
   <%- end -%>
 
@@ -25,7 +25,7 @@ description: |
     * `Store/AMO Page Fault` if virtual memory translation fails <% if ext?(:H) %>when V=0 or during VS-stage translation<% end %>
     * `Store/AMO Access Fault` if a PMP or PMA access check fails.
 
-  <%- if CACHE_BLOCK_SIZE.bit_length <= [PMP_GRANULARITY, PMA_GRANULARITY].min -%>
+  <%- if (CACHE_BLOCK_SIZE.bit_length - 1) <= [PMP_GRANULARITY, PMA_GRANULARITY].min -%>
   Because cache blocks are naturally aligned and always fit in a single PMP or PMA regions, the PMP
   and PMA access checks only need to check a single address in the line.
   <%- end -%>

data/.data/spec/std/isa/inst/Zicbom/cbo.inval.yaml

@@ -51,7 +51,7 @@ description: |
 
   `cbo.inval` is ordered by `FENCE` instructions but not `FENCE.I` or `SFENCE.VMA`.
 
-  <%- if CACHE_BLOCK_SIZE.bit_length > [PMP_GRANULARITY, PMA_GRANULARITY].min -%>
+  <%- if (CACHE_BLOCK_SIZE.bit_length - 1) > [PMP_GRANULARITY, PMA_GRANULARITY].min -%>
   Both PMP and PMA access control must be the same for all bytes in the block; otherwise, `cbo.inval` has UNSPECIFIED behavior.
   <%- end -%>
 
@@ -64,7 +64,7 @@ description: |
     * `Store/AMO Page Fault` if virtual memory translation fails <% if ext?(:H) %>when V=0 or during VS-stage translation<% end %>
     * `Store/AMO Access Fault` if a PMP or PMA access check fails.
 
-  <%- if CACHE_BLOCK_SIZE.bit_length <= [PMP_GRANULARITY, PMA_GRANULARITY].min -%>
+  <%- if (CACHE_BLOCK_SIZE.bit_length - 1) <= [PMP_GRANULARITY, PMA_GRANULARITY].min -%>
   Because cache blocks are naturally aligned and always fit in a single PMP or PMA regions, the PMP
   and PMA access checks only need to check a single address in the line.
   <%- end -%>

data/.data/spec/std/isa/inst/Zicboz/cbo.zero.yaml

@@ -14,7 +14,7 @@ description: |
 
   `cbo.zero` is ordered by `FENCE` instructions but not `FENCE.I` or `SFENCE.VMA`.
 
-  <%- if CACHE_BLOCK_SIZE.bit_length > [PMP_GRANULARITY, PMA_GRANULARITY].min -%>
+  <%- if (CACHE_BLOCK_SIZE.bit_length - 1) > [PMP_GRANULARITY, PMA_GRANULARITY].min -%>
   Both PMP and PMA access control must be the same for all bytes in the block; otherwise, `cbo.zero` has UNSPECIFIED behavior.
   <%- end -%>
 
@@ -27,7 +27,7 @@ description: |
     * `Store/AMO Page Fault` if virtual memory translation fails <% if ext?(:H) %>when V=0 or during VS-stage translation<% end %>
     * `Store/AMO Access Fault` if a PMP or PMA access check fails.
 
-  <%- if CACHE_BLOCK_SIZE.bit_length <= [PMP_GRANULARITY, PMA_GRANULARITY].min -%>
+  <%- if (CACHE_BLOCK_SIZE.bit_length - 1) <= [PMP_GRANULARITY, PMA_GRANULARITY].min -%>
   Because cache blocks are naturally aligned and always fit in a single PMP or PMA regions, the PMP
   and PMA access checks only need to check a single address in the line.
   <%- end -%>

data/.data/spec/std/isa/inst/Zvabd/vabd.vv.yaml

@@ -11,13 +11,13 @@ description: |
   Computes the element-wise absolute difference of two signed integer SEW-bit
   source operands vs1 and vs2 and writes the result to vd according to mask vm.
 
-  Reserved when SEW is neither 8 nor 16.
+  Supports SEW of 8, 16, and 32. If the Zve64x extension is supported, SEW 64 is also supported.
 definedBy:
   extension:
     name: Zvabd
 assembly: vd, vs2, vs1, vm
 encoding:
-  match: 010001-----------010-----1010111
+  match: 010101-----------010-----1010111
   variables:
     - name: vm
       location: 25
@@ -35,7 +35,7 @@ access:
 operation(): |
   VectorState state = vector_state();
 
-  if (state.sew != 8 && state.sew != 16) {
+  if (!implemented?(ExtensionName::Zve64x) && state.sew > 32) {
     raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
   }
 

data/.data/spec/std/isa/inst/Zvabd/vabd.vx.yaml

@@ -0,0 +1,69 @@
+# Copyright (c) Alibaba Damo Academy
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: vabd.vx
+long_name: Vector Single-Width Signed Integer Absolute Difference with Scalar
+description: |
+  Computes the element-wise absolute difference of signed integer operands from
+  vector register vs2 and scalar register xs1, and writes the SEW-bit results to
+  vd according to mask vm. The scalar is sign-extended or truncated to SEW.
+
+  Supports SEW of 8, 16, and 32, and SEW of 64 when Zve64x is implemented.
+definedBy:
+  extension:
+    name: Zvabd
+assembly: vd, vs2, xs1, vm
+encoding:
+  match: 010101-----------110-----1010111
+  variables:
+    - name: vm
+      location: 25
+    - name: vs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: vd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+pseudoinstructions:
+  - when: xs1 == 0
+    to: vabs.v vd, vs2, vm
+operation(): |
+  VectorState state = vector_state();
+
+  VectorLmulType lmul_type = state.lmul_type;
+
+  XReg vlen = VLEN;
+  XReg vlmax;
+  if (lmul_type == VectorLmulType::Multiply) {
+    vlmax = (vlen << state.log2_lmul) >> state.log2_sew;
+  } else {
+    vlmax = (vlen >> state.log2_lmul) >> state.log2_sew;
+  }
+
+  Bits<64> scalar = $signed(X[xs1]);
+
+  for (U32 i = CSR[vstart].VALUE; i < CSR[vl].VALUE; i++) {
+    U32 start_bit_pos = i * state.sew;
+    U32 end_bit_pos = start_bit_pos + state.sew - 1;
+    if (vm == 1'b1 || V[0][i:i] == 1'b1) {
+      # active element
+      if ($signed(V[vs2][end_bit_pos:start_bit_pos]) >= $signed(scalar[state.sew-1:0])) {
+        V[vd][end_bit_pos:start_bit_pos] = V[vs2][end_bit_pos:start_bit_pos] - scalar[state.sew-1:0];
+      } else {
+        V[vd][end_bit_pos:start_bit_pos] = scalar[state.sew-1:0] - V[vs2][end_bit_pos:start_bit_pos];
+      }
+    }
+    # inactive element: handled according to vtype.VMA policy
+  }
+  # tail elements (i >= vl): handled according to vtype.VTA policy
+
+  CSR[vstart].VALUE = 0;

data/.data/spec/std/isa/inst/Zvabd/vabdu.vv.yaml

@@ -11,13 +11,13 @@ description: |
   Computes the element-wise absolute difference of two unsigned integer SEW-bit
   source operands vs1 and vs2 and writes the result to vd according to mask vm.
 
-  Reserved when SEW is neither 8 nor 16.
+  Supports SEW of 8, 16, and 32. If the Zve64x extension is supported, SEW 64 is also supported.
 definedBy:
   extension:
     name: Zvabd
 assembly: vd, vs2, vs1, vm
 encoding:
-  match: 010011-----------010-----1010111
+  match: 010110-----------010-----1010111
   variables:
     - name: vm
       location: 25
@@ -35,7 +35,7 @@ access:
 operation(): |
   VectorState state = vector_state();
 
-  if (state.sew != 8 && state.sew != 16) {
+  if (!implemented?(ExtensionName::Zve64x) && state.sew > 32) {
     raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
   }
 

data/.data/spec/std/isa/inst/Zvabd/{vabs.v.yaml → vabdu.vx.yaml}

@@ -5,25 +5,28 @@
 
 $schema: "inst_schema.json#"
 kind: instruction
-name: vabs.v
-long_name: Vector Single-Width Signed Integer Absolute
+name: vabdu.vx
+long_name: Vector Single-Width Unsigned Integer Absolute Difference with Scalar
 description: |
-  An absolute value operation is performed on each element of vs2, storing the
-  result in vector register vd according to mask vm.
+  Computes the element-wise absolute difference of unsigned integer operands
+  from vector register vs2 and scalar register xs1, and writes the SEW-bit
+  results to vd according to mask vm. The scalar is sign-extended or truncated
+  to SEW before being interpreted as an unsigned value.
 
-  vabs.v supports SEW of 8, 16, and 32 when Zve32x is implemented.
-  When Zve64x is implemented, vabs.v also supports SEW of 64.
+  Supports SEW of 8, 16, and 32, and SEW of 64 when Zve64x is implemented.
 definedBy:
   extension:
     name: Zvabd
-assembly: vd, vs2, vm
+assembly: vd, vs2, xs1, vm
 encoding:
-  match: 010010------10000010-----1010111
+  match: 010110-----------110-----1010111
   variables:
     - name: vm
       location: 25
     - name: vs2
       location: 24-20
+    - name: xs1
+      location: 19-15
     - name: vd
       location: 11-7
 access:
@@ -33,6 +36,7 @@ access:
   vu: always
 operation(): |
   VectorState state = vector_state();
+
   VectorLmulType lmul_type = state.lmul_type;
 
   XReg vlen = VLEN;
@@ -43,15 +47,17 @@ operation(): |
     vlmax = (vlen >> state.log2_lmul) >> state.log2_sew;
   }
 
+  Bits<64> scalar = $signed(X[xs1]);
+
   for (U32 i = CSR[vstart].VALUE; i < CSR[vl].VALUE; i++) {
     U32 start_bit_pos = i * state.sew;
     U32 end_bit_pos = start_bit_pos + state.sew - 1;
     if (vm == 1'b1 || V[0][i:i] == 1'b1) {
       # active element
-      if (V[vs2][end_bit_pos:end_bit_pos] == 1'b1) {
-        V[vd][end_bit_pos:start_bit_pos] = -$signed(V[vs2][end_bit_pos:start_bit_pos]);
+      if (V[vs2][end_bit_pos:start_bit_pos] >= scalar[state.sew-1:0]) {
+        V[vd][end_bit_pos:start_bit_pos] = V[vs2][end_bit_pos:start_bit_pos] - scalar[state.sew-1:0];
       } else {
-        V[vd][end_bit_pos:start_bit_pos] = V[vs2][end_bit_pos:start_bit_pos];
+        V[vd][end_bit_pos:start_bit_pos] = scalar[state.sew-1:0] - V[vs2][end_bit_pos:start_bit_pos];
       }
     }
     # inactive element: handled according to vtype.VMA policy

data/.data/spec/std/isa/inst/Zvabd/vwabda.vv.yaml

@@ -18,7 +18,7 @@ definedBy:
     name: Zvabd
 assembly: vd, vs2, vs1, vm
 encoding:
-  match: 010101-----------010-----1010111
+  match: 111101-----------000-----1010111
   variables:
     - name: vm
       location: 25

data/.data/spec/std/isa/inst/Zvabd/vwabda.vx.yaml

@@ -0,0 +1,73 @@
+# Copyright (c) Alibaba Damo Academy
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: vwabda.vx
+long_name: Vector Widening Signed Integer Absolute Difference and Accumulate with Scalar
+description: |
+  Computes the element-wise absolute difference of signed integer operands from
+  vector register vs2 and scalar register xs1, and accumulates the results into
+  the 2*SEW-bit elements of vd. The scalar is sign-extended or truncated to SEW.
+
+  Reserved when SEW is neither 8 nor 16.
+definedBy:
+  extension:
+    name: Zvabd
+assembly: vd, vs2, xs1, vm
+encoding:
+  match: 111101-----------100-----1010111
+  variables:
+    - name: vm
+      location: 25
+    - name: vs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: vd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  VectorState state = vector_state();
+
+  if (state.sew != 8 && state.sew != 16) {
+    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  }
+
+  VectorLmulType lmul_type = state.lmul_type;
+
+  XReg vlen = VLEN;
+  XReg vlmax;
+  if (lmul_type == VectorLmulType::Multiply) {
+    vlmax = (vlen << state.log2_lmul) >> state.log2_sew;
+  } else {
+    vlmax = (vlen >> state.log2_lmul) >> state.log2_sew;
+  }
+
+  Bits<64> scalar = $signed(X[xs1]);
+  U32 sew2 = state.sew + state.sew;
+
+  for (U32 i = CSR[vstart].VALUE; i < CSR[vl].VALUE; i++) {
+    U32 src_start = i * state.sew;
+    U32 src_end = src_start + state.sew - 1;
+    U32 dst_start = i * sew2;
+    U32 dst_end = dst_start + sew2 - 1;
+    if (vm == 1'b1 || V[0][i:i] == 1'b1) {
+      # active element
+      if ($signed(V[vs2][src_end:src_start]) >= $signed(scalar[state.sew-1:0])) {
+        V[vd][dst_end:dst_start] = V[vd][dst_end:dst_start] + (V[vs2][src_end:src_start] - scalar[state.sew-1:0]);
+      } else {
+        V[vd][dst_end:dst_start] = V[vd][dst_end:dst_start] + (scalar[state.sew-1:0] - V[vs2][src_end:src_start]);
+      }
+    }
+    # inactive element: handled according to vtype.VMA policy
+  }
+  # tail elements (i >= vl): handled according to vtype.VTA policy
+
+  CSR[vstart].VALUE = 0;

data/.data/spec/std/isa/inst/Zvabd/vwabdau.vv.yaml

@@ -18,7 +18,7 @@ definedBy:
     name: Zvabd
 assembly: vd, vs2, vs1, vm
 encoding:
-  match: 010110-----------010-----1010111
+  match: 111110-----------000-----1010111
   variables:
     - name: vm
       location: 25

data/.data/spec/std/isa/inst/Zvabd/vwabdau.vx.yaml

@@ -0,0 +1,74 @@
+# Copyright (c) Alibaba Damo Academy
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: vwabdau.vx
+long_name: Vector Widening Unsigned Integer Absolute Difference and Accumulate with Scalar
+description: |
+  Computes the element-wise absolute difference of unsigned integer operands
+  from vector register vs2 and scalar register xs1, and accumulates the results
+  into the 2*SEW-bit elements of vd. The scalar is sign-extended or truncated
+  to SEW before being interpreted as an unsigned value.
+
+  Reserved when SEW is neither 8 nor 16.
+definedBy:
+  extension:
+    name: Zvabd
+assembly: vd, vs2, xs1, vm
+encoding:
+  match: 111110-----------100-----1010111
+  variables:
+    - name: vm
+      location: 25
+    - name: vs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: vd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  VectorState state = vector_state();
+
+  if (state.sew != 8 && state.sew != 16) {
+    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  }
+
+  VectorLmulType lmul_type = state.lmul_type;
+
+  XReg vlen = VLEN;
+  XReg vlmax;
+  if (lmul_type == VectorLmulType::Multiply) {
+    vlmax = (vlen << state.log2_lmul) >> state.log2_sew;
+  } else {
+    vlmax = (vlen >> state.log2_lmul) >> state.log2_sew;
+  }
+
+  Bits<64> scalar = $signed(X[xs1]);
+  U32 sew2 = state.sew + state.sew;
+
+  for (U32 i = CSR[vstart].VALUE; i < CSR[vl].VALUE; i++) {
+    U32 src_start = i * state.sew;
+    U32 src_end = src_start + state.sew - 1;
+    U32 dst_start = i * sew2;
+    U32 dst_end = dst_start + sew2 - 1;
+    if (vm == 1'b1 || V[0][i:i] == 1'b1) {
+      # active element
+      if (V[vs2][src_end:src_start] >= scalar[state.sew-1:0]) {
+        V[vd][dst_end:dst_start] = V[vd][dst_end:dst_start] + (V[vs2][src_end:src_start] - scalar[state.sew-1:0]);
+      } else {
+        V[vd][dst_end:dst_start] = V[vd][dst_end:dst_start] + (scalar[state.sew-1:0] - V[vs2][src_end:src_start]);
+      }
+    }
+    # inactive element: handled according to vtype.VMA policy
+  }
+  # tail elements (i >= vl): handled according to vtype.VTA policy
+
+  CSR[vstart].VALUE = 0;

data/.data/spec/std/isa/inst/Zvfbdota32f/vfbdota.vv.yaml

@@ -0,0 +1,68 @@
+# Copyright (c) 2026 Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: vfbdota.vv
+long_name: Vector FP32 Batched Dot Product Accumulate
+description: |
+  Performs a batched
+  dot-product operation on FP32 vectors, accumulating into FP32. The
+  instruction is reserved unless `SEW=32` and `LMUL=1`. The `vs1`, `vs2`, and
+  `vd` operands all have `EEW=SEW`.
+
+  The batched dot-product family treats `vs1` as an EMUL=1 vector register
+  group and `vs2` as an EMUL=8 vector register group, computing eight
+  independent dot products and accumulating the results into `vd`. `vl` sets
+  the length of each dot product. Tail elements are substituted with the bit
+  pattern of all zeros, then the computation is performed as though
+  `vl=VLMAX`.
+
+  For long-vector implementations with `VLEN > 8*EEW`, `ci` is a 3-bit
+  scaled-by-8 immediate indicating which eight elements of `vd` are read and
+  written. The `ci` field is encoded in `vs2[2:0]`; those bits are not needed
+  for the register address because `vs2` addresses an EMUL=8 register group.
+  The instruction is reserved if `ci >= VLEN/(8*EEW)`. Destination elements
+  at or beyond `ci+8` are tail elements, elements below `ci` are prestart
+  elements, and the remaining elements are body elements. The destination
+  vector register group cannot overlap either source vector register group.
+  Masked-off body elements follow the current mask agnostic or undisturbed
+  policy, and the instruction is reserved when `vstart` is nonzero; exceptions
+  are always reported with `vstart=0`.
+
+  The FP32 products are first computed to full precision, setting the invalid
+  operation exception flag as appropriate. The products are then optionally
+  rounded to FP32 according to the dynamic rounding mode, setting the inexact,
+  overflow, and underflow exception flags as appropriate. The sum of these
+  products and the accumulator is then computed as though by `vfredusum.vs`
+  with `SEW=32`, including the setting of exception flags.
+
+  This formulation allows significant implementation flexibility while being
+  sufficiently precise to implement SGEMM. The algorithm used by
+  `vfredusum.vs` offers several implementation choices; implementations are
+  not required to use the same algorithm configuration for `vfbdota.vv` as for
+  `vfredusum.vs`.
+definedBy:
+  extension:
+    name: Zvfbdota32f
+assembly: vd, vs2, vs1, ci, vm
+encoding:
+  match: 101011-----------001-----1110111
+  variables:
+    - name: vm
+      location: 25-25
+    - name: vs2
+      location: 24-23
+    - name: ci
+      location: 22-20
+    - name: vs1
+      location: 19-15
+    - name: vd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+data_independent_timing: false
+operation(): |