udb 0.1.16 → 0.1.18

data/.data/spec/std/isa/inst/V/vfwmacc.vv.yaml

@@ -11,7 +11,9 @@ description: |
   No description available.
 definedBy:
   extension:
-    name: Zvl32b
+    anyOf:
+      - name: Zvl32b
+      - name: Zvfbfa
 assembly: vd, vs1, vs2, vm
 encoding:
   match: 111100-----------001-----1010111

data/.data/spec/std/isa/inst/V/vfwmsac.vf.yaml

@@ -11,7 +11,9 @@ description: |
   No description available.
 definedBy:
   extension:
-    name: Zvl32b
+    anyOf:
+      - name: Zvl32b
+      - name: Zvfbfa
 assembly: vd, fs1, vs2, vm
 encoding:
   match: 111110-----------101-----1010111

data/.data/spec/std/isa/inst/V/vfwmsac.vv.yaml

@@ -11,7 +11,9 @@ description: |
   No description available.
 definedBy:
   extension:
-    name: Zvl32b
+    anyOf:
+      - name: Zvl32b
+      - name: Zvfbfa
 assembly: vd, vs1, vs2, vm
 encoding:
   match: 111110-----------001-----1010111

data/.data/spec/std/isa/inst/V/vfwmul.vf.yaml

@@ -11,7 +11,9 @@ description: |
   No description available.
 definedBy:
   extension:
-    name: Zvl32b
+    anyOf:
+      - name: Zvl32b
+      - name: Zvfbfa
 assembly: vd, vs2, fs1, vm
 encoding:
   match: 111000-----------101-----1010111

data/.data/spec/std/isa/inst/V/vfwmul.vv.yaml

@@ -11,7 +11,9 @@ description: |
   No description available.
 definedBy:
   extension:
-    name: Zvl32b
+    anyOf:
+      - name: Zvl32b
+      - name: Zvfbfa
 assembly: vd, vs2, vs1, vm
 encoding:
   match: 111000-----------001-----1010111

data/.data/spec/std/isa/inst/V/vfwnmacc.vf.yaml

@@ -11,7 +11,9 @@ description: |
   No description available.
 definedBy:
   extension:
-    name: Zvl32b
+    anyOf:
+      - name: Zvl32b
+      - name: Zvfbfa
 assembly: vd, fs1, vs2, vm
 encoding:
   match: 111101-----------101-----1010111

data/.data/spec/std/isa/inst/V/vfwnmacc.vv.yaml

@@ -11,7 +11,9 @@ description: |
   No description available.
 definedBy:
   extension:
-    name: Zvl32b
+    anyOf:
+      - name: Zvl32b
+      - name: Zvfbfa
 assembly: vd, vs1, vs2, vm
 encoding:
   match: 111101-----------001-----1010111

data/.data/spec/std/isa/inst/V/vfwnmsac.vf.yaml

@@ -11,7 +11,9 @@ description: |
   No description available.
 definedBy:
   extension:
-    name: Zvl32b
+    anyOf:
+      - name: Zvl32b
+      - name: Zvfbfa
 assembly: vd, fs1, vs2, vm
 encoding:
   match: 111111-----------101-----1010111

data/.data/spec/std/isa/inst/V/vfwnmsac.vv.yaml

@@ -11,7 +11,9 @@ description: |
   No description available.
 definedBy:
   extension:
-    name: Zvl32b
+    anyOf:
+      - name: Zvl32b
+      - name: Zvfbfa
 assembly: vd, vs1, vs2, vm
 encoding:
   match: 111111-----------001-----1010111

data/.data/spec/std/isa/inst/V/vfwsub.vf.yaml

@@ -11,7 +11,9 @@ description: |
   Performs floating-point subtraction on elements from vector register vs2 and floating-point scalar register fs1, widens the results, and stores them in vector register vd, using vector mask vm. The operation follows IEEE 754 floating-point arithmetic rules.
 definedBy:
   extension:
-    name: Zvl32b
+    anyOf:
+      - name: Zvl32b
+      - name: Zvfbfa
 assembly: vd, vs2, fs1, vm
 encoding:
   match: 110010-----------101-----1010111

data/.data/spec/std/isa/inst/V/vfwsub.vv.yaml

@@ -11,7 +11,9 @@ description: |
   Performs floating-point subtraction on elements from vector registers vs2 and vs1, widens the results, and stores them in vector register vd, using vector mask vm. The operation follows IEEE 754 floating-point arithmetic rules.
 definedBy:
   extension:
-    name: Zvl32b
+    anyOf:
+      - name: Zvl32b
+      - name: Zvfbfa
 assembly: vd, vs2, vs1, vm
 encoding:
   match: 110010-----------001-----1010111

data/.data/spec/std/isa/inst/V/vfwsub.wf.yaml

@@ -11,7 +11,9 @@ description: |
   No description available.
 definedBy:
   extension:
-    name: Zvl32b
+    anyOf:
+      - name: Zvl32b
+      - name: Zvfbfa
 assembly: vd, vs2, fs1, vm
 encoding:
   match: 110110-----------101-----1010111

data/.data/spec/std/isa/inst/V/vfwsub.wv.yaml

@@ -11,7 +11,9 @@ description: |
   No description available.
 definedBy:
   extension:
-    name: Zvl32b
+    anyOf:
+      - name: Zvl32b
+      - name: Zvfbfa
 assembly: vd, vs2, vs1, vm
 encoding:
   match: 110110-----------001-----1010111

data/.data/spec/std/isa/inst/V/vmfeq.vf.yaml

@@ -11,7 +11,9 @@ description: |
   No description available.
 definedBy:
   extension:
-    name: Zvl32b
+    anyOf:
+      - name: Zvl32b
+      - name: Zvfbfa
 assembly: vd, vs2, fs1, vm
 encoding:
   match: 011000-----------101-----1010111

data/.data/spec/std/isa/inst/V/vmfeq.vv.yaml

@@ -11,7 +11,9 @@ description: |
   No description available.
 definedBy:
   extension:
-    name: Zvl32b
+    anyOf:
+      - name: Zvl32b
+      - name: Zvfbfa
 assembly: vd, vs2, vs1, vm
 encoding:
   match: 011000-----------001-----1010111

data/.data/spec/std/isa/inst/V/vmfge.vf.yaml

@@ -11,7 +11,9 @@ description: |
   No description available.
 definedBy:
   extension:
-    name: Zvl32b
+    anyOf:
+      - name: Zvl32b
+      - name: Zvfbfa
 assembly: vd, vs2, fs1, vm
 encoding:
   match: 011111-----------101-----1010111

data/.data/spec/std/isa/inst/V/vmfgt.vf.yaml

@@ -11,7 +11,9 @@ description: |
   No description available.
 definedBy:
   extension:
-    name: Zvl32b
+    anyOf:
+      - name: Zvl32b
+      - name: Zvfbfa
 assembly: vd, vs2, fs1, vm
 encoding:
   match: 011101-----------101-----1010111

data/.data/spec/std/isa/inst/V/vmfle.vf.yaml

@@ -11,7 +11,9 @@ description: |
   No description available.
 definedBy:
   extension:
-    name: Zvl32b
+    anyOf:
+      - name: Zvl32b
+      - name: Zvfbfa
 assembly: vd, vs2, fs1, vm
 encoding:
   match: 011001-----------101-----1010111

data/.data/spec/std/isa/inst/V/vmfle.vv.yaml

@@ -11,7 +11,9 @@ description: |
   No description available.
 definedBy:
   extension:
-    name: Zvl32b
+    anyOf:
+      - name: Zvl32b
+      - name: Zvfbfa
 assembly: vd, vs2, vs1, vm
 encoding:
   match: 011001-----------001-----1010111

data/.data/spec/std/isa/inst/V/vmflt.vf.yaml

@@ -11,7 +11,9 @@ description: |
   No description available.
 definedBy:
   extension:
-    name: Zvl32b
+    anyOf:
+      - name: Zvl32b
+      - name: Zvfbfa
 assembly: vd, vs2, fs1, vm
 encoding:
   match: 011011-----------101-----1010111

data/.data/spec/std/isa/inst/V/vmflt.vv.yaml

@@ -11,7 +11,9 @@ description: |
   No description available.
 definedBy:
   extension:
-    name: Zvl32b
+    anyOf:
+      - name: Zvl32b
+      - name: Zvfbfa
 assembly: vd, vs2, vs1, vm
 encoding:
   match: 011011-----------001-----1010111

data/.data/spec/std/isa/inst/V/vmfne.vf.yaml

@@ -11,7 +11,9 @@ description: |
   No description available.
 definedBy:
   extension:
-    name: Zvl32b
+    anyOf:
+      - name: Zvl32b
+      - name: Zvfbfa
 assembly: vd, vs2, fs1, vm
 encoding:
   match: 011100-----------101-----1010111

data/.data/spec/std/isa/inst/V/vmfne.vv.yaml

@@ -11,7 +11,9 @@ description: |
   No description available.
 definedBy:
   extension:
-    name: Zvl32b
+    anyOf:
+      - name: Zvl32b
+      - name: Zvfbfa
 assembly: vd, vs2, vs1, vm
 encoding:
   match: 011100-----------001-----1010111

data/.data/spec/std/isa/inst/V/vnclip.wi.yaml

@@ -6,9 +6,9 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: vnclip.wi
-long_name: "Vector widening signed clip with immediate"
+long_name: "Vector narrowing signed clip with immediate"
 description: |
-  Performs widening signed clip operation on elements from vector register vs2 using immediate clip value and stores results in vector register vd, using vector mask vm. The operation clips values to a specified range and widens the result.
+  Performs narrowing signed clip operation on double-width elements from vector register vs2 using immediate clip value and stores results in vector register vd, using vector mask vm. The operation clips values to a specified range and packs the result into a narrower destination.
 definedBy:
   extension:
     name: Zvl32b

data/.data/spec/std/isa/inst/V/vnclip.wv.yaml

@@ -6,9 +6,9 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: vnclip.wv
-long_name: "Vector widening signed clip"
+long_name: "Vector narrowing signed clip"
 description: |
-  Performs widening signed clip operation on elements from vector register vs2 using clip values from vector register vs1 and stores results in vector register vd, using vector mask vm. The operation clips values to a specified range and widens the result.
+  Performs narrowing signed clip operation on double-width elements from vector register vs2 using clip values from vector register vs1 and stores results in vector register vd, using vector mask vm. The operation clips values to a specified range and packs the result into a narrower destination.
 definedBy:
   extension:
     name: Zvl32b

data/.data/spec/std/isa/inst/V/vnclip.wx.yaml

@@ -6,9 +6,9 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: vnclip.wx
-long_name: "Vector widening signed clip with scalar"
+long_name: "Vector narrowing signed clip with scalar"
 description: |
-  Performs widening signed clip operation on elements from vector register vs2 using scalar clip value from register xs1 and stores results in vector register vd, using vector mask vm. The operation clips values to a specified range and widens the result.
+  Performs narrowing signed clip operation on double-width elements from vector register vs2 using scalar clip value from register xs1 and stores results in vector register vd, using vector mask vm. The operation clips values to a specified range and packs the result into a narrower destination.
 definedBy:
   extension:
     name: Zvl32b

data/.data/spec/std/isa/inst/V/vnclipu.wi.yaml

@@ -6,9 +6,9 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: vnclipu.wi
-long_name: "Vector widening unsigned clip with immediate"
+long_name: "Vector narrowing unsigned clip with immediate"
 description: |
-  Performs widening unsigned clip operation on elements from vector register vs2 using immediate clip value and stores results in vector register vd, using vector mask vm. The operation clips values to a specified range and widens the result.
+  Performs narrowing unsigned clip operation on double-width elements from vector register vs2 using immediate clip value and stores results in vector register vd, using vector mask vm. The operation clips values to a specified range and packs the result into a narrower destination.
 definedBy:
   extension:
     name: Zvl32b

data/.data/spec/std/isa/inst/V/vnclipu.wv.yaml

@@ -6,9 +6,9 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: vnclipu.wv
-long_name: "Vector widening unsigned clip"
+long_name: "Vector narrowing unsigned clip"
 description: |
-  Performs widening unsigned clip operation on elements from vector register vs2 using clip values from vector register vs1 and stores results in vector register vd, using vector mask vm. The operation clips values to a specified range and widens the result.
+  Performs narrowing unsigned clip operation on double-width elements from vector register vs2 using clip values from vector register vs1 and stores results in vector register vd, using vector mask vm. The operation clips values to a specified range and packs the result into a narrower destination.
 definedBy:
   extension:
     name: Zvl32b

data/.data/spec/std/isa/inst/V/vnclipu.wx.yaml

@@ -6,9 +6,9 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: vnclipu.wx
-long_name: "Vector widening unsigned clip with scalar"
+long_name: "Vector narrowing unsigned clip with scalar"
 description: |
-  Performs widening unsigned clip operation on elements from vector register vs2 using scalar clip value from register xs1 and stores results in vector register vd, using vector mask vm. The operation clips values to a specified range and widens the result.
+  Performs narrowing unsigned clip operation on double-width elements from vector register vs2 using scalar clip value from register xs1 and stores results in vector register vd, using vector mask vm. The operation clips values to a specified range and packs the result into a narrower destination.
 definedBy:
   extension:
     name: Zvl32b

data/.data/spec/std/isa/inst/V/vnsra.wi.yaml

@@ -6,9 +6,9 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: vnsra.wi
-long_name: "Vector widening signed shift right arithmetic with immediate"
+long_name: "Vector narrowing signed shift right arithmetic with immediate"
 description: |
-  Performs widening signed arithmetic right shift on elements from vector register vs2 by immediate shift amount and stores results in vector register vd, using vector mask vm. The operation preserves the sign bit and widens the result.
+  Performs narrowing signed arithmetic right shift on double-width elements from vector register vs2 by immediate shift amount and stores results in vector register vd, using vector mask vm. The operation preserves the sign bit and writes a single-width destination.
 definedBy:
   extension:
     name: Zvl32b

data/.data/spec/std/isa/inst/V/vnsra.wv.yaml

@@ -6,9 +6,9 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: vnsra.wv
-long_name: "Vector widening signed shift right arithmetic"
+long_name: "Vector narrowing signed shift right arithmetic"
 description: |
-  Performs widening signed arithmetic right shift on elements from vector register vs2 by shift amounts from vector register vs1 and stores results in vector register vd, using vector mask vm. The operation preserves the sign bit and widens the result.
+  Performs narrowing signed arithmetic right shift on double-width elements from vector register vs2 by shift amounts from vector register vs1 and stores results in vector register vd, using vector mask vm. The operation preserves the sign bit and writes a single-width destination.
 definedBy:
   extension:
     name: Zvl32b

data/.data/spec/std/isa/inst/V/vnsra.wx.yaml

@@ -6,9 +6,9 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: vnsra.wx
-long_name: "Vector widening signed shift right arithmetic with scalar"
+long_name: "Vector narrowing signed shift right arithmetic with scalar"
 description: |
-  Performs widening signed arithmetic right shift on elements from vector register vs2 by shift amount from scalar register xs1 and stores results in vector register vd, using vector mask vm. The operation preserves the sign bit and widens the result.
+  Performs narrowing signed arithmetic right shift on double-width elements from vector register vs2 by shift amount from scalar register xs1 and stores results in vector register vd, using vector mask vm. The operation preserves the sign bit and writes a single-width destination.
 definedBy:
   extension:
     name: Zvl32b

data/.data/spec/std/isa/inst/V/vnsrl.wi.yaml

@@ -6,9 +6,9 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: vnsrl.wi
-long_name: "Vector widening logical shift right with immediate"
+long_name: "Vector narrowing logical shift right with immediate"
 description: |
-  Performs widening logical right shift on elements from vector register vs2 by immediate shift amount and stores results in vector register vd, using vector mask vm. The operation fills with zeros and widens the result.
+  Performs narrowing logical right shift on double-width elements from vector register vs2 by immediate shift amount and stores results in vector register vd, using vector mask vm. The operation fills with zeros and writes a single-width destination.
 definedBy:
   extension:
     name: Zvl32b

data/.data/spec/std/isa/inst/V/vnsrl.wv.yaml

@@ -6,9 +6,9 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: vnsrl.wv
-long_name: "Vector widening logical shift right"
+long_name: "Vector narrowing logical shift right"
 description: |
-  Performs widening logical right shift on elements from vector register vs2 by shift amounts from vector register vs1 and stores results in vector register vd, using vector mask vm. The operation fills with zeros and widens the result.
+  Performs narrowing logical right shift on double-width elements from vector register vs2 by shift amounts from vector register vs1 and stores results in vector register vd, using vector mask vm. The operation fills with zeros and writes a single-width destination.
 definedBy:
   extension:
     name: Zvl32b

data/.data/spec/std/isa/inst/V/vnsrl.wx.yaml

@@ -6,9 +6,9 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: vnsrl.wx
-long_name: "Vector widening logical shift right with scalar"
+long_name: "Vector narrowing logical shift right with scalar"
 description: |
-  Performs widening logical right shift on elements from vector register vs2 by shift amount from scalar register xs1 and stores results in vector register vd, using vector mask vm. The operation fills with zeros and widens the result.
+  Performs narrowing logical right shift on double-width elements from vector register vs2 by shift amount from scalar register xs1 and stores results in vector register vd, using vector mask vm. The operation fills with zeros and writes a single-width destination.
 definedBy:
   extension:
     name: Zvl32b

data/.data/spec/std/isa/inst/Zaamo/amoadd.SIZE.AQRL.layout

@@ -69,16 +69,12 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && MISA_CSR_IMPLEMENTED && CSR[misa].A == 1'b0) {
-    reserved_instruction($encoding);
-  }
-
 <% if aq -%>
   memory_model_acquire();
 
 <% end -%>
   XReg virtual_address = X[xs1];
-  X[xd] = amo(<%= current_size[:operation_bits] %>, virtual_address, X[xs2]<%= %w[b h w].include?(size) ? "[#{current_size[:bits]-1}:0]" : "" %>, AmoOperation::Add, <%= aq ? "1'b1" : "1'b0" %>, <%= rl ? "1'b1" : "1'b0" %>, $encoding);
+  X[xd] = <%= %w[b h w].include?(size) ? "sext(" : "" %>amo(<%= current_size[:operation_bits] %>, virtual_address, X[xs2]<%= %w[b h w].include?(size) ? "[#{current_size[:bits]-1}:0]" : "" %>, AmoOperation::Add, <%= aq ? "1'b1" : "1'b0" %>, <%= rl ? "1'b1" : "1'b0" %>, $encoding)<%= %w[b h w].include?(size) ? ", #{current_size[:bits]})" : "" %>;
 <% if rl -%>
 
   memory_model_release();

data/.data/spec/std/isa/inst/Zaamo/amoadd.d.aq.yaml

@@ -39,10 +39,6 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && MISA_CSR_IMPLEMENTED && CSR[misa].A == 1'b0) {
-    reserved_instruction($encoding);
-  }
-
   memory_model_acquire();
 
   XReg virtual_address = X[xs1];

data/.data/spec/std/isa/inst/Zaamo/amoadd.d.aqrl.yaml

@@ -39,10 +39,6 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && MISA_CSR_IMPLEMENTED && CSR[misa].A == 1'b0) {
-    reserved_instruction($encoding);
-  }
-
   memory_model_acquire();
 
   XReg virtual_address = X[xs1];

data/.data/spec/std/isa/inst/Zaamo/amoadd.d.rl.yaml

@@ -39,10 +39,6 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && MISA_CSR_IMPLEMENTED && CSR[misa].A == 1'b0) {
-    reserved_instruction($encoding);
-  }
-
   XReg virtual_address = X[xs1];
   X[xd] = amo(64, virtual_address, X[xs2], AmoOperation::Add, 1'b0, 1'b1, $encoding);
 

data/.data/spec/std/isa/inst/Zaamo/amoadd.d.yaml

@@ -39,9 +39,5 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && MISA_CSR_IMPLEMENTED && CSR[misa].A == 1'b0) {
-    reserved_instruction($encoding);
-  }
-
   XReg virtual_address = X[xs1];
   X[xd] = amo(64, virtual_address, X[xs2], AmoOperation::Add, 1'b0, 1'b0, $encoding);

data/.data/spec/std/isa/inst/Zaamo/amoadd.w.aq.yaml

@@ -37,11 +37,7 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && MISA_CSR_IMPLEMENTED && CSR[misa].A == 1'b0) {
-    reserved_instruction($encoding);
-  }
-
   memory_model_acquire();
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo(32, virtual_address, X[xs2][31:0], AmoOperation::Add, 1'b1, 1'b0, $encoding);
+  X[xd] = sext(amo(32, virtual_address, X[xs2][31:0], AmoOperation::Add, 1'b1, 1'b0, $encoding), 32);

data/.data/spec/std/isa/inst/Zaamo/amoadd.w.aqrl.yaml

@@ -37,13 +37,9 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && MISA_CSR_IMPLEMENTED && CSR[misa].A == 1'b0) {
-    reserved_instruction($encoding);
-  }
-
   memory_model_acquire();
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo(32, virtual_address, X[xs2][31:0], AmoOperation::Add, 1'b1, 1'b1, $encoding);
+  X[xd] = sext(amo(32, virtual_address, X[xs2][31:0], AmoOperation::Add, 1'b1, 1'b1, $encoding), 32);
 
   memory_model_release();

data/.data/spec/std/isa/inst/Zaamo/amoadd.w.rl.yaml

@@ -37,11 +37,7 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && MISA_CSR_IMPLEMENTED && CSR[misa].A == 1'b0) {
-    reserved_instruction($encoding);
-  }
-
   XReg virtual_address = X[xs1];
-  X[xd] = amo(32, virtual_address, X[xs2][31:0], AmoOperation::Add, 1'b0, 1'b1, $encoding);
+  X[xd] = sext(amo(32, virtual_address, X[xs2][31:0], AmoOperation::Add, 1'b0, 1'b1, $encoding), 32);
 
   memory_model_release();

data/.data/spec/std/isa/inst/Zaamo/amoadd.w.yaml

@@ -37,9 +37,5 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && MISA_CSR_IMPLEMENTED && CSR[misa].A == 1'b0) {
-    reserved_instruction($encoding);
-  }
-
   XReg virtual_address = X[xs1];
-  X[xd] = amo(32, virtual_address, X[xs2][31:0], AmoOperation::Add, 1'b0, 1'b0, $encoding);
+  X[xd] = sext(amo(32, virtual_address, X[xs2][31:0], AmoOperation::Add, 1'b0, 1'b0, $encoding), 32);

data/.data/spec/std/isa/inst/Zaamo/amoand.SIZE.AQRL.layout

@@ -69,16 +69,12 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && MISA_CSR_IMPLEMENTED && CSR[misa].A == 1'b0) {
-    reserved_instruction($encoding);
-  }
-
 <% if aq -%>
   memory_model_acquire();
 
 <% end -%>
   XReg virtual_address = X[xs1];
-  X[xd] = amo(<%= current_size[:operation_bits] %>, virtual_address, X[xs2]<%= %w[b h w].include?(size) ? "[#{current_size[:bits]-1}:0]" : "" %>, AmoOperation::And, <%= aq ? "1'b1" : "1'b0" %>, <%= rl ? "1'b1" : "1'b0" %>, $encoding);
+  X[xd] = <%= %w[b h w].include?(size) ? "sext(" : "" %>amo(<%= current_size[:operation_bits] %>, virtual_address, X[xs2]<%= %w[b h w].include?(size) ? "[#{current_size[:bits]-1}:0]" : "" %>, AmoOperation::And, <%= aq ? "1'b1" : "1'b0" %>, <%= rl ? "1'b1" : "1'b0" %>, $encoding)<%= %w[b h w].include?(size) ? ", #{current_size[:bits]})" : "" %>;
 <% if rl -%>
 
   memory_model_release();

data/.data/spec/std/isa/inst/Zaamo/amoand.d.aq.yaml

@@ -39,10 +39,6 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && MISA_CSR_IMPLEMENTED && CSR[misa].A == 1'b0) {
-    reserved_instruction($encoding);
-  }
-
   memory_model_acquire();
 
   XReg virtual_address = X[xs1];

data/.data/spec/std/isa/inst/Zaamo/amoand.d.aqrl.yaml

@@ -39,10 +39,6 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && MISA_CSR_IMPLEMENTED && CSR[misa].A == 1'b0) {
-    reserved_instruction($encoding);
-  }
-
   memory_model_acquire();
 
   XReg virtual_address = X[xs1];

data/.data/spec/std/isa/inst/Zaamo/amoand.d.rl.yaml

@@ -39,10 +39,6 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && MISA_CSR_IMPLEMENTED && CSR[misa].A == 1'b0) {
-    reserved_instruction($encoding);
-  }
-
   XReg virtual_address = X[xs1];
   X[xd] = amo(64, virtual_address, X[xs2], AmoOperation::And, 1'b0, 1'b1, $encoding);
 

data/.data/spec/std/isa/inst/Zaamo/amoand.d.yaml

@@ -39,9 +39,5 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && MISA_CSR_IMPLEMENTED && CSR[misa].A == 1'b0) {
-    reserved_instruction($encoding);
-  }
-
   XReg virtual_address = X[xs1];
   X[xd] = amo(64, virtual_address, X[xs2], AmoOperation::And, 1'b0, 1'b0, $encoding);