udb 0.1.16 → 0.1.18

data/.data/spec/std/isa/inst/C/c.sdsp.yaml

@@ -8,7 +8,7 @@ kind: instruction
 name: c.sdsp
 long_name: Store doubleword to stack
 description: |
-  Stores a 64-bit value in register rs2 to memory.
+  Stores a 64-bit value in register xs2 to memory.
   It computes an effective address by adding the zero-extended offset, scaled by 8,
   to the stack pointer, x2.
   It expands to `sd` `xs2, offset(x2)`.
@@ -45,19 +45,19 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::C) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   XReg virtual_address = X[2] + imm;
 
   if (xlen() == 32) {
     if (implemented?(ExtensionName::Zclsd)) {
-      Bits<64> data = {X[creg2reg(xs2) + 1], X[creg2reg(xs2)]};
+      Bits<64> data = {X[xs2 + 1], X[xs2]};
       write_memory(64, virtual_address, data, $encoding);
     } else {
       raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
     }
   } else {
-    write_memory(64, virtual_address, X[creg2reg(xs2)], $encoding);
+    write_memory(64, virtual_address, X[xs2], $encoding);
   }

data/.data/spec/std/isa/inst/C/c.sw.yaml

@@ -32,8 +32,8 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::C) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   XReg virtual_address = X[creg2reg(xs1)] + imm;

data/.data/spec/std/isa/inst/C/c.swsp.yaml

@@ -30,8 +30,8 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::C) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   XReg virtual_address = X[2] + imm;

data/.data/spec/std/isa/inst/H/hlv.b.yaml

@@ -13,7 +13,7 @@ description: |
 definedBy:
   extension:
     name: H
-assembly: xd, xs1
+assembly: xd, (xs1)
 encoding:
   match: 011000000000-----100-----1110011
   variables:

data/.data/spec/std/isa/inst/H/hlv.bu.yaml

@@ -13,7 +13,7 @@ description: |
 definedBy:
   extension:
     name: H
-assembly: xd, xs1
+assembly: xd, (xs1)
 encoding:
   match: 011000000001-----100-----1110011
   variables:

data/.data/spec/std/isa/inst/H/hlv.d.yaml

@@ -15,7 +15,7 @@ definedBy:
     - xlen: 64
     - extension:
         name: H
-assembly: xd, xs1
+assembly: xd, (xs1)
 encoding:
   match: 011011000000-----100-----1110011
   variables:

data/.data/spec/std/isa/inst/H/hlv.h.yaml

@@ -13,7 +13,7 @@ description: |
 definedBy:
   extension:
     name: H
-assembly: xd, xs1
+assembly: xd, (xs1)
 encoding:
   match: 011001000000-----100-----1110011
   variables:

data/.data/spec/std/isa/inst/H/hlv.hu.yaml

@@ -13,7 +13,7 @@ description: |
 definedBy:
   extension:
     name: H
-assembly: xd, xs1
+assembly: xd, (xs1)
 encoding:
   match: 011001000001-----100-----1110011
   variables:

data/.data/spec/std/isa/inst/H/hlv.w.yaml

@@ -13,7 +13,7 @@ description: |
 definedBy:
   extension:
     name: H
-assembly: xd, xs1
+assembly: xd, (xs1)
 encoding:
   match: 011010000000-----100-----1110011
   variables:

data/.data/spec/std/isa/inst/H/hlv.wu.yaml

@@ -15,7 +15,7 @@ definedBy:
     - xlen: 64
     - extension:
         name: H
-assembly: xd, xs1
+assembly: xd, (xs1)
 encoding:
   match: 011010000001-----100-----1110011
   variables:

data/.data/spec/std/isa/inst/H/hlvx.hu.yaml

@@ -15,7 +15,7 @@ description: |
 definedBy:
   extension:
     name: H
-assembly: xd, xs1
+assembly: xd, (xs1)
 encoding:
   match: 011001000011-----100-----1110011
   variables:

data/.data/spec/std/isa/inst/H/hlvx.wu.yaml

@@ -15,7 +15,7 @@ description: |
 definedBy:
   extension:
     name: H
-assembly: xd, xs1
+assembly: xd, (xs1)
 encoding:
   match: 011010000011-----100-----1110011
   variables:

data/.data/spec/std/isa/inst/H/hsv.b.yaml

@@ -13,7 +13,7 @@ description: |
 definedBy:
   extension:
     name: H
-assembly: xs1, xs2
+assembly: xs2, (xs1)
 encoding:
   match: 0110001----------100000001110011
   variables:

data/.data/spec/std/isa/inst/H/hsv.d.yaml

@@ -15,7 +15,7 @@ definedBy:
     - xlen: 64
     - extension:
         name: H
-assembly: xs1, xs2
+assembly: xs2, (xs1)
 encoding:
   match: 0110111----------100000001110011
   variables:

data/.data/spec/std/isa/inst/H/hsv.h.yaml

@@ -13,7 +13,7 @@ description: |
 definedBy:
   extension:
     name: H
-assembly: xs1, xs2
+assembly: xs2, (xs1)
 encoding:
   match: 0110011----------100000001110011
   variables:

data/.data/spec/std/isa/inst/H/hsv.w.yaml

@@ -13,7 +13,7 @@ description: |
 definedBy:
   extension:
     name: H
-assembly: xs1, xs2
+assembly: xs2, (xs1)
 encoding:
   match: 0110101----------100000001110011
   variables:

data/.data/spec/std/isa/inst/I/ld.yaml

@@ -18,10 +18,15 @@ description: |
   <% end %>
 
 definedBy:
-  extension:
-    anyOf:
-      - name: I
-      - name: Zilsd
+  anyOf:
+    - allOf:
+        - xlen: 64
+        - extension:
+            name: I
+    - allOf:
+        - xlen: 32
+        - extension:
+            name: Zilsd
 assembly: xd, imm(xs1)
 encoding:
   RV32:
@@ -53,15 +58,16 @@ access:
 operation(): |
   XReg virtual_address = X[xs1] + $signed(imm);
 
-  if (xlen() == 32) {
-    if (implemented?(ExtensionName::Zilsd)) {
-      Bits<64> data = read_memory(64, virtual_address, $encoding);
-
-      X[xd] = data[31:0];
-      X[xd+1] = data[63:32];
+  if (xlen() == 64) {
+    X[xd] = read_memory(64, virtual_address, $encoding);
+  } else if (implemented?(ExtensionName::Zilsd)) {
+    if (endianness() == Endian::Big) {
+      X[xd+1] = read_memory(32, virtual_address, $encoding);
+      X[xd] = read_memory(32, virtual_address + 4, $encoding);
     } else {
-      raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+      X[xd] = read_memory(32, virtual_address, $encoding);
+      X[xd+1] = read_memory(32, virtual_address + 4, $encoding);
     }
   } else {
-    X[xd] = read_memory(64, virtual_address, $encoding);
+    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
   }

data/.data/spec/std/isa/inst/I/sd.yaml

@@ -14,10 +14,15 @@ description: |
   For RV32, store doubleword from even/odd register pair.
   <% end %>
 definedBy:
-  extension:
-    anyOf:
-      - name: I
-      - name: Zilsd
+  anyOf:
+    - allOf:
+        - xlen: 64
+        - extension:
+            name: I
+    - allOf:
+        - xlen: 32
+        - extension:
+            name: Zilsd
 assembly: xs2, imm(xs1)
 encoding:
   RV32:
@@ -47,17 +52,18 @@ access:
   vs: always
   vu: always
 operation(): |
-  Bits<64> data;
   XReg virtual_address = X[xs1] + $signed(imm);
 
-  if (xlen() == 32) {
-    if (implemented?(ExtensionName::Zilsd)) {
-      data = {X[xs2 + 1], X[xs2]};
+  if (xlen() == 64) {
+    write_memory(64, virtual_address, X[xs2], $encoding);
+  } else if (implemented?(ExtensionName::Zilsd)) {
+    if (endianness() == Endian::Big) {
+      write_memory(32, virtual_address, X[xs2 + 1], $encoding);
+      write_memory(32, virtual_address + 4, X[xs2], $encoding);
     } else {
-      raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+      write_memory(32, virtual_address, X[xs2], $encoding);
+      write_memory(32, virtual_address + 4, X[xs2 + 1], $encoding);
     }
   } else {
-    data = X[xs2];
+    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
   }
-
-  write_memory(64, virtual_address, data, $encoding);

data/.data/spec/std/isa/inst/I/wfi.yaml

@@ -93,7 +93,7 @@ access_detail: |
   <%- end -%>
 operation(): |
   # first, perform all the access checks
-  if (mode() == PrivilegeMode::U) {
+  if (mode() == PrivilegeMode::U && !WFI_U_MODE) {
     raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
   }
   if ((CSR[misa].S == 1) && (CSR[mstatus].TW == 1'b1)) {

data/.data/spec/std/isa/inst/M/div.yaml

@@ -33,8 +33,8 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::M) && (CSR[misa].M == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::M) && MISA_CSR_IMPLEMENTED && (CSR[misa].M == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   XReg src1 = X[xs1];

data/.data/spec/std/isa/inst/M/divu.yaml

@@ -32,8 +32,8 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::M) && (CSR[misa].M == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::M) && MISA_CSR_IMPLEMENTED && (CSR[misa].M == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   XReg src1 = X[xs1];

data/.data/spec/std/isa/inst/M/divuw.yaml

@@ -34,8 +34,8 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::M) && (CSR[misa].M == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::M) && MISA_CSR_IMPLEMENTED && (CSR[misa].M == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   Bits<32> src1 = X[xs1][31:0];

data/.data/spec/std/isa/inst/M/divw.yaml

@@ -38,8 +38,8 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::M) && (CSR[misa].M == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::M) && MISA_CSR_IMPLEMENTED && (CSR[misa].M == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   Bits<32> src1 = X[xs1][31:0];

data/.data/spec/std/isa/inst/M/mul.yaml

@@ -40,10 +40,6 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
-  if (implemented?(ExtensionName::M) && (CSR[misa].M == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   XReg src1 = X[xs1];
   XReg src2 = X[xs2];
 

data/.data/spec/std/isa/inst/M/mulh.yaml

@@ -39,10 +39,6 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
-  if (implemented?(ExtensionName::M) && (CSR[misa].M == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   # enlarge and sign extend the sources
   Bits<1> xs1_sign_bit = X[xs1][xlen()-1];
   Bits<MXLEN `* 2> src1 = {{xlen(){xs1_sign_bit}}, X[xs1]};

data/.data/spec/std/isa/inst/M/mulhsu.yaml

@@ -39,10 +39,6 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
-  if (implemented?(ExtensionName::M) && (CSR[misa].M == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   # enlarge and extend the sources
   Bits<1> xs1_sign_bit = X[xs1][MXLEN-1];
   Bits<MXLEN*8'd2> src1 = {{MXLEN{xs1_sign_bit}}, X[xs1]};

data/.data/spec/std/isa/inst/M/mulhu.yaml

@@ -39,10 +39,6 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
-  if (implemented?(ExtensionName::M) && (CSR[misa].M == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   # enlarge and zero-extend the sources
   Bits<MXLEN*8'd2> src1 = {{MXLEN{1'b0}}, X[xs1]};
   Bits<MXLEN*8'd2> src2 = {{MXLEN{1'b0}}, X[xs2]};

data/.data/spec/std/isa/inst/M/mulw.yaml

@@ -40,10 +40,6 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
-  if (implemented?(ExtensionName::M) && (CSR[misa].M == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   Bits<32> src1 = X[xs1][31:0];
   Bits<32> src2 = X[xs2][31:0];
 

data/.data/spec/std/isa/inst/M/rem.yaml

@@ -32,8 +32,8 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::M) && (CSR[misa].M == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::M) && MISA_CSR_IMPLEMENTED && (CSR[misa].M == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   XReg src1 = X[xs1];

data/.data/spec/std/isa/inst/M/remu.yaml

@@ -28,8 +28,8 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::M) && (CSR[misa].M == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::M) && MISA_CSR_IMPLEMENTED && (CSR[misa].M == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   XReg src1 = X[xs1];

data/.data/spec/std/isa/inst/M/remuw.yaml

@@ -33,8 +33,8 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::M) && (CSR[misa].M == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::M) && MISA_CSR_IMPLEMENTED && (CSR[misa].M == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   Bits<32> src1 = X[xs1][31:0];

data/.data/spec/std/isa/inst/M/remw.yaml

@@ -35,8 +35,8 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::M) && (CSR[misa].M == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::M) && MISA_CSR_IMPLEMENTED && (CSR[misa].M == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   Bits<32> src1 = X[xs1][31:0];

data/.data/spec/std/isa/inst/Q/fcvt.q.d.yaml

@@ -11,7 +11,7 @@ definedBy:
   extension:
     name: Q
 description: |
-  `fcvt.d.q` converts a double-precision floating-point number to a quad-precision floating-point number.
+  `fcvt.q.d` converts a double-precision floating-point number to a quad-precision floating-point number.
 assembly: fd, fs1, rm
 encoding:
   match: 010001100001-------------1010011

data/.data/spec/std/isa/inst/Q/flq.yaml

@@ -18,7 +18,7 @@ description: |
 definedBy:
   extension:
     name: Q
-assembly: fd, xs1, imm
+assembly: fd, imm(xs1)
 encoding:
   match: "-----------------100-----0000111"
   variables:

data/.data/spec/std/isa/inst/Sdext/dret.yaml

@@ -6,9 +6,26 @@
 $schema: inst_schema.json#
 kind: instruction
 name: dret
-long_name: No synopsis available
+long_name: Return from Debug Mode
 description: |
-  No description available.
+  Resumes execution after Debug Mode. `dret` is only legal in Debug Mode;
+  executing it in any other mode raises an Illegal Instruction exception.
+
+  When executed in Debug Mode, `dret`:
+
+  . Sets the PC to the value in `dpc`.
+  . Changes the privilege and virtualization mode to those held in
+    `dcsr.PRV` and `dcsr.V`.
+  . If the new privilege mode is less privileged than M-mode, clears
+    `mstatus.MPRV`.
+  . If Smdbltrp is implemented and the new privilege mode is less privileged
+    than M-mode, clears `mstatus.MDT`.
+  . If Ssdbltrp is implemented and the new privilege mode is U, VS, or VU,
+    clears `sstatus.SDT`; if the new mode is VU, also clears `vsstatus.SDT`.
+  . If Zicfilp is implemented, sets `ELP` to `dcsr.PELP` if Zicfilp is
+    enabled (`xLPE`=1) in the new privilege mode, otherwise to
+    `NO_LP_EXPECTED`, and then clears `dcsr.PELP`.
+  . Leaves Debug Mode.
 definedBy:
   extension:
     name: Sdext
@@ -17,9 +34,58 @@ encoding:
   match: "01111011001000000000000001110011"
   variables: []
 access:
-  s: always
-  u: always
-  vs: always
-  vu: always
+  s: never
+  u: never
+  vs: never
+  vu: never
 data_independent_timing: false
 operation(): |
+  # UDB does not yet model Debug Mode state, so the hart can never be in Debug
+  # Mode and dret is always illegal, regardless of privilege mode.
+  # TODO: once Debug Mode is modeled, raise this only when the hart is not in
+  # Debug Mode.
+  raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
+
+  # determine the resume mode from dcsr.PRV/dcsr.V
+  PrivilegeMode new_mode = PrivilegeMode::M;
+  if (CSR[dcsr].PRV == 2'b11) {
+    new_mode = PrivilegeMode::M;
+  } else if (CSR[dcsr].PRV == 2'b01) {
+    new_mode = PrivilegeMode::S;
+    if (implemented?(ExtensionName::H)) {
+      if (CSR[dcsr].V == 1'b1) {
+        new_mode = PrivilegeMode::VS;
+      }
+    }
+  } else if (CSR[dcsr].PRV == 2'b00) {
+    new_mode = PrivilegeMode::U;
+    if (implemented?(ExtensionName::H)) {
+      if (CSR[dcsr].V == 1'b1) {
+        new_mode = PrivilegeMode::VU;
+      }
+    }
+  } else {
+    unpredictable("dcsr.PRV holds a reserved encoding; the hart may resume in any supported privilege mode");
+  }
+
+  if (new_mode != PrivilegeMode::M) {
+    if (implemented?(ExtensionName::U)) {
+      CSR[mstatus].MPRV = 0;
+    }
+    if (implemented?(ExtensionName::Smdbltrp)) {
+      CSR[mstatus].MDT = 1'b0;
+    }
+  }
+
+  # TODO: Ssdbltrp: if new_mode is U, VS, or VU, clear sstatus.SDT; if new_mode
+  # is VU, also clear vsstatus.SDT. UDB does not yet define the SDT fields.
+
+  if (implemented?(ExtensionName::Zicfilp)) {
+    # TODO: set ELP to dcsr.PELP if xLPE is enabled for new_mode, otherwise to
+    # NO_LP_EXPECTED. UDB does not yet model the ELP state, so this restore
+    # must happen before dcsr.PELP is cleared below once it is added.
+    CSR[dcsr].PELP = 1'b0;
+  }
+
+  set_mode(new_mode);
+  $pc = $bits(CSR[dpc]);

data/.data/spec/std/isa/inst/V/vfadd.vf.yaml

@@ -11,7 +11,9 @@ description: |
   Performs floating-point addition on elements from vs2 and scalar from rs1, according to mask vm, and stores results in vd. Element width is determined by SEW setting. Follows IEEE-754 floating-point standards. Supports vector masking and follows vector tail policy.
 definedBy:
   extension:
-    name: Zvl32b
+    anyOf:
+      - name: Zvl32b
+      - name: Zvfbfa
 assembly: vd, vs2, fs1, vm
 encoding:
   match: 000000-----------101-----1010111

data/.data/spec/std/isa/inst/V/vfadd.vv.yaml

@@ -11,7 +11,9 @@ description: |
   Performs floating-point addition on elements from vs2 and vs1, according to mask vm, and stores results in vd. Element width is determined by SEW setting. Follows IEEE-754 floating-point standards. Supports vector masking and follows vector tail policy.
 definedBy:
   extension:
-    name: Zvl32b
+    anyOf:
+      - name: Zvl32b
+      - name: Zvfbfa
 assembly: vd, vs2, vs1, vm
 encoding:
   match: 000000-----------001-----1010111

data/.data/spec/std/isa/inst/V/vfclass.v.yaml

@@ -11,7 +11,9 @@ description: |
   No description available.
 definedBy:
   extension:
-    name: Zvl32b
+    anyOf:
+      - name: Zvl32b
+      - name: Zvfbfa
 assembly: vd, vs2, vm
 encoding:
   match: 010011------10000001-----1010111

data/.data/spec/std/isa/inst/V/vfmacc.vf.yaml

@@ -11,7 +11,9 @@ description: |
   No description available.
 definedBy:
   extension:
-    name: Zvl32b
+    anyOf:
+      - name: Zvl32b
+      - name: Zvfbfa
 assembly: vd, fs1, vs2, vm
 encoding:
   match: 101100-----------101-----1010111

data/.data/spec/std/isa/inst/V/vfmacc.vv.yaml

@@ -11,7 +11,9 @@ description: |
   No description available.
 definedBy:
   extension:
-    name: Zvl32b
+    anyOf:
+      - name: Zvl32b
+      - name: Zvfbfa
 assembly: vd, vs1, vs2, vm
 encoding:
   match: 101100-----------001-----1010111

data/.data/spec/std/isa/inst/V/vfmadd.vf.yaml

@@ -11,7 +11,9 @@ description: |
   No description available.
 definedBy:
   extension:
-    name: Zvl32b
+    anyOf:
+      - name: Zvl32b
+      - name: Zvfbfa
 assembly: vd, fs1, vs2, vm
 encoding:
   match: 101000-----------101-----1010111

data/.data/spec/std/isa/inst/V/vfmadd.vv.yaml

@@ -11,7 +11,9 @@ description: |
   No description available.
 definedBy:
   extension:
-    name: Zvl32b
+    anyOf:
+      - name: Zvl32b
+      - name: Zvfbfa
 assembly: vd, vs1, vs2, vm
 encoding:
   match: 101000-----------001-----1010111

data/.data/spec/std/isa/inst/V/vfmax.vf.yaml

@@ -11,7 +11,9 @@ description: |
   No description available.
 definedBy:
   extension:
-    name: Zvl32b
+    anyOf:
+      - name: Zvl32b
+      - name: Zvfbfa
 assembly: vd, vs2, fs1, vm
 encoding:
   match: 000110-----------101-----1010111