udb 0.1.16 → 0.1.18

data/.data/spec/std/isa/csr/Zkr/seed.yaml

@@ -0,0 +1,75 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/csr_schema.json
+
+$schema: "csr_schema.json#"
+kind: csr
+name: seed
+long_name: Seed for cryptographic random bit generators
+address: 0x015
+writable: true
+priv_mode: U
+length: 32
+description: |
+  The seed CSR provides an interface to a NIST SP 800-90B (Turan et al., 2018)
+  or BSI AIS-31 (Killmann & Schindler, 2011) compliant physical Entropy Source (ES).
+
+  The CSR provides up to 16 physical entropy bits that can be used to seed
+  cryptographic random bit generators. The write value is ignored by
+  implementations; the write is used to signal polling and flushing.
+definedBy:
+  extension:
+    name: Zkr
+fields:
+  OPST:
+    location: 31-30
+    description: |
+      Status bits returned by the entropy source.
+
+      Encodings are:
+
+      * 0 - BIST
+      * 1 - WAIT
+      * 2 - ES16
+      * 3 - DEAD
+    type: RW-H
+    sw_write(csr_value): |
+      write_seed();
+      return CSR[seed].OPST;
+    reset_value: 0
+  ENTROPY:
+    location: 15-0
+    description: |
+      Sixteen bits of randomness.
+
+      This field is valid only when `OPST` is ES16. When `OPST` is not ES16,
+      `ENTROPY` must be zero.
+    type: RW-H
+    sw_write(csr_value): |
+      return CSR[seed].ENTROPY;
+    reset_value: 0
+sw_read(): |
+  # CSRRS/CSRRC/CSRRSI/CSRRCI are the CSR instructions with funct3[1] set.
+  # Bits 19:15 hold rs1 for the register forms and uimm for the immediate
+  # forms, so a single zero check covers rs1 == x0 and uimm == 0.
+  Boolean read_only_access = ($encoding[13] == 1'b1) && ($encoding[19:15] == 5'b00000);
+
+  if (read_only_access) {
+    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  }
+
+  if (mode() == PrivilegeMode::U && CSR[mseccfg].USEED == 1'b0) {
+    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  } else if (mode() == PrivilegeMode::S && CSR[mseccfg].SSEED == 1'b0) {
+    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  } else if (mode() == PrivilegeMode::VS || mode() == PrivilegeMode::VU) {
+    if (CSR[mseccfg].SSEED == 1'b1) {
+      raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
+    } else {
+      raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+    }
+  }
+
+  # A single poll returns both the status and the entropy it goes with.
+  return read_seed();

data/.data/spec/std/isa/csr/hcontext.yaml

@@ -39,8 +39,8 @@ fields:
         unimplemented_csr($encoding);
       }
 
-      # check if HCONTEXT is available
-      if (!HCONTEXT_AVAILABLE) {
+      # check if HCONTEXT is implemented
+      if (!HCONTEXT_IMPLEMENTED) {
         unimplemented_csr($encoding);
       }
 
@@ -55,8 +55,8 @@ sw_read(): |
     unimplemented_csr($encoding);
   }
 
-  # check if HCONTEXT is available
-  if (!HCONTEXT_AVAILABLE) {
+  # check if HCONTEXT is implemented
+  if (!HCONTEXT_IMPLEMENTED) {
     unimplemented_csr($encoding);
   }
 

data/.data/spec/std/isa/csr/mcontext.yaml

@@ -39,8 +39,8 @@ fields:
       implement 7 bits on RV32 and 14 bits on RV64.
     reset_value: 0
     sw_write(csr_value): |
-      # check if MCONTEXT is available
-      if (!MCONTEXT_AVAILABLE) {
+      # check if MCONTEXT is implemented
+      if (!MCONTEXT_IMPLEMENTED) {
         unimplemented_csr($encoding);
       }
 
@@ -48,8 +48,8 @@ fields:
       Bits<14> hcontext_value = csr_value.HCONTEXT & ((14'1 << DBG_HCONTEXT_WIDTH) - 1);
       return hcontext_value;
 sw_read(): |
-  # check if MCONTEXT is available
-  if (!MCONTEXT_AVAILABLE) {
+  # check if MCONTEXT is implemented
+  if (!MCONTEXT_IMPLEMENTED) {
     unimplemented_csr($encoding);
   }
   return $bits(CSR[mcontext]);

data/.data/spec/std/isa/csr/mcycle.yaml

@@ -11,6 +11,8 @@ definedBy:
   extension:
     name: Sm
 address: 0xB00
+indirect_address: 0x40
+indirect_slot: 1
 writable: true
 description: |
   Counts the number of clock cycles executed by the processor core on which

data/.data/spec/std/isa/csr/mcycleh.yaml

@@ -13,6 +13,8 @@ definedBy:
     - extension:
         name: Sm
 address: 0xB80
+indirect_address: 0x40
+indirect_slot: 4
 writable: true
 description: |
   High-half alias of `mcycle`.

data/.data/spec/std/isa/csr/medeleg.yaml

@@ -76,8 +76,10 @@ fields:
       ! 1 ! M ! S
       !===
       <%- end -%>
-    type: RW
-    reset_value: UNDEFINED_LEGAL
+    type(): |
+      return MEDELEG_DELEGATABLE[0] ? CsrFieldType::RW : CsrFieldType::RO;
+    reset_value(): |
+      return MEDELEG_DELEGATABLE[0] ? UNDEFINED_LEGAL : 0;
   IAF:
     location: 1
     description: |
@@ -114,8 +116,10 @@ fields:
       !===
       <%- end -%>
 
-    type: RW
-    reset_value: UNDEFINED_LEGAL
+    type(): |
+      return MEDELEG_DELEGATABLE[1] ? CsrFieldType::RW : CsrFieldType::RO;
+    reset_value(): |
+      return MEDELEG_DELEGATABLE[1] ? UNDEFINED_LEGAL : 0;
   II:
     location: 2
     description: |
@@ -151,8 +155,10 @@ fields:
       ! 1 ! M ! S
       !===
       <%- end -%>
-    type: RW
-    reset_value: UNDEFINED_LEGAL
+    type(): |
+      return MEDELEG_DELEGATABLE[2] ? CsrFieldType::RW : CsrFieldType::RO;
+    reset_value(): |
+      return MEDELEG_DELEGATABLE[2] ? UNDEFINED_LEGAL : 0;
   B:
     location: 3
     description: |
@@ -188,8 +194,10 @@ fields:
       ! 1 ! M ! S
       !===
       <%- end -%>
-    type: RW
-    reset_value: UNDEFINED_LEGAL
+    type(): |
+      return MEDELEG_DELEGATABLE[3] ? CsrFieldType::RW : CsrFieldType::RO;
+    reset_value(): |
+      return MEDELEG_DELEGATABLE[3] ? UNDEFINED_LEGAL : 0;
   LAM:
     location: 4
     description: |
@@ -230,8 +238,10 @@ fields:
       !===
       <%- end -%>
 
-    type: RW
-    reset_value: UNDEFINED_LEGAL
+    type(): |
+      return MEDELEG_DELEGATABLE[4] ? CsrFieldType::RW : CsrFieldType::RO;
+    reset_value(): |
+      return MEDELEG_DELEGATABLE[4] ? UNDEFINED_LEGAL : 0;
   LAF:
     location: 5
     description: |
@@ -268,8 +278,10 @@ fields:
       !===
       <%- end -%>
 
-    type: RW
-    reset_value: UNDEFINED_LEGAL
+    type(): |
+      return MEDELEG_DELEGATABLE[5] ? CsrFieldType::RW : CsrFieldType::RO;
+    reset_value(): |
+      return MEDELEG_DELEGATABLE[5] ? UNDEFINED_LEGAL : 0;
   SAM:
     location: 6
     description: |
@@ -310,8 +322,10 @@ fields:
       !===
       <%- end -%>
 
-    type: RW
-    reset_value: UNDEFINED_LEGAL
+    type(): |
+      return MEDELEG_DELEGATABLE[6] ? CsrFieldType::RW : CsrFieldType::RO;
+    reset_value(): |
+      return MEDELEG_DELEGATABLE[6] ? UNDEFINED_LEGAL : 0;
   SAF:
     location: 7
     description: |
@@ -347,8 +361,10 @@ fields:
       ! 1 ! M ! S
       !===
       <%- end -%>
-    type: RW
-    reset_value: UNDEFINED_LEGAL
+    type(): |
+      return MEDELEG_DELEGATABLE[7] ? CsrFieldType::RW : CsrFieldType::RO;
+    reset_value(): |
+      return MEDELEG_DELEGATABLE[7] ? UNDEFINED_LEGAL : 0;
   EU:
     location: 8
     description: |
@@ -385,8 +401,10 @@ fields:
       !===
       <%- end -%>
 
-    type: RW
-    reset_value: UNDEFINED_LEGAL
+    type(): |
+      return MEDELEG_DELEGATABLE[8] ? CsrFieldType::RW : CsrFieldType::RO;
+    reset_value(): |
+      return MEDELEG_DELEGATABLE[8] ? UNDEFINED_LEGAL : 0;
   ES:
     location: 9
     description: |
@@ -409,8 +427,10 @@ fields:
       ! 0 ! M ! M
       ! 1 ! M ! (H)S
       !===
-    type: RW
-    reset_value: UNDEFINED_LEGAL
+    type(): |
+      return MEDELEG_DELEGATABLE[9] ? CsrFieldType::RW : CsrFieldType::RO;
+    reset_value(): |
+      return MEDELEG_DELEGATABLE[9] ? UNDEFINED_LEGAL : 0;
   EVS:
     location: 10
     description: |
@@ -433,8 +453,10 @@ fields:
       ! 0 ! M ! M
       ! 1 ! M ! (H)S
       !===
-    type: RW
-    reset_value: UNDEFINED_LEGAL
+    type(): |
+      return MEDELEG_DELEGATABLE[10] ? CsrFieldType::RW : CsrFieldType::RO;
+    reset_value(): |
+      return MEDELEG_DELEGATABLE[10] ? UNDEFINED_LEGAL : 0;
     definedBy:
       extension:
         name: H
@@ -483,8 +505,10 @@ fields:
       ! 1 ! M ! S
       !===
       <%- end -%>
-    type: RW
-    reset_value: UNDEFINED_LEGAL
+    type(): |
+      return MEDELEG_DELEGATABLE[12] ? CsrFieldType::RW : CsrFieldType::RO;
+    reset_value(): |
+      return MEDELEG_DELEGATABLE[12] ? UNDEFINED_LEGAL : 0;
   LPF:
     location: 13
     description: |
@@ -521,8 +545,10 @@ fields:
       !===
       <%- end -%>
 
-    type: RW
-    reset_value: UNDEFINED_LEGAL
+    type(): |
+      return MEDELEG_DELEGATABLE[13] ? CsrFieldType::RW : CsrFieldType::RO;
+    reset_value(): |
+      return MEDELEG_DELEGATABLE[13] ? UNDEFINED_LEGAL : 0;
   SPF:
     location: 15
     description: |
@@ -558,8 +584,10 @@ fields:
       ! 1 ! M ! S
       !===
       <%- end -%>
-    type: RW
-    reset_value: UNDEFINED_LEGAL
+    type(): |
+      return MEDELEG_DELEGATABLE[15] ? CsrFieldType::RW : CsrFieldType::RO;
+    reset_value(): |
+      return MEDELEG_DELEGATABLE[15] ? UNDEFINED_LEGAL : 0;
   IGPF:
     location: 20
     description: |
@@ -582,8 +610,10 @@ fields:
       ! 0 ! M ! M
       ! 1 ! M ! HS
       !===
-    type: RW
-    reset_value: UNDEFINED_LEGAL
+    type(): |
+      return MEDELEG_DELEGATABLE[20] ? CsrFieldType::RW : CsrFieldType::RO;
+    reset_value(): |
+      return MEDELEG_DELEGATABLE[20] ? UNDEFINED_LEGAL : 0;
     definedBy:
       extension:
         name: H
@@ -610,8 +640,10 @@ fields:
       ! 1 ! M ! HS
       !===
 
-    type: RW
-    reset_value: UNDEFINED_LEGAL
+    type(): |
+      return MEDELEG_DELEGATABLE[21] ? CsrFieldType::RW : CsrFieldType::RO;
+    reset_value(): |
+      return MEDELEG_DELEGATABLE[21] ? UNDEFINED_LEGAL : 0;
     definedBy:
       extension:
         name: H
@@ -638,8 +670,10 @@ fields:
       ! 1 ! M ! HS
       !===
 
-    type: RW
-    reset_value: UNDEFINED_LEGAL
+    type(): |
+      return MEDELEG_DELEGATABLE[22] ? CsrFieldType::RW : CsrFieldType::RO;
+    reset_value(): |
+      return MEDELEG_DELEGATABLE[22] ? UNDEFINED_LEGAL : 0;
     definedBy:
       extension:
         name: H
@@ -665,8 +699,10 @@ fields:
       ! 0 ! M ! M
       ! 1 ! M ! HS
       !===
-    type: RW
-    reset_value: UNDEFINED_LEGAL
+    type(): |
+      return MEDELEG_DELEGATABLE[23] ? CsrFieldType::RW : CsrFieldType::RO;
+    reset_value(): |
+      return MEDELEG_DELEGATABLE[23] ? UNDEFINED_LEGAL : 0;
     definedBy:
       extension:
         name: H

data/.data/spec/std/isa/csr/menvcfg.yaml

@@ -88,7 +88,7 @@ description: |
   NOTE: The Svade extension requires page-fault exceptions be raised when PTE
   A/D bits need be set, hence Svade is implemented when ADUE=0.
 
-  If the Smcdeleg extension is implemented, the CDE (Counter Delegation Enable) bit controls whether Zicntr and Zihpm counters can be delegated to S-mode. When CDE=1, the Smcdeleg extension is enabled, see <<smcdeleg>>. When CDE=0, the Smcdeleg and Ssccfg extensions appear to be not implemented. If Smcdeleg is not implemented, CDE is read-only zero.
+  The definition of the CDE field is furnished by the Smcdeleg extension.
 
   The definition of the STCE field is furnished by the Sstc extension.
 
@@ -204,6 +204,17 @@ fields:
       return (implemented?(ExtensionName::Svadu)) ? CsrFieldType::RW : CsrFieldType::RO;
     reset_value(): |
       return (implemented?(ExtensionName::Svadu)) ? UNDEFINED_LEGAL : 0;
+  CDE:
+    location: 60
+    description: |
+      *Counter Delegation Enable*
+
+      If the Smcdeleg extension is implemented, the CDE (Counter Delegation Enable) bit controls whether Zicntr and Zihpm counters can be delegated to S-mode. When CDE=1, the Smcdeleg extension is enabled, see <<smcdeleg>>. When CDE=0, the Smcdeleg and Ssccfg extensions appear to be not implemented. If Smcdeleg is not implemented, CDE is read-only zero.
+    definedBy:
+      extension:
+        name: Smcdeleg
+    type: RW
+    reset_value: UNDEFINED_LEGAL
   CBZE:
     location: 7
     description: |

data/.data/spec/std/isa/csr/menvcfgh.yaml

@@ -57,3 +57,15 @@ fields:
       return (implemented?(ExtensionName::Svadu)) ? CsrFieldType::RW : CsrFieldType::RO;
     reset_value(): |
       return (implemented?(ExtensionName::Svadu)) ? UNDEFINED_LEGAL : 0;
+  CDE:
+    location: 28
+    alias: menvcfg.CDE
+    description: |
+      *Counter Delegation Enable*
+
+      Alias of `menvcfg.CDE`
+    definedBy:
+      extension:
+        name: Smcdeleg
+    type: RW
+    reset_value: UNDEFINED_LEGAL

data/.data/spec/std/isa/csr/mideleg.yaml

@@ -101,8 +101,16 @@ fields:
       *Supervisor Software Interrupt delegation*
 
       When 1, Supervisor Software interrupts are delegated to HS/S-mode.
-    type: RW
+    type(): |
+      return MIDELEG_DELEGATABLE[1] ? CsrFieldType::RW : CsrFieldType::RO;
     reset_value: 0
+    sw_write(csr_value): |
+      if (csr_value.SSI == 0) {
+        if (implemented?(ExtensionName::H)) {
+          CSR[hideleg].SSI = 0;
+        }
+      }
+      return csr_value.SSI;
   VSSI:
     location: 2
     description: |
@@ -121,8 +129,10 @@ fields:
     description: |
       *Machine Software interrupt delegation*
 
-      Since M-mode interrupts cannot be delegated, this field is read-only zero.
-    type: RO
+      When 1, Machine Software interrupts are delegated to HS/S-mode.
+      This is unusual but permitted. See https://github.com/riscv/riscv-isa-manual/issues/3162.
+    type(): |
+      return MIDELEG_DELEGATABLE[3] ? CsrFieldType::RW : CsrFieldType::RO;
     reset_value: 0
   STI:
     location: 5
@@ -130,7 +140,8 @@ fields:
       *Supervisor Timer interrupt delegation*
 
       When 1, Supervisor Timer interrupts are delegated to HS/S-mode.
-    type: RW
+    type(): |
+      return MIDELEG_DELEGATABLE[5] ? CsrFieldType::RW : CsrFieldType::RO;
     reset_value: 0
   VSTI:
     location: 6
@@ -150,8 +161,10 @@ fields:
     description: |
       *Machine Timer interrupt delegation*
 
-      Since M-mode interrupts cannot be delegated, this field is read-only zero.
-    type: RO
+      When 1, Machine Timer interrupts are delegated to HS/S-mode.
+      This is unusual but permitted. See https://github.com/riscv/riscv-isa-manual/issues/3162.
+    type(): |
+      return MIDELEG_DELEGATABLE[7] ? CsrFieldType::RW : CsrFieldType::RO;
     reset_value: 0
   SEI:
     location: 9
@@ -159,7 +172,8 @@ fields:
       *Supervisor External interrupt delegation*
 
       When 1, Supervisor External interrupts are delegated to HS/S-mode.
-    type: RW
+    type(): |
+      return MIDELEG_DELEGATABLE[9] ? CsrFieldType::RW : CsrFieldType::RO;
     reset_value: 0
   VSEI:
     location: 10
@@ -177,17 +191,22 @@ fields:
     description: |
       *Machine External interrupt delegation*
 
-      Since M-mode interrupts cannot be delegated, this field is read-only zero.
-    type: RO
+      When 1, Machine External interrupts are delegated to HS/S-mode.
+      This is unusual but permitted. See https://github.com/riscv/riscv-isa-manual/issues/3162.
+    type(): |
+      return MIDELEG_DELEGATABLE[11] ? CsrFieldType::RW : CsrFieldType::RO;
     reset_value: 0
   SGEI:
     location: 12
     description: |
       *Supervisor Guest External Interrupt delegation*
 
-      Supervisor Guest External interrupts are always delegated to HS-mode, so this field is read-only one.
+      Supervisor Guest External interrupts are always delegated to HS-mode when any guest external interrupts
+      are implemented (`NUM_EXTERNAL_GUEST_INTERRUPTS` is nonzero), so this field is read-only one;
+      otherwise it is read-only zero.
     type: RO
-    reset_value: 1
+    reset_value(): |
+      return MIDELEG_DELEGATABLE[12] ? 1 : 0;
     definedBy:
       extension:
         name: H
@@ -197,8 +216,14 @@ fields:
       *Local Counter Overflow Interrupt delegation*
 
       When 1, local counter overflow interrupts are delegated to (H)S-mode.
-    type: RW
+    type(): |
+      return MIDELEG_DELEGATABLE[13] ? CsrFieldType::RW : CsrFieldType::RO;
     reset_value: 0
     definedBy:
       extension:
         name: Sscofpmf
+    sw_write(csr_value): |
+      if (csr_value.LCOFI == 0) {
+        CSR[hideleg].LCOFI = 0;
+      }
+      return csr_value.LCOFI;

data/.data/spec/std/isa/csr/mie.yaml

@@ -20,7 +20,8 @@ fields:
     location: 1
     description: |
       Enables Supervisor Software Interrupts.
-    type: RW
+    type(): |
+      return SSI_INTR_IMPL ? CsrFieldType::RW : CsrFieldType::RO;
     definedBy:
       extension:
         name: S
@@ -37,13 +38,15 @@ fields:
   MSIE:
     location: 3
     description: Enables Machine Software Interrupts.
-    type: RW
+    type(): |
+      return MSI_INTR_IMPL ? CsrFieldType::RW : CsrFieldType::RO;
     reset_value: 0
   STIE:
     location: 5
     description: |
       Enables Supervisor Timer Interrupts.
-    type: RW
+    type(): |
+      return STI_INTR_IMPL ? CsrFieldType::RW : CsrFieldType::RO;
     definedBy:
       extension:
         name: S
@@ -60,13 +63,15 @@ fields:
   MTIE:
     location: 7
     description: Enables Machine Timer Interrupts.
-    type: RW
+    type(): |
+      return MTI_INTR_IMPL ? CsrFieldType::RW : CsrFieldType::RO;
     reset_value: 0
   SEIE:
     location: 9
     description: |
       Enables Supervisor External Interrupts.
-    type: RW
+    type(): |
+      return SEI_INTR_IMPL ? CsrFieldType::RW : CsrFieldType::RO;
     definedBy:
       extension:
         name: S
@@ -83,7 +88,8 @@ fields:
   MEIE:
     location: 11
     description: Enables Machine External Interrupts.
-    type: RW
+    type(): |
+      return MEI_INTR_IMPL ? CsrFieldType::RW : CsrFieldType::RO;
     reset_value: 0
   SGEIE:
     location: 12

data/.data/spec/std/isa/csr/minstret.yaml

@@ -8,6 +8,8 @@ kind: csr
 name: minstret
 long_name: Machine Instructions Retired Counter
 address: 0xB02
+indirect_address: 0x42
+indirect_slot: 1
 writable: true
 description: |
   Counts the number of instructions retired by this hart from some arbitrary start point in the past.

data/.data/spec/std/isa/csr/minstreth.yaml

@@ -8,6 +8,8 @@ kind: csr
 name: minstreth
 long_name: Machine Instructions Retired Counter
 address: 0xB82
+indirect_address: 0x42
+indirect_slot: 4
 writable: true
 description: |
   Upper half of 64-bit instructions retired counters.

data/.data/spec/std/isa/csr/mip.yaml

@@ -185,7 +185,8 @@ fields:
       <%- if ext?(:Smaia) -%>
       * `mvip.SSIP`
       <%- end -%>
-    type: RW
+    type(): |
+      return SSI_INTR_IMPL ? CsrFieldType::RW : CsrFieldType::RO;
     reset_value: 0
     definedBy:
       extension:
@@ -225,13 +226,16 @@ fields:
     description: |
       *Machine Software Interrupt Pending*
 
-      Unused field.
+      Interrupt-pending bit for machine-level software interrupts.
+      MSIP is read-only in mip, and is written by accesses to memory-mapped control registers,
+      which are used to provide machine-level interprocessor interrupts.
 
       <%- if ext?(:Smaia) -%>
       With AIA/IMSIC, IPIs are delivered as external interrupts. As a result, this bit is
       unused and hardwired to 0.
       <%- end -%>
-    type: RO
+    type(): |
+      return MSI_INTR_IMPL ? CsrFieldType::ROH : CsrFieldType::RO;
     reset_value: 0
   STIP:
     location: 5
@@ -261,7 +265,8 @@ fields:
       * `mvip.STIP` when when `menvcfg.STCE` is clear
       <%- end -%>
 
-    type: RW
+    type(): |
+      return STI_INTR_IMPL ? CsrFieldType::RW : CsrFieldType::RO;
     reset_value: 0
     definedBy:
       extension:
@@ -312,7 +317,8 @@ fields:
       Reports the current pending state of an M-mode timer interrupt.
 
       Bit is controlled by the timer device (using `mtimecmp`), and is not writable.
-    type: RO-H
+    type(): |
+      return MTI_INTR_IMPL ? CsrFieldType::ROH : CsrFieldType::RO;
     reset_value: 0
   SEIP:
     location: 9
@@ -334,7 +340,8 @@ fields:
       _Alias_:
 
       * `sip.SEIP` when `mideleg.SEI` is set (though `sip.SEIP` is read-only)
-    type: RW-H
+    type(): |
+      return SEI_INTR_IMPL ? CsrFieldType::RWH : CsrFieldType::RO;
     definedBy:
       extension:
         name: S
@@ -378,7 +385,8 @@ fields:
 
       MEIP is controlled by the external interrupt controller <% if ext?(:Smaia) %>(AIA) <% end %>.
       It is not writable by software.
-    type: RO-H
+    type(): |
+      return MEI_INTR_IMPL ? CsrFieldType::ROH : CsrFieldType::RO;
     reset_value: 0
   SGEIP:
     location: 12