udb 0.1.16 → 0.1.18

data/.data/spec/std/isa/inst/Zvfbfmin/vfncvtbf16.f.f.w.yaml

@@ -11,7 +11,9 @@ description: |
   Converts each single-precision floating-point element in vector register vs2 to BFloat16 format, storing results in vector register vd according to mask vm. This is a narrowing conversion that compresses 32-bit single-precision values to 16-bit BFloat16 values.
 definedBy:
   extension:
-    name: Zvfbfmin
+    anyOf:
+      - name: Zvfbfmin
+      - name: Zvfofp8min
 assembly: vd, vs2, vm
 encoding:
   match: 010010------11101001-----1010111

data/.data/spec/std/isa/inst/Zvfbfmin/vfwcvtbf16.f.f.v.yaml

@@ -11,7 +11,9 @@ description: |
   Converts each BFloat16 element in vector register vs2 to single-precision floating-point format, storing results in vector register vd according to mask vm. This is a widening conversion that expands 16-bit BFloat16 values to 32-bit single-precision values.
 definedBy:
   extension:
-    name: Zvfbfmin
+    anyOf:
+      - name: Zvfbfmin
+      - name: Zvfofp8min
 assembly: vd, vs2, vm
 encoding:
   match: 010010------01101001-----1010111

data/.data/spec/std/isa/inst/Zvfofp4min/vfext.vf2.yaml

@@ -0,0 +1,35 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+$schema: "inst_schema.json#"
+kind: instruction
+name: vfext.vf2
+long_name: Vector OFP4 to OFP8 widening conversion
+description: |
+  Converts a vector of OFP4 E2M1 values in vector register vs2 (EEW=4,
+  EMUL=LMUL/2) to a vector of OFP8 E4M3 values in vector register vd
+  (EEW=8, EMUL=LMUL), according to mask vm. Defined only for SEW=8,
+  altfmt=0, and LMUL >= 1/4. No rounding occurs, and no floating-point
+  exception flags are set. This instruction does not access the fcsr
+  and is not considered a floating-point instruction for the purposes
+  of the floating-point context status (FS) setting.
+definedBy:
+  extension:
+    name: Zvfofp4min
+assembly: vd, vs2, vm
+encoding:
+  match: "010010------10110010-----1010111"
+  variables:
+    - name: vm
+      location: 25-25
+    - name: vs2
+      location: 24-20
+    - name: vd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+data_independent_timing: false
+operation(): |

data/.data/spec/std/isa/inst/Zvfofp8min/vfncvt.f.f.q.yaml

@@ -0,0 +1,31 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+$schema: "inst_schema.json#"
+kind: instruction
+name: vfncvt.f.f.q
+long_name: Vector floating-point FP32 conversion to OFP8
+description: |
+  Converts FP32 floating-point elements in vector register vs2 to OFP8
+  elements and stores the results in vector register vd according to mask vm.
+  Results are rounded using the dynamic floating-point rounding mode.
+definedBy:
+  extension:
+    name: Zvfofp8min
+assembly: vd, vs2, vm
+encoding:
+  match: 010010------11001001-----1010111
+  variables:
+    - name: vm
+      location: 25-25
+    - name: vs2
+      location: 24-20
+    - name: vd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+data_independent_timing: false
+operation(): |

data/.data/spec/std/isa/inst/Zvfofp8min/vfncvt.sat.f.f.q.yaml

@@ -0,0 +1,32 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+$schema: "inst_schema.json#"
+kind: instruction
+name: vfncvt.sat.f.f.q
+long_name: Vector floating-point FP32 saturating conversion to OFP8
+description: |
+  Converts FP32 floating-point elements in vector register vs2 to OFP8
+  elements and stores the results in vector register vd according to mask vm.
+  Infinite results are converted to the maximum-magnitude finite value of the
+  same sign.
+definedBy:
+  extension:
+    name: Zvfofp8min
+assembly: vd, vs2, vm
+encoding:
+  match: 010010------11011001-----1010111
+  variables:
+    - name: vm
+      location: 25-25
+    - name: vs2
+      location: 24-20
+    - name: vd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+data_independent_timing: false
+operation(): |

data/.data/spec/std/isa/inst/Zvfofp8min/vfncvtbf16.sat.f.f.w.yaml

@@ -0,0 +1,32 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+$schema: "inst_schema.json#"
+kind: instruction
+name: vfncvtbf16.sat.f.f.w
+long_name: Vector saturating narrowing BFloat16 to OFP8 conversion
+description: |
+  Converts BFloat16 floating-point elements in vector register vs2 to OFP8
+  elements and stores the results in vector register vd according to mask vm.
+  Infinite results are converted to the maximum-magnitude finite value of the
+  same sign.
+definedBy:
+  extension:
+    name: Zvfofp8min
+assembly: vd, vs2, vm
+encoding:
+  match: 010010------11111001-----1010111
+  variables:
+    - name: vm
+      location: 25-25
+    - name: vs2
+      location: 24-20
+    - name: vd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+data_independent_timing: false
+operation(): |

data/.data/spec/std/isa/inst/Zvzip/vpaire.vv.yaml

@@ -0,0 +1,36 @@
+# Copyright (c) 2026 Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+$schema: "inst_schema.json#"
+kind: instruction
+name: vpaire.vv
+long_name: Vector pair even
+description: |
+  Interleaves even-indexed elements of two source vector register groups into
+  the destination. All operands have EMUL=LMUL. For destination index `i`,
+  even indices read `vs2[i]` and odd indices read `vs1[i-1]`, producing
+  `[vs2[0], vs1[0], vs2[2], vs1[2], ...]`. Standard vector masking,
+  prestart, inactive, and tail handling applies. The destination may not
+  overlap either source group.
+definedBy:
+  extension:
+    name: Zvzip
+assembly: vd, vs2, vs1, vm
+encoding:
+  match: 001111-----------000-----1010111
+  variables:
+    - name: vm
+      location: 25
+    - name: vs2
+      location: 24-20
+    - name: vs1
+      location: 19-15
+    - name: vd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+data_independent_timing: true
+operation(): |

data/.data/spec/std/isa/inst/Zvzip/vpairo.vv.yaml

@@ -0,0 +1,37 @@
+# Copyright (c) 2026 Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+$schema: "inst_schema.json#"
+kind: instruction
+name: vpairo.vv
+long_name: Vector pair odd
+description: |
+  Interleaves odd-indexed elements of two source vector register groups into
+  the destination. All operands have EMUL=LMUL. For destination index `i`,
+  even indices read `vs2[i+1]` and odd indices read `vs1[i]`, producing
+  `[vs2[1], vs1[1], vs2[3], vs1[3], ...]`. When `vl` is odd, the final
+  out-of-range source position contributes zero; no source at or above `vl`
+  is read. Standard vector masking, prestart, inactive, and tail handling
+  applies. The destination may not overlap either source group.
+definedBy:
+  extension:
+    name: Zvzip
+assembly: vd, vs2, vs1, vm
+encoding:
+  match: 001111-----------010-----1010111
+  variables:
+    - name: vm
+      location: 25
+    - name: vs2
+      location: 24-20
+    - name: vs1
+      location: 19-15
+    - name: vd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+data_independent_timing: true
+operation(): |

data/.data/spec/std/isa/inst/Zvzip/vunzipe.v.yaml

@@ -0,0 +1,33 @@
+# Copyright (c) 2026 Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+$schema: "inst_schema.json#"
+kind: instruction
+name: vunzipe.v
+long_name: Vector unzip even
+description: |
+  Extracts even-indexed elements from source vector register group `vs2`,
+  with EMUL=2*LMUL, into destination `vd`, with EMUL=LMUL. For `0 <= i < vl`,
+  `vd[i] = vs2[2*i]`; source indices below `2*vl` may be read. `LMUL=8`
+  and masked encodings (`vm=0`) are illegal. Destination/source overlap is
+  allowed only when `vd` equals `vs2`, as for narrowing instructions.
+definedBy:
+  extension:
+    name: Zvzip
+assembly: vd, vs2, vm
+encoding:
+  match: 010010------01011010-----1010111
+  variables:
+    - name: vm
+      location: 25
+    - name: vs2
+      location: 24-20
+    - name: vd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+data_independent_timing: true
+operation(): |

data/.data/spec/std/isa/inst/Zvzip/vunzipo.v.yaml

@@ -0,0 +1,33 @@
+# Copyright (c) 2026 Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+$schema: "inst_schema.json#"
+kind: instruction
+name: vunzipo.v
+long_name: Vector unzip odd
+description: |
+  Extracts odd-indexed elements from source vector register group `vs2`,
+  with EMUL=2*LMUL, into destination `vd`, with EMUL=LMUL. For `0 <= i < vl`,
+  `vd[i] = vs2[2*i+1]`; source indices below `2*vl` may be read. `LMUL=8`
+  and masked encodings (`vm=0`) are illegal. Destination/source overlap is
+  allowed only when `vd` equals `vs2`, as for narrowing instructions.
+definedBy:
+  extension:
+    name: Zvzip
+assembly: vd, vs2, vm
+encoding:
+  match: 010010------01111010-----1010111
+  variables:
+    - name: vm
+      location: 25
+    - name: vs2
+      location: 24-20
+    - name: vd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+data_independent_timing: true
+operation(): |

data/.data/spec/std/isa/inst/Zvzip/vzip.vv.yaml

@@ -0,0 +1,37 @@
+# Copyright (c) 2026 Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+$schema: "inst_schema.json#"
+kind: instruction
+name: vzip.vv
+long_name: Vector zip
+description: |
+  Interleaves source vector register groups `vs2` and `vs1`, each with
+  EMUL=LMUL/2, into destination `vd` with EMUL=LMUL. For destination index
+  `i`, even indices read `vs2[i/2]` and odd indices read `vs1[i/2]`.
+  Standard vector masking, prestart, inactive, and tail handling applies.
+  The source and destination groups may overlap only when source EMUL is at
+  least 1 and their highest-numbered registers coincide. The encoding is
+  illegal when `2*SEW > LMUL * ELEN` or overlap rules are violated.
+definedBy:
+  extension:
+    name: Zvzip
+assembly: vd, vs2, vs1, vm
+encoding:
+  match: 111110-----------010-----1010111
+  variables:
+    - name: vm
+      location: 25
+    - name: vs2
+      location: 24-20
+    - name: vs1
+      location: 19-15
+    - name: vd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+data_independent_timing: true
+operation(): |

data/.data/spec/std/isa/isa/builtin_functions.idl

@@ -58,10 +58,12 @@ generated function direct_csr_lookup {
 generated function indirect_csr_lookup {
   returns Csr
   arguments
+    PrivilegeMode target_mode,
     Bits<MXLEN> csr_addr,
     Bits<4> window_slot  # 1-indexed "slot" in the window (corresponding to *ireg<window_slot>)
   description {
-    Return CSR info for a CSR with indirect address +csr_addr+ at window slot +window_slot+.
+    Return CSR info for a CSR with indirect address +csr_addr+ in the target privilege-mode
+    indirect address space at window slot +window_slot+.
 
     If no CSR exists, <return_value>.valid == false
   }
@@ -654,6 +656,38 @@ builtin function atomically_set_pte_a_d {
   }
 }
 
+builtin function atomic_read_modify_write_8 {
+  returns Bits<8>
+  arguments
+    Bits<PHYS_ADDR_WIDTH>  phys_addr,
+    Bits<8>                value,
+    AmoOperation           op
+  description {
+    Atomically read-modify-write 8-bits starting at phys_address using +value+ and +op+.
+
+    Return the original (unmodified) read value.
+
+    All access checks/alignment checks/etc. should be done before calling this function;
+    it's assumed the RMW is OK to proceed.
+  }
+}
+
+builtin function atomic_read_modify_write_16 {
+  returns Bits<16>
+  arguments
+    Bits<PHYS_ADDR_WIDTH>  phys_addr,
+    Bits<16>               value,
+    AmoOperation           op
+  description {
+    Atomically read-modify-write 16-bits starting at phys_address using +value+ and +op+.
+
+    Return the original (unmodified) read value.
+
+    All access checks/alignment checks/etc. should be done before calling this function;
+    it's assumed the RMW is OK to proceed.
+  }
+}
+
 builtin function atomic_read_modify_write_32 {
   returns Bits<32>
   arguments
@@ -685,3 +719,22 @@ builtin function atomic_read_modify_write_64 {
     it's assumed the RMW is OK to proceed.
   }
 }
+builtin function read_seed {
+ returns Bits<32>
+ description {
+   Poll the implementation's entropy source and return the 32-bit seed value.
+   Bits 31:30 hold the OPST status and bits 15:0 hold the entropy, which is
+   only meaningful when OPST is ES16. Each poll returns unique randomness,
+   even if its numerical value happens to match a previous poll.
+   A single call represents one complete poll, so the status and the entropy
+   it returns describe the same state of the source.
+ }
+}
+builtin function write_seed {
+ description {
+   Signal a write to the seed CSR.
+   The written value is ignored; the write exists to signal polling and
+   flushing, so an implementation may use this to advance the state of its
+   entropy source.
+ }
+}

data/.data/spec/std/isa/isa/globals.isa

@@ -945,6 +945,76 @@ function xlen {
   }
 }
 
+enum Endian {
+  Little  0
+  Big     1
+}
+
+function endianness {
+  returns Endian
+  description {
+    Returns the endianness for the effective privilege mode.
+  }
+  body {
+    if (effective_ldst_mode() == PrivilegeMode::M) {
+      if (CSR[mstatus].MBE == 1'b1) {
+        return Endian::Big;
+      } else {
+        return Endian::Little;
+      }
+    } else if (implemented?(ExtensionName::S) && effective_ldst_mode() == PrivilegeMode::S) {
+      if (CSR[mstatus].SBE == 1'b1) {
+        return Endian::Big;
+      } else {
+        return Endian::Little;
+      }
+    } else if (implemented?(ExtensionName::U) && effective_ldst_mode() == PrivilegeMode::U) {
+      if (CSR[mstatus].UBE == 1'b1) {
+        return Endian::Big;
+      } else {
+        return Endian::Little;
+      }
+    } else if (implemented?(ExtensionName::H)) {
+      if (effective_ldst_mode() == PrivilegeMode::VS) {
+        if(CSR[hstatus].VSBE == 1'b1) {
+          return Endian::Big;
+        } else {
+          return Endian::Little;
+        }
+      } else if (effective_ldst_mode() == PrivilegeMode::VU) {
+        if(CSR[vsstatus].UBE == 1'b1) {
+          return Endian::Big;
+        } else {
+          return Endian::Little;
+        }
+      } else {
+        unreachable();
+      }
+    } else {
+      unreachable();
+    }
+  }
+}
+
+function byte_swap {
+  returns XReg
+  arguments
+    U32 LEN,
+    XReg value
+  description {
+    Swaps bytes in register based on LEN.
+  }
+  body {
+    XReg result;
+
+    result = 0;
+    for (U32 i=0; i < LEN; i = i+8) {
+      result[(i+7):i] = value[(LEN-1-i):(LEN-8-i)];
+    }
+    return result;
+  }
+}
+
 function virtual_mode? {
   returns Boolean
   description {
@@ -2627,9 +2697,19 @@ function read_memory {
   body {
     Boolean aligned = is_naturally_aligned(LEN, virtual_address);
     XReg physical_address;
+    XReg result;
 
     if (aligned) {
-      return read_memory_aligned(LEN, virtual_address, encoding, 1'b0, 1'b0);
+      result = read_memory_aligned(LEN, virtual_address, encoding, 1'b0, 1'b0);
+      if (LEN > 8 && endianness() == Endian::Big ) {
+        U32 tmp;
+        for (U32 i=0; i < LEN/2; i = i+8) {
+          tmp = result[(i+7):i];
+          result[(i+7):i] = result[(LEN-1-i):(LEN-8-i)];
+          result[(LEN-1-i):(LEN-8-i)] = tmp[7:0];
+        }
+      }
+      return result;
     }
 
     # access isn't naturally aligned, but it still might be atomic if this hart supports
@@ -2646,7 +2726,16 @@ function read_memory {
 
       if (misaligned_is_atomic?(LEN, physical_address)) {
         access_check(physical_address, LEN, virtual_address, MemoryOperation::Read, ExceptionCode::LoadAccessFault, effective_ldst_mode());
-        return read_physical_memory(LEN, physical_address);
+        result = read_physical_memory(LEN, physical_address);
+        if (LEN > 8 && endianness() == Endian::Big) {
+          U32 tmp;
+          for (U32 i=0; i < LEN/2; i = i+8) {
+            tmp = result[(i+7):i];
+            result[(i+7):i] = result[(LEN-1-i):(LEN-8-i)];
+            result[(LEN-1-i):(LEN-8-i)] = tmp[7:0];
+          }
+        }
+        return result;
       }
     }
 
@@ -2666,10 +2755,18 @@ function read_memory {
 
       # misaligned, must break into multiple reads
       if (MISALIGNED_SPLIT_STRATEGY == "sequential_bytes") {
-        XReg result = 0;
+        result = 0;
         for (U32 I = 0; I < (LEN/8); I++) {
           result = result | (read_memory_aligned(8, virtual_address + I, encoding, 1'b0, 1'b0) `<< (8*I));
         }
+        if(LEN > 8 && endianness() == Endian::Big) {
+          U32 tmp;
+          for (U32 i=0; i < LEN/2; i = i+8) {
+            tmp = result[(i+7):i];
+            result[(i+7):i] = result[(LEN-1-i):(LEN-8-i)];
+            result[(LEN-1-i):(LEN-8-i)] = tmp[7:0];
+          }
+        }
         return result;
       } else if (MISALIGNED_SPLIT_STRATEGY == "custom") {
         unpredictable("An implementation is free to break a misaligned access any way, leading to unpredictable behavior when any part of the misaligned access causes an exception");
@@ -2972,10 +3069,16 @@ function amo {
       raise (ExceptionCode::StoreAmoAddressMisaligned, mode(), virtual_address);
     }
 
-    if (N == 32) {
+    if (N == 8) {
+      return atomic_read_modify_write_8(physical_address, value, op);
+    } else if (N == 16) {
+      return atomic_read_modify_write_16(physical_address, value, op);
+    } else if (N == 32) {
       return atomic_read_modify_write_32(physical_address, value, op);
-    } else {
+    } else if (N == 64) {
       return atomic_read_modify_write_64(physical_address, value, op);
+    } else {
+      unreachable();
     }
 
   }
@@ -3033,6 +3136,15 @@ function write_memory {
     Boolean aligned = is_naturally_aligned(LEN, virtual_address);
     XReg physical_address;
 
+    if(LEN > 8 && endianness() == Endian::Big) {
+      U32 tmp;
+      for (U32 i=0; i < LEN/2; i = i+8) {
+        tmp = value[(i+7):i];
+        value[(i+7):i] = value[(LEN-1-i):(LEN-8-i)];
+        value[(LEN-1-i):(LEN-8-i)] = tmp[7:0];
+      }
+    }
+
     if (aligned) {
       write_memory_aligned(LEN, virtual_address, value, encoding, 1'b0, 1'b0);
       return;

data/.data/spec/std/isa/isa/util.idl

@@ -71,6 +71,7 @@ function highest_set_bit {
   description {
     Returns the position of the highest (nearest MSB) bit that is '1',
     or -1 if value is zero.
+    Callers should cast the return value with $signed().
   }
   body {
     for (Bits<8> i=xlen(); i > 0; i--) {

data/.data/spec/std/isa/param/COUNTINHIBIT_EN.yaml

@@ -9,8 +9,8 @@ name: COUNTINHIBIT_EN
 description: |
   Indicates which hardware performance monitor counters can be disabled from `mcountinhibit`.
 
-  An unimplemented counter cannot be specified, i.e., if HPM_COUNTER_EN[3] is false,
-  it would be illegal to set COUNTINHIBIT_EN[3] to true.
+  `COUNTINHIBIT_EN[n]` controls whether `mcountinhibit.HPM<n>` is writable. It does
+  not depend on whether `hpmcounter<n>`/`mhpmcounter<n>` is read-only zero.
 
   COUNTINHIBIT_EN[1] can never be true, since it corresponds to `mcountinhibit.TM`,
   which is always read-only-0.
@@ -26,14 +26,6 @@ schema:
   maxItems: 32
   minItems: 32
 
-requirements:
-  idl(): |
-    for (U32 i = 3; i < 32; i++) {
-      (!HPM_COUNTER_EN[i]) -> !COUNTINHIBIT_EN[i];
-    }
-  reason: |
-    When mhpmcounter[i] is not implemented, it cannot be inhibited.
-
 definedBy:
   allOf:
     - extension:

data/.data/spec/std/isa/param/HCONTEXT_IMPLEMENTED.yaml

@@ -0,0 +1,29 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/param_schema.json
+
+$schema: param_schema.json#
+kind: parameter
+name: HCONTEXT_IMPLEMENTED
+description: |
+  Specifies if the hcontext CSR is implemented
+long_name: hcontext CSR is implemented
+schema:
+  type: boolean
+definedBy:
+  allOf:
+    - extension:
+        name: Sdtrig
+    - extension:
+        name: H
+requirements:
+  if:
+    param:
+      name: HCONTEXT_IMPLEMENTED
+      equal: true
+  then:
+    param:
+      name: MCONTEXT_IMPLEMENTED
+      equal: true
+      reason: HCONTEXT cannot exist without MCONTEXT

data/.data/spec/std/isa/param/HCOUNTENABLE_EN.yaml

@@ -9,9 +9,8 @@ name: HCOUNTENABLE_EN
 description: |
   Indicates which counters can delegated via `hcounteren`
 
-  An unimplemented counter cannot be specified, i.e., if
-  HPM_COUNTER_EN[3] is false, it would be illegal to set
-  HCOUNTENABLE_EN[3] to true.
+  `HCOUNTENABLE_EN[n]` controls whether `hcounteren.HPM<n>` is writable. It does not
+  depend on whether `hpmcounter<n>`/`mhpmcounter<n>` is read-only zero.
 
   HCOUNTENABLE_EN[0:2] must all be false if `Zicntr` is not implemented.
   HCOUNTENABLE_EN[3:31] must all be false if `Zihpm` is not implemented.
@@ -32,9 +31,7 @@ requirements:
     }
     for (U32 i = 3; i < 32; i++) {
       !implemented?(ExtensionName::Zihpm) -> !HCOUNTENABLE_EN[i];
-      (!HPM_COUNTER_EN[i]) -> !HCOUNTENABLE_EN[i];
     }
   reason: |
     Counters 0-2 are defined by Zicntr
     Counters 3..31 are defined by Zihpm
-    When mhpmcounter[i] is not implemented, it cannot be enabled.